xref: /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 #include "dm_services.h"
26 #include "dce_calcs.h"
27 #include "reg_helper.h"
28 #include "basics/conversion.h"
29 #include "dcn10_hubp.h"
30 
31 #define REG(reg)\
32 	hubp1->hubp_regs->reg
33 
34 #define CTX \
35 	hubp1->base.ctx
36 
37 #undef FN
38 #define FN(reg_name, field_name) \
39 	hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name
40 
hubp1_set_blank(struct hubp * hubp,bool blank)41 void hubp1_set_blank(struct hubp *hubp, bool blank)
42 {
43 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
44 	uint32_t blank_en = blank ? 1 : 0;
45 
46 	REG_UPDATE_2(DCHUBP_CNTL,
47 			HUBP_BLANK_EN, blank_en,
48 			HUBP_TTU_DISABLE, blank_en);
49 
50 	if (blank) {
51 		uint32_t reg_val = REG_READ(DCHUBP_CNTL);
52 
53 		if (reg_val) {
54 			/* init sequence workaround: in case HUBP is
55 			 * power gated, this wait would timeout.
56 			 *
57 			 * we just wrote reg_val to non-0, if it stay 0
58 			 * it means HUBP is gated
59 			 */
60 			REG_WAIT(DCHUBP_CNTL,
61 					HUBP_NO_OUTSTANDING_REQ, 1,
62 					1, 200);
63 		}
64 
65 		hubp->mpcc_id = 0xf;
66 		hubp->opp_id = OPP_ID_INVALID;
67 	}
68 }
69 
hubp1_disconnect(struct hubp * hubp)70 static void hubp1_disconnect(struct hubp *hubp)
71 {
72 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
73 
74 	REG_UPDATE(DCHUBP_CNTL,
75 			HUBP_TTU_DISABLE, 1);
76 
77 	REG_UPDATE(CURSOR_CONTROL,
78 			CURSOR_ENABLE, 0);
79 }
80 
hubp1_disable_control(struct hubp * hubp,bool disable_hubp)81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp)
82 {
83 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
84 	uint32_t disable = disable_hubp ? 1 : 0;
85 
86 	REG_UPDATE(DCHUBP_CNTL,
87 			HUBP_DISABLE, disable);
88 }
89 
hubp1_get_underflow_status(struct hubp * hubp)90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp)
91 {
92 	uint32_t hubp_underflow = 0;
93 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
94 
95 	REG_GET(DCHUBP_CNTL,
96 		HUBP_UNDERFLOW_STATUS,
97 		&hubp_underflow);
98 
99 	return hubp_underflow;
100 }
101 
102 
hubp1_clear_underflow(struct hubp * hubp)103 void hubp1_clear_underflow(struct hubp *hubp)
104 {
105 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
106 
107 	REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
108 }
109 
hubp1_set_hubp_blank_en(struct hubp * hubp,bool blank)110 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
111 {
112 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
113 	uint32_t blank_en = blank ? 1 : 0;
114 
115 	REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);
116 }
117 
hubp1_vready_workaround(struct hubp * hubp,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dest)118 void hubp1_vready_workaround(struct hubp *hubp,
119 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
120 {
121 	uint32_t value = 0;
122 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
123 
124 	/* set HBUBREQ_DEBUG_DB[12] = 1 */
125 	value = REG_READ(HUBPREQ_DEBUG_DB);
126 
127 	/* hack mode disable */
128 	value |= 0x100;
129 	value &= ~0x1000;
130 
131 	if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width
132 		+ pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
133 		/* if (eco_fix_needed(otg_global_sync_timing)
134 		 * set HBUBREQ_DEBUG_DB[12] = 1 */
135 		value |= 0x1000;
136 	}
137 
138 	REG_WRITE(HUBPREQ_DEBUG_DB, value);
139 }
140 
hubp1_program_tiling(struct hubp * hubp,const struct dc_tiling_info * info,const enum surface_pixel_format pixel_format)141 void hubp1_program_tiling(
142 	struct hubp *hubp,
143 	const struct dc_tiling_info *info,
144 	const enum surface_pixel_format pixel_format)
145 {
146 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
147 
148 	REG_UPDATE_6(DCSURF_ADDR_CONFIG,
149 			NUM_PIPES, log_2(info->gfx9.num_pipes),
150 			NUM_BANKS, log_2(info->gfx9.num_banks),
151 			PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
152 			NUM_SE, log_2(info->gfx9.num_shader_engines),
153 			NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
154 			MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
155 
156 	REG_UPDATE_4(DCSURF_TILING_CONFIG,
157 			SW_MODE, info->gfx9.swizzle,
158 			META_LINEAR, info->gfx9.meta_linear,
159 			RB_ALIGNED, info->gfx9.rb_aligned,
160 			PIPE_ALIGNED, info->gfx9.pipe_aligned);
161 }
162 
hubp1_program_size(struct hubp * hubp,enum surface_pixel_format format,const struct plane_size * plane_size,struct dc_plane_dcc_param * dcc)163 void hubp1_program_size(
164 	struct hubp *hubp,
165 	enum surface_pixel_format format,
166 	const struct plane_size *plane_size,
167 	struct dc_plane_dcc_param *dcc)
168 {
169 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
170 	uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
171 
172 	/* Program data and meta surface pitch (calculation from addrlib)
173 	 * 444 or 420 luma
174 	 */
175 	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) {
176 		ASSERT(plane_size->chroma_pitch != 0);
177 		/* Chroma pitch zero can cause system hang! */
178 
179 		pitch = plane_size->surface_pitch - 1;
180 		meta_pitch = dcc->meta_pitch - 1;
181 		pitch_c = plane_size->chroma_pitch - 1;
182 		meta_pitch_c = dcc->meta_pitch_c - 1;
183 	} else {
184 		pitch = plane_size->surface_pitch - 1;
185 		meta_pitch = dcc->meta_pitch - 1;
186 		pitch_c = 0;
187 		meta_pitch_c = 0;
188 	}
189 
190 	if (!dcc->enable) {
191 		meta_pitch = 0;
192 		meta_pitch_c = 0;
193 	}
194 
195 	REG_UPDATE_2(DCSURF_SURFACE_PITCH,
196 			PITCH, pitch, META_PITCH, meta_pitch);
197 
198 	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
199 		REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
200 			PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
201 }
202 
hubp1_program_rotation(struct hubp * hubp,enum dc_rotation_angle rotation,bool horizontal_mirror)203 void hubp1_program_rotation(
204 	struct hubp *hubp,
205 	enum dc_rotation_angle rotation,
206 	bool horizontal_mirror)
207 {
208 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
209 	uint32_t mirror;
210 
211 
212 	if (horizontal_mirror)
213 		mirror = 1;
214 	else
215 		mirror = 0;
216 
217 	/* Program rotation angle and horz mirror - no mirror */
218 	if (rotation == ROTATION_ANGLE_0)
219 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
220 				ROTATION_ANGLE, 0,
221 				H_MIRROR_EN, mirror);
222 	else if (rotation == ROTATION_ANGLE_90)
223 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
224 				ROTATION_ANGLE, 1,
225 				H_MIRROR_EN, mirror);
226 	else if (rotation == ROTATION_ANGLE_180)
227 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
228 				ROTATION_ANGLE, 2,
229 				H_MIRROR_EN, mirror);
230 	else if (rotation == ROTATION_ANGLE_270)
231 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
232 				ROTATION_ANGLE, 3,
233 				H_MIRROR_EN, mirror);
234 }
235 
hubp1_program_pixel_format(struct hubp * hubp,enum surface_pixel_format format)236 void hubp1_program_pixel_format(
237 	struct hubp *hubp,
238 	enum surface_pixel_format format)
239 {
240 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
241 	uint32_t red_bar = 3;
242 	uint32_t blue_bar = 2;
243 
244 	/* swap for ABGR format */
245 	if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
246 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
247 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
248 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
249 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
250 		red_bar = 2;
251 		blue_bar = 3;
252 	}
253 
254 	REG_UPDATE_2(HUBPRET_CONTROL,
255 			CROSSBAR_SRC_CB_B, blue_bar,
256 			CROSSBAR_SRC_CR_R, red_bar);
257 
258 	/* Mapping is same as ipp programming (cnvc) */
259 
260 	switch (format)	{
261 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
262 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
263 				SURFACE_PIXEL_FORMAT, 1);
264 		break;
265 	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
266 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
267 				SURFACE_PIXEL_FORMAT, 3);
268 		break;
269 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
270 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
271 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
272 				SURFACE_PIXEL_FORMAT, 8);
273 		break;
274 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
275 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
276 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
277 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
278 				SURFACE_PIXEL_FORMAT, 10);
279 		break;
280 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
281 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/
282 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
283 				SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
284 		break;
285 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
286 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
287 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
288 				SURFACE_PIXEL_FORMAT, 24);
289 		break;
290 
291 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
292 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
293 				SURFACE_PIXEL_FORMAT, 65);
294 		break;
295 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
296 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
297 				SURFACE_PIXEL_FORMAT, 64);
298 		break;
299 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
300 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
301 				SURFACE_PIXEL_FORMAT, 67);
302 		break;
303 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
304 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
305 				SURFACE_PIXEL_FORMAT, 66);
306 		break;
307 	case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
308 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
309 				SURFACE_PIXEL_FORMAT, 12);
310 		break;
311 	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
312 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
313 				SURFACE_PIXEL_FORMAT, 112);
314 		break;
315 	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
316 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
317 				SURFACE_PIXEL_FORMAT, 113);
318 		break;
319 	case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
320 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
321 				SURFACE_PIXEL_FORMAT, 114);
322 		break;
323 	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
324 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
325 				SURFACE_PIXEL_FORMAT, 118);
326 		break;
327 	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
328 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
329 				SURFACE_PIXEL_FORMAT, 119);
330 		break;
331 	case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
332 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
333 				SURFACE_PIXEL_FORMAT, 116,
334 				ALPHA_PLANE_EN, 0);
335 		break;
336 	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
337 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
338 				SURFACE_PIXEL_FORMAT, 116,
339 				ALPHA_PLANE_EN, 1);
340 		break;
341 	default:
342 		BREAK_TO_DEBUGGER();
343 		break;
344 	}
345 
346 	/* don't see the need of program the xbar in DCN 1.0 */
347 }
348 
hubp1_program_surface_flip_and_addr(struct hubp * hubp,const struct dc_plane_address * address,bool flip_immediate)349 bool hubp1_program_surface_flip_and_addr(
350 	struct hubp *hubp,
351 	const struct dc_plane_address *address,
352 	bool flip_immediate)
353 {
354 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
355 
356 
357 	//program flip type
358 	REG_UPDATE(DCSURF_FLIP_CONTROL,
359 			SURFACE_FLIP_TYPE, flip_immediate);
360 
361 
362 	if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {
363 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1);
364 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
365 
366 	} else {
367 		// turn off stereo if not in stereo
368 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
369 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
370 	}
371 
372 
373 
374 	/* HW automatically latch rest of address register on write to
375 	 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
376 	 *
377 	 * program high first and then the low addr, order matters!
378 	 */
379 	switch (address->type) {
380 	case PLN_ADDR_TYPE_GRAPHICS:
381 		/* DCN1.0 does not support const color
382 		 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
383 		 * base on address->grph.dcc_const_color
384 		 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
385 		 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
386 		 */
387 
388 		if (address->grph.addr.quad_part == 0)
389 			break;
390 
391 		REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
392 				PRIMARY_SURFACE_TMZ, address->tmz_surface,
393 				PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
394 
395 		if (address->grph.meta_addr.quad_part != 0) {
396 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
397 					PRIMARY_META_SURFACE_ADDRESS_HIGH,
398 					address->grph.meta_addr.high_part);
399 
400 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
401 					PRIMARY_META_SURFACE_ADDRESS,
402 					address->grph.meta_addr.low_part);
403 		}
404 
405 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
406 				PRIMARY_SURFACE_ADDRESS_HIGH,
407 				address->grph.addr.high_part);
408 
409 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
410 				PRIMARY_SURFACE_ADDRESS,
411 				address->grph.addr.low_part);
412 		break;
413 	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
414 		if (address->video_progressive.luma_addr.quad_part == 0
415 			|| address->video_progressive.chroma_addr.quad_part == 0)
416 			break;
417 
418 		REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
419 				PRIMARY_SURFACE_TMZ, address->tmz_surface,
420 				PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
421 				PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
422 				PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
423 
424 		if (address->video_progressive.luma_meta_addr.quad_part != 0) {
425 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
426 				PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
427 				address->video_progressive.chroma_meta_addr.high_part);
428 
429 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
430 				PRIMARY_META_SURFACE_ADDRESS_C,
431 				address->video_progressive.chroma_meta_addr.low_part);
432 
433 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
434 				PRIMARY_META_SURFACE_ADDRESS_HIGH,
435 				address->video_progressive.luma_meta_addr.high_part);
436 
437 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
438 				PRIMARY_META_SURFACE_ADDRESS,
439 				address->video_progressive.luma_meta_addr.low_part);
440 		}
441 
442 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
443 			PRIMARY_SURFACE_ADDRESS_HIGH_C,
444 			address->video_progressive.chroma_addr.high_part);
445 
446 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
447 			PRIMARY_SURFACE_ADDRESS_C,
448 			address->video_progressive.chroma_addr.low_part);
449 
450 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
451 			PRIMARY_SURFACE_ADDRESS_HIGH,
452 			address->video_progressive.luma_addr.high_part);
453 
454 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
455 			PRIMARY_SURFACE_ADDRESS,
456 			address->video_progressive.luma_addr.low_part);
457 		break;
458 	case PLN_ADDR_TYPE_GRPH_STEREO:
459 		if (address->grph_stereo.left_addr.quad_part == 0)
460 			break;
461 		if (address->grph_stereo.right_addr.quad_part == 0)
462 			break;
463 
464 		REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
465 				PRIMARY_SURFACE_TMZ, address->tmz_surface,
466 				PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
467 				PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
468 				PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
469 				SECONDARY_SURFACE_TMZ, address->tmz_surface,
470 				SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
471 				SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
472 				SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
473 
474 		if (address->grph_stereo.right_meta_addr.quad_part != 0) {
475 
476 			REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
477 					SECONDARY_META_SURFACE_ADDRESS_HIGH,
478 					address->grph_stereo.right_meta_addr.high_part);
479 
480 			REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
481 					SECONDARY_META_SURFACE_ADDRESS,
482 					address->grph_stereo.right_meta_addr.low_part);
483 		}
484 		if (address->grph_stereo.left_meta_addr.quad_part != 0) {
485 
486 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
487 					PRIMARY_META_SURFACE_ADDRESS_HIGH,
488 					address->grph_stereo.left_meta_addr.high_part);
489 
490 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
491 					PRIMARY_META_SURFACE_ADDRESS,
492 					address->grph_stereo.left_meta_addr.low_part);
493 		}
494 
495 		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
496 				SECONDARY_SURFACE_ADDRESS_HIGH,
497 				address->grph_stereo.right_addr.high_part);
498 
499 		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
500 				SECONDARY_SURFACE_ADDRESS,
501 				address->grph_stereo.right_addr.low_part);
502 
503 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
504 				PRIMARY_SURFACE_ADDRESS_HIGH,
505 				address->grph_stereo.left_addr.high_part);
506 
507 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
508 				PRIMARY_SURFACE_ADDRESS,
509 				address->grph_stereo.left_addr.low_part);
510 		break;
511 	default:
512 		BREAK_TO_DEBUGGER();
513 		break;
514 	}
515 
516 	hubp->request_address = *address;
517 
518 	return true;
519 }
520 
hubp1_clear_tiling(struct hubp * hubp)521 void hubp1_clear_tiling(struct hubp *hubp)
522 {
523 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
524 
525 	REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);
526 	REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);
527 
528 	REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
529 		     PRIMARY_SURFACE_DCC_EN, 0,
530 		     PRIMARY_SURFACE_DCC_IND_64B_BLK, 0,
531 		     SECONDARY_SURFACE_DCC_EN, 0,
532 		     SECONDARY_SURFACE_DCC_IND_64B_BLK, 0);
533 }
534 
hubp1_dcc_control(struct hubp * hubp,bool enable,enum hubp_ind_block_size independent_64b_blks)535 void hubp1_dcc_control(struct hubp *hubp, bool enable,
536 		enum hubp_ind_block_size independent_64b_blks)
537 {
538 	uint32_t dcc_en = enable ? 1 : 0;
539 	uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
540 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
541 
542 	REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
543 			PRIMARY_SURFACE_DCC_EN, dcc_en,
544 			PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
545 			SECONDARY_SURFACE_DCC_EN, dcc_en,
546 			SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
547 }
548 
hubp_reset(struct hubp * hubp)549 void hubp_reset(struct hubp *hubp)
550 {
551 	memset(&hubp->pos, 0, sizeof(hubp->pos));
552 	memset(&hubp->att, 0, sizeof(hubp->att));
553 }
554 
hubp1_program_surface_config(struct hubp * hubp,enum surface_pixel_format format,struct dc_tiling_info * tiling_info,struct plane_size * plane_size,enum dc_rotation_angle rotation,struct dc_plane_dcc_param * dcc,bool horizontal_mirror,unsigned int compat_level)555 void hubp1_program_surface_config(
556 	struct hubp *hubp,
557 	enum surface_pixel_format format,
558 	struct dc_tiling_info *tiling_info,
559 	struct plane_size *plane_size,
560 	enum dc_rotation_angle rotation,
561 	struct dc_plane_dcc_param *dcc,
562 	bool horizontal_mirror,
563 	unsigned int compat_level)
564 {
565 	hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
566 	hubp1_program_tiling(hubp, tiling_info, format);
567 	hubp1_program_size(hubp, format, plane_size, dcc);
568 	hubp1_program_rotation(hubp, rotation, horizontal_mirror);
569 	hubp1_program_pixel_format(hubp, format);
570 }
571 
hubp1_program_requestor(struct hubp * hubp,struct _vcs_dpi_display_rq_regs_st * rq_regs)572 void hubp1_program_requestor(
573 		struct hubp *hubp,
574 		struct _vcs_dpi_display_rq_regs_st *rq_regs)
575 {
576 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
577 
578 	REG_UPDATE(HUBPRET_CONTROL,
579 			DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
580 	REG_SET_4(DCN_EXPANSION_MODE, 0,
581 			DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
582 			PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
583 			MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
584 			CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
585 	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
586 		CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
587 		MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
588 		META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
589 		MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
590 		DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
591 		MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
592 		SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
593 		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
594 	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
595 		CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
596 		MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
597 		META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
598 		MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
599 		DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
600 		MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
601 		SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
602 		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
603 }
604 
605 
hubp1_program_deadline(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr)606 void hubp1_program_deadline(
607 		struct hubp *hubp,
608 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
609 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
610 {
611 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
612 
613 	/* DLG - Per hubp */
614 	REG_SET_2(BLANK_OFFSET_0, 0,
615 		REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
616 		DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
617 
618 	REG_SET(BLANK_OFFSET_1, 0,
619 		MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
620 
621 	REG_SET(DST_DIMENSIONS, 0,
622 		REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
623 
624 	REG_SET_2(DST_AFTER_SCALER, 0,
625 		REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
626 		DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
627 
628 	REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
629 		REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
630 
631 	/* DLG - Per luma/chroma */
632 	REG_SET(VBLANK_PARAMETERS_1, 0,
633 		REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
634 
635 	if (REG(NOM_PARAMETERS_0))
636 		REG_SET(NOM_PARAMETERS_0, 0,
637 			DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
638 
639 	if (REG(NOM_PARAMETERS_1))
640 		REG_SET(NOM_PARAMETERS_1, 0,
641 			REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
642 
643 	REG_SET(NOM_PARAMETERS_4, 0,
644 		DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
645 
646 	REG_SET(NOM_PARAMETERS_5, 0,
647 		REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
648 
649 	REG_SET_2(PER_LINE_DELIVERY, 0,
650 		REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
651 		REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
652 
653 	REG_SET(VBLANK_PARAMETERS_2, 0,
654 		REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
655 
656 	if (REG(NOM_PARAMETERS_2))
657 		REG_SET(NOM_PARAMETERS_2, 0,
658 			DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
659 
660 	if (REG(NOM_PARAMETERS_3))
661 		REG_SET(NOM_PARAMETERS_3, 0,
662 			REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
663 
664 	REG_SET(NOM_PARAMETERS_6, 0,
665 		DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
666 
667 	REG_SET(NOM_PARAMETERS_7, 0,
668 		REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
669 
670 	/* TTU - per hubp */
671 	REG_SET_2(DCN_TTU_QOS_WM, 0,
672 		QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
673 		QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
674 
675 	/* TTU - per luma/chroma */
676 	/* Assumed surf0 is luma and 1 is chroma */
677 
678 	REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
679 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
680 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
681 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
682 
683 	REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
684 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
685 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
686 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
687 
688 	REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
689 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
690 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
691 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
692 }
693 
hubp1_setup(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr,struct _vcs_dpi_display_rq_regs_st * rq_regs,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dest)694 static void hubp1_setup(
695 		struct hubp *hubp,
696 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
697 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
698 		struct _vcs_dpi_display_rq_regs_st *rq_regs,
699 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
700 {
701 	/* otg is locked when this func is called. Register are double buffered.
702 	 * disable the requestors is not needed
703 	 */
704 	hubp1_program_requestor(hubp, rq_regs);
705 	hubp1_program_deadline(hubp, dlg_attr, ttu_attr);
706 	hubp1_vready_workaround(hubp, pipe_dest);
707 }
708 
hubp1_setup_interdependent(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr)709 static void hubp1_setup_interdependent(
710 		struct hubp *hubp,
711 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
712 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
713 {
714 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
715 
716 	REG_SET_2(PREFETCH_SETTINS, 0,
717 		DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
718 		VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
719 
720 	REG_SET(PREFETCH_SETTINS_C, 0,
721 		VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
722 
723 	REG_SET_2(VBLANK_PARAMETERS_0, 0,
724 		DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
725 		DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
726 
727 	REG_SET(VBLANK_PARAMETERS_3, 0,
728 		REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
729 
730 	REG_SET(VBLANK_PARAMETERS_4, 0,
731 		REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
732 
733 	REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
734 		REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
735 		REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
736 
737 	REG_SET(DCN_SURF0_TTU_CNTL1, 0,
738 		REFCYC_PER_REQ_DELIVERY_PRE,
739 		ttu_attr->refcyc_per_req_delivery_pre_l);
740 	REG_SET(DCN_SURF1_TTU_CNTL1, 0,
741 		REFCYC_PER_REQ_DELIVERY_PRE,
742 		ttu_attr->refcyc_per_req_delivery_pre_c);
743 	REG_SET(DCN_CUR0_TTU_CNTL1, 0,
744 		REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
745 
746 	REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
747 		MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
748 		QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
749 }
750 
hubp1_is_flip_pending(struct hubp * hubp)751 bool hubp1_is_flip_pending(struct hubp *hubp)
752 {
753 	uint32_t flip_pending = 0;
754 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
755 	struct dc_plane_address earliest_inuse_address;
756 
757 	if (hubp && hubp->power_gated)
758 		return false;
759 
760 	REG_GET(DCSURF_FLIP_CONTROL,
761 			SURFACE_FLIP_PENDING, &flip_pending);
762 
763 	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
764 			SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
765 
766 	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
767 			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
768 
769 	if (flip_pending)
770 		return true;
771 
772 	if (hubp &&
773 	    earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
774 		return true;
775 
776 	return false;
777 }
778 
779 static uint32_t aperture_default_system = 1;
780 static uint32_t context0_default_system; /* = 0;*/
781 
hubp1_set_vm_system_aperture_settings(struct hubp * hubp,struct vm_system_aperture_param * apt)782 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp,
783 		struct vm_system_aperture_param *apt)
784 {
785 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
786 	PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
787 	PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
788 	PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
789 
790 	mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
791 	mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12;
792 	mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12;
793 
794 	REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0,
795 		MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */
796 		MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
797 	REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
798 		MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
799 
800 	REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0,
801 			MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part);
802 	REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0,
803 			MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part);
804 
805 	REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0,
806 			MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part);
807 	REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0,
808 			MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part);
809 }
810 
hubp1_set_vm_context0_settings(struct hubp * hubp,const struct vm_context0_param * vm0)811 static void hubp1_set_vm_context0_settings(struct hubp *hubp,
812 		const struct vm_context0_param *vm0)
813 {
814 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
815 	/* pte base */
816 	REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0,
817 			VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part);
818 	REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0,
819 			VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part);
820 
821 	/* pte start */
822 	REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0,
823 			VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part);
824 	REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0,
825 			VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part);
826 
827 	/* pte end */
828 	REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0,
829 			VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part);
830 	REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0,
831 			VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part);
832 
833 	/* fault handling */
834 	REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
835 			VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part,
836 			VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system);
837 	REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
838 			VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part);
839 
840 	/* control: enable VM PTE*/
841 	REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
842 			ENABLE_L1_TLB, 1,
843 			SYSTEM_ACCESS_MODE, 3);
844 }
845 
min_set_viewport(struct hubp * hubp,const struct rect * viewport,const struct rect * viewport_c)846 void min_set_viewport(
847 	struct hubp *hubp,
848 	const struct rect *viewport,
849 	const struct rect *viewport_c)
850 {
851 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
852 
853 	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
854 		  PRI_VIEWPORT_WIDTH, viewport->width,
855 		  PRI_VIEWPORT_HEIGHT, viewport->height);
856 
857 	REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
858 		  PRI_VIEWPORT_X_START, viewport->x,
859 		  PRI_VIEWPORT_Y_START, viewport->y);
860 
861 	/*for stereo*/
862 	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
863 		  SEC_VIEWPORT_WIDTH, viewport->width,
864 		  SEC_VIEWPORT_HEIGHT, viewport->height);
865 
866 	REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
867 		  SEC_VIEWPORT_X_START, viewport->x,
868 		  SEC_VIEWPORT_Y_START, viewport->y);
869 
870 	/* DC supports NV12 only at the moment */
871 	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
872 		  PRI_VIEWPORT_WIDTH_C, viewport_c->width,
873 		  PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
874 
875 	REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
876 		  PRI_VIEWPORT_X_START_C, viewport_c->x,
877 		  PRI_VIEWPORT_Y_START_C, viewport_c->y);
878 
879 	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
880 		  SEC_VIEWPORT_WIDTH_C, viewport_c->width,
881 		  SEC_VIEWPORT_HEIGHT_C, viewport_c->height);
882 
883 	REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
884 		  SEC_VIEWPORT_X_START_C, viewport_c->x,
885 		  SEC_VIEWPORT_Y_START_C, viewport_c->y);
886 }
887 
hubp1_read_state_common(struct hubp * hubp)888 void hubp1_read_state_common(struct hubp *hubp)
889 {
890 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
891 	struct dcn_hubp_state *s = &hubp1->state;
892 	struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
893 	struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
894 	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
895 	uint32_t aperture_low_msb, aperture_low_lsb;
896 	uint32_t aperture_high_msb, aperture_high_lsb;
897 
898 	/* Requester */
899 	REG_GET(HUBPRET_CONTROL,
900 			DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
901 	REG_GET_4(DCN_EXPANSION_MODE,
902 			DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
903 			PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
904 			MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
905 			CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
906 
907 	REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB,
908 			MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, &aperture_low_msb);
909 
910 	REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB,
911 			MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, &aperture_low_lsb);
912 
913 	REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB,
914 			MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, &aperture_high_msb);
915 
916 	REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB,
917 			MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, &aperture_high_lsb);
918 
919 	// On DCN1, aperture is broken down into MSB and LSB; only keep bits [47:18] to match later DCN format
920 	rq_regs->aperture_low_addr = (aperture_low_msb << 26) | (aperture_low_lsb >> 6);
921 	rq_regs->aperture_high_addr = (aperture_high_msb << 26) | (aperture_high_lsb >> 6);
922 
923 	/* DLG - Per hubp */
924 	REG_GET_2(BLANK_OFFSET_0,
925 		REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
926 		DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
927 
928 	REG_GET(BLANK_OFFSET_1,
929 		MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
930 
931 	REG_GET(DST_DIMENSIONS,
932 		REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
933 
934 	REG_GET_2(DST_AFTER_SCALER,
935 		REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
936 		DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
937 
938 	if (REG(PREFETCH_SETTINS))
939 		REG_GET_2(PREFETCH_SETTINS,
940 			DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
941 			VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
942 	else
943 		REG_GET_2(PREFETCH_SETTINGS,
944 			DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
945 			VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
946 
947 	REG_GET_2(VBLANK_PARAMETERS_0,
948 		DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
949 		DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
950 
951 	REG_GET(REF_FREQ_TO_PIX_FREQ,
952 		REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
953 
954 	/* DLG - Per luma/chroma */
955 	REG_GET(VBLANK_PARAMETERS_1,
956 		REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
957 
958 	REG_GET(VBLANK_PARAMETERS_3,
959 		REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
960 
961 	if (REG(NOM_PARAMETERS_0))
962 		REG_GET(NOM_PARAMETERS_0,
963 			DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
964 
965 	if (REG(NOM_PARAMETERS_1))
966 		REG_GET(NOM_PARAMETERS_1,
967 			REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
968 
969 	REG_GET(NOM_PARAMETERS_4,
970 		DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
971 
972 	REG_GET(NOM_PARAMETERS_5,
973 		REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
974 
975 	REG_GET_2(PER_LINE_DELIVERY_PRE,
976 		REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
977 		REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
978 
979 	REG_GET_2(PER_LINE_DELIVERY,
980 		REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
981 		REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
982 
983 	if (REG(PREFETCH_SETTINS_C))
984 		REG_GET(PREFETCH_SETTINS_C,
985 			VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
986 	else
987 		REG_GET(PREFETCH_SETTINGS_C,
988 			VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
989 
990 	REG_GET(VBLANK_PARAMETERS_2,
991 		REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
992 
993 	REG_GET(VBLANK_PARAMETERS_4,
994 		REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
995 
996 	if (REG(NOM_PARAMETERS_2))
997 		REG_GET(NOM_PARAMETERS_2,
998 			DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
999 
1000 	if (REG(NOM_PARAMETERS_3))
1001 		REG_GET(NOM_PARAMETERS_3,
1002 			REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
1003 
1004 	REG_GET(NOM_PARAMETERS_6,
1005 		DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
1006 
1007 	REG_GET(NOM_PARAMETERS_7,
1008 		REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
1009 
1010 	/* TTU - per hubp */
1011 	REG_GET_2(DCN_TTU_QOS_WM,
1012 		QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
1013 		QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
1014 
1015 	REG_GET_2(DCN_GLOBAL_TTU_CNTL,
1016 		MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
1017 		QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
1018 
1019 	/* TTU - per luma/chroma */
1020 	/* Assumed surf0 is luma and 1 is chroma */
1021 
1022 	REG_GET_3(DCN_SURF0_TTU_CNTL0,
1023 		REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
1024 		QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
1025 		QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
1026 
1027 	REG_GET(DCN_SURF0_TTU_CNTL1,
1028 		REFCYC_PER_REQ_DELIVERY_PRE,
1029 		&ttu_attr->refcyc_per_req_delivery_pre_l);
1030 
1031 	REG_GET_3(DCN_SURF1_TTU_CNTL0,
1032 		REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
1033 		QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
1034 		QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
1035 
1036 	REG_GET(DCN_SURF1_TTU_CNTL1,
1037 		REFCYC_PER_REQ_DELIVERY_PRE,
1038 		&ttu_attr->refcyc_per_req_delivery_pre_c);
1039 
1040 	/* Rest of hubp */
1041 	REG_GET(DCSURF_SURFACE_CONFIG,
1042 			SURFACE_PIXEL_FORMAT, &s->pixel_format);
1043 
1044 	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
1045 			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
1046 
1047 	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
1048 			SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
1049 
1050 	REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
1051 			PRI_VIEWPORT_WIDTH, &s->viewport_width,
1052 			PRI_VIEWPORT_HEIGHT, &s->viewport_height);
1053 
1054 	REG_GET_2(DCSURF_SURFACE_CONFIG,
1055 			ROTATION_ANGLE, &s->rotation_angle,
1056 			H_MIRROR_EN, &s->h_mirror_en);
1057 
1058 	REG_GET(DCSURF_TILING_CONFIG,
1059 			SW_MODE, &s->sw_mode);
1060 
1061 	REG_GET(DCSURF_SURFACE_CONTROL,
1062 			PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
1063 
1064 	REG_GET_3(DCHUBP_CNTL,
1065 			HUBP_BLANK_EN, &s->blank_en,
1066 			HUBP_TTU_DISABLE, &s->ttu_disable,
1067 			HUBP_UNDERFLOW_STATUS, &s->underflow_status);
1068 
1069 	REG_GET(HUBP_CLK_CNTL,
1070 			HUBP_CLOCK_ENABLE, &s->clock_en);
1071 
1072 	REG_GET(DCN_GLOBAL_TTU_CNTL,
1073 			MIN_TTU_VBLANK, &s->min_ttu_vblank);
1074 
1075 	REG_GET_2(DCN_TTU_QOS_WM,
1076 			QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
1077 			QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
1078 
1079 	REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
1080 			PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo);
1081 
1082 	REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
1083 			PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi);
1084 
1085 	REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
1086 			PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo);
1087 
1088 	REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
1089 			PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi);
1090 }
1091 
hubp1_read_state(struct hubp * hubp)1092 void hubp1_read_state(struct hubp *hubp)
1093 {
1094 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1095 	struct dcn_hubp_state *s = &hubp1->state;
1096 	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1097 
1098 	hubp1_read_state_common(hubp);
1099 
1100 	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1101 		CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1102 		MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
1103 		META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
1104 		MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
1105 		DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
1106 		MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
1107 		SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
1108 		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
1109 
1110 	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1111 		CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
1112 		MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
1113 		META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
1114 		MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
1115 		DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
1116 		MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
1117 		SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
1118 		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
1119 
1120 }
hubp1_get_cursor_pitch(unsigned int pitch)1121 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch)
1122 {
1123 	enum cursor_pitch hw_pitch;
1124 
1125 	switch (pitch) {
1126 	case 64:
1127 		hw_pitch = CURSOR_PITCH_64_PIXELS;
1128 		break;
1129 	case 128:
1130 		hw_pitch = CURSOR_PITCH_128_PIXELS;
1131 		break;
1132 	case 256:
1133 		hw_pitch = CURSOR_PITCH_256_PIXELS;
1134 		break;
1135 	default:
1136 		DC_ERR("Invalid cursor pitch of %d. "
1137 				"Only 64/128/256 is supported on DCN.\n", pitch);
1138 		hw_pitch = CURSOR_PITCH_64_PIXELS;
1139 		break;
1140 	}
1141 	return hw_pitch;
1142 }
1143 
hubp1_get_lines_per_chunk(unsigned int cur_width,enum dc_cursor_color_format format)1144 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk(
1145 		unsigned int cur_width,
1146 		enum dc_cursor_color_format format)
1147 {
1148 	enum cursor_lines_per_chunk line_per_chunk;
1149 
1150 	if (format == CURSOR_MODE_MONO)
1151 		/* impl B. expansion in CUR Buffer reader */
1152 		line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
1153 	else if (cur_width <= 32)
1154 		line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
1155 	else if (cur_width <= 64)
1156 		line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
1157 	else if (cur_width <= 128)
1158 		line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
1159 	else
1160 		line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
1161 
1162 	return line_per_chunk;
1163 }
1164 
hubp1_cursor_set_attributes(struct hubp * hubp,const struct dc_cursor_attributes * attr)1165 void hubp1_cursor_set_attributes(
1166 		struct hubp *hubp,
1167 		const struct dc_cursor_attributes *attr)
1168 {
1169 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1170 	enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
1171 	enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk(
1172 			attr->width, attr->color_format);
1173 
1174 	hubp->curs_attr = *attr;
1175 
1176 	REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
1177 			CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
1178 	REG_UPDATE(CURSOR_SURFACE_ADDRESS,
1179 			CURSOR_SURFACE_ADDRESS, attr->address.low_part);
1180 
1181 	REG_UPDATE_2(CURSOR_SIZE,
1182 			CURSOR_WIDTH, attr->width,
1183 			CURSOR_HEIGHT, attr->height);
1184 
1185 	REG_UPDATE_3(CURSOR_CONTROL,
1186 			CURSOR_MODE, attr->color_format,
1187 			CURSOR_PITCH, hw_pitch,
1188 			CURSOR_LINES_PER_CHUNK, lpc);
1189 
1190 	REG_SET_2(CURSOR_SETTINS, 0,
1191 			/* no shift of the cursor HDL schedule */
1192 			CURSOR0_DST_Y_OFFSET, 0,
1193 			 /* used to shift the cursor chunk request deadline */
1194 			CURSOR0_CHUNK_HDL_ADJUST, 3);
1195 }
1196 
hubp1_cursor_set_position(struct hubp * hubp,const struct dc_cursor_position * pos,const struct dc_cursor_mi_param * param)1197 void hubp1_cursor_set_position(
1198 		struct hubp *hubp,
1199 		const struct dc_cursor_position *pos,
1200 		const struct dc_cursor_mi_param *param)
1201 {
1202 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1203 	int x_pos = pos->x - param->viewport.x;
1204 	int y_pos = pos->y - param->viewport.y;
1205 	int x_hotspot = pos->x_hotspot;
1206 	int y_hotspot = pos->y_hotspot;
1207 	int src_x_offset = x_pos - pos->x_hotspot;
1208 	int src_y_offset = y_pos - pos->y_hotspot;
1209 	int cursor_height = (int)hubp->curs_attr.height;
1210 	int cursor_width = (int)hubp->curs_attr.width;
1211 	uint32_t dst_x_offset;
1212 	uint32_t cur_en = pos->enable ? 1 : 0;
1213 
1214 	hubp->curs_pos = *pos;
1215 
1216 	/*
1217 	 * Guard aganst cursor_set_position() from being called with invalid
1218 	 * attributes
1219 	 *
1220 	 * TODO: Look at combining cursor_set_position() and
1221 	 * cursor_set_attributes() into cursor_update()
1222 	 */
1223 	if (hubp->curs_attr.address.quad_part == 0)
1224 		return;
1225 
1226 	// Transform cursor width / height and hotspots for offset calculations
1227 	if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
1228 		swap(cursor_height, cursor_width);
1229 		swap(x_hotspot, y_hotspot);
1230 
1231 		if (param->rotation == ROTATION_ANGLE_90) {
1232 			// hotspot = (-y, x)
1233 			src_x_offset = x_pos - (cursor_width - x_hotspot);
1234 			src_y_offset = y_pos - y_hotspot;
1235 		} else if (param->rotation == ROTATION_ANGLE_270) {
1236 			// hotspot = (y, -x)
1237 			src_x_offset = x_pos - x_hotspot;
1238 			src_y_offset = y_pos - (cursor_height - y_hotspot);
1239 		}
1240 	} else if (param->rotation == ROTATION_ANGLE_180) {
1241 		// hotspot = (-x, -y)
1242 		if (!param->mirror)
1243 			src_x_offset = x_pos - (cursor_width - x_hotspot);
1244 
1245 		src_y_offset = y_pos - (cursor_height - y_hotspot);
1246 	}
1247 
1248 	dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
1249 	dst_x_offset *= param->ref_clk_khz;
1250 	dst_x_offset /= param->pixel_clk_khz;
1251 
1252 	ASSERT(param->h_scale_ratio.value);
1253 
1254 	if (param->h_scale_ratio.value)
1255 		dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
1256 				dc_fixpt_from_int(dst_x_offset),
1257 				param->h_scale_ratio));
1258 
1259 	if (src_x_offset >= (int)param->viewport.width)
1260 		cur_en = 0;  /* not visible beyond right edge*/
1261 
1262 	if (src_x_offset + cursor_width <= 0)
1263 		cur_en = 0;  /* not visible beyond left edge*/
1264 
1265 	if (src_y_offset >= (int)param->viewport.height)
1266 		cur_en = 0;  /* not visible beyond bottom edge*/
1267 
1268 	if (src_y_offset + cursor_height <= 0)
1269 		cur_en = 0;  /* not visible beyond top edge*/
1270 
1271 	if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
1272 		hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
1273 
1274 	REG_UPDATE(CURSOR_CONTROL,
1275 			CURSOR_ENABLE, cur_en);
1276 
1277 	REG_SET_2(CURSOR_POSITION, 0,
1278 			CURSOR_X_POSITION, pos->x,
1279 			CURSOR_Y_POSITION, pos->y);
1280 
1281 	REG_SET_2(CURSOR_HOT_SPOT, 0,
1282 			CURSOR_HOT_SPOT_X, pos->x_hotspot,
1283 			CURSOR_HOT_SPOT_Y, pos->y_hotspot);
1284 
1285 	REG_SET(CURSOR_DST_OFFSET, 0,
1286 			CURSOR_DST_X_OFFSET, dst_x_offset);
1287 	/* TODO Handle surface pixel formats other than 4:4:4 */
1288 }
1289 
1290 /**
1291  * hubp1_clk_cntl - Disable or enable clocks for DCHUBP
1292  *
1293  * @hubp: hubp struct reference.
1294  * @enable: Set true for enabling gate clock.
1295  *
1296  * When enabling/disabling DCHUBP clock, we affect dcfclk/dppclk.
1297  */
hubp1_clk_cntl(struct hubp * hubp,bool enable)1298 void hubp1_clk_cntl(struct hubp *hubp, bool enable)
1299 {
1300 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1301 	uint32_t clk_enable = enable ? 1 : 0;
1302 
1303 	REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
1304 }
1305 
hubp1_vtg_sel(struct hubp * hubp,uint32_t otg_inst)1306 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
1307 {
1308 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1309 
1310 	REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
1311 }
1312 
hubp1_in_blank(struct hubp * hubp)1313 bool hubp1_in_blank(struct hubp *hubp)
1314 {
1315 	uint32_t in_blank;
1316 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1317 
1318 	REG_GET(DCHUBP_CNTL, HUBP_IN_BLANK, &in_blank);
1319 	return in_blank ? true : false;
1320 }
1321 
hubp1_soft_reset(struct hubp * hubp,bool reset)1322 void hubp1_soft_reset(struct hubp *hubp, bool reset)
1323 {
1324 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1325 
1326 	REG_UPDATE(DCHUBP_CNTL, HUBP_DISABLE, reset ? 1 : 0);
1327 }
1328 
1329 /**
1330  * hubp1_set_flip_int - Enable surface flip interrupt
1331  *
1332  * @hubp: hubp struct reference.
1333  */
hubp1_set_flip_int(struct hubp * hubp)1334 void hubp1_set_flip_int(struct hubp *hubp)
1335 {
1336 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1337 
1338 	REG_UPDATE(DCSURF_SURFACE_FLIP_INTERRUPT,
1339 		SURFACE_FLIP_INT_MASK, 1);
1340 
1341 	return;
1342 }
1343 
1344 /**
1345  * hubp1_wait_pipe_read_start - wait for hubp ret path starting read.
1346  *
1347  * @hubp: hubp struct reference.
1348  */
hubp1_wait_pipe_read_start(struct hubp * hubp)1349 static void hubp1_wait_pipe_read_start(struct hubp *hubp)
1350 {
1351 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1352 
1353 	REG_WAIT(HUBPRET_READ_LINE_STATUS,
1354 		PIPE_READ_VBLANK, 0,
1355 		 1, 1000);
1356 }
1357 
hubp1_init(struct hubp * hubp)1358 void hubp1_init(struct hubp *hubp)
1359 {
1360 	hubp_reset(hubp);
1361 }
1362 
1363 static const struct hubp_funcs dcn10_hubp_funcs = {
1364 	.hubp_program_surface_flip_and_addr =
1365 			hubp1_program_surface_flip_and_addr,
1366 	.hubp_program_surface_config =
1367 			hubp1_program_surface_config,
1368 	.hubp_is_flip_pending = hubp1_is_flip_pending,
1369 	.hubp_setup = hubp1_setup,
1370 	.hubp_setup_interdependent = hubp1_setup_interdependent,
1371 	.hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings,
1372 	.hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings,
1373 	.set_blank = hubp1_set_blank,
1374 	.dcc_control = hubp1_dcc_control,
1375 	.hubp_reset = hubp_reset,
1376 	.mem_program_viewport = min_set_viewport,
1377 	.set_hubp_blank_en = hubp1_set_hubp_blank_en,
1378 	.set_cursor_attributes	= hubp1_cursor_set_attributes,
1379 	.set_cursor_position	= hubp1_cursor_set_position,
1380 	.hubp_disconnect = hubp1_disconnect,
1381 	.hubp_clk_cntl = hubp1_clk_cntl,
1382 	.hubp_vtg_sel = hubp1_vtg_sel,
1383 	.hubp_read_state = hubp1_read_state,
1384 	.hubp_clear_underflow = hubp1_clear_underflow,
1385 	.hubp_disable_control =  hubp1_disable_control,
1386 	.hubp_get_underflow_status = hubp1_get_underflow_status,
1387 	.hubp_init = hubp1_init,
1388 	.hubp_clear_tiling = hubp1_clear_tiling,
1389 
1390 	.dmdata_set_attributes = NULL,
1391 	.dmdata_load = NULL,
1392 	.hubp_soft_reset = hubp1_soft_reset,
1393 	.hubp_in_blank = hubp1_in_blank,
1394 	.hubp_set_flip_int = hubp1_set_flip_int,
1395 	.hubp_wait_pipe_read_start = hubp1_wait_pipe_read_start,
1396 };
1397 
1398 /*****************************************/
1399 /* Constructor, Destructor               */
1400 /*****************************************/
1401 
dcn10_hubp_construct(struct dcn10_hubp * hubp1,struct dc_context * ctx,uint32_t inst,const struct dcn_mi_registers * hubp_regs,const struct dcn_mi_shift * hubp_shift,const struct dcn_mi_mask * hubp_mask)1402 void dcn10_hubp_construct(
1403 	struct dcn10_hubp *hubp1,
1404 	struct dc_context *ctx,
1405 	uint32_t inst,
1406 	const struct dcn_mi_registers *hubp_regs,
1407 	const struct dcn_mi_shift *hubp_shift,
1408 	const struct dcn_mi_mask *hubp_mask)
1409 {
1410 	hubp1->base.funcs = &dcn10_hubp_funcs;
1411 	hubp1->base.ctx = ctx;
1412 	hubp1->hubp_regs = hubp_regs;
1413 	hubp1->hubp_shift = hubp_shift;
1414 	hubp1->hubp_mask = hubp_mask;
1415 	hubp1->base.inst = inst;
1416 	hubp1->base.opp_id = OPP_ID_INVALID;
1417 	hubp1->base.mpcc_id = 0xf;
1418 }
1419 
1420 
1421