1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 6 */ 7 8 #include <linux/export.h> 9 #include <linux/etherdevice.h> 10 #include "htt.h" 11 #include "mac.h" 12 #include "hif.h" 13 #include "txrx.h" 14 #include "debug.h" 15 16 static u8 ath10k_htt_tx_txq_calc_size(size_t count) 17 { 18 int exp; 19 int factor; 20 21 exp = 0; 22 factor = count >> 7; 23 24 while (factor >= 64 && exp < 4) { 25 factor >>= 3; 26 exp++; 27 } 28 29 if (exp == 4) 30 return 0xff; 31 32 if (count > 0) 33 factor = max(1, factor); 34 35 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) | 36 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR); 37 } 38 39 static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 40 struct ieee80211_txq *txq) 41 { 42 struct ath10k *ar = hw->priv; 43 struct ath10k_sta *arsta; 44 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv; 45 unsigned long byte_cnt; 46 int idx; 47 u32 bit; 48 u16 peer_id; 49 u8 tid; 50 u8 count; 51 52 lockdep_assert_held(&ar->htt.tx_lock); 53 54 if (!ar->htt.tx_q_state.enabled) 55 return; 56 57 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 58 return; 59 60 if (txq->sta) { 61 arsta = (void *)txq->sta->drv_priv; 62 peer_id = arsta->peer_id; 63 } else { 64 peer_id = arvif->peer_id; 65 } 66 67 tid = txq->tid; 68 bit = BIT(peer_id % 32); 69 idx = peer_id / 32; 70 71 ieee80211_txq_get_depth(txq, NULL, &byte_cnt); 72 count = ath10k_htt_tx_txq_calc_size(byte_cnt); 73 74 if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) || 75 unlikely(tid >= ar->htt.tx_q_state.num_tids)) { 76 ath10k_warn(ar, "refusing to update txq for peer_id %u tid %u due to out of bounds\n", 77 peer_id, tid); 78 return; 79 } 80 81 ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count; 82 ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit; 83 ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0; 84 85 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %u tid %u count %u\n", 86 peer_id, tid, count); 87 } 88 89 static void __ath10k_htt_tx_txq_sync(struct ath10k *ar) 90 { 91 u32 seq; 92 size_t size; 93 94 lockdep_assert_held(&ar->htt.tx_lock); 95 96 if (!ar->htt.tx_q_state.enabled) 97 return; 98 99 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 100 return; 101 102 seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq); 103 seq++; 104 ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq); 105 106 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n", 107 seq); 108 109 size = sizeof(*ar->htt.tx_q_state.vaddr); 110 dma_sync_single_for_device(ar->dev, 111 ar->htt.tx_q_state.paddr, 112 size, 113 DMA_TO_DEVICE); 114 } 115 116 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 117 struct ieee80211_txq *txq) 118 { 119 struct ath10k *ar = hw->priv; 120 121 spin_lock_bh(&ar->htt.tx_lock); 122 __ath10k_htt_tx_txq_recalc(hw, txq); 123 spin_unlock_bh(&ar->htt.tx_lock); 124 } 125 126 void ath10k_htt_tx_txq_sync(struct ath10k *ar) 127 { 128 spin_lock_bh(&ar->htt.tx_lock); 129 __ath10k_htt_tx_txq_sync(ar); 130 spin_unlock_bh(&ar->htt.tx_lock); 131 } 132 133 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 134 struct ieee80211_txq *txq) 135 { 136 struct ath10k *ar = hw->priv; 137 138 spin_lock_bh(&ar->htt.tx_lock); 139 __ath10k_htt_tx_txq_recalc(hw, txq); 140 __ath10k_htt_tx_txq_sync(ar); 141 spin_unlock_bh(&ar->htt.tx_lock); 142 } 143 144 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt) 145 { 146 lockdep_assert_held(&htt->tx_lock); 147 148 htt->num_pending_tx--; 149 if (htt->num_pending_tx == htt->max_num_pending_tx - 1) 150 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 151 152 if (htt->num_pending_tx == 0) 153 wake_up(&htt->empty_tx_wq); 154 } 155 156 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt) 157 { 158 lockdep_assert_held(&htt->tx_lock); 159 160 if (htt->num_pending_tx >= htt->max_num_pending_tx) 161 return -EBUSY; 162 163 htt->num_pending_tx++; 164 if (htt->num_pending_tx == htt->max_num_pending_tx) 165 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 166 167 return 0; 168 } 169 170 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 171 bool is_presp) 172 { 173 struct ath10k *ar = htt->ar; 174 175 lockdep_assert_held(&htt->tx_lock); 176 177 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres) 178 return 0; 179 180 if (is_presp && 181 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx) 182 return -EBUSY; 183 184 htt->num_pending_mgmt_tx++; 185 186 return 0; 187 } 188 189 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt) 190 { 191 lockdep_assert_held(&htt->tx_lock); 192 193 if (!htt->ar->hw_params.max_probe_resp_desc_thres) 194 return; 195 196 htt->num_pending_mgmt_tx--; 197 } 198 199 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb) 200 { 201 struct ath10k *ar = htt->ar; 202 int ret; 203 204 spin_lock_bh(&htt->tx_lock); 205 ret = idr_alloc(&htt->pending_tx, skb, 0, 206 htt->max_num_pending_tx, GFP_ATOMIC); 207 spin_unlock_bh(&htt->tx_lock); 208 209 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret); 210 211 return ret; 212 } 213 214 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id) 215 { 216 struct ath10k *ar = htt->ar; 217 218 lockdep_assert_held(&htt->tx_lock); 219 220 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %u\n", msdu_id); 221 222 idr_remove(&htt->pending_tx, msdu_id); 223 } 224 225 static void ath10k_htt_tx_free_cont_txbuf_32(struct ath10k_htt *htt) 226 { 227 struct ath10k *ar = htt->ar; 228 size_t size; 229 230 if (!htt->txbuf.vaddr_txbuff_32) 231 return; 232 233 size = htt->txbuf.size; 234 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_32, 235 htt->txbuf.paddr); 236 htt->txbuf.vaddr_txbuff_32 = NULL; 237 } 238 239 static int ath10k_htt_tx_alloc_cont_txbuf_32(struct ath10k_htt *htt) 240 { 241 struct ath10k *ar = htt->ar; 242 size_t size; 243 244 size = htt->max_num_pending_tx * 245 sizeof(struct ath10k_htt_txbuf_32); 246 247 htt->txbuf.vaddr_txbuff_32 = dma_alloc_coherent(ar->dev, size, 248 &htt->txbuf.paddr, 249 GFP_KERNEL); 250 if (!htt->txbuf.vaddr_txbuff_32) 251 return -ENOMEM; 252 253 htt->txbuf.size = size; 254 255 return 0; 256 } 257 258 static void ath10k_htt_tx_free_cont_txbuf_64(struct ath10k_htt *htt) 259 { 260 struct ath10k *ar = htt->ar; 261 size_t size; 262 263 if (!htt->txbuf.vaddr_txbuff_64) 264 return; 265 266 size = htt->txbuf.size; 267 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_64, 268 htt->txbuf.paddr); 269 htt->txbuf.vaddr_txbuff_64 = NULL; 270 } 271 272 static int ath10k_htt_tx_alloc_cont_txbuf_64(struct ath10k_htt *htt) 273 { 274 struct ath10k *ar = htt->ar; 275 size_t size; 276 277 size = htt->max_num_pending_tx * 278 sizeof(struct ath10k_htt_txbuf_64); 279 280 htt->txbuf.vaddr_txbuff_64 = dma_alloc_coherent(ar->dev, size, 281 &htt->txbuf.paddr, 282 GFP_KERNEL); 283 if (!htt->txbuf.vaddr_txbuff_64) 284 return -ENOMEM; 285 286 htt->txbuf.size = size; 287 288 return 0; 289 } 290 291 static void ath10k_htt_tx_free_cont_frag_desc_32(struct ath10k_htt *htt) 292 { 293 size_t size; 294 295 if (!htt->frag_desc.vaddr_desc_32) 296 return; 297 298 size = htt->max_num_pending_tx * 299 sizeof(struct htt_msdu_ext_desc); 300 301 dma_free_coherent(htt->ar->dev, 302 size, 303 htt->frag_desc.vaddr_desc_32, 304 htt->frag_desc.paddr); 305 306 htt->frag_desc.vaddr_desc_32 = NULL; 307 } 308 309 static int ath10k_htt_tx_alloc_cont_frag_desc_32(struct ath10k_htt *htt) 310 { 311 struct ath10k *ar = htt->ar; 312 size_t size; 313 314 if (!ar->hw_params.continuous_frag_desc) 315 return 0; 316 317 size = htt->max_num_pending_tx * 318 sizeof(struct htt_msdu_ext_desc); 319 htt->frag_desc.vaddr_desc_32 = dma_alloc_coherent(ar->dev, size, 320 &htt->frag_desc.paddr, 321 GFP_KERNEL); 322 if (!htt->frag_desc.vaddr_desc_32) { 323 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 324 return -ENOMEM; 325 } 326 htt->frag_desc.size = size; 327 328 return 0; 329 } 330 331 static void ath10k_htt_tx_free_cont_frag_desc_64(struct ath10k_htt *htt) 332 { 333 size_t size; 334 335 if (!htt->frag_desc.vaddr_desc_64) 336 return; 337 338 size = htt->max_num_pending_tx * 339 sizeof(struct htt_msdu_ext_desc_64); 340 341 dma_free_coherent(htt->ar->dev, 342 size, 343 htt->frag_desc.vaddr_desc_64, 344 htt->frag_desc.paddr); 345 346 htt->frag_desc.vaddr_desc_64 = NULL; 347 } 348 349 static int ath10k_htt_tx_alloc_cont_frag_desc_64(struct ath10k_htt *htt) 350 { 351 struct ath10k *ar = htt->ar; 352 size_t size; 353 354 if (!ar->hw_params.continuous_frag_desc) 355 return 0; 356 357 size = htt->max_num_pending_tx * 358 sizeof(struct htt_msdu_ext_desc_64); 359 360 htt->frag_desc.vaddr_desc_64 = dma_alloc_coherent(ar->dev, size, 361 &htt->frag_desc.paddr, 362 GFP_KERNEL); 363 if (!htt->frag_desc.vaddr_desc_64) { 364 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 365 return -ENOMEM; 366 } 367 htt->frag_desc.size = size; 368 369 return 0; 370 } 371 372 static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt) 373 { 374 struct ath10k *ar = htt->ar; 375 size_t size; 376 377 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 378 ar->running_fw->fw_file.fw_features)) 379 return; 380 381 size = sizeof(*htt->tx_q_state.vaddr); 382 383 dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE); 384 kfree(htt->tx_q_state.vaddr); 385 } 386 387 static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt) 388 { 389 struct ath10k *ar = htt->ar; 390 size_t size; 391 int ret; 392 393 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 394 ar->running_fw->fw_file.fw_features)) 395 return 0; 396 397 htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS; 398 htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS; 399 htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES; 400 401 size = sizeof(*htt->tx_q_state.vaddr); 402 htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL); 403 if (!htt->tx_q_state.vaddr) 404 return -ENOMEM; 405 406 htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr, 407 size, DMA_TO_DEVICE); 408 ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr); 409 if (ret) { 410 ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret); 411 kfree(htt->tx_q_state.vaddr); 412 return -EIO; 413 } 414 415 return 0; 416 } 417 418 static void ath10k_htt_tx_free_txdone_fifo(struct ath10k_htt *htt) 419 { 420 WARN_ON(!kfifo_is_empty(&htt->txdone_fifo)); 421 kfifo_free(&htt->txdone_fifo); 422 } 423 424 static int ath10k_htt_tx_alloc_txdone_fifo(struct ath10k_htt *htt) 425 { 426 int ret; 427 size_t size; 428 429 size = roundup_pow_of_two(htt->max_num_pending_tx); 430 ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL); 431 return ret; 432 } 433 434 static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt) 435 { 436 struct ath10k *ar = htt->ar; 437 int ret; 438 439 ret = ath10k_htt_alloc_txbuff(htt); 440 if (ret) { 441 ath10k_err(ar, "failed to alloc cont tx buffer: %d\n", ret); 442 return ret; 443 } 444 445 ret = ath10k_htt_alloc_frag_desc(htt); 446 if (ret) { 447 ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret); 448 goto free_txbuf; 449 } 450 451 ret = ath10k_htt_tx_alloc_txq(htt); 452 if (ret) { 453 ath10k_err(ar, "failed to alloc txq: %d\n", ret); 454 goto free_frag_desc; 455 } 456 457 ret = ath10k_htt_tx_alloc_txdone_fifo(htt); 458 if (ret) { 459 ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret); 460 goto free_txq; 461 } 462 463 return 0; 464 465 free_txq: 466 ath10k_htt_tx_free_txq(htt); 467 468 free_frag_desc: 469 ath10k_htt_free_frag_desc(htt); 470 471 free_txbuf: 472 ath10k_htt_free_txbuff(htt); 473 474 return ret; 475 } 476 477 int ath10k_htt_tx_start(struct ath10k_htt *htt) 478 { 479 struct ath10k *ar = htt->ar; 480 int ret; 481 482 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n", 483 htt->max_num_pending_tx); 484 485 spin_lock_init(&htt->tx_lock); 486 idr_init(&htt->pending_tx); 487 488 if (htt->tx_mem_allocated) 489 return 0; 490 491 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) 492 return 0; 493 494 ret = ath10k_htt_tx_alloc_buf(htt); 495 if (ret) 496 goto free_idr_pending_tx; 497 498 htt->tx_mem_allocated = true; 499 500 return 0; 501 502 free_idr_pending_tx: 503 idr_destroy(&htt->pending_tx); 504 505 return ret; 506 } 507 508 static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx) 509 { 510 struct ath10k *ar = ctx; 511 struct ath10k_htt *htt = &ar->htt; 512 struct htt_tx_done tx_done = {}; 513 514 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %u\n", msdu_id); 515 516 tx_done.msdu_id = msdu_id; 517 tx_done.status = HTT_TX_COMPL_STATE_DISCARD; 518 519 ath10k_txrx_tx_unref(htt, &tx_done); 520 521 return 0; 522 } 523 524 void ath10k_htt_tx_destroy(struct ath10k_htt *htt) 525 { 526 if (!htt->tx_mem_allocated) 527 return; 528 529 ath10k_htt_free_txbuff(htt); 530 ath10k_htt_tx_free_txq(htt); 531 ath10k_htt_free_frag_desc(htt); 532 ath10k_htt_tx_free_txdone_fifo(htt); 533 htt->tx_mem_allocated = false; 534 } 535 536 static void ath10k_htt_flush_tx_queue(struct ath10k_htt *htt) 537 { 538 ath10k_htc_stop_hl(htt->ar); 539 idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar); 540 } 541 542 void ath10k_htt_tx_stop(struct ath10k_htt *htt) 543 { 544 ath10k_htt_flush_tx_queue(htt); 545 idr_destroy(&htt->pending_tx); 546 } 547 548 void ath10k_htt_tx_free(struct ath10k_htt *htt) 549 { 550 ath10k_htt_tx_stop(htt); 551 ath10k_htt_tx_destroy(htt); 552 } 553 554 void ath10k_htt_op_ep_tx_credits(struct ath10k *ar) 555 { 556 queue_work(ar->workqueue, &ar->bundle_tx_work); 557 } 558 559 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb) 560 { 561 struct ath10k_htt *htt = &ar->htt; 562 struct htt_tx_done tx_done = {}; 563 struct htt_cmd_hdr *htt_hdr; 564 struct htt_data_tx_desc *desc_hdr = NULL; 565 u16 flags1 = 0; 566 u8 msg_type = 0; 567 568 if (htt->disable_tx_comp) { 569 htt_hdr = (struct htt_cmd_hdr *)skb->data; 570 msg_type = htt_hdr->msg_type; 571 572 if (msg_type == HTT_H2T_MSG_TYPE_TX_FRM) { 573 desc_hdr = (struct htt_data_tx_desc *) 574 (skb->data + sizeof(*htt_hdr)); 575 flags1 = __le16_to_cpu(desc_hdr->flags1); 576 skb_pull(skb, sizeof(struct htt_cmd_hdr)); 577 skb_pull(skb, sizeof(struct htt_data_tx_desc)); 578 } 579 } 580 581 dev_kfree_skb_any(skb); 582 583 if ((!htt->disable_tx_comp) || (msg_type != HTT_H2T_MSG_TYPE_TX_FRM)) 584 return; 585 586 ath10k_dbg(ar, ATH10K_DBG_HTT, 587 "htt tx complete msdu id:%u ,flags1:%x\n", 588 __le16_to_cpu(desc_hdr->id), flags1); 589 590 if (flags1 & HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE) 591 return; 592 593 tx_done.status = HTT_TX_COMPL_STATE_ACK; 594 tx_done.msdu_id = __le16_to_cpu(desc_hdr->id); 595 ath10k_txrx_tx_unref(&ar->htt, &tx_done); 596 } 597 598 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb) 599 { 600 dev_kfree_skb_any(skb); 601 } 602 EXPORT_SYMBOL(ath10k_htt_hif_tx_complete); 603 604 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt) 605 { 606 struct ath10k *ar = htt->ar; 607 struct sk_buff *skb; 608 struct htt_cmd *cmd; 609 int len = 0; 610 int ret; 611 612 len += sizeof(cmd->hdr); 613 len += sizeof(cmd->ver_req); 614 615 skb = ath10k_htc_alloc_skb(ar, len); 616 if (!skb) 617 return -ENOMEM; 618 619 skb_put(skb, len); 620 cmd = (struct htt_cmd *)skb->data; 621 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ; 622 623 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 624 if (ret) { 625 dev_kfree_skb_any(skb); 626 return ret; 627 } 628 629 return 0; 630 } 631 632 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, 633 u64 cookie) 634 { 635 struct ath10k *ar = htt->ar; 636 struct htt_stats_req *req; 637 struct sk_buff *skb; 638 struct htt_cmd *cmd; 639 int len = 0, ret; 640 641 len += sizeof(cmd->hdr); 642 len += sizeof(cmd->stats_req); 643 644 skb = ath10k_htc_alloc_skb(ar, len); 645 if (!skb) 646 return -ENOMEM; 647 648 skb_put(skb, len); 649 cmd = (struct htt_cmd *)skb->data; 650 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ; 651 652 req = &cmd->stats_req; 653 654 memset(req, 0, sizeof(*req)); 655 656 /* currently we support only max 24 bit masks so no need to worry 657 * about endian support 658 */ 659 memcpy(req->upload_types, &mask, 3); 660 memcpy(req->reset_types, &reset_mask, 3); 661 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID; 662 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff); 663 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32); 664 665 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 666 if (ret) { 667 ath10k_warn(ar, "failed to send htt type stats request: %d", 668 ret); 669 dev_kfree_skb_any(skb); 670 return ret; 671 } 672 673 return 0; 674 } 675 676 static int ath10k_htt_send_frag_desc_bank_cfg_32(struct ath10k_htt *htt) 677 { 678 struct ath10k *ar = htt->ar; 679 struct sk_buff *skb; 680 struct htt_cmd *cmd; 681 struct htt_frag_desc_bank_cfg32 *cfg; 682 int ret, size; 683 u8 info; 684 685 if (!ar->hw_params.continuous_frag_desc) 686 return 0; 687 688 if (!htt->frag_desc.paddr) { 689 ath10k_warn(ar, "invalid frag desc memory\n"); 690 return -EINVAL; 691 } 692 693 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg32); 694 skb = ath10k_htc_alloc_skb(ar, size); 695 if (!skb) 696 return -ENOMEM; 697 698 skb_put(skb, size); 699 cmd = (struct htt_cmd *)skb->data; 700 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 701 702 info = 0; 703 info |= SM(htt->tx_q_state.type, 704 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 705 706 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 707 ar->running_fw->fw_file.fw_features)) 708 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 709 710 cfg = &cmd->frag_desc_bank_cfg32; 711 cfg->info = info; 712 cfg->num_banks = 1; 713 cfg->desc_size = sizeof(struct htt_msdu_ext_desc); 714 cfg->bank_base_addrs[0] = __cpu_to_le32(htt->frag_desc.paddr); 715 cfg->bank_id[0].bank_min_id = 0; 716 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 717 1); 718 719 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 720 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 721 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 722 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 723 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 724 725 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 726 727 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 728 if (ret) { 729 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 730 ret); 731 dev_kfree_skb_any(skb); 732 return ret; 733 } 734 735 return 0; 736 } 737 738 static int ath10k_htt_send_frag_desc_bank_cfg_64(struct ath10k_htt *htt) 739 { 740 struct ath10k *ar = htt->ar; 741 struct sk_buff *skb; 742 struct htt_cmd *cmd; 743 struct htt_frag_desc_bank_cfg64 *cfg; 744 int ret, size; 745 u8 info; 746 747 if (!ar->hw_params.continuous_frag_desc) 748 return 0; 749 750 if (!htt->frag_desc.paddr) { 751 ath10k_warn(ar, "invalid frag desc memory\n"); 752 return -EINVAL; 753 } 754 755 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg64); 756 skb = ath10k_htc_alloc_skb(ar, size); 757 if (!skb) 758 return -ENOMEM; 759 760 skb_put(skb, size); 761 cmd = (struct htt_cmd *)skb->data; 762 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 763 764 info = 0; 765 info |= SM(htt->tx_q_state.type, 766 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 767 768 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 769 ar->running_fw->fw_file.fw_features)) 770 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 771 772 cfg = &cmd->frag_desc_bank_cfg64; 773 cfg->info = info; 774 cfg->num_banks = 1; 775 cfg->desc_size = sizeof(struct htt_msdu_ext_desc_64); 776 cfg->bank_base_addrs[0] = __cpu_to_le64(htt->frag_desc.paddr); 777 cfg->bank_id[0].bank_min_id = 0; 778 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 779 1); 780 781 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 782 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 783 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 784 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 785 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 786 787 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 788 789 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 790 if (ret) { 791 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 792 ret); 793 dev_kfree_skb_any(skb); 794 return ret; 795 } 796 797 return 0; 798 } 799 800 static void ath10k_htt_fill_rx_desc_offset_32(struct ath10k_hw_params *hw, 801 struct htt_rx_ring_setup_ring32 *rx_ring) 802 { 803 ath10k_htt_rx_desc_get_offsets(hw, &rx_ring->offsets); 804 } 805 806 static void ath10k_htt_fill_rx_desc_offset_64(struct ath10k_hw_params *hw, 807 struct htt_rx_ring_setup_ring64 *rx_ring) 808 { 809 ath10k_htt_rx_desc_get_offsets(hw, &rx_ring->offsets); 810 } 811 812 static int ath10k_htt_send_rx_ring_cfg_32(struct ath10k_htt *htt) 813 { 814 struct ath10k *ar = htt->ar; 815 struct ath10k_hw_params *hw = &ar->hw_params; 816 struct sk_buff *skb; 817 struct htt_cmd *cmd; 818 struct htt_rx_ring_setup_ring32 *ring; 819 const int num_rx_ring = 1; 820 u16 flags; 821 u32 fw_idx; 822 int len; 823 int ret; 824 825 /* 826 * the HW expects the buffer to be an integral number of 4-byte 827 * "words" 828 */ 829 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 830 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 831 832 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr) 833 + (sizeof(*ring) * num_rx_ring); 834 skb = ath10k_htc_alloc_skb(ar, len); 835 if (!skb) 836 return -ENOMEM; 837 838 skb_put(skb, len); 839 840 cmd = (struct htt_cmd *)skb->data; 841 ring = &cmd->rx_setup_32.rings[0]; 842 843 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 844 cmd->rx_setup_32.hdr.num_rings = 1; 845 846 /* FIXME: do we need all of this? */ 847 flags = 0; 848 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 849 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 850 flags |= HTT_RX_RING_FLAGS_PPDU_START; 851 flags |= HTT_RX_RING_FLAGS_PPDU_END; 852 flags |= HTT_RX_RING_FLAGS_MPDU_START; 853 flags |= HTT_RX_RING_FLAGS_MPDU_END; 854 flags |= HTT_RX_RING_FLAGS_MSDU_START; 855 flags |= HTT_RX_RING_FLAGS_MSDU_END; 856 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 857 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 858 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 859 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 860 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 861 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 862 flags |= HTT_RX_RING_FLAGS_NULL_RX; 863 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 864 865 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 866 867 ring->fw_idx_shadow_reg_paddr = 868 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr); 869 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr); 870 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 871 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 872 ring->flags = __cpu_to_le16(flags); 873 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 874 875 ath10k_htt_fill_rx_desc_offset_32(hw, ring); 876 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 877 if (ret) { 878 dev_kfree_skb_any(skb); 879 return ret; 880 } 881 882 return 0; 883 } 884 885 static int ath10k_htt_send_rx_ring_cfg_64(struct ath10k_htt *htt) 886 { 887 struct ath10k *ar = htt->ar; 888 struct ath10k_hw_params *hw = &ar->hw_params; 889 struct sk_buff *skb; 890 struct htt_cmd *cmd; 891 struct htt_rx_ring_setup_ring64 *ring; 892 const int num_rx_ring = 1; 893 u16 flags; 894 u32 fw_idx; 895 int len; 896 int ret; 897 898 /* HW expects the buffer to be an integral number of 4-byte 899 * "words" 900 */ 901 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 902 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 903 904 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_64.hdr) 905 + (sizeof(*ring) * num_rx_ring); 906 skb = ath10k_htc_alloc_skb(ar, len); 907 if (!skb) 908 return -ENOMEM; 909 910 skb_put(skb, len); 911 912 cmd = (struct htt_cmd *)skb->data; 913 ring = &cmd->rx_setup_64.rings[0]; 914 915 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 916 cmd->rx_setup_64.hdr.num_rings = 1; 917 918 flags = 0; 919 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 920 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 921 flags |= HTT_RX_RING_FLAGS_PPDU_START; 922 flags |= HTT_RX_RING_FLAGS_PPDU_END; 923 flags |= HTT_RX_RING_FLAGS_MPDU_START; 924 flags |= HTT_RX_RING_FLAGS_MPDU_END; 925 flags |= HTT_RX_RING_FLAGS_MSDU_START; 926 flags |= HTT_RX_RING_FLAGS_MSDU_END; 927 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 928 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 929 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 930 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 931 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 932 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 933 flags |= HTT_RX_RING_FLAGS_NULL_RX; 934 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 935 936 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 937 938 ring->fw_idx_shadow_reg_paddr = __cpu_to_le64(htt->rx_ring.alloc_idx.paddr); 939 ring->rx_ring_base_paddr = __cpu_to_le64(htt->rx_ring.base_paddr); 940 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 941 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 942 ring->flags = __cpu_to_le16(flags); 943 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 944 945 ath10k_htt_fill_rx_desc_offset_64(hw, ring); 946 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 947 if (ret) { 948 dev_kfree_skb_any(skb); 949 return ret; 950 } 951 952 return 0; 953 } 954 955 static int ath10k_htt_send_rx_ring_cfg_hl(struct ath10k_htt *htt) 956 { 957 struct ath10k *ar = htt->ar; 958 struct sk_buff *skb; 959 struct htt_cmd *cmd; 960 struct htt_rx_ring_setup_ring32 *ring; 961 const int num_rx_ring = 1; 962 u16 flags; 963 int len; 964 int ret; 965 966 /* 967 * the HW expects the buffer to be an integral number of 4-byte 968 * "words" 969 */ 970 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 971 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 972 973 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr) 974 + (sizeof(*ring) * num_rx_ring); 975 skb = ath10k_htc_alloc_skb(ar, len); 976 if (!skb) 977 return -ENOMEM; 978 979 skb_put(skb, len); 980 981 cmd = (struct htt_cmd *)skb->data; 982 ring = &cmd->rx_setup_32.rings[0]; 983 984 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 985 cmd->rx_setup_32.hdr.num_rings = 1; 986 987 flags = 0; 988 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 989 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 990 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 991 992 memset(ring, 0, sizeof(*ring)); 993 ring->rx_ring_len = __cpu_to_le16(HTT_RX_RING_SIZE_MIN); 994 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 995 ring->flags = __cpu_to_le16(flags); 996 997 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 998 if (ret) { 999 dev_kfree_skb_any(skb); 1000 return ret; 1001 } 1002 1003 return 0; 1004 } 1005 1006 static int ath10k_htt_h2t_aggr_cfg_msg_32(struct ath10k_htt *htt, 1007 u8 max_subfrms_ampdu, 1008 u8 max_subfrms_amsdu) 1009 { 1010 struct ath10k *ar = htt->ar; 1011 struct htt_aggr_conf *aggr_conf; 1012 struct sk_buff *skb; 1013 struct htt_cmd *cmd; 1014 int len; 1015 int ret; 1016 1017 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 1018 1019 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 1020 return -EINVAL; 1021 1022 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 1023 return -EINVAL; 1024 1025 len = sizeof(cmd->hdr); 1026 len += sizeof(cmd->aggr_conf); 1027 1028 skb = ath10k_htc_alloc_skb(ar, len); 1029 if (!skb) 1030 return -ENOMEM; 1031 1032 skb_put(skb, len); 1033 cmd = (struct htt_cmd *)skb->data; 1034 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 1035 1036 aggr_conf = &cmd->aggr_conf; 1037 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 1038 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 1039 1040 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 1041 aggr_conf->max_num_amsdu_subframes, 1042 aggr_conf->max_num_ampdu_subframes); 1043 1044 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1045 if (ret) { 1046 dev_kfree_skb_any(skb); 1047 return ret; 1048 } 1049 1050 return 0; 1051 } 1052 1053 static int ath10k_htt_h2t_aggr_cfg_msg_v2(struct ath10k_htt *htt, 1054 u8 max_subfrms_ampdu, 1055 u8 max_subfrms_amsdu) 1056 { 1057 struct ath10k *ar = htt->ar; 1058 struct htt_aggr_conf_v2 *aggr_conf; 1059 struct sk_buff *skb; 1060 struct htt_cmd *cmd; 1061 int len; 1062 int ret; 1063 1064 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 1065 1066 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 1067 return -EINVAL; 1068 1069 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 1070 return -EINVAL; 1071 1072 len = sizeof(cmd->hdr); 1073 len += sizeof(cmd->aggr_conf_v2); 1074 1075 skb = ath10k_htc_alloc_skb(ar, len); 1076 if (!skb) 1077 return -ENOMEM; 1078 1079 skb_put(skb, len); 1080 cmd = (struct htt_cmd *)skb->data; 1081 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 1082 1083 aggr_conf = &cmd->aggr_conf_v2; 1084 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 1085 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 1086 1087 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 1088 aggr_conf->max_num_amsdu_subframes, 1089 aggr_conf->max_num_ampdu_subframes); 1090 1091 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 1092 if (ret) { 1093 dev_kfree_skb_any(skb); 1094 return ret; 1095 } 1096 1097 return 0; 1098 } 1099 1100 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 1101 __le32 token, 1102 __le16 fetch_seq_num, 1103 struct htt_tx_fetch_record *records, 1104 size_t num_records) 1105 { 1106 struct sk_buff *skb; 1107 struct htt_cmd *cmd; 1108 const u16 resp_id = 0; 1109 int len = 0; 1110 int ret; 1111 1112 /* Response IDs are echo-ed back only for host driver convenience 1113 * purposes. They aren't used for anything in the driver yet so use 0. 1114 */ 1115 1116 len += sizeof(cmd->hdr); 1117 len += sizeof(cmd->tx_fetch_resp); 1118 len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records; 1119 1120 skb = ath10k_htc_alloc_skb(ar, len); 1121 if (!skb) 1122 return -ENOMEM; 1123 1124 skb_put(skb, len); 1125 cmd = (struct htt_cmd *)skb->data; 1126 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP; 1127 cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id); 1128 cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num; 1129 cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records); 1130 cmd->tx_fetch_resp.token = token; 1131 1132 memcpy(cmd->tx_fetch_resp.records, records, 1133 sizeof(records[0]) * num_records); 1134 1135 ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb); 1136 if (ret) { 1137 ath10k_warn(ar, "failed to submit htc command: %d\n", ret); 1138 goto err_free_skb; 1139 } 1140 1141 return 0; 1142 1143 err_free_skb: 1144 dev_kfree_skb_any(skb); 1145 1146 return ret; 1147 } 1148 1149 static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb) 1150 { 1151 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1152 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1153 struct ath10k_vif *arvif; 1154 1155 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) { 1156 return ar->scan.vdev_id; 1157 } else if (cb->vif) { 1158 arvif = (void *)cb->vif->drv_priv; 1159 return arvif->vdev_id; 1160 } else if (ar->monitor_started) { 1161 return ar->monitor_vdev_id; 1162 } else { 1163 return 0; 1164 } 1165 } 1166 1167 static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth) 1168 { 1169 struct ieee80211_hdr *hdr = (void *)skb->data; 1170 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1171 1172 if (!is_eth && ieee80211_is_mgmt(hdr->frame_control)) 1173 return HTT_DATA_TX_EXT_TID_MGMT; 1174 else if (cb->flags & ATH10K_SKB_F_QOS) 1175 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 1176 else 1177 return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST; 1178 } 1179 1180 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu) 1181 { 1182 struct ath10k *ar = htt->ar; 1183 struct device *dev = ar->dev; 1184 struct sk_buff *txdesc = NULL; 1185 struct htt_cmd *cmd; 1186 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1187 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1188 int len = 0; 1189 int msdu_id = -1; 1190 int res; 1191 const u8 *peer_addr; 1192 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1193 1194 len += sizeof(cmd->hdr); 1195 len += sizeof(cmd->mgmt_tx); 1196 1197 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1198 if (res < 0) 1199 goto err; 1200 1201 msdu_id = res; 1202 1203 if ((ieee80211_is_action(hdr->frame_control) || 1204 ieee80211_is_deauth(hdr->frame_control) || 1205 ieee80211_is_disassoc(hdr->frame_control)) && 1206 ieee80211_has_protected(hdr->frame_control)) { 1207 peer_addr = hdr->addr1; 1208 if (is_multicast_ether_addr(peer_addr)) { 1209 skb_put(msdu, sizeof(struct ieee80211_mmie_16)); 1210 } else { 1211 if (skb_cb->ucast_cipher == WLAN_CIPHER_SUITE_GCMP || 1212 skb_cb->ucast_cipher == WLAN_CIPHER_SUITE_GCMP_256) 1213 skb_put(msdu, IEEE80211_GCMP_MIC_LEN); 1214 else 1215 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1216 } 1217 } 1218 1219 txdesc = ath10k_htc_alloc_skb(ar, len); 1220 if (!txdesc) { 1221 res = -ENOMEM; 1222 goto err_free_msdu_id; 1223 } 1224 1225 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1226 DMA_TO_DEVICE); 1227 res = dma_mapping_error(dev, skb_cb->paddr); 1228 if (res) { 1229 res = -EIO; 1230 goto err_free_txdesc; 1231 } 1232 1233 skb_put(txdesc, len); 1234 cmd = (struct htt_cmd *)txdesc->data; 1235 memset(cmd, 0, len); 1236 1237 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX; 1238 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr); 1239 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len); 1240 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id); 1241 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id); 1242 memcpy(cmd->mgmt_tx.hdr, msdu->data, 1243 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN)); 1244 1245 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc); 1246 if (res) 1247 goto err_unmap_msdu; 1248 1249 return 0; 1250 1251 err_unmap_msdu: 1252 if (ar->bus_param.dev_type != ATH10K_DEV_TYPE_HL) 1253 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1254 err_free_txdesc: 1255 dev_kfree_skb_any(txdesc); 1256 err_free_msdu_id: 1257 spin_lock_bh(&htt->tx_lock); 1258 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1259 spin_unlock_bh(&htt->tx_lock); 1260 err: 1261 return res; 1262 } 1263 1264 #define HTT_TX_HL_NEEDED_HEADROOM \ 1265 (unsigned int)(sizeof(struct htt_cmd_hdr) + \ 1266 sizeof(struct htt_data_tx_desc) + \ 1267 sizeof(struct ath10k_htc_hdr)) 1268 1269 static int ath10k_htt_tx_hl(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 1270 struct sk_buff *msdu) 1271 { 1272 struct ath10k *ar = htt->ar; 1273 int res, data_len; 1274 struct htt_cmd_hdr *cmd_hdr; 1275 struct htt_data_tx_desc *tx_desc; 1276 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1277 struct sk_buff *tmp_skb; 1278 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1279 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1280 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1281 u8 flags0 = 0; 1282 u16 flags1 = 0; 1283 u16 msdu_id = 0; 1284 1285 if (!is_eth) { 1286 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1287 1288 if ((ieee80211_is_action(hdr->frame_control) || 1289 ieee80211_is_deauth(hdr->frame_control) || 1290 ieee80211_is_disassoc(hdr->frame_control)) && 1291 ieee80211_has_protected(hdr->frame_control)) { 1292 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1293 } 1294 } 1295 1296 data_len = msdu->len; 1297 1298 switch (txmode) { 1299 case ATH10K_HW_TXRX_RAW: 1300 case ATH10K_HW_TXRX_NATIVE_WIFI: 1301 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1302 fallthrough; 1303 case ATH10K_HW_TXRX_ETHERNET: 1304 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1305 break; 1306 case ATH10K_HW_TXRX_MGMT: 1307 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1308 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1309 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1310 1311 if (htt->disable_tx_comp) 1312 flags1 |= HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE; 1313 break; 1314 } 1315 1316 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1317 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1318 1319 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1320 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1321 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1322 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1323 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1324 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1325 } 1326 1327 /* Prepend the HTT header and TX desc struct to the data message 1328 * and realloc the skb if it does not have enough headroom. 1329 */ 1330 if (skb_headroom(msdu) < HTT_TX_HL_NEEDED_HEADROOM) { 1331 tmp_skb = msdu; 1332 1333 ath10k_dbg(htt->ar, ATH10K_DBG_HTT, 1334 "Not enough headroom in skb. Current headroom: %u, needed: %u. Reallocating...\n", 1335 skb_headroom(msdu), HTT_TX_HL_NEEDED_HEADROOM); 1336 msdu = skb_realloc_headroom(msdu, HTT_TX_HL_NEEDED_HEADROOM); 1337 kfree_skb(tmp_skb); 1338 if (!msdu) { 1339 ath10k_warn(htt->ar, "htt hl tx: Unable to realloc skb!\n"); 1340 res = -ENOMEM; 1341 goto out; 1342 } 1343 } 1344 1345 if (ar->bus_param.hl_msdu_ids) { 1346 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1347 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1348 if (res < 0) { 1349 ath10k_err(ar, "msdu_id allocation failed %d\n", res); 1350 goto out; 1351 } 1352 msdu_id = res; 1353 } 1354 1355 /* As msdu is freed by mac80211 (in ieee80211_tx_status_skb()) and by 1356 * ath10k (in ath10k_htt_htc_tx_complete()) we have to increase 1357 * reference by one to avoid a use-after-free case and a double 1358 * free. 1359 */ 1360 skb_get(msdu); 1361 1362 skb_push(msdu, sizeof(*cmd_hdr)); 1363 skb_push(msdu, sizeof(*tx_desc)); 1364 cmd_hdr = (struct htt_cmd_hdr *)msdu->data; 1365 tx_desc = (struct htt_data_tx_desc *)(msdu->data + sizeof(*cmd_hdr)); 1366 1367 cmd_hdr->msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1368 tx_desc->flags0 = flags0; 1369 tx_desc->flags1 = __cpu_to_le16(flags1); 1370 tx_desc->len = __cpu_to_le16(data_len); 1371 tx_desc->id = __cpu_to_le16(msdu_id); 1372 tx_desc->frags_paddr = 0; /* always zero */ 1373 /* Initialize peer_id to INVALID_PEER because this is NOT 1374 * Reinjection path 1375 */ 1376 tx_desc->peerid = __cpu_to_le32(HTT_INVALID_PEERID); 1377 1378 res = ath10k_htc_send_hl(&htt->ar->htc, htt->eid, msdu); 1379 1380 out: 1381 return res; 1382 } 1383 1384 static int ath10k_htt_tx_32(struct ath10k_htt *htt, 1385 enum ath10k_hw_txrx_mode txmode, 1386 struct sk_buff *msdu) 1387 { 1388 struct ath10k *ar = htt->ar; 1389 struct device *dev = ar->dev; 1390 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1391 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1392 struct ath10k_hif_sg_item sg_items[2]; 1393 struct ath10k_htt_txbuf_32 *txbuf; 1394 struct htt_data_tx_desc_frag *frags; 1395 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1396 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1397 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1398 int prefetch_len; 1399 int res; 1400 u8 flags0 = 0; 1401 u16 msdu_id, flags1 = 0; 1402 u16 freq = 0; 1403 u32 frags_paddr = 0; 1404 u32 txbuf_paddr; 1405 struct htt_msdu_ext_desc *ext_desc = NULL; 1406 struct htt_msdu_ext_desc *ext_desc_t = NULL; 1407 1408 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1409 if (res < 0) 1410 goto err; 1411 1412 msdu_id = res; 1413 1414 prefetch_len = min(htt->prefetch_len, msdu->len); 1415 prefetch_len = roundup(prefetch_len, 4); 1416 1417 txbuf = htt->txbuf.vaddr_txbuff_32 + msdu_id; 1418 txbuf_paddr = htt->txbuf.paddr + 1419 (sizeof(struct ath10k_htt_txbuf_32) * msdu_id); 1420 1421 if (!is_eth) { 1422 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1423 1424 if ((ieee80211_is_action(hdr->frame_control) || 1425 ieee80211_is_deauth(hdr->frame_control) || 1426 ieee80211_is_disassoc(hdr->frame_control)) && 1427 ieee80211_has_protected(hdr->frame_control)) { 1428 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1429 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1430 txmode == ATH10K_HW_TXRX_RAW && 1431 ieee80211_has_protected(hdr->frame_control)) { 1432 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1433 } 1434 } 1435 1436 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1437 DMA_TO_DEVICE); 1438 res = dma_mapping_error(dev, skb_cb->paddr); 1439 if (res) { 1440 res = -EIO; 1441 goto err_free_msdu_id; 1442 } 1443 1444 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1445 freq = ar->scan.roc_freq; 1446 1447 switch (txmode) { 1448 case ATH10K_HW_TXRX_RAW: 1449 case ATH10K_HW_TXRX_NATIVE_WIFI: 1450 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1451 fallthrough; 1452 case ATH10K_HW_TXRX_ETHERNET: 1453 if (ar->hw_params.continuous_frag_desc) { 1454 ext_desc_t = htt->frag_desc.vaddr_desc_32; 1455 memset(&ext_desc_t[msdu_id], 0, 1456 sizeof(struct htt_msdu_ext_desc)); 1457 frags = (struct htt_data_tx_desc_frag *) 1458 &ext_desc_t[msdu_id].frags; 1459 ext_desc = &ext_desc_t[msdu_id]; 1460 frags[0].tword_addr.paddr_lo = 1461 __cpu_to_le32(skb_cb->paddr); 1462 frags[0].tword_addr.paddr_hi = 0; 1463 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1464 1465 frags_paddr = htt->frag_desc.paddr + 1466 (sizeof(struct htt_msdu_ext_desc) * msdu_id); 1467 } else { 1468 frags = txbuf->frags; 1469 frags[0].dword_addr.paddr = 1470 __cpu_to_le32(skb_cb->paddr); 1471 frags[0].dword_addr.len = __cpu_to_le32(msdu->len); 1472 frags[1].dword_addr.paddr = 0; 1473 frags[1].dword_addr.len = 0; 1474 1475 frags_paddr = txbuf_paddr; 1476 } 1477 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1478 break; 1479 case ATH10K_HW_TXRX_MGMT: 1480 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1481 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1482 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1483 1484 frags_paddr = skb_cb->paddr; 1485 break; 1486 } 1487 1488 /* Normally all commands go through HTC which manages tx credits for 1489 * each endpoint and notifies when tx is completed. 1490 * 1491 * HTT endpoint is creditless so there's no need to care about HTC 1492 * flags. In that case it is trivial to fill the HTC header here. 1493 * 1494 * MSDU transmission is considered completed upon HTT event. This 1495 * implies no relevant resources can be freed until after the event is 1496 * received. That's why HTC tx completion handler itself is ignored by 1497 * setting NULL to transfer_context for all sg items. 1498 * 1499 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1500 * as it's a waste of resources. By bypassing HTC it is possible to 1501 * avoid extra memory allocations, compress data structures and thus 1502 * improve performance. 1503 */ 1504 1505 txbuf->htc_hdr.eid = htt->eid; 1506 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1507 sizeof(txbuf->cmd_tx) + 1508 prefetch_len); 1509 txbuf->htc_hdr.flags = 0; 1510 1511 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1512 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1513 1514 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1515 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1516 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1517 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1518 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1519 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1520 if (ar->hw_params.continuous_frag_desc) 1521 ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE; 1522 } 1523 1524 /* Prevent firmware from sending up tx inspection requests. There's 1525 * nothing ath10k can do with frames requested for inspection so force 1526 * it to simply rely a regular tx completion with discard status. 1527 */ 1528 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1529 1530 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1531 txbuf->cmd_tx.flags0 = flags0; 1532 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1533 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1534 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1535 txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr); 1536 if (ath10k_mac_tx_frm_has_freq(ar)) { 1537 txbuf->cmd_tx.offchan_tx.peerid = 1538 __cpu_to_le16(HTT_INVALID_PEERID); 1539 txbuf->cmd_tx.offchan_tx.freq = 1540 __cpu_to_le16(freq); 1541 } else { 1542 txbuf->cmd_tx.peerid = 1543 __cpu_to_le32(HTT_INVALID_PEERID); 1544 } 1545 1546 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1547 ath10k_dbg(ar, ATH10K_DBG_HTT, 1548 "htt tx flags0 %u flags1 %u len %d id %u frags_paddr %pad, msdu_paddr %pad vdev %u tid %u freq %u\n", 1549 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1550 &skb_cb->paddr, vdev_id, tid, freq); 1551 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1552 msdu->data, msdu->len); 1553 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1554 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1555 1556 sg_items[0].transfer_id = 0; 1557 sg_items[0].transfer_context = NULL; 1558 sg_items[0].vaddr = &txbuf->htc_hdr; 1559 sg_items[0].paddr = txbuf_paddr + 1560 sizeof(txbuf->frags); 1561 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1562 sizeof(txbuf->cmd_hdr) + 1563 sizeof(txbuf->cmd_tx); 1564 1565 sg_items[1].transfer_id = 0; 1566 sg_items[1].transfer_context = NULL; 1567 sg_items[1].vaddr = msdu->data; 1568 sg_items[1].paddr = skb_cb->paddr; 1569 sg_items[1].len = prefetch_len; 1570 1571 res = ath10k_hif_tx_sg(htt->ar, 1572 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1573 sg_items, ARRAY_SIZE(sg_items)); 1574 if (res) 1575 goto err_unmap_msdu; 1576 1577 return 0; 1578 1579 err_unmap_msdu: 1580 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1581 err_free_msdu_id: 1582 spin_lock_bh(&htt->tx_lock); 1583 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1584 spin_unlock_bh(&htt->tx_lock); 1585 err: 1586 return res; 1587 } 1588 1589 static int ath10k_htt_tx_64(struct ath10k_htt *htt, 1590 enum ath10k_hw_txrx_mode txmode, 1591 struct sk_buff *msdu) 1592 { 1593 struct ath10k *ar = htt->ar; 1594 struct device *dev = ar->dev; 1595 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1596 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1597 struct ath10k_hif_sg_item sg_items[2]; 1598 struct ath10k_htt_txbuf_64 *txbuf; 1599 struct htt_data_tx_desc_frag *frags; 1600 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1601 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1602 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1603 int prefetch_len; 1604 int res; 1605 u8 flags0 = 0; 1606 u16 msdu_id, flags1 = 0; 1607 u16 freq = 0; 1608 dma_addr_t frags_paddr = 0; 1609 dma_addr_t txbuf_paddr; 1610 struct htt_msdu_ext_desc_64 *ext_desc = NULL; 1611 struct htt_msdu_ext_desc_64 *ext_desc_t = NULL; 1612 1613 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1614 if (res < 0) 1615 goto err; 1616 1617 msdu_id = res; 1618 1619 prefetch_len = min(htt->prefetch_len, msdu->len); 1620 prefetch_len = roundup(prefetch_len, 4); 1621 1622 txbuf = htt->txbuf.vaddr_txbuff_64 + msdu_id; 1623 txbuf_paddr = htt->txbuf.paddr + 1624 (sizeof(struct ath10k_htt_txbuf_64) * msdu_id); 1625 1626 if (!is_eth) { 1627 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1628 1629 if ((ieee80211_is_action(hdr->frame_control) || 1630 ieee80211_is_deauth(hdr->frame_control) || 1631 ieee80211_is_disassoc(hdr->frame_control)) && 1632 ieee80211_has_protected(hdr->frame_control)) { 1633 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1634 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1635 txmode == ATH10K_HW_TXRX_RAW && 1636 ieee80211_has_protected(hdr->frame_control)) { 1637 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1638 } 1639 } 1640 1641 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1642 DMA_TO_DEVICE); 1643 res = dma_mapping_error(dev, skb_cb->paddr); 1644 if (res) { 1645 res = -EIO; 1646 goto err_free_msdu_id; 1647 } 1648 1649 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1650 freq = ar->scan.roc_freq; 1651 1652 switch (txmode) { 1653 case ATH10K_HW_TXRX_RAW: 1654 case ATH10K_HW_TXRX_NATIVE_WIFI: 1655 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1656 fallthrough; 1657 case ATH10K_HW_TXRX_ETHERNET: 1658 if (ar->hw_params.continuous_frag_desc) { 1659 ext_desc_t = htt->frag_desc.vaddr_desc_64; 1660 memset(&ext_desc_t[msdu_id], 0, 1661 sizeof(struct htt_msdu_ext_desc_64)); 1662 frags = (struct htt_data_tx_desc_frag *) 1663 &ext_desc_t[msdu_id].frags; 1664 ext_desc = &ext_desc_t[msdu_id]; 1665 frags[0].tword_addr.paddr_lo = 1666 __cpu_to_le32(skb_cb->paddr); 1667 frags[0].tword_addr.paddr_hi = 1668 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1669 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1670 1671 frags_paddr = htt->frag_desc.paddr + 1672 (sizeof(struct htt_msdu_ext_desc_64) * msdu_id); 1673 } else { 1674 frags = txbuf->frags; 1675 frags[0].tword_addr.paddr_lo = 1676 __cpu_to_le32(skb_cb->paddr); 1677 frags[0].tword_addr.paddr_hi = 1678 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1679 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1680 frags[1].tword_addr.paddr_lo = 0; 1681 frags[1].tword_addr.paddr_hi = 0; 1682 frags[1].tword_addr.len_16 = 0; 1683 } 1684 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1685 break; 1686 case ATH10K_HW_TXRX_MGMT: 1687 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1688 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1689 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1690 1691 frags_paddr = skb_cb->paddr; 1692 break; 1693 } 1694 1695 /* Normally all commands go through HTC which manages tx credits for 1696 * each endpoint and notifies when tx is completed. 1697 * 1698 * HTT endpoint is creditless so there's no need to care about HTC 1699 * flags. In that case it is trivial to fill the HTC header here. 1700 * 1701 * MSDU transmission is considered completed upon HTT event. This 1702 * implies no relevant resources can be freed until after the event is 1703 * received. That's why HTC tx completion handler itself is ignored by 1704 * setting NULL to transfer_context for all sg items. 1705 * 1706 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1707 * as it's a waste of resources. By bypassing HTC it is possible to 1708 * avoid extra memory allocations, compress data structures and thus 1709 * improve performance. 1710 */ 1711 1712 txbuf->htc_hdr.eid = htt->eid; 1713 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1714 sizeof(txbuf->cmd_tx) + 1715 prefetch_len); 1716 txbuf->htc_hdr.flags = 0; 1717 1718 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1719 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1720 1721 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1722 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1723 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1724 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1725 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1726 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1727 if (ar->hw_params.continuous_frag_desc) { 1728 memset(ext_desc->tso_flag, 0, sizeof(ext_desc->tso_flag)); 1729 ext_desc->tso_flag[3] |= 1730 __cpu_to_le32(HTT_MSDU_CHECKSUM_ENABLE_64); 1731 } 1732 } 1733 1734 /* Prevent firmware from sending up tx inspection requests. There's 1735 * nothing ath10k can do with frames requested for inspection so force 1736 * it to simply rely a regular tx completion with discard status. 1737 */ 1738 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1739 1740 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1741 txbuf->cmd_tx.flags0 = flags0; 1742 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1743 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1744 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1745 1746 /* fill fragment descriptor */ 1747 txbuf->cmd_tx.frags_paddr = __cpu_to_le64(frags_paddr); 1748 if (ath10k_mac_tx_frm_has_freq(ar)) { 1749 txbuf->cmd_tx.offchan_tx.peerid = 1750 __cpu_to_le16(HTT_INVALID_PEERID); 1751 txbuf->cmd_tx.offchan_tx.freq = 1752 __cpu_to_le16(freq); 1753 } else { 1754 txbuf->cmd_tx.peerid = 1755 __cpu_to_le32(HTT_INVALID_PEERID); 1756 } 1757 1758 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1759 ath10k_dbg(ar, ATH10K_DBG_HTT, 1760 "htt tx flags0 %u flags1 %u len %d id %u frags_paddr %pad, msdu_paddr %pad vdev %u tid %u freq %u\n", 1761 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1762 &skb_cb->paddr, vdev_id, tid, freq); 1763 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1764 msdu->data, msdu->len); 1765 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1766 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1767 1768 sg_items[0].transfer_id = 0; 1769 sg_items[0].transfer_context = NULL; 1770 sg_items[0].vaddr = &txbuf->htc_hdr; 1771 sg_items[0].paddr = txbuf_paddr + 1772 sizeof(txbuf->frags); 1773 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1774 sizeof(txbuf->cmd_hdr) + 1775 sizeof(txbuf->cmd_tx); 1776 1777 sg_items[1].transfer_id = 0; 1778 sg_items[1].transfer_context = NULL; 1779 sg_items[1].vaddr = msdu->data; 1780 sg_items[1].paddr = skb_cb->paddr; 1781 sg_items[1].len = prefetch_len; 1782 1783 res = ath10k_hif_tx_sg(htt->ar, 1784 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1785 sg_items, ARRAY_SIZE(sg_items)); 1786 if (res) 1787 goto err_unmap_msdu; 1788 1789 return 0; 1790 1791 err_unmap_msdu: 1792 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1793 err_free_msdu_id: 1794 spin_lock_bh(&htt->tx_lock); 1795 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1796 spin_unlock_bh(&htt->tx_lock); 1797 err: 1798 return res; 1799 } 1800 1801 static const struct ath10k_htt_tx_ops htt_tx_ops_32 = { 1802 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_32, 1803 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32, 1804 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_32, 1805 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_32, 1806 .htt_tx = ath10k_htt_tx_32, 1807 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_32, 1808 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_32, 1809 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_32, 1810 }; 1811 1812 static const struct ath10k_htt_tx_ops htt_tx_ops_64 = { 1813 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_64, 1814 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_64, 1815 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_64, 1816 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_64, 1817 .htt_tx = ath10k_htt_tx_64, 1818 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_64, 1819 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_64, 1820 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_v2, 1821 }; 1822 1823 static const struct ath10k_htt_tx_ops htt_tx_ops_hl = { 1824 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_hl, 1825 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32, 1826 .htt_tx = ath10k_htt_tx_hl, 1827 .htt_h2t_aggr_cfg_msg = ath10k_htt_h2t_aggr_cfg_msg_32, 1828 .htt_flush_tx = ath10k_htt_flush_tx_queue, 1829 }; 1830 1831 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt) 1832 { 1833 struct ath10k *ar = htt->ar; 1834 1835 if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) 1836 htt->tx_ops = &htt_tx_ops_hl; 1837 else if (ar->hw_params.target_64bit) 1838 htt->tx_ops = &htt_tx_ops_64; 1839 else 1840 htt->tx_ops = &htt_tx_ops_32; 1841 } 1842