1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include "dp_panel.h" 7 #include "dp_reg.h" 8 #include "dp_utils.h" 9 10 #include <drm/drm_connector.h> 11 #include <drm/drm_edid.h> 12 #include <drm/drm_of.h> 13 #include <drm/drm_print.h> 14 15 #include <linux/io.h> 16 #include <linux/types.h> 17 #include <asm/byteorder.h> 18 19 #define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4) 20 21 struct msm_dp_panel_private { 22 struct device *dev; 23 struct drm_device *drm_dev; 24 struct msm_dp_panel msm_dp_panel; 25 struct drm_dp_aux *aux; 26 struct msm_dp_link *link; 27 void __iomem *link_base; 28 void __iomem *mst2link_base; 29 void __iomem *mst3link_base; 30 void __iomem *pixel_base; 31 bool panel_on; 32 }; 33 34 u32 msm_dp_stream_reg(enum msm_dp_stream_id id, u32 reg) 35 { 36 bool is_s1 = (id == DP_STREAM_1); 37 38 if (id == DP_STREAM_0) 39 return reg; 40 41 switch (reg) { 42 case REG_DP_STATE_CTRL: 43 return is_s1 ? REG_DP_STATE_CTRL : REG_DP_MSTLINK_STATE_CTRL; 44 case REG_DP_CONFIGURATION_CTRL: 45 return is_s1 ? REG_DP1_CONFIGURATION_CTRL : REG_DP_MSTLINK_CONFIGURATION_CTRL; 46 case REG_DP_SOFTWARE_MVID: 47 return is_s1 ? REG_DP1_SOFTWARE_MVID : REG_DP_MSTLINK_SOFTWARE_MVID; 48 case REG_DP_SOFTWARE_NVID: 49 return is_s1 ? REG_DP1_SOFTWARE_NVID : REG_DP_MSTLINK_SOFTWARE_NVID; 50 case REG_DP_TOTAL_HOR_VER: 51 return is_s1 ? REG_DP1_TOTAL_HOR_VER : REG_DP_MSTLINK_TOTAL_HOR_VER; 52 case REG_DP_START_HOR_VER_FROM_SYNC: 53 return is_s1 ? REG_DP1_START_HOR_VER_FROM_SYNC 54 : REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC; 55 case REG_DP_HSYNC_VSYNC_WIDTH_POLARITY: 56 return is_s1 ? REG_DP1_HSYNC_VSYNC_WIDTH_POLARITY 57 : REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY; 58 case REG_DP_ACTIVE_HOR_VER: 59 return is_s1 ? REG_DP1_ACTIVE_HOR_VER : REG_DP_MSTLINK_ACTIVE_HOR_VER; 60 case REG_DP_MISC1_MISC0: 61 return is_s1 ? REG_DP1_MISC1_MISC0 : REG_DP_MSTLINK_MISC1_MISC0; 62 case REG_DP_DP0_TIMESLOT_1_32: 63 return is_s1 ? REG_DP_DP1_TIMESLOT_1_32 : REG_DP_MSTLINK_TIMESLOT_1_32; 64 case REG_DP_DP0_TIMESLOT_33_63: 65 return is_s1 ? REG_DP_DP1_TIMESLOT_33_63 : REG_DP_MSTLINK_TIMESLOT_33_63; 66 case REG_DP_DP0_RG: 67 return is_s1 ? REG_DP_DP1_RG : REG_DP_MSTLINK_DP_RG; 68 case MMSS_DP_SDP_CFG: 69 return is_s1 ? MMSS_DP1_SDP_CFG : MMSS_DP_MSTLINK_SDP_CFG; 70 case MMSS_DP_SDP_CFG2: 71 return is_s1 ? MMSS_DP1_SDP_CFG2 : MMSS_DP_MSTLINK_SDP_CFG2; 72 case MMSS_DP_SDP_CFG3: 73 return is_s1 ? MMSS_DP1_SDP_CFG3 : MMSS_DP_MSTLINK_SDP_CFG3; 74 case MMSS_DP_GENERIC0_0: 75 return is_s1 ? MMSS_DP1_GENERIC0_0 : MMSS_DP_MSTLINK_GENERIC0_0; 76 case MMSS_DP_GENERIC0_1: 77 return is_s1 ? MMSS_DP1_GENERIC0_1 : MMSS_DP_MSTLINK_GENERIC0_1; 78 case MMSS_DP_GENERIC0_2: 79 return is_s1 ? MMSS_DP1_GENERIC0_2 : MMSS_DP_MSTLINK_GENERIC0_2; 80 case MMSS_DP_GENERIC0_3: 81 return is_s1 ? MMSS_DP1_GENERIC0_3 : MMSS_DP_MSTLINK_GENERIC0_3; 82 case MMSS_DP_GENERIC0_4: 83 return is_s1 ? MMSS_DP1_GENERIC0_4 : MMSS_DP_MSTLINK_GENERIC0_4; 84 case MMSS_DP_GENERIC0_5: 85 return is_s1 ? MMSS_DP1_GENERIC0_5 : MMSS_DP_MSTLINK_GENERIC0_5; 86 case MMSS_DP_GENERIC0_6: 87 return is_s1 ? MMSS_DP1_GENERIC0_6 : MMSS_DP_MSTLINK_GENERIC0_6; 88 case MMSS_DP_GENERIC0_7: 89 return is_s1 ? MMSS_DP1_GENERIC0_7 : MMSS_DP_MSTLINK_GENERIC0_7; 90 case MMSS_DP_GENERIC0_8: 91 return is_s1 ? MMSS_DP1_GENERIC0_8 : MMSS_DP_MSTLINK_GENERIC0_8; 92 case MMSS_DP_GENERIC0_9: 93 return is_s1 ? MMSS_DP1_GENERIC0_9 : MMSS_DP_MSTLINK_GENERIC0_9; 94 default: 95 return reg; 96 } 97 } 98 99 static inline u32 msm_dp_read_link(struct msm_dp_panel_private *panel, u32 offset) 100 { 101 offset = msm_dp_stream_reg(panel->msm_dp_panel.stream_id, offset); 102 switch (panel->msm_dp_panel.stream_id) { 103 case DP_STREAM_0: 104 case DP_STREAM_1: 105 return readl_relaxed(panel->link_base + offset); 106 case DP_STREAM_2: 107 return readl_relaxed(panel->mst2link_base + offset); 108 case DP_STREAM_3: 109 return readl_relaxed(panel->mst3link_base + offset); 110 default: 111 DRM_ERROR("error stream_id\n"); 112 return 0; 113 } 114 } 115 116 static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, 117 u32 offset, u32 data) 118 { 119 /* 120 * To make sure link reg writes happens before any other operation, 121 * this function uses writel() instread of writel_relaxed() 122 */ 123 offset = msm_dp_stream_reg(panel->msm_dp_panel.stream_id, offset); 124 switch (panel->msm_dp_panel.stream_id) { 125 case DP_STREAM_0: 126 case DP_STREAM_1: 127 writel(data, panel->link_base + offset); 128 break; 129 case DP_STREAM_2: 130 writel(data, panel->mst2link_base + offset); 131 break; 132 case DP_STREAM_3: 133 writel(data, panel->mst3link_base + offset); 134 break; 135 default: 136 DRM_ERROR("error stream_id\n"); 137 break; 138 } 139 } 140 141 static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, 142 u32 offset, u32 data) 143 { 144 /* 145 * Use writel() instead of writel_relaxed() to ensure the interface 146 * register write reaches the hardware before subsequent operations. 147 */ 148 writel(data, panel->pixel_base + offset); 149 } 150 151 static inline u32 msm_dp_read_pn(struct msm_dp_panel_private *panel, 152 u32 offset) 153 { 154 /* 155 * Only reads a configuration register: no DMA or memory ordering is 156 * required, so readl_relaxed() is sufficient. 157 */ 158 return readl_relaxed(panel->pixel_base + offset); 159 } 160 161 static void msm_dp_panel_read_psr_cap(struct msm_dp_panel_private *panel) 162 { 163 ssize_t rlen; 164 struct msm_dp_panel *msm_dp_panel; 165 166 msm_dp_panel = &panel->msm_dp_panel; 167 168 /* edp sink */ 169 if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { 170 rlen = drm_dp_dpcd_read(panel->aux, DP_PSR_SUPPORT, 171 &msm_dp_panel->psr_cap, sizeof(msm_dp_panel->psr_cap)); 172 if (rlen == sizeof(msm_dp_panel->psr_cap)) { 173 drm_dbg_dp(panel->drm_dev, 174 "psr version: 0x%x, psr_cap: 0x%x\n", 175 msm_dp_panel->psr_cap.version, 176 msm_dp_panel->psr_cap.capabilities); 177 } else 178 DRM_ERROR("failed to read psr info, rlen=%zd\n", rlen); 179 } 180 } 181 182 static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel) 183 { 184 int rc, max_lttpr_lanes, max_lttpr_rate; 185 struct msm_dp_panel_private *panel; 186 struct msm_dp_link_info *link_info; 187 struct msm_dp_link *link; 188 u8 *dpcd, major, minor; 189 190 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 191 dpcd = msm_dp_panel->dpcd; 192 rc = drm_dp_read_dpcd_caps(panel->aux, dpcd); 193 if (rc) 194 return rc; 195 196 msm_dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd); 197 link_info = &msm_dp_panel->link_info; 198 link_info->revision = dpcd[DP_DPCD_REV]; 199 major = (link_info->revision >> 4) & 0x0f; 200 minor = link_info->revision & 0x0f; 201 202 link = panel->link; 203 drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n", 204 link->max_dp_lanes, link->max_dp_link_rate); 205 206 max_lttpr_lanes = drm_dp_lttpr_max_lane_count(link->lttpr_common_caps); 207 max_lttpr_rate = drm_dp_lttpr_max_link_rate(link->lttpr_common_caps); 208 209 /* eDP sink */ 210 if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { 211 u8 edp_rev; 212 213 rc = drm_dp_dpcd_read_byte(panel->aux, DP_EDP_DPCD_REV, &edp_rev); 214 if (rc) 215 return rc; 216 217 drm_dbg_dp(panel->drm_dev, "edp_rev=0x%x\n", edp_rev); 218 219 /* For eDP v1.4+, parse the SUPPORTED_LINK_RATES table */ 220 if (edp_rev >= DP_EDP_14) { 221 __le16 rates[DP_MAX_SUPPORTED_RATES]; 222 u8 bw_set; 223 int i; 224 225 rc = drm_dp_dpcd_read_data(panel->aux, DP_SUPPORTED_LINK_RATES, 226 rates, sizeof(rates)); 227 if (rc) 228 return rc; 229 230 rc = drm_dp_dpcd_read_byte(panel->aux, DP_LINK_BW_SET, &bw_set); 231 if (rc) 232 return rc; 233 234 /* Find index of max supported link rate that does not exceed dtsi limits */ 235 for (i = 0; i < ARRAY_SIZE(rates); i++) { 236 /* 237 * The value from the DPCD multiplied by 200 gives 238 * the link rate in kHz. Divide by 10 to convert to 239 * symbol rate, accounting for 8b/10b encoding. 240 */ 241 u32 rate = (le16_to_cpu(rates[i]) * 200) / 10; 242 243 if (!rate) 244 break; 245 246 drm_dbg_dp(panel->drm_dev, 247 "SUPPORTED_LINK_RATES[%d]: %d\n", i, rate); 248 249 /* 250 * Limit link rate from link-frequencies of endpoint 251 * property of dtsi 252 */ 253 if (rate > link->max_dp_link_rate) 254 break; 255 256 /* Limit link rate from LTTPR capabilities, if any */ 257 if (max_lttpr_rate && rate > max_lttpr_rate) 258 break; 259 260 link_info->rate = rate; 261 link_info->supported_rates[i] = rate; 262 link_info->rate_set = i; 263 } 264 265 /* Only use LINK_RATE_SET if LINK_BW_SET hasn't already been written to */ 266 if (!bw_set && link_info->rate) 267 link_info->use_rate_set = true; 268 } 269 } 270 271 /* Fall back on MAX_LINK_RATE/LINK_BW_SET (DP, eDP <= v1.3) */ 272 if (!link_info->rate) { 273 link_info->rate = drm_dp_max_link_rate(dpcd); 274 275 /* Limit link rate from link-frequencies of endpoint property of dtsi */ 276 if (link_info->rate > link->max_dp_link_rate) 277 link_info->rate = link->max_dp_link_rate; 278 279 /* Limit link rate from LTTPR capabilities, if any */ 280 if (max_lttpr_rate && max_lttpr_rate < link_info->rate) 281 link_info->rate = max_lttpr_rate; 282 } 283 284 link_info->num_lanes = drm_dp_max_lane_count(dpcd); 285 286 /* Limit data lanes from data-lanes of endpoint property of dtsi */ 287 if (link_info->num_lanes > link->max_dp_lanes) 288 link_info->num_lanes = link->max_dp_lanes; 289 290 /* Limit data lanes from LTTPR capabilities, if any */ 291 if (max_lttpr_lanes && max_lttpr_lanes < link_info->num_lanes) 292 link_info->num_lanes = max_lttpr_lanes; 293 294 drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); 295 drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate); 296 drm_dbg_dp(panel->drm_dev, "link_rate_set=%d\n", link_info->rate_set); 297 drm_dbg_dp(panel->drm_dev, "use_rate_set=%d\n", link_info->use_rate_set); 298 drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", link_info->num_lanes); 299 300 if (drm_dp_enhanced_frame_cap(dpcd)) 301 link_info->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; 302 303 msm_dp_panel_read_psr_cap(panel); 304 305 return rc; 306 } 307 308 static u32 msm_dp_panel_get_supported_bpp(struct msm_dp_panel *msm_dp_panel, 309 u32 mode_edid_bpp, u32 mode_pclk_khz) 310 { 311 const struct msm_dp_link_info *link_info; 312 const u32 max_supported_bpp = 30, min_supported_bpp = 18; 313 u32 bpp, data_rate_khz; 314 315 bpp = min(mode_edid_bpp, max_supported_bpp); 316 317 link_info = &msm_dp_panel->link_info; 318 data_rate_khz = link_info->num_lanes * link_info->rate * 8; 319 320 do { 321 if (mode_pclk_khz * bpp <= data_rate_khz) 322 return bpp; 323 bpp -= 6; 324 } while (bpp > min_supported_bpp); 325 326 return min_supported_bpp; 327 } 328 329 int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel, 330 struct drm_connector *connector) 331 { 332 int rc, bw_code; 333 int count; 334 struct msm_dp_panel_private *panel; 335 336 if (!msm_dp_panel || !connector) { 337 DRM_ERROR("invalid input\n"); 338 return -EINVAL; 339 } 340 341 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 342 343 rc = msm_dp_panel_read_dpcd(msm_dp_panel); 344 if (rc) { 345 DRM_ERROR("read dpcd failed %d\n", rc); 346 return rc; 347 } 348 349 bw_code = drm_dp_link_rate_to_bw_code(msm_dp_panel->link_info.rate); 350 if (!is_link_rate_valid(bw_code) || 351 !is_lane_count_valid(msm_dp_panel->link_info.num_lanes) || 352 (bw_code > msm_dp_panel->max_bw_code)) { 353 DRM_ERROR("Illegal link rate=%d lane=%d\n", msm_dp_panel->link_info.rate, 354 msm_dp_panel->link_info.num_lanes); 355 return -EINVAL; 356 } 357 358 if (drm_dp_is_branch(msm_dp_panel->dpcd)) { 359 count = drm_dp_read_sink_count(panel->aux); 360 if (!count) { 361 panel->link->sink_count = 0; 362 return -ENOTCONN; 363 } 364 } 365 366 rc = drm_dp_read_downstream_info(panel->aux, msm_dp_panel->dpcd, 367 msm_dp_panel->downstream_ports); 368 return rc; 369 } 370 371 u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, 372 u32 mode_edid_bpp, u32 mode_pclk_khz) 373 { 374 struct msm_dp_panel_private *panel; 375 u32 bpp; 376 377 if (!msm_dp_panel || !mode_edid_bpp || !mode_pclk_khz) { 378 DRM_ERROR("invalid input\n"); 379 return 0; 380 } 381 382 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 383 384 if (msm_dp_panel->video_test) 385 bpp = msm_dp_link_bit_depth_to_bpp( 386 panel->link->test_video.test_bit_depth); 387 else 388 bpp = msm_dp_panel_get_supported_bpp(msm_dp_panel, mode_edid_bpp, 389 mode_pclk_khz); 390 391 return bpp; 392 } 393 394 static u8 msm_dp_panel_get_edid_checksum(const struct edid *edid) 395 { 396 edid += edid->extensions; 397 398 return edid->checksum; 399 } 400 401 void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel, 402 const struct drm_edid *drm_edid) 403 { 404 struct msm_dp_panel_private *panel; 405 406 if (!msm_dp_panel) { 407 DRM_ERROR("invalid input\n"); 408 return; 409 } 410 411 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 412 413 if (panel->link->sink_request & DP_TEST_LINK_EDID_READ) { 414 /* FIXME: get rid of drm_edid_raw() */ 415 const struct edid *edid = drm_edid_raw(drm_edid); 416 u8 checksum; 417 418 if (edid) 419 checksum = msm_dp_panel_get_edid_checksum(edid); 420 else 421 checksum = msm_dp_panel->connector->real_edid_checksum; 422 423 msm_dp_link_send_edid_checksum(panel->link, checksum); 424 msm_dp_link_send_test_response(panel->link); 425 } 426 } 427 428 static void msm_dp_panel_tpg_enable(struct msm_dp_panel *msm_dp_panel, 429 struct drm_display_mode *drm_mode) 430 { 431 struct msm_dp_panel_private *panel = 432 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 433 u32 hsync_period, vsync_period; 434 u32 display_v_start, display_v_end; 435 u32 hsync_start_x, hsync_end_x; 436 u32 v_sync_width; 437 u32 hsync_ctl; 438 u32 display_hctl; 439 440 /* TPG config parameters*/ 441 hsync_period = drm_mode->htotal; 442 vsync_period = drm_mode->vtotal; 443 444 display_v_start = ((drm_mode->vtotal - drm_mode->vsync_start) * 445 hsync_period); 446 display_v_end = ((vsync_period - (drm_mode->vsync_start - 447 drm_mode->vdisplay)) 448 * hsync_period) - 1; 449 450 display_v_start += drm_mode->htotal - drm_mode->hsync_start; 451 display_v_end -= (drm_mode->hsync_start - drm_mode->hdisplay); 452 453 hsync_start_x = drm_mode->htotal - drm_mode->hsync_start; 454 hsync_end_x = hsync_period - (drm_mode->hsync_start - 455 drm_mode->hdisplay) - 1; 456 457 v_sync_width = drm_mode->vsync_end - drm_mode->vsync_start; 458 459 hsync_ctl = (hsync_period << 16) | 460 (drm_mode->hsync_end - drm_mode->hsync_start); 461 display_hctl = (hsync_end_x << 16) | hsync_start_x; 462 463 464 msm_dp_write_pn(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); 465 msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * 466 hsync_period); 467 msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * 468 hsync_period); 469 msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); 470 msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); 471 msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); 472 msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); 473 msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); 474 msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); 475 msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); 476 msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); 477 msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); 478 msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); 479 msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); 480 msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); 481 msm_dp_write_pn(panel, MMSS_DP_INTF_POLARITY_CTL, 0); 482 483 msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, 484 DP_TPG_CHECKERED_RECT_PATTERN); 485 msm_dp_write_pn(panel, MMSS_DP_TPG_VIDEO_CONFIG, 486 DP_TPG_VIDEO_CONFIG_BPP_8BIT | 487 DP_TPG_VIDEO_CONFIG_RGB); 488 msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, 489 DP_BIST_ENABLE_DPBIST_EN); 490 msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, 491 DP_TIMING_ENGINE_EN_EN); 492 drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__); 493 } 494 495 static void msm_dp_panel_tpg_disable(struct msm_dp_panel *msm_dp_panel) 496 { 497 struct msm_dp_panel_private *panel = 498 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 499 500 msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); 501 msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, 0x0); 502 msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); 503 } 504 505 void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable) 506 { 507 struct msm_dp_panel_private *panel; 508 509 if (!msm_dp_panel) { 510 DRM_ERROR("invalid input\n"); 511 return; 512 } 513 514 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 515 516 if (!panel->panel_on) { 517 drm_dbg_dp(panel->drm_dev, 518 "DP panel not enabled, handle TPG on next on\n"); 519 return; 520 } 521 522 if (!enable) { 523 msm_dp_panel_tpg_disable(msm_dp_panel); 524 return; 525 } 526 527 drm_dbg_dp(panel->drm_dev, "calling panel's tpg_enable\n"); 528 msm_dp_panel_tpg_enable(msm_dp_panel, &panel->msm_dp_panel.msm_dp_mode.drm_mode); 529 } 530 531 void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel) 532 { 533 struct msm_dp_panel_private *panel = 534 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 535 536 msm_dp_write_pn(panel, MMSS_DP_DSC_DTO, 0x0); 537 } 538 539 static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct dp_sdp *vsc_sdp) 540 { 541 u32 header[2]; 542 u32 val; 543 int i; 544 545 msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); 546 547 msm_dp_write_link(panel, MMSS_DP_GENERIC0_0, header[0]); 548 msm_dp_write_link(panel, MMSS_DP_GENERIC0_1, header[1]); 549 550 for (i = 0; i < sizeof(vsc_sdp->db); i += 4) { 551 val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) | 552 (vsc_sdp->db[i + 3] << 24)); 553 msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i, val); 554 } 555 } 556 557 static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) 558 { 559 u32 hw_revision = panel->msm_dp_panel.hw_revision; 560 561 if (hw_revision >= DP_HW_VERSION_1_0 && 562 hw_revision < DP_HW_VERSION_1_2) { 563 msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, UPDATE_SDP); 564 msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, 0x0); 565 } 566 } 567 568 void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sdp *vsc_sdp) 569 { 570 struct msm_dp_panel_private *panel = 571 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 572 u32 cfg, cfg2, misc; 573 574 cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG); 575 cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); 576 misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0); 577 578 cfg |= GEN0_SDP_EN; 579 msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); 580 581 cfg2 |= GENERIC0_SDPSIZE_VALID; 582 msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); 583 584 msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); 585 586 /* indicates presence of VSC (BIT(6) of MISC1) */ 587 misc |= DP_MISC1_VSC_SDP; 588 589 drm_dbg_dp(panel->drm_dev, "vsc sdp enable=1\n"); 590 591 pr_debug("misc settings = 0x%x\n", misc); 592 msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); 593 594 msm_dp_panel_update_sdp(panel); 595 } 596 597 void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) 598 { 599 struct msm_dp_panel_private *panel = 600 container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 601 u32 cfg, cfg2, misc; 602 603 cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG); 604 cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); 605 misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0); 606 607 cfg &= ~GEN0_SDP_EN; 608 msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); 609 610 cfg2 &= ~GENERIC0_SDPSIZE_VALID; 611 msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); 612 613 /* switch back to MSA */ 614 misc &= ~DP_MISC1_VSC_SDP; 615 616 drm_dbg_dp(panel->drm_dev, "vsc sdp enable=0\n"); 617 618 pr_debug("misc settings = 0x%x\n", misc); 619 msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); 620 621 msm_dp_panel_update_sdp(panel); 622 } 623 624 static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_panel) 625 { 626 struct msm_dp_display_mode *msm_dp_mode; 627 struct drm_dp_vsc_sdp vsc_sdp_data; 628 struct dp_sdp vsc_sdp; 629 ssize_t len; 630 631 if (!msm_dp_panel) { 632 DRM_ERROR("invalid input\n"); 633 return -EINVAL; 634 } 635 636 msm_dp_mode = &msm_dp_panel->msm_dp_mode; 637 638 memset(&vsc_sdp_data, 0, sizeof(vsc_sdp_data)); 639 640 /* VSC SDP header as per table 2-118 of DP 1.4 specification */ 641 vsc_sdp_data.sdp_type = DP_SDP_VSC; 642 vsc_sdp_data.revision = 0x05; 643 vsc_sdp_data.length = 0x13; 644 645 /* VSC SDP Payload for DB16 */ 646 vsc_sdp_data.pixelformat = DP_PIXELFORMAT_YUV420; 647 vsc_sdp_data.colorimetry = DP_COLORIMETRY_DEFAULT; 648 649 /* VSC SDP Payload for DB17 */ 650 vsc_sdp_data.bpc = msm_dp_mode->bpp / 3; 651 vsc_sdp_data.dynamic_range = DP_DYNAMIC_RANGE_CTA; 652 653 /* VSC SDP Payload for DB18 */ 654 vsc_sdp_data.content_type = DP_CONTENT_TYPE_GRAPHICS; 655 656 len = drm_dp_vsc_sdp_pack(&vsc_sdp_data, &vsc_sdp); 657 if (len < 0) { 658 DRM_ERROR("unable to pack vsc sdp\n"); 659 return len; 660 } 661 662 msm_dp_panel_enable_vsc_sdp(msm_dp_panel, &vsc_sdp); 663 664 return 0; 665 } 666 667 int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) 668 { 669 u32 data, total_ver, total_hor; 670 struct msm_dp_panel_private *panel; 671 struct drm_display_mode *drm_mode; 672 u32 width_blanking; 673 u32 sync_start; 674 u32 msm_dp_active; 675 u32 total; 676 u32 reg; 677 678 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 679 drm_mode = &panel->msm_dp_panel.msm_dp_mode.drm_mode; 680 681 drm_dbg_dp(panel->drm_dev, "width=%d hporch= %d %d %d\n", 682 drm_mode->hdisplay, drm_mode->htotal - drm_mode->hsync_end, 683 drm_mode->hsync_start - drm_mode->hdisplay, 684 drm_mode->hsync_end - drm_mode->hsync_start); 685 686 drm_dbg_dp(panel->drm_dev, "height=%d vporch= %d %d %d\n", 687 drm_mode->vdisplay, drm_mode->vtotal - drm_mode->vsync_end, 688 drm_mode->vsync_start - drm_mode->vdisplay, 689 drm_mode->vsync_end - drm_mode->vsync_start); 690 691 total_hor = drm_mode->htotal; 692 693 total_ver = drm_mode->vtotal; 694 695 data = total_ver; 696 data <<= 16; 697 data |= total_hor; 698 699 total = data; 700 701 data = (drm_mode->vtotal - drm_mode->vsync_start); 702 data <<= 16; 703 data |= (drm_mode->htotal - drm_mode->hsync_start); 704 705 sync_start = data; 706 707 data = drm_mode->vsync_end - drm_mode->vsync_start; 708 data <<= 16; 709 data |= (panel->msm_dp_panel.msm_dp_mode.v_active_low << 31); 710 data |= drm_mode->hsync_end - drm_mode->hsync_start; 711 data |= (panel->msm_dp_panel.msm_dp_mode.h_active_low << 15); 712 713 width_blanking = data; 714 715 data = drm_mode->vdisplay; 716 data <<= 16; 717 data |= drm_mode->hdisplay; 718 719 msm_dp_active = data; 720 721 msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER, total); 722 msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); 723 msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking); 724 msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active); 725 726 reg = msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); 727 if (wide_bus_en) 728 reg |= DP_INTF_CONFIG_DATABUS_WIDEN; 729 else 730 reg &= ~DP_INTF_CONFIG_DATABUS_WIDEN; 731 732 drm_dbg_dp(panel->drm_dev, "wide_bus_en=%d reg=%#x\n", wide_bus_en, reg); 733 734 msm_dp_write_pn(panel, MMSS_DP_INTF_CONFIG, reg); 735 736 if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) 737 msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); 738 739 panel->panel_on = true; 740 741 return 0; 742 } 743 744 int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel, 745 const struct drm_display_mode *adjusted_mode, 746 u32 bpp) 747 { 748 struct drm_display_mode *drm_mode; 749 struct msm_dp_panel_private *panel; 750 751 panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 752 753 drm_mode_copy(&msm_dp_panel->msm_dp_mode.drm_mode, adjusted_mode); 754 msm_dp_panel->msm_dp_mode.bpp = bpp; 755 msm_dp_panel->msm_dp_mode.v_active_low = 756 !!(adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC); 757 msm_dp_panel->msm_dp_mode.h_active_low = 758 !!(adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC); 759 msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 = 760 drm_mode_is_420_only(&msm_dp_panel->connector->display_info, adjusted_mode) && 761 msm_dp_panel->vsc_sdp_supported; 762 763 drm_mode = &msm_dp_panel->msm_dp_mode.drm_mode; 764 765 /* 766 * print resolution info as this is a result 767 * of user initiated action of cable connection 768 */ 769 drm_dbg_dp(panel->drm_dev, "SET NEW RESOLUTION:\n"); 770 drm_dbg_dp(panel->drm_dev, "%dx%d@%dfps\n", 771 drm_mode->hdisplay, drm_mode->vdisplay, drm_mode_vrefresh(drm_mode)); 772 drm_dbg_dp(panel->drm_dev, 773 "h_porches(back|front|width) = (%d|%d|%d)\n", 774 drm_mode->htotal - drm_mode->hsync_end, 775 drm_mode->hsync_start - drm_mode->hdisplay, 776 drm_mode->hsync_end - drm_mode->hsync_start); 777 drm_dbg_dp(panel->drm_dev, 778 "v_porches(back|front|width) = (%d|%d|%d)\n", 779 drm_mode->vtotal - drm_mode->vsync_end, 780 drm_mode->vsync_start - drm_mode->vdisplay, 781 drm_mode->vsync_end - drm_mode->vsync_start); 782 drm_dbg_dp(panel->drm_dev, "pixel clock (KHz)=(%d)\n", 783 drm_mode->clock); 784 drm_dbg_dp(panel->drm_dev, "bpp = %d\n", msm_dp_panel->msm_dp_mode.bpp); 785 786 msm_dp_panel->msm_dp_mode.bpp = msm_dp_panel_get_mode_bpp(msm_dp_panel, msm_dp_panel->msm_dp_mode.bpp, 787 msm_dp_panel->msm_dp_mode.drm_mode.clock); 788 789 drm_dbg_dp(panel->drm_dev, "updated bpp = %d\n", 790 msm_dp_panel->msm_dp_mode.bpp); 791 792 return 0; 793 } 794 795 struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, 796 struct msm_dp_link *link, 797 void __iomem *link_base, 798 void __iomem *mst2link_base, 799 void __iomem *mst3link_base, 800 void __iomem *pixel_base) 801 { 802 struct msm_dp_panel_private *panel; 803 struct msm_dp_panel *msm_dp_panel; 804 805 if (!dev || !aux || !link) { 806 DRM_ERROR("invalid input\n"); 807 return ERR_PTR(-EINVAL); 808 } 809 810 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 811 if (!panel) 812 return ERR_PTR(-ENOMEM); 813 814 panel->dev = dev; 815 panel->aux = aux; 816 panel->link = link; 817 panel->link_base = link_base; 818 panel->pixel_base = pixel_base; 819 panel->mst2link_base = mst2link_base; 820 panel->mst3link_base = mst3link_base; 821 822 msm_dp_panel = &panel->msm_dp_panel; 823 msm_dp_panel->max_bw_code = DP_LINK_BW_8_1; 824 msm_dp_panel->stream_id = DP_STREAM_0; 825 826 return msm_dp_panel; 827 } 828 829