1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27
28 #include "core_types.h"
29 #include "link_encoder.h"
30 #include "dce_link_encoder.h"
31 #include "stream_encoder.h"
32 #include "dc_bios_types.h"
33
34 #include "gpio_service_interface.h"
35
36 #include "dce/dce_11_0_d.h"
37 #include "dce/dce_11_0_sh_mask.h"
38 #include "dce/dce_11_0_enum.h"
39
40 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT
41 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa
42 #endif
43
44 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK
45 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L
46 #endif
47
48 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK
49 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L
50 #endif
51
52 #ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT
53 #define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
54 #endif
55
56 #define CTX \
57 enc110->base.ctx
58 #define DC_LOGGER \
59 enc110->base.ctx->logger
60
61 #define REG(reg)\
62 (enc110->link_regs->reg)
63
64 #define AUX_REG(reg)\
65 (enc110->aux_regs->reg)
66
67 #define HPD_REG(reg)\
68 (enc110->hpd_regs->reg)
69
70 #define DEFAULT_AUX_MAX_DATA_SIZE 16
71 #define AUX_MAX_DEFER_WRITE_RETRY 20
72 /*
73 * @brief
74 * Trigger Source Select
75 * ASIC-dependent, actual values for register programming
76 */
77 #define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0
78 #define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1
79 #define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2
80 #define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4
81 #define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08
82 #define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10
83 #define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
84 #define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40
85
86 enum {
87 DP_MST_UPDATE_MAX_RETRY = 50
88 };
89
90 #define DIG_REG(reg)\
91 (reg + enc110->offsets.dig)
92
93 #define DP_REG(reg)\
94 (reg + enc110->offsets.dp)
95
96 static const struct link_encoder_funcs dce110_lnk_enc_funcs = {
97 .validate_output_with_stream =
98 dce110_link_encoder_validate_output_with_stream,
99 .hw_init = dce110_link_encoder_hw_init,
100 .setup = dce110_link_encoder_setup,
101 .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
102 .enable_dp_output = dce110_link_encoder_enable_dp_output,
103 .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
104 .enable_lvds_output = dce110_link_encoder_enable_lvds_output,
105 .enable_analog_output = dce110_link_encoder_enable_analog_output,
106 .disable_output = dce110_link_encoder_disable_output,
107 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
108 .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
109 .update_mst_stream_allocation_table =
110 dce110_link_encoder_update_mst_stream_allocation_table,
111 .psr_program_dp_dphy_fast_training =
112 dce110_psr_program_dp_dphy_fast_training,
113 .psr_program_secondary_packet = dce110_psr_program_secondary_packet,
114 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
115 .enable_hpd = dce110_link_encoder_enable_hpd,
116 .disable_hpd = dce110_link_encoder_disable_hpd,
117 .is_dig_enabled = dce110_is_dig_enabled,
118 .destroy = dce110_link_encoder_destroy,
119 .get_max_link_cap = dce110_link_encoder_get_max_link_cap,
120 .get_dig_frontend = dce110_get_dig_frontend,
121 .get_hpd_state = dce110_get_hpd_state,
122 .program_hpd_filter = dce110_program_hpd_filter,
123 };
124
125 static const struct link_encoder_funcs dce110_lnk_enc_funcs_no_hpd = {
126 .validate_output_with_stream =
127 dce110_link_encoder_validate_output_with_stream,
128 .hw_init = dce110_link_encoder_hw_init,
129 .setup = dce110_link_encoder_setup,
130 .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
131 .enable_dp_output = dce110_link_encoder_enable_dp_output,
132 .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
133 .enable_lvds_output = dce110_link_encoder_enable_lvds_output,
134 .enable_analog_output = dce110_link_encoder_enable_analog_output,
135 .disable_output = dce110_link_encoder_disable_output,
136 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
137 .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
138 .update_mst_stream_allocation_table =
139 dce110_link_encoder_update_mst_stream_allocation_table,
140 .psr_program_dp_dphy_fast_training =
141 dce110_psr_program_dp_dphy_fast_training,
142 .psr_program_secondary_packet = dce110_psr_program_secondary_packet,
143 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
144 .is_dig_enabled = dce110_is_dig_enabled,
145 .destroy = dce110_link_encoder_destroy,
146 .get_max_link_cap = dce110_link_encoder_get_max_link_cap,
147 .get_dig_frontend = dce110_get_dig_frontend,
148 .get_hpd_state = dce110_get_hpd_state,
149 .program_hpd_filter = dce110_program_hpd_filter,
150 };
151
link_transmitter_control(struct dce110_link_encoder * enc110,struct bp_transmitter_control * cntl)152 static enum bp_result link_transmitter_control(
153 struct dce110_link_encoder *enc110,
154 struct bp_transmitter_control *cntl)
155 {
156 enum bp_result result;
157 struct dc_bios *bp = enc110->base.ctx->dc_bios;
158
159 result = bp->funcs->transmitter_control(bp, cntl);
160
161 return result;
162 }
163
link_dac_encoder_control(struct dce110_link_encoder * link_enc,enum bp_encoder_control_action action,uint32_t pix_clk_100hz)164 static enum bp_result link_dac_encoder_control(
165 struct dce110_link_encoder *link_enc,
166 enum bp_encoder_control_action action,
167 uint32_t pix_clk_100hz)
168 {
169 struct dc_bios *bios = link_enc->base.ctx->dc_bios;
170 struct bp_encoder_control encoder_control = {0};
171
172 encoder_control.action = action;
173 encoder_control.engine_id = link_enc->base.analog_engine;
174 encoder_control.pixel_clock = pix_clk_100hz / 10;
175
176 return bios->funcs->encoder_control(bios, &encoder_control);
177 }
178
enable_phy_bypass_mode(struct dce110_link_encoder * enc110,bool enable)179 static void enable_phy_bypass_mode(
180 struct dce110_link_encoder *enc110,
181 bool enable)
182 {
183 /* This register resides in DP back end block;
184 * transmitter is used for the offset */
185
186 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
187
188 }
189
disable_prbs_symbols(struct dce110_link_encoder * enc110,bool disable)190 static void disable_prbs_symbols(
191 struct dce110_link_encoder *enc110,
192 bool disable)
193 {
194 /* This register resides in DP back end block;
195 * transmitter is used for the offset */
196
197 REG_UPDATE_4(DP_DPHY_CNTL,
198 DPHY_ATEST_SEL_LANE0, disable,
199 DPHY_ATEST_SEL_LANE1, disable,
200 DPHY_ATEST_SEL_LANE2, disable,
201 DPHY_ATEST_SEL_LANE3, disable);
202 }
203
disable_prbs_mode(struct dce110_link_encoder * enc110)204 static void disable_prbs_mode(
205 struct dce110_link_encoder *enc110)
206 {
207 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
208 }
209
program_pattern_symbols(struct dce110_link_encoder * enc110,uint16_t pattern_symbols[8])210 static void program_pattern_symbols(
211 struct dce110_link_encoder *enc110,
212 uint16_t pattern_symbols[8])
213 {
214 /* This register resides in DP back end block;
215 * transmitter is used for the offset */
216
217 REG_SET_3(DP_DPHY_SYM0, 0,
218 DPHY_SYM1, pattern_symbols[0],
219 DPHY_SYM2, pattern_symbols[1],
220 DPHY_SYM3, pattern_symbols[2]);
221
222 /* This register resides in DP back end block;
223 * transmitter is used for the offset */
224
225 REG_SET_3(DP_DPHY_SYM1, 0,
226 DPHY_SYM4, pattern_symbols[3],
227 DPHY_SYM5, pattern_symbols[4],
228 DPHY_SYM6, pattern_symbols[5]);
229
230 /* This register resides in DP back end block;
231 * transmitter is used for the offset */
232
233 REG_SET_2(DP_DPHY_SYM2, 0,
234 DPHY_SYM7, pattern_symbols[6],
235 DPHY_SYM8, pattern_symbols[7]);
236 }
237
set_dp_phy_pattern_d102(struct dce110_link_encoder * enc110)238 static void set_dp_phy_pattern_d102(
239 struct dce110_link_encoder *enc110)
240 {
241 /* Disable PHY Bypass mode to setup the test pattern */
242 enable_phy_bypass_mode(enc110, false);
243
244 /* For 10-bit PRBS or debug symbols
245 * please use the following sequence: */
246
247 /* Enable debug symbols on the lanes */
248
249 disable_prbs_symbols(enc110, true);
250
251 /* Disable PRBS mode */
252 disable_prbs_mode(enc110);
253
254 /* Program debug symbols to be output */
255 {
256 uint16_t pattern_symbols[8] = {
257 0x2AA, 0x2AA, 0x2AA, 0x2AA,
258 0x2AA, 0x2AA, 0x2AA, 0x2AA
259 };
260
261 program_pattern_symbols(enc110, pattern_symbols);
262 }
263
264 /* Enable phy bypass mode to enable the test pattern */
265
266 enable_phy_bypass_mode(enc110, true);
267 }
268
set_link_training_complete(struct dce110_link_encoder * enc110,bool complete)269 static void set_link_training_complete(
270 struct dce110_link_encoder *enc110,
271 bool complete)
272 {
273 /* This register resides in DP back end block;
274 * transmitter is used for the offset */
275
276 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
277
278 }
279
dce110_get_dig_frontend(struct link_encoder * enc)280 unsigned int dce110_get_dig_frontend(struct link_encoder *enc)
281 {
282 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
283 u32 value;
284 enum engine_id result;
285
286 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
287
288 switch (value) {
289 case DCE110_DIG_FE_SOURCE_SELECT_DIGA:
290 result = ENGINE_ID_DIGA;
291 break;
292 case DCE110_DIG_FE_SOURCE_SELECT_DIGB:
293 result = ENGINE_ID_DIGB;
294 break;
295 case DCE110_DIG_FE_SOURCE_SELECT_DIGC:
296 result = ENGINE_ID_DIGC;
297 break;
298 case DCE110_DIG_FE_SOURCE_SELECT_DIGD:
299 result = ENGINE_ID_DIGD;
300 break;
301 case DCE110_DIG_FE_SOURCE_SELECT_DIGE:
302 result = ENGINE_ID_DIGE;
303 break;
304 case DCE110_DIG_FE_SOURCE_SELECT_DIGF:
305 result = ENGINE_ID_DIGF;
306 break;
307 case DCE110_DIG_FE_SOURCE_SELECT_DIGG:
308 result = ENGINE_ID_DIGG;
309 break;
310 default:
311 // invalid source select DIG
312 result = ENGINE_ID_UNKNOWN;
313 }
314
315 return result;
316 }
317
dce110_link_encoder_set_dp_phy_pattern_training_pattern(struct link_encoder * enc,uint32_t index)318 void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
319 struct link_encoder *enc,
320 uint32_t index)
321 {
322 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
323 /* Write Training Pattern */
324
325 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
326
327 /* Set HW Register Training Complete to false */
328
329 set_link_training_complete(enc110, false);
330
331 /* Disable PHY Bypass mode to output Training Pattern */
332
333 enable_phy_bypass_mode(enc110, false);
334
335 /* Disable PRBS mode */
336 disable_prbs_mode(enc110);
337 }
338
setup_panel_mode(struct dce110_link_encoder * enc110,enum dp_panel_mode panel_mode)339 static void setup_panel_mode(
340 struct dce110_link_encoder *enc110,
341 enum dp_panel_mode panel_mode)
342 {
343 uint32_t value;
344 struct dc_context *ctx = enc110->base.ctx;
345
346 /* if psp set panel mode, dal should be program it */
347 if (ctx->dc->caps.psp_setup_panel_mode)
348 return;
349
350 /* The code below is only applicable to encoders with a digital transmitter. */
351 if (enc110->base.transmitter == TRANSMITTER_UNKNOWN)
352 return;
353
354 ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
355 value = REG_READ(DP_DPHY_INTERNAL_CTRL);
356
357 switch (panel_mode) {
358 case DP_PANEL_MODE_EDP:
359 value = 0x1;
360 break;
361 case DP_PANEL_MODE_SPECIAL:
362 value = 0x11;
363 break;
364 default:
365 value = 0x0;
366 break;
367 }
368
369 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
370 }
371
set_dp_phy_pattern_symbol_error(struct dce110_link_encoder * enc110)372 static void set_dp_phy_pattern_symbol_error(
373 struct dce110_link_encoder *enc110)
374 {
375 /* Disable PHY Bypass mode to setup the test pattern */
376 enable_phy_bypass_mode(enc110, false);
377
378 /* program correct panel mode*/
379 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
380
381 /* A PRBS23 pattern is used for most DP electrical measurements. */
382
383 /* Enable PRBS symbols on the lanes */
384 disable_prbs_symbols(enc110, false);
385
386 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
387 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
388 DPHY_PRBS_SEL, 1,
389 DPHY_PRBS_EN, 1);
390
391 /* Enable phy bypass mode to enable the test pattern */
392 enable_phy_bypass_mode(enc110, true);
393 }
394
set_dp_phy_pattern_prbs7(struct dce110_link_encoder * enc110)395 static void set_dp_phy_pattern_prbs7(
396 struct dce110_link_encoder *enc110)
397 {
398 /* Disable PHY Bypass mode to setup the test pattern */
399 enable_phy_bypass_mode(enc110, false);
400
401 /* A PRBS7 pattern is used for most DP electrical measurements. */
402
403 /* Enable PRBS symbols on the lanes */
404 disable_prbs_symbols(enc110, false);
405
406 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
407 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
408 DPHY_PRBS_SEL, 0,
409 DPHY_PRBS_EN, 1);
410
411 /* Enable phy bypass mode to enable the test pattern */
412 enable_phy_bypass_mode(enc110, true);
413 }
414
set_dp_phy_pattern_80bit_custom(struct dce110_link_encoder * enc110,const uint8_t * pattern)415 static void set_dp_phy_pattern_80bit_custom(
416 struct dce110_link_encoder *enc110,
417 const uint8_t *pattern)
418 {
419 /* Disable PHY Bypass mode to setup the test pattern */
420 enable_phy_bypass_mode(enc110, false);
421
422 /* Enable debug symbols on the lanes */
423
424 disable_prbs_symbols(enc110, true);
425
426 /* Enable PHY bypass mode to enable the test pattern */
427 /* TODO is it really needed ? */
428
429 enable_phy_bypass_mode(enc110, true);
430
431 /* Program 80 bit custom pattern */
432 {
433 uint16_t pattern_symbols[8];
434
435 pattern_symbols[0] =
436 ((pattern[1] & 0x03) << 8) | pattern[0];
437 pattern_symbols[1] =
438 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
439 pattern_symbols[2] =
440 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
441 pattern_symbols[3] =
442 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
443 pattern_symbols[4] =
444 ((pattern[6] & 0x03) << 8) | pattern[5];
445 pattern_symbols[5] =
446 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
447 pattern_symbols[6] =
448 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
449 pattern_symbols[7] =
450 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
451
452 program_pattern_symbols(enc110, pattern_symbols);
453 }
454
455 /* Enable phy bypass mode to enable the test pattern */
456
457 enable_phy_bypass_mode(enc110, true);
458 }
459
set_dp_phy_pattern_hbr2_compliance_cp2520_2(struct dce110_link_encoder * enc110,unsigned int cp2520_pattern)460 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
461 struct dce110_link_encoder *enc110,
462 unsigned int cp2520_pattern)
463 {
464
465 /* previously there is a register DP_HBR2_EYE_PATTERN
466 * that is enabled to get the pattern.
467 * But it does not work with the latest spec change,
468 * so we are programming the following registers manually.
469 *
470 * The following settings have been confirmed
471 * by Nick Chorney and Sandra Liu */
472
473 /* Disable PHY Bypass mode to setup the test pattern */
474
475 enable_phy_bypass_mode(enc110, false);
476
477 /* Setup DIG encoder in DP SST mode */
478 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT);
479
480 /* ensure normal panel mode. */
481 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
482
483 /* no vbid after BS (SR)
484 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
485 * 11000260 / 11000104 / 110000FC */
486 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
487 DP_IDLE_BS_INTERVAL, 0xFC,
488 DP_VBID_DISABLE, 1,
489 DP_VID_ENHANCED_FRAME_MODE, 1);
490
491 /* swap every BS with SR */
492 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
493
494 /* select cp2520 patterns */
495 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
496 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
497 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
498 else
499 /* pre-DCE11 can only generate CP2520 pattern 2 */
500 ASSERT(cp2520_pattern == 2);
501
502 /* set link training complete */
503 set_link_training_complete(enc110, true);
504
505 /* disable video stream */
506 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
507
508 /* Disable PHY Bypass mode to setup the test pattern */
509 enable_phy_bypass_mode(enc110, false);
510 }
511
512 #if defined(CONFIG_DRM_AMD_DC_SI)
dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(struct dce110_link_encoder * enc110,unsigned int cp2520_pattern)513 static void dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(
514 struct dce110_link_encoder *enc110,
515 unsigned int cp2520_pattern)
516 {
517
518 /* previously there is a register DP_HBR2_EYE_PATTERN
519 * that is enabled to get the pattern.
520 * But it does not work with the latest spec change,
521 * so we are programming the following registers manually.
522 *
523 * The following settings have been confirmed
524 * by Nick Chorney and Sandra Liu */
525
526 /* Disable PHY Bypass mode to setup the test pattern */
527
528 enable_phy_bypass_mode(enc110, false);
529
530 /* Setup DIG encoder in DP SST mode */
531 enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT);
532
533 /* ensure normal panel mode. */
534 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
535
536 /* no vbid after BS (SR)
537 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
538 * 11000260 / 11000104 / 110000FC */
539 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
540 DP_IDLE_BS_INTERVAL, 0xFC,
541 DP_VBID_DISABLE, 1,
542 DP_VID_ENHANCED_FRAME_MODE, 1);
543
544 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip swap BS with SR */
545
546 /* select cp2520 patterns */
547 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
548 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
549 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
550 else
551 /* pre-DCE11 can only generate CP2520 pattern 2 */
552 ASSERT(cp2520_pattern == 2);
553
554 /* set link training complete */
555 set_link_training_complete(enc110, true);
556
557 /* disable video stream */
558 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
559
560 /* Disable PHY Bypass mode to setup the test pattern */
561 enable_phy_bypass_mode(enc110, false);
562 }
563 #endif
564
set_dp_phy_pattern_passthrough_mode(struct dce110_link_encoder * enc110,enum dp_panel_mode panel_mode)565 static void set_dp_phy_pattern_passthrough_mode(
566 struct dce110_link_encoder *enc110,
567 enum dp_panel_mode panel_mode)
568 {
569 /* program correct panel mode */
570 setup_panel_mode(enc110, panel_mode);
571
572 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
573 * in case we were doing HBR2 compliance pattern before
574 */
575 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
576 DP_IDLE_BS_INTERVAL, 0x2000,
577 DP_VBID_DISABLE, 0,
578 DP_VID_ENHANCED_FRAME_MODE, 1);
579
580 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
581
582 /* set link training complete */
583 set_link_training_complete(enc110, true);
584
585 /* Disable PHY Bypass mode to setup the test pattern */
586 enable_phy_bypass_mode(enc110, false);
587
588 /* Disable PRBS mode */
589 disable_prbs_mode(enc110);
590 }
591
592 #if defined(CONFIG_DRM_AMD_DC_SI)
dce60_set_dp_phy_pattern_passthrough_mode(struct dce110_link_encoder * enc110,enum dp_panel_mode panel_mode)593 static void dce60_set_dp_phy_pattern_passthrough_mode(
594 struct dce110_link_encoder *enc110,
595 enum dp_panel_mode panel_mode)
596 {
597 /* program correct panel mode */
598 setup_panel_mode(enc110, panel_mode);
599
600 /* restore LINK_FRAMING_CNTL
601 * in case we were doing HBR2 compliance pattern before
602 */
603 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
604 DP_IDLE_BS_INTERVAL, 0x2000,
605 DP_VBID_DISABLE, 0,
606 DP_VID_ENHANCED_FRAME_MODE, 1);
607
608 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip DPHY_SCRAMBLER_BS_COUNT restore */
609
610 /* set link training complete */
611 set_link_training_complete(enc110, true);
612
613 /* Disable PHY Bypass mode to setup the test pattern */
614 enable_phy_bypass_mode(enc110, false);
615
616 /* Disable PRBS mode */
617 disable_prbs_mode(enc110);
618 }
619 #endif
620
621 /* return value is bit-vector */
get_frontend_source(enum engine_id engine)622 static uint8_t get_frontend_source(
623 enum engine_id engine)
624 {
625 switch (engine) {
626 case ENGINE_ID_DIGA:
627 return DCE110_DIG_FE_SOURCE_SELECT_DIGA;
628 case ENGINE_ID_DIGB:
629 return DCE110_DIG_FE_SOURCE_SELECT_DIGB;
630 case ENGINE_ID_DIGC:
631 return DCE110_DIG_FE_SOURCE_SELECT_DIGC;
632 case ENGINE_ID_DIGD:
633 return DCE110_DIG_FE_SOURCE_SELECT_DIGD;
634 case ENGINE_ID_DIGE:
635 return DCE110_DIG_FE_SOURCE_SELECT_DIGE;
636 case ENGINE_ID_DIGF:
637 return DCE110_DIG_FE_SOURCE_SELECT_DIGF;
638 case ENGINE_ID_DIGG:
639 return DCE110_DIG_FE_SOURCE_SELECT_DIGG;
640 default:
641 ASSERT_CRITICAL(false);
642 return DCE110_DIG_FE_SOURCE_SELECT_INVALID;
643 }
644 }
645
configure_encoder(struct dce110_link_encoder * enc110,const struct dc_link_settings * link_settings)646 static void configure_encoder(
647 struct dce110_link_encoder *enc110,
648 const struct dc_link_settings *link_settings)
649 {
650 /* set number of lanes */
651
652 REG_SET(DP_CONFIG, 0,
653 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
654
655 /* setup scrambler */
656 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
657 }
658
659 #if defined(CONFIG_DRM_AMD_DC_SI)
dce60_configure_encoder(struct dce110_link_encoder * enc110,const struct dc_link_settings * link_settings)660 static void dce60_configure_encoder(
661 struct dce110_link_encoder *enc110,
662 const struct dc_link_settings *link_settings)
663 {
664 /* set number of lanes */
665
666 REG_SET(DP_CONFIG, 0,
667 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
668
669 /* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip setup scrambler */
670 }
671 #endif
672
aux_initialize(struct dce110_link_encoder * enc110)673 static void aux_initialize(
674 struct dce110_link_encoder *enc110)
675 {
676 struct dc_context *ctx = enc110->base.ctx;
677 enum hpd_source_id hpd_source = enc110->base.hpd_source;
678 uint32_t addr = AUX_REG(AUX_CONTROL);
679 uint32_t value = dm_read_reg(ctx, addr);
680
681 set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL);
682 set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN);
683 dm_write_reg(ctx, addr, value);
684
685 addr = AUX_REG(AUX_DPHY_RX_CONTROL0);
686 value = dm_read_reg(ctx, addr);
687
688 /* 1/4 window (the maximum allowed) */
689 set_reg_field_value(value, 1,
690 AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW);
691 dm_write_reg(ctx, addr, value);
692
693 }
694
dce110_psr_program_dp_dphy_fast_training(struct link_encoder * enc,bool exit_link_training_required)695 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
696 bool exit_link_training_required)
697 {
698 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
699
700 if (exit_link_training_required)
701 REG_UPDATE(DP_DPHY_FAST_TRAINING,
702 DPHY_RX_FAST_TRAINING_CAPABLE, 1);
703 else {
704 REG_UPDATE(DP_DPHY_FAST_TRAINING,
705 DPHY_RX_FAST_TRAINING_CAPABLE, 0);
706 /*In DCE 11, we are able to pre-program a Force SR register
707 * to be able to trigger SR symbol after 5 idle patterns
708 * transmitted. Upon PSR Exit, DMCU can trigger
709 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
710 * DPHY_LOAD_BS_COUNT_START and the internal counter
711 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
712 * replaced by SR symbol once.
713 */
714
715 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
716 }
717 }
718
dce110_psr_program_secondary_packet(struct link_encoder * enc,unsigned int sdp_transmit_line_num_deadline)719 void dce110_psr_program_secondary_packet(struct link_encoder *enc,
720 unsigned int sdp_transmit_line_num_deadline)
721 {
722 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
723
724 REG_UPDATE_2(DP_SEC_CNTL1,
725 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
726 DP_SEC_GSP0_PRIORITY, 1);
727 }
728
dce110_is_dig_enabled(struct link_encoder * enc)729 bool dce110_is_dig_enabled(struct link_encoder *enc)
730 {
731 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
732 uint32_t value;
733
734 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
735 return value;
736 }
737
link_encoder_disable(struct dce110_link_encoder * enc110)738 static void link_encoder_disable(struct dce110_link_encoder *enc110)
739 {
740 /* reset training pattern */
741 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
742 DPHY_TRAINING_PATTERN_SEL, 0);
743
744 /* reset training complete */
745 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
746
747 /* reset panel mode */
748 setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
749 }
750
hpd_initialize(struct dce110_link_encoder * enc110)751 static void hpd_initialize(
752 struct dce110_link_encoder *enc110)
753 {
754 /* Associate HPD with DIG_BE */
755 enum hpd_source_id hpd_source = enc110->base.hpd_source;
756
757 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
758 }
759
dce110_link_encoder_validate_dvi_output(const struct dce110_link_encoder * enc110,enum signal_type connector_signal,enum signal_type signal,const struct dc_crtc_timing * crtc_timing)760 bool dce110_link_encoder_validate_dvi_output(
761 const struct dce110_link_encoder *enc110,
762 enum signal_type connector_signal,
763 enum signal_type signal,
764 const struct dc_crtc_timing *crtc_timing)
765 {
766 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
767
768 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
769 max_pixel_clock *= 2;
770
771 /* This handles the case of HDMI downgrade to DVI we don't want to
772 * we don't want to cap the pixel clock if the DDI is not DVI.
773 */
774 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
775 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
776 max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock;
777
778 /* DVI only support RGB pixel encoding */
779 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
780 return false;
781
782 /*connect DVI via adpater's HDMI connector*/
783 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
784 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
785 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
786 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10))
787 return false;
788 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
789 return false;
790
791 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
792 return false;
793
794 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
795 switch (crtc_timing->display_color_depth) {
796 case COLOR_DEPTH_666:
797 case COLOR_DEPTH_888:
798 break;
799 case COLOR_DEPTH_101010:
800 case COLOR_DEPTH_161616:
801 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
802 return false;
803 break;
804 default:
805 return false;
806 }
807
808 return true;
809 }
810
dce110_link_encoder_validate_hdmi_output(const struct dce110_link_encoder * enc110,const struct dc_crtc_timing * crtc_timing,int adjusted_pix_clk_khz)811 static bool dce110_link_encoder_validate_hdmi_output(
812 const struct dce110_link_encoder *enc110,
813 const struct dc_crtc_timing *crtc_timing,
814 int adjusted_pix_clk_khz)
815 {
816 enum dc_color_depth max_deep_color =
817 enc110->base.features.max_hdmi_deep_color;
818
819 if (max_deep_color < crtc_timing->display_color_depth)
820 return false;
821
822 if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
823 return false;
824 if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
825 return false;
826
827 if ((adjusted_pix_clk_khz == 0) ||
828 (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock))
829 return false;
830
831 /* DCE11 HW does not support 420 */
832 if (!enc110->base.features.hdmi_ycbcr420_supported &&
833 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
834 return false;
835
836 if ((!enc110->base.features.flags.bits.HDMI_6GB_EN ||
837 enc110->base.ctx->dc->debug.hdmi20_disable) &&
838 adjusted_pix_clk_khz >= 300000)
839 return false;
840 if (enc110->base.ctx->dc->debug.hdmi20_disable &&
841 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
842 return false;
843 return true;
844 }
845
dce110_link_encoder_validate_dp_output(const struct dce110_link_encoder * enc110,const struct dc_crtc_timing * crtc_timing)846 bool dce110_link_encoder_validate_dp_output(
847 const struct dce110_link_encoder *enc110,
848 const struct dc_crtc_timing *crtc_timing)
849 {
850 (void)enc110;
851 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
852 return false;
853
854 return true;
855 }
856
dce110_link_encoder_validate_rgb_output(const struct dce110_link_encoder * enc110,const struct dc_crtc_timing * crtc_timing)857 static bool dce110_link_encoder_validate_rgb_output(
858 const struct dce110_link_encoder *enc110,
859 const struct dc_crtc_timing *crtc_timing)
860 {
861 /* When the VBIOS doesn't specify any limits, use 400 MHz.
862 * The value comes from amdgpu_atombios_get_clock_info.
863 */
864 uint32_t max_pixel_clock_khz = 400000;
865
866 if (enc110->base.ctx->dc_bios->fw_info_valid &&
867 enc110->base.ctx->dc_bios->fw_info.max_pixel_clock) {
868 max_pixel_clock_khz =
869 enc110->base.ctx->dc_bios->fw_info.max_pixel_clock;
870 }
871
872 if (crtc_timing->pix_clk_100hz > max_pixel_clock_khz * 10)
873 return false;
874
875 if (crtc_timing->display_color_depth != COLOR_DEPTH_888)
876 return false;
877
878 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
879 return false;
880
881 return true;
882 }
883
dce110_link_encoder_construct(struct dce110_link_encoder * enc110,const struct encoder_init_data * init_data,const struct encoder_feature_support * enc_features,const struct dce110_link_enc_registers * link_regs,const struct dce110_link_enc_aux_registers * aux_regs,const struct dce110_link_enc_hpd_registers * hpd_regs)884 void dce110_link_encoder_construct(
885 struct dce110_link_encoder *enc110,
886 const struct encoder_init_data *init_data,
887 const struct encoder_feature_support *enc_features,
888 const struct dce110_link_enc_registers *link_regs,
889 const struct dce110_link_enc_aux_registers *aux_regs,
890 const struct dce110_link_enc_hpd_registers *hpd_regs)
891 {
892 struct bp_encoder_cap_info bp_cap_info = {0};
893 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
894 enum bp_result result = BP_RESULT_OK;
895
896 if (hpd_regs)
897 enc110->base.funcs = &dce110_lnk_enc_funcs;
898 else
899 enc110->base.funcs = &dce110_lnk_enc_funcs_no_hpd;
900 enc110->base.ctx = init_data->ctx;
901 enc110->base.id = init_data->encoder;
902 enc110->base.analog_id = init_data->analog_encoder;
903
904 enc110->base.hpd_gpio = init_data->hpd_gpio;
905 enc110->base.hpd_source = init_data->hpd_source;
906 enc110->base.connector = init_data->connector;
907
908 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
909 enc110->base.analog_engine = init_data->analog_engine;
910
911 enc110->base.features = *enc_features;
912
913 enc110->base.transmitter = init_data->transmitter;
914
915 /* set the flag to indicate whether driver poll the I2C data pin
916 * while doing the DP sink detect
917 */
918
919 /* if (dal_adapter_service_is_feature_supported(as,
920 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
921 enc110->base.features.flags.bits.
922 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
923
924 enc110->base.output_signals =
925 SIGNAL_TYPE_DVI_SINGLE_LINK |
926 SIGNAL_TYPE_DVI_DUAL_LINK |
927 SIGNAL_TYPE_LVDS |
928 SIGNAL_TYPE_DISPLAY_PORT |
929 SIGNAL_TYPE_DISPLAY_PORT_MST |
930 SIGNAL_TYPE_EDP |
931 SIGNAL_TYPE_HDMI_TYPE_A;
932
933 if ((enc110->base.connector.id == CONNECTOR_ID_DUAL_LINK_DVII ||
934 enc110->base.connector.id == CONNECTOR_ID_SINGLE_LINK_DVII) &&
935 enc110->base.analog_engine != ENGINE_ID_UNKNOWN)
936 enc110->base.output_signals |= SIGNAL_TYPE_RGB;
937
938 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
939 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
940 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
941 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
942 * Prefer DIG assignment is decided by board design.
943 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
944 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
945 * By this, adding DIGG should not hurt DCE 8.0.
946 * This will let DCE 8.1 share DCE 8.0 as much as possible
947 */
948
949 enc110->link_regs = link_regs;
950 enc110->aux_regs = aux_regs;
951 enc110->hpd_regs = hpd_regs;
952
953 switch (enc110->base.transmitter) {
954 case TRANSMITTER_UNIPHY_A:
955 enc110->base.preferred_engine = ENGINE_ID_DIGA;
956 break;
957 case TRANSMITTER_UNIPHY_B:
958 enc110->base.preferred_engine = ENGINE_ID_DIGB;
959 break;
960 case TRANSMITTER_UNIPHY_C:
961 enc110->base.preferred_engine = ENGINE_ID_DIGC;
962 break;
963 case TRANSMITTER_UNIPHY_D:
964 enc110->base.preferred_engine = ENGINE_ID_DIGD;
965 break;
966 case TRANSMITTER_UNIPHY_E:
967 enc110->base.preferred_engine = ENGINE_ID_DIGE;
968 break;
969 case TRANSMITTER_UNIPHY_F:
970 enc110->base.preferred_engine = ENGINE_ID_DIGF;
971 break;
972 case TRANSMITTER_UNIPHY_G:
973 enc110->base.preferred_engine = ENGINE_ID_DIGG;
974 break;
975 default:
976 if (init_data->analog_engine != ENGINE_ID_UNKNOWN) {
977 /* The connector is analog-only, ie. VGA */
978 enc110->base.preferred_engine = init_data->analog_engine;
979 enc110->base.output_signals = SIGNAL_TYPE_RGB;
980 enc110->base.transmitter = TRANSMITTER_UNKNOWN;
981 break;
982 }
983 ASSERT_CRITICAL(false);
984 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
985 }
986
987 /* default to one to mirror Windows behavior */
988 enc110->base.features.flags.bits.HDMI_6GB_EN = 1;
989
990 result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios,
991 enc110->base.id, &bp_cap_info);
992
993 /* Override features with DCE-specific values */
994 if (result == BP_RESULT_OK) {
995 enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
996 bp_cap_info.DP_HBR2_EN;
997 enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
998 bp_cap_info.DP_HBR3_EN;
999 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
1000 } else if (result != BP_RESULT_NORECORD) {
1001 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
1002 __func__,
1003 result);
1004 }
1005 if (enc110->base.ctx->dc->debug.hdmi20_disable) {
1006 enc110->base.features.flags.bits.HDMI_6GB_EN = 0;
1007 }
1008 }
1009
dce110_link_encoder_validate_output_with_stream(struct link_encoder * enc,const struct dc_stream_state * stream)1010 bool dce110_link_encoder_validate_output_with_stream(
1011 struct link_encoder *enc,
1012 const struct dc_stream_state *stream)
1013 {
1014 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1015 bool is_valid;
1016
1017 switch (stream->signal) {
1018 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1019 case SIGNAL_TYPE_DVI_DUAL_LINK:
1020 is_valid = dce110_link_encoder_validate_dvi_output(
1021 enc110,
1022 stream->link->connector_signal,
1023 stream->signal,
1024 &stream->timing);
1025 break;
1026 case SIGNAL_TYPE_HDMI_TYPE_A:
1027 is_valid = dce110_link_encoder_validate_hdmi_output(
1028 enc110,
1029 &stream->timing,
1030 stream->phy_pix_clk);
1031 break;
1032 case SIGNAL_TYPE_DISPLAY_PORT:
1033 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1034 is_valid = dce110_link_encoder_validate_dp_output(
1035 enc110, &stream->timing);
1036 break;
1037 case SIGNAL_TYPE_RGB:
1038 is_valid = dce110_link_encoder_validate_rgb_output(
1039 enc110, &stream->timing);
1040 break;
1041 case SIGNAL_TYPE_EDP:
1042 case SIGNAL_TYPE_LVDS:
1043 is_valid = stream->timing.pixel_encoding == PIXEL_ENCODING_RGB;
1044 break;
1045 case SIGNAL_TYPE_VIRTUAL:
1046 is_valid = true;
1047 break;
1048 default:
1049 is_valid = false;
1050 break;
1051 }
1052
1053 return is_valid;
1054 }
1055
dce110_link_encoder_hw_init(struct link_encoder * enc)1056 void dce110_link_encoder_hw_init(
1057 struct link_encoder *enc)
1058 {
1059 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1060 struct bp_transmitter_control cntl = { 0 };
1061 enum bp_result result;
1062
1063 cntl.action = TRANSMITTER_CONTROL_INIT;
1064 cntl.engine_id = ENGINE_ID_UNKNOWN;
1065 cntl.transmitter = enc110->base.transmitter;
1066 cntl.connector_obj_id = enc110->base.connector;
1067 cntl.lanes_number = LANE_COUNT_FOUR;
1068 cntl.coherent = false;
1069 cntl.hpd_sel = enc110->base.hpd_source;
1070
1071 if (enc110->base.analog_engine != ENGINE_ID_UNKNOWN) {
1072 result = link_dac_encoder_control(enc110, ENCODER_CONTROL_INIT, 0);
1073 if (result != BP_RESULT_OK) {
1074 DC_LOG_ERROR("%s: Failed to execute VBIOS command table for DAC!\n",
1075 __func__);
1076 BREAK_TO_DEBUGGER();
1077 return;
1078 }
1079 }
1080
1081 /* The code below is only applicable to encoders with a digital transmitter. */
1082 if (enc110->base.transmitter == TRANSMITTER_UNKNOWN)
1083 return;
1084
1085 if (enc110->base.connector.id == CONNECTOR_ID_EDP)
1086 cntl.signal = SIGNAL_TYPE_EDP;
1087
1088 result = link_transmitter_control(enc110, &cntl);
1089
1090 if (result != BP_RESULT_OK) {
1091 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1092 __func__);
1093 BREAK_TO_DEBUGGER();
1094 return;
1095 }
1096
1097 if (enc110->base.connector.id == CONNECTOR_ID_LVDS) {
1098 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
1099
1100 result = link_transmitter_control(enc110, &cntl);
1101
1102 ASSERT(result == BP_RESULT_OK);
1103
1104 }
1105
1106 if (enc110->aux_regs)
1107 aux_initialize(enc110);
1108
1109 /* reinitialize HPD.
1110 * hpd_initialize() will pass DIG_FE id to HW context.
1111 * All other routine within HW context will use fe_engine_offset
1112 * as DIG_FE id even caller pass DIG_FE id.
1113 * So this routine must be called first. */
1114 hpd_initialize(enc110);
1115 }
1116
dce110_link_encoder_destroy(struct link_encoder ** enc)1117 void dce110_link_encoder_destroy(struct link_encoder **enc)
1118 {
1119 if ((*enc)->hpd_gpio) {
1120 dal_gpio_destroy_irq(&(*enc)->hpd_gpio);
1121 (*enc)->hpd_gpio = NULL;
1122 }
1123
1124 kfree(TO_DCE110_LINK_ENC(*enc));
1125 *enc = NULL;
1126 }
1127
dce110_link_encoder_setup(struct link_encoder * enc,enum signal_type signal)1128 void dce110_link_encoder_setup(
1129 struct link_encoder *enc,
1130 enum signal_type signal)
1131 {
1132 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1133
1134 switch (signal) {
1135 case SIGNAL_TYPE_EDP:
1136 case SIGNAL_TYPE_DISPLAY_PORT:
1137 /* DP SST */
1138 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
1139 break;
1140 case SIGNAL_TYPE_LVDS:
1141 /* LVDS */
1142 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
1143 break;
1144 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1145 case SIGNAL_TYPE_DVI_DUAL_LINK:
1146 /* TMDS-DVI */
1147 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
1148 break;
1149 case SIGNAL_TYPE_HDMI_TYPE_A:
1150 /* TMDS-HDMI */
1151 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
1152 break;
1153 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1154 /* DP MST */
1155 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
1156 break;
1157 case SIGNAL_TYPE_RGB:
1158 break;
1159 default:
1160 ASSERT_CRITICAL(false);
1161 /* invalid mode ! */
1162 break;
1163 }
1164
1165 }
1166
1167 /* TODO: still need depth or just pass in adjusted pixel clock? */
dce110_link_encoder_enable_tmds_output(struct link_encoder * enc,enum clock_source_id clock_source,enum dc_color_depth color_depth,enum signal_type signal,uint32_t pixel_clock)1168 void dce110_link_encoder_enable_tmds_output(
1169 struct link_encoder *enc,
1170 enum clock_source_id clock_source,
1171 enum dc_color_depth color_depth,
1172 enum signal_type signal,
1173 uint32_t pixel_clock)
1174 {
1175 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1176 struct bp_transmitter_control cntl = { 0 };
1177 enum bp_result result;
1178
1179 /* Enable the PHY */
1180 cntl.connector_obj_id = enc110->base.connector;
1181 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1182 cntl.engine_id = enc->preferred_engine;
1183 cntl.transmitter = enc110->base.transmitter;
1184 cntl.pll_id = clock_source;
1185 cntl.signal = signal;
1186 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
1187 cntl.lanes_number = 8;
1188 else
1189 cntl.lanes_number = 4;
1190
1191 cntl.hpd_sel = enc110->base.hpd_source;
1192
1193 cntl.pixel_clock = pixel_clock;
1194 cntl.color_depth = color_depth;
1195
1196 result = link_transmitter_control(enc110, &cntl);
1197
1198 if (result != BP_RESULT_OK) {
1199 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1200 __func__);
1201 BREAK_TO_DEBUGGER();
1202 }
1203 }
1204
1205 /* TODO: still need depth or just pass in adjusted pixel clock? */
dce110_link_encoder_enable_lvds_output(struct link_encoder * enc,enum clock_source_id clock_source,uint32_t pixel_clock)1206 void dce110_link_encoder_enable_lvds_output(
1207 struct link_encoder *enc,
1208 enum clock_source_id clock_source,
1209 uint32_t pixel_clock)
1210 {
1211 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1212 struct bp_transmitter_control cntl = { 0 };
1213 enum bp_result result;
1214
1215 /* Enable the PHY */
1216 cntl.connector_obj_id = enc110->base.connector;
1217 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1218 cntl.engine_id = enc->preferred_engine;
1219 cntl.transmitter = enc110->base.transmitter;
1220 cntl.pll_id = clock_source;
1221 cntl.signal = SIGNAL_TYPE_LVDS;
1222 cntl.lanes_number = 4;
1223
1224 cntl.hpd_sel = enc110->base.hpd_source;
1225
1226 cntl.pixel_clock = pixel_clock;
1227
1228 result = link_transmitter_control(enc110, &cntl);
1229
1230 if (result != BP_RESULT_OK) {
1231 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1232 __func__);
1233 BREAK_TO_DEBUGGER();
1234 }
1235 }
1236
dce110_link_encoder_enable_analog_output(struct link_encoder * enc,uint32_t pixel_clock)1237 void dce110_link_encoder_enable_analog_output(
1238 struct link_encoder *enc,
1239 uint32_t pixel_clock)
1240 {
1241 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1242 enum bp_result result;
1243
1244 result = link_dac_encoder_control(enc110, ENCODER_CONTROL_ENABLE, pixel_clock);
1245
1246 if (result != BP_RESULT_OK) {
1247 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1248 __func__);
1249 BREAK_TO_DEBUGGER();
1250 }
1251 }
1252
1253 /* enables DP PHY output */
dce110_link_encoder_enable_dp_output(struct link_encoder * enc,const struct dc_link_settings * link_settings,enum clock_source_id clock_source)1254 void dce110_link_encoder_enable_dp_output(
1255 struct link_encoder *enc,
1256 const struct dc_link_settings *link_settings,
1257 enum clock_source_id clock_source)
1258 {
1259 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1260 struct bp_transmitter_control cntl = { 0 };
1261 enum bp_result result;
1262
1263 /* Enable the PHY */
1264
1265 /* number_of_lanes is used for pixel clock adjust,
1266 * but it's not passed to asic_control.
1267 * We need to set number of lanes manually.
1268 */
1269 configure_encoder(enc110, link_settings);
1270 cntl.connector_obj_id = enc110->base.connector;
1271 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1272 cntl.engine_id = enc->preferred_engine;
1273 cntl.transmitter = enc110->base.transmitter;
1274 cntl.pll_id = clock_source;
1275 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
1276 cntl.lanes_number = link_settings->lane_count;
1277 cntl.hpd_sel = enc110->base.hpd_source;
1278 cntl.pixel_clock = link_settings->link_rate
1279 * LINK_RATE_REF_FREQ_IN_KHZ;
1280 /* TODO: check if undefined works */
1281 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1282
1283 result = link_transmitter_control(enc110, &cntl);
1284
1285 if (result != BP_RESULT_OK) {
1286 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1287 __func__);
1288 BREAK_TO_DEBUGGER();
1289 }
1290 }
1291
1292 /* enables DP PHY output in MST mode */
dce110_link_encoder_enable_dp_mst_output(struct link_encoder * enc,const struct dc_link_settings * link_settings,enum clock_source_id clock_source)1293 void dce110_link_encoder_enable_dp_mst_output(
1294 struct link_encoder *enc,
1295 const struct dc_link_settings *link_settings,
1296 enum clock_source_id clock_source)
1297 {
1298 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1299 struct bp_transmitter_control cntl = { 0 };
1300 enum bp_result result;
1301
1302 /* Enable the PHY */
1303
1304 /* number_of_lanes is used for pixel clock adjust,
1305 * but it's not passed to asic_control.
1306 * We need to set number of lanes manually.
1307 */
1308 configure_encoder(enc110, link_settings);
1309
1310 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1311 cntl.engine_id = ENGINE_ID_UNKNOWN;
1312 cntl.transmitter = enc110->base.transmitter;
1313 cntl.pll_id = clock_source;
1314 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1315 cntl.lanes_number = link_settings->lane_count;
1316 cntl.hpd_sel = enc110->base.hpd_source;
1317 cntl.pixel_clock = link_settings->link_rate
1318 * LINK_RATE_REF_FREQ_IN_KHZ;
1319 /* TODO: check if undefined works */
1320 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1321
1322 result = link_transmitter_control(enc110, &cntl);
1323
1324 if (result != BP_RESULT_OK) {
1325 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1326 __func__);
1327 BREAK_TO_DEBUGGER();
1328 }
1329 }
1330
1331 #if defined(CONFIG_DRM_AMD_DC_SI)
1332 /* enables DP PHY output */
dce60_link_encoder_enable_dp_output(struct link_encoder * enc,const struct dc_link_settings * link_settings,enum clock_source_id clock_source)1333 static void dce60_link_encoder_enable_dp_output(
1334 struct link_encoder *enc,
1335 const struct dc_link_settings *link_settings,
1336 enum clock_source_id clock_source)
1337 {
1338 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1339 struct bp_transmitter_control cntl = { 0 };
1340 enum bp_result result;
1341
1342 /* Enable the PHY */
1343
1344 /* number_of_lanes is used for pixel clock adjust,
1345 * but it's not passed to asic_control.
1346 * We need to set number of lanes manually.
1347 */
1348 dce60_configure_encoder(enc110, link_settings);
1349 cntl.connector_obj_id = enc110->base.connector;
1350 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1351 cntl.engine_id = enc->preferred_engine;
1352 cntl.transmitter = enc110->base.transmitter;
1353 cntl.pll_id = clock_source;
1354 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
1355 cntl.lanes_number = link_settings->lane_count;
1356 cntl.hpd_sel = enc110->base.hpd_source;
1357 cntl.pixel_clock = link_settings->link_rate
1358 * LINK_RATE_REF_FREQ_IN_KHZ;
1359 /* TODO: check if undefined works */
1360 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1361
1362 result = link_transmitter_control(enc110, &cntl);
1363
1364 if (result != BP_RESULT_OK) {
1365 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1366 __func__);
1367 BREAK_TO_DEBUGGER();
1368 }
1369 }
1370
1371 /* enables DP PHY output in MST mode */
dce60_link_encoder_enable_dp_mst_output(struct link_encoder * enc,const struct dc_link_settings * link_settings,enum clock_source_id clock_source)1372 static void dce60_link_encoder_enable_dp_mst_output(
1373 struct link_encoder *enc,
1374 const struct dc_link_settings *link_settings,
1375 enum clock_source_id clock_source)
1376 {
1377 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1378 struct bp_transmitter_control cntl = { 0 };
1379 enum bp_result result;
1380
1381 /* Enable the PHY */
1382
1383 /* number_of_lanes is used for pixel clock adjust,
1384 * but it's not passed to asic_control.
1385 * We need to set number of lanes manually.
1386 */
1387 dce60_configure_encoder(enc110, link_settings);
1388
1389 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1390 cntl.engine_id = ENGINE_ID_UNKNOWN;
1391 cntl.transmitter = enc110->base.transmitter;
1392 cntl.pll_id = clock_source;
1393 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1394 cntl.lanes_number = link_settings->lane_count;
1395 cntl.hpd_sel = enc110->base.hpd_source;
1396 cntl.pixel_clock = link_settings->link_rate
1397 * LINK_RATE_REF_FREQ_IN_KHZ;
1398 /* TODO: check if undefined works */
1399 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1400
1401 result = link_transmitter_control(enc110, &cntl);
1402
1403 if (result != BP_RESULT_OK) {
1404 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1405 __func__);
1406 BREAK_TO_DEBUGGER();
1407 }
1408 }
1409 #endif
1410
1411 /*
1412 * @brief
1413 * Disable transmitter and its encoder
1414 */
dce110_link_encoder_disable_output(struct link_encoder * enc,enum signal_type signal)1415 void dce110_link_encoder_disable_output(
1416 struct link_encoder *enc,
1417 enum signal_type signal)
1418 {
1419 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1420 struct bp_transmitter_control cntl = { 0 };
1421 enum bp_result result;
1422
1423 if (enc->analog_engine != ENGINE_ID_UNKNOWN)
1424 link_dac_encoder_control(enc110, ENCODER_CONTROL_DISABLE, 0);
1425
1426 /* The code below only applies to connectors that support digital signals. */
1427 if (enc->transmitter == TRANSMITTER_UNKNOWN)
1428 return;
1429
1430 if (!dce110_is_dig_enabled(enc)) {
1431 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
1432 return;
1433 }
1434 /* Power-down RX and disable GPU PHY should be paired.
1435 * Disabling PHY without powering down RX may cause
1436 * symbol lock loss, on which we will get DP Sink interrupt. */
1437
1438 /* There is a case for the DP active dongles
1439 * where we want to disable the PHY but keep RX powered,
1440 * for those we need to ignore DP Sink interrupt
1441 * by checking lane count that has been set
1442 * on the last do_enable_output(). */
1443
1444 /* disable transmitter */
1445 cntl.action = TRANSMITTER_CONTROL_DISABLE;
1446 cntl.transmitter = enc110->base.transmitter;
1447 cntl.hpd_sel = enc110->base.hpd_source;
1448 cntl.signal = signal;
1449 cntl.connector_obj_id = enc110->base.connector;
1450
1451 result = link_transmitter_control(enc110, &cntl);
1452
1453 if (result != BP_RESULT_OK) {
1454 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1455 __func__);
1456 BREAK_TO_DEBUGGER();
1457 return;
1458 }
1459
1460 /* disable encoder */
1461 if (dc_is_dp_signal(signal))
1462 link_encoder_disable(enc110);
1463 }
1464
dce110_link_encoder_dp_set_lane_settings(struct link_encoder * enc,const struct dc_link_settings * link_settings,const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])1465 void dce110_link_encoder_dp_set_lane_settings(
1466 struct link_encoder *enc,
1467 const struct dc_link_settings *link_settings,
1468 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
1469 {
1470 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1471 union dpcd_training_lane_set training_lane_set = { { 0 } };
1472 int32_t lane = 0;
1473 struct bp_transmitter_control cntl = { 0 };
1474
1475 if (!link_settings) {
1476 BREAK_TO_DEBUGGER();
1477 return;
1478 }
1479
1480 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1481 cntl.transmitter = enc110->base.transmitter;
1482 cntl.connector_obj_id = enc110->base.connector;
1483 cntl.lanes_number = link_settings->lane_count;
1484 cntl.hpd_sel = enc110->base.hpd_source;
1485 cntl.pixel_clock = link_settings->link_rate *
1486 LINK_RATE_REF_FREQ_IN_KHZ;
1487
1488 for (lane = 0; lane < link_settings->lane_count; lane++) {
1489 /* translate lane settings */
1490
1491 training_lane_set.bits.VOLTAGE_SWING_SET =
1492 lane_settings[lane].VOLTAGE_SWING;
1493 training_lane_set.bits.PRE_EMPHASIS_SET =
1494 lane_settings[lane].PRE_EMPHASIS;
1495
1496 /* post cursor 2 setting only applies to HBR2 link rate */
1497 if (link_settings->link_rate == LINK_RATE_HIGH2) {
1498 /* this is passed to VBIOS
1499 * to program post cursor 2 level */
1500
1501 training_lane_set.bits.POST_CURSOR2_SET =
1502 lane_settings[lane].POST_CURSOR2;
1503 }
1504
1505 cntl.lane_select = lane;
1506 cntl.lane_settings = training_lane_set.raw;
1507
1508 /* call VBIOS table to set voltage swing and pre-emphasis */
1509 if (link_transmitter_control(enc110, &cntl) != BP_RESULT_OK) {
1510 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", __func__);
1511 BREAK_TO_DEBUGGER();
1512 }
1513 }
1514 }
1515
1516 /* set DP PHY test and training patterns */
dce110_link_encoder_dp_set_phy_pattern(struct link_encoder * enc,const struct encoder_set_dp_phy_pattern_param * param)1517 void dce110_link_encoder_dp_set_phy_pattern(
1518 struct link_encoder *enc,
1519 const struct encoder_set_dp_phy_pattern_param *param)
1520 {
1521 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1522
1523 switch (param->dp_phy_pattern) {
1524 case DP_TEST_PATTERN_TRAINING_PATTERN1:
1525 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1526 break;
1527 case DP_TEST_PATTERN_TRAINING_PATTERN2:
1528 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1529 break;
1530 case DP_TEST_PATTERN_TRAINING_PATTERN3:
1531 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1532 break;
1533 case DP_TEST_PATTERN_TRAINING_PATTERN4:
1534 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1535 break;
1536 case DP_TEST_PATTERN_D102:
1537 set_dp_phy_pattern_d102(enc110);
1538 break;
1539 case DP_TEST_PATTERN_SYMBOL_ERROR:
1540 set_dp_phy_pattern_symbol_error(enc110);
1541 break;
1542 case DP_TEST_PATTERN_PRBS7:
1543 set_dp_phy_pattern_prbs7(enc110);
1544 break;
1545 case DP_TEST_PATTERN_80BIT_CUSTOM:
1546 set_dp_phy_pattern_80bit_custom(
1547 enc110, param->custom_pattern);
1548 break;
1549 case DP_TEST_PATTERN_CP2520_1:
1550 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1);
1551 break;
1552 case DP_TEST_PATTERN_CP2520_2:
1553 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2);
1554 break;
1555 case DP_TEST_PATTERN_CP2520_3:
1556 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3);
1557 break;
1558 case DP_TEST_PATTERN_VIDEO_MODE: {
1559 set_dp_phy_pattern_passthrough_mode(
1560 enc110, param->dp_panel_mode);
1561 break;
1562 }
1563
1564 default:
1565 /* invalid phy pattern */
1566 ASSERT_CRITICAL(false);
1567 break;
1568 }
1569 }
1570
1571 #if defined(CONFIG_DRM_AMD_DC_SI)
1572 /* set DP PHY test and training patterns */
dce60_link_encoder_dp_set_phy_pattern(struct link_encoder * enc,const struct encoder_set_dp_phy_pattern_param * param)1573 static void dce60_link_encoder_dp_set_phy_pattern(
1574 struct link_encoder *enc,
1575 const struct encoder_set_dp_phy_pattern_param *param)
1576 {
1577 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1578
1579 switch (param->dp_phy_pattern) {
1580 case DP_TEST_PATTERN_TRAINING_PATTERN1:
1581 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1582 break;
1583 case DP_TEST_PATTERN_TRAINING_PATTERN2:
1584 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1585 break;
1586 case DP_TEST_PATTERN_TRAINING_PATTERN3:
1587 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1588 break;
1589 case DP_TEST_PATTERN_TRAINING_PATTERN4:
1590 dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1591 break;
1592 case DP_TEST_PATTERN_D102:
1593 set_dp_phy_pattern_d102(enc110);
1594 break;
1595 case DP_TEST_PATTERN_SYMBOL_ERROR:
1596 set_dp_phy_pattern_symbol_error(enc110);
1597 break;
1598 case DP_TEST_PATTERN_PRBS7:
1599 set_dp_phy_pattern_prbs7(enc110);
1600 break;
1601 case DP_TEST_PATTERN_80BIT_CUSTOM:
1602 set_dp_phy_pattern_80bit_custom(
1603 enc110, param->custom_pattern);
1604 break;
1605 case DP_TEST_PATTERN_CP2520_1:
1606 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1);
1607 break;
1608 case DP_TEST_PATTERN_CP2520_2:
1609 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2);
1610 break;
1611 case DP_TEST_PATTERN_CP2520_3:
1612 dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3);
1613 break;
1614 case DP_TEST_PATTERN_VIDEO_MODE: {
1615 dce60_set_dp_phy_pattern_passthrough_mode(
1616 enc110, param->dp_panel_mode);
1617 break;
1618 }
1619
1620 default:
1621 /* invalid phy pattern */
1622 ASSERT_CRITICAL(false);
1623 break;
1624 }
1625 }
1626 #endif
1627
fill_stream_allocation_row_info(const struct link_mst_stream_allocation * stream_allocation,uint32_t * src,uint32_t * slots)1628 static void fill_stream_allocation_row_info(
1629 const struct link_mst_stream_allocation *stream_allocation,
1630 uint32_t *src,
1631 uint32_t *slots)
1632 {
1633 const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1634
1635 if (stream_enc) {
1636 *src = stream_enc->id;
1637 *slots = stream_allocation->slot_count;
1638 } else {
1639 *src = 0;
1640 *slots = 0;
1641 }
1642 }
1643
1644 /* programs DP MST VC payload allocation */
dce110_link_encoder_update_mst_stream_allocation_table(struct link_encoder * enc,const struct link_mst_stream_allocation_table * table)1645 void dce110_link_encoder_update_mst_stream_allocation_table(
1646 struct link_encoder *enc,
1647 const struct link_mst_stream_allocation_table *table)
1648 {
1649 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1650 uint32_t value1 = 0;
1651 uint32_t value2 = 0;
1652 uint32_t slots = 0;
1653 uint32_t src = 0;
1654 uint32_t retries = 0;
1655
1656 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1657
1658 /* --- Set MSE Stream Attribute -
1659 * Setup VC Payload Table on Tx Side,
1660 * Issue allocation change trigger
1661 * to commit payload on both tx and rx side */
1662
1663 /* we should clean-up table each time */
1664
1665 if (table->stream_count >= 1) {
1666 fill_stream_allocation_row_info(
1667 &table->stream_allocations[0],
1668 &src,
1669 &slots);
1670 } else {
1671 src = 0;
1672 slots = 0;
1673 }
1674
1675 REG_UPDATE_2(DP_MSE_SAT0,
1676 DP_MSE_SAT_SRC0, src,
1677 DP_MSE_SAT_SLOT_COUNT0, slots);
1678
1679 if (table->stream_count >= 2) {
1680 fill_stream_allocation_row_info(
1681 &table->stream_allocations[1],
1682 &src,
1683 &slots);
1684 } else {
1685 src = 0;
1686 slots = 0;
1687 }
1688
1689 REG_UPDATE_2(DP_MSE_SAT0,
1690 DP_MSE_SAT_SRC1, src,
1691 DP_MSE_SAT_SLOT_COUNT1, slots);
1692
1693 if (table->stream_count >= 3) {
1694 fill_stream_allocation_row_info(
1695 &table->stream_allocations[2],
1696 &src,
1697 &slots);
1698 } else {
1699 src = 0;
1700 slots = 0;
1701 }
1702
1703 REG_UPDATE_2(DP_MSE_SAT1,
1704 DP_MSE_SAT_SRC2, src,
1705 DP_MSE_SAT_SLOT_COUNT2, slots);
1706
1707 if (table->stream_count >= 4) {
1708 fill_stream_allocation_row_info(
1709 &table->stream_allocations[3],
1710 &src,
1711 &slots);
1712 } else {
1713 src = 0;
1714 slots = 0;
1715 }
1716
1717 REG_UPDATE_2(DP_MSE_SAT1,
1718 DP_MSE_SAT_SRC3, src,
1719 DP_MSE_SAT_SLOT_COUNT3, slots);
1720
1721 /* --- wait for transaction finish */
1722
1723 /* send allocation change trigger (ACT) ?
1724 * this step first sends the ACT,
1725 * then double buffers the SAT into the hardware
1726 * making the new allocation active on the DP MST mode link */
1727
1728
1729 /* DP_MSE_SAT_UPDATE:
1730 * 0 - No Action
1731 * 1 - Update SAT with trigger
1732 * 2 - Update SAT without trigger */
1733
1734 REG_UPDATE(DP_MSE_SAT_UPDATE,
1735 DP_MSE_SAT_UPDATE, 1);
1736
1737 /* wait for update to complete
1738 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1739 * then wait for the transmission
1740 * of at least 16 MTP headers on immediate local link.
1741 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1742 * a value of 1 indicates that DP MST mode
1743 * is in the 16 MTP keepout region after a VC has been added.
1744 * MST stream bandwidth (VC rate) can be configured
1745 * after this bit is cleared */
1746
1747 do {
1748 udelay(10);
1749
1750 REG_READ(DP_MSE_SAT_UPDATE);
1751
1752 REG_GET(DP_MSE_SAT_UPDATE,
1753 DP_MSE_SAT_UPDATE, &value1);
1754
1755 REG_GET(DP_MSE_SAT_UPDATE,
1756 DP_MSE_16_MTP_KEEPOUT, &value2);
1757
1758 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1759 if (!value1 && !value2)
1760 break;
1761 ++retries;
1762 } while (retries < DP_MST_UPDATE_MAX_RETRY);
1763 }
1764
dce110_link_encoder_connect_dig_be_to_fe(struct link_encoder * enc,enum engine_id engine,bool connect)1765 void dce110_link_encoder_connect_dig_be_to_fe(
1766 struct link_encoder *enc,
1767 enum engine_id engine,
1768 bool connect)
1769 {
1770 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1771 uint32_t field;
1772
1773 if (engine != ENGINE_ID_UNKNOWN) {
1774
1775 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1776
1777 if (connect)
1778 field |= get_frontend_source(engine);
1779 else
1780 field &= ~get_frontend_source(engine);
1781
1782 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1783 }
1784 }
1785
dce110_link_encoder_enable_hpd(struct link_encoder * enc)1786 void dce110_link_encoder_enable_hpd(struct link_encoder *enc)
1787 {
1788 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1789 struct dc_context *ctx = enc110->base.ctx;
1790 uint32_t addr = HPD_REG(DC_HPD_CONTROL);
1791 uint32_t hpd_enable = 0;
1792 uint32_t value = dm_read_reg(ctx, addr);
1793
1794 hpd_enable = get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN);
1795
1796 if (hpd_enable == 0)
1797 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN);
1798 }
1799
dce110_link_encoder_disable_hpd(struct link_encoder * enc)1800 void dce110_link_encoder_disable_hpd(struct link_encoder *enc)
1801 {
1802 struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
1803 struct dc_context *ctx = enc110->base.ctx;
1804 uint32_t addr = HPD_REG(DC_HPD_CONTROL);
1805 uint32_t value = dm_read_reg(ctx, addr);
1806
1807 set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN);
1808 }
1809
dce110_link_encoder_get_max_link_cap(struct link_encoder * enc,struct dc_link_settings * link_settings)1810 void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc,
1811 struct dc_link_settings *link_settings)
1812 {
1813 /* Set Default link settings */
1814 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1815 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
1816
1817 /* Higher link settings based on feature supported */
1818 if (enc->features.flags.bits.IS_HBR2_CAPABLE)
1819 max_link_cap.link_rate = LINK_RATE_HIGH2;
1820
1821 if (enc->features.flags.bits.IS_HBR3_CAPABLE)
1822 max_link_cap.link_rate = LINK_RATE_HIGH3;
1823
1824 *link_settings = max_link_cap;
1825 }
1826
dce110_get_hpd_state(struct link_encoder * enc)1827 bool dce110_get_hpd_state(struct link_encoder *enc)
1828 {
1829 uint32_t state = 0;
1830
1831 if (!enc->hpd_gpio)
1832 return false;
1833
1834 dal_gpio_lock_pin(enc->hpd_gpio);
1835 dal_gpio_get_value(enc->hpd_gpio, &state);
1836 dal_gpio_unlock_pin(enc->hpd_gpio);
1837
1838 return state;
1839 }
1840
dce110_program_hpd_filter(struct link_encoder * enc,int delay_on_connect_in_ms,int delay_on_disconnect_in_ms)1841 bool dce110_program_hpd_filter(struct link_encoder *enc, int delay_on_connect_in_ms, int delay_on_disconnect_in_ms)
1842 {
1843 /* Setup HPD filtering */
1844 if (enc->hpd_gpio && dal_gpio_lock_pin(enc->hpd_gpio) == GPIO_RESULT_OK) {
1845 struct gpio_hpd_config config;
1846
1847 config.delay_on_connect = delay_on_connect_in_ms;
1848 config.delay_on_disconnect = delay_on_disconnect_in_ms;
1849
1850 dal_irq_setup_hpd_filter(enc->hpd_gpio, &config);
1851
1852 dal_gpio_unlock_pin(enc->hpd_gpio);
1853
1854 return true;
1855 } else {
1856 ASSERT(0);
1857 return false;
1858 }
1859 }
1860
1861 #if defined(CONFIG_DRM_AMD_DC_SI)
1862 static const struct link_encoder_funcs dce60_lnk_enc_funcs = {
1863 .validate_output_with_stream =
1864 dce110_link_encoder_validate_output_with_stream,
1865 .hw_init = dce110_link_encoder_hw_init,
1866 .setup = dce110_link_encoder_setup,
1867 .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
1868 .enable_dp_output = dce60_link_encoder_enable_dp_output,
1869 .enable_dp_mst_output = dce60_link_encoder_enable_dp_mst_output,
1870 .enable_lvds_output = dce110_link_encoder_enable_lvds_output,
1871 .enable_analog_output = dce110_link_encoder_enable_analog_output,
1872 .disable_output = dce110_link_encoder_disable_output,
1873 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
1874 .dp_set_phy_pattern = dce60_link_encoder_dp_set_phy_pattern,
1875 .update_mst_stream_allocation_table =
1876 dce110_link_encoder_update_mst_stream_allocation_table,
1877 .psr_program_dp_dphy_fast_training =
1878 dce110_psr_program_dp_dphy_fast_training,
1879 .psr_program_secondary_packet = dce110_psr_program_secondary_packet,
1880 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
1881 .enable_hpd = dce110_link_encoder_enable_hpd,
1882 .disable_hpd = dce110_link_encoder_disable_hpd,
1883 .is_dig_enabled = dce110_is_dig_enabled,
1884 .destroy = dce110_link_encoder_destroy,
1885 .get_max_link_cap = dce110_link_encoder_get_max_link_cap,
1886 .get_dig_frontend = dce110_get_dig_frontend,
1887 .get_hpd_state = dce110_get_hpd_state,
1888 .program_hpd_filter = dce110_program_hpd_filter,
1889 };
1890
1891 static const struct link_encoder_funcs dce60_lnk_enc_funcs_no_hpd = {
1892 .validate_output_with_stream =
1893 dce110_link_encoder_validate_output_with_stream,
1894 .hw_init = dce110_link_encoder_hw_init,
1895 .setup = dce110_link_encoder_setup,
1896 .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
1897 .enable_dp_output = dce60_link_encoder_enable_dp_output,
1898 .enable_dp_mst_output = dce60_link_encoder_enable_dp_mst_output,
1899 .enable_lvds_output = dce110_link_encoder_enable_lvds_output,
1900 .enable_analog_output = dce110_link_encoder_enable_analog_output,
1901 .disable_output = dce110_link_encoder_disable_output,
1902 .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
1903 .dp_set_phy_pattern = dce60_link_encoder_dp_set_phy_pattern,
1904 .update_mst_stream_allocation_table =
1905 dce110_link_encoder_update_mst_stream_allocation_table,
1906 .psr_program_dp_dphy_fast_training =
1907 dce110_psr_program_dp_dphy_fast_training,
1908 .psr_program_secondary_packet = dce110_psr_program_secondary_packet,
1909 .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
1910 .is_dig_enabled = dce110_is_dig_enabled,
1911 .destroy = dce110_link_encoder_destroy,
1912 .get_max_link_cap = dce110_link_encoder_get_max_link_cap,
1913 .get_dig_frontend = dce110_get_dig_frontend,
1914 .get_hpd_state = dce110_get_hpd_state,
1915 .program_hpd_filter = dce110_program_hpd_filter,
1916 };
1917
dce60_link_encoder_construct(struct dce110_link_encoder * enc110,const struct encoder_init_data * init_data,const struct encoder_feature_support * enc_features,const struct dce110_link_enc_registers * link_regs,const struct dce110_link_enc_aux_registers * aux_regs,const struct dce110_link_enc_hpd_registers * hpd_regs)1918 void dce60_link_encoder_construct(
1919 struct dce110_link_encoder *enc110,
1920 const struct encoder_init_data *init_data,
1921 const struct encoder_feature_support *enc_features,
1922 const struct dce110_link_enc_registers *link_regs,
1923 const struct dce110_link_enc_aux_registers *aux_regs,
1924 const struct dce110_link_enc_hpd_registers *hpd_regs)
1925 {
1926 struct bp_encoder_cap_info bp_cap_info = {0};
1927 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
1928 enum bp_result result = BP_RESULT_OK;
1929
1930 if (hpd_regs)
1931 enc110->base.funcs = &dce60_lnk_enc_funcs;
1932 else
1933 enc110->base.funcs = &dce60_lnk_enc_funcs_no_hpd;
1934 enc110->base.ctx = init_data->ctx;
1935 enc110->base.id = init_data->encoder;
1936 enc110->base.analog_id = init_data->analog_encoder;
1937
1938 enc110->base.hpd_gpio = init_data->hpd_gpio;
1939 enc110->base.hpd_source = init_data->hpd_source;
1940 enc110->base.connector = init_data->connector;
1941
1942 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
1943 enc110->base.analog_engine = init_data->analog_engine;
1944
1945 enc110->base.features = *enc_features;
1946
1947 enc110->base.transmitter = init_data->transmitter;
1948
1949 /* set the flag to indicate whether driver poll the I2C data pin
1950 * while doing the DP sink detect
1951 */
1952
1953 /* if (dal_adapter_service_is_feature_supported(as,
1954 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
1955 enc110->base.features.flags.bits.
1956 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
1957
1958 enc110->base.output_signals =
1959 SIGNAL_TYPE_DVI_SINGLE_LINK |
1960 SIGNAL_TYPE_DVI_DUAL_LINK |
1961 SIGNAL_TYPE_LVDS |
1962 SIGNAL_TYPE_DISPLAY_PORT |
1963 SIGNAL_TYPE_DISPLAY_PORT_MST |
1964 SIGNAL_TYPE_EDP |
1965 SIGNAL_TYPE_HDMI_TYPE_A;
1966
1967 if ((enc110->base.connector.id == CONNECTOR_ID_DUAL_LINK_DVII ||
1968 enc110->base.connector.id == CONNECTOR_ID_SINGLE_LINK_DVII) &&
1969 enc110->base.analog_engine != ENGINE_ID_UNKNOWN)
1970 enc110->base.output_signals |= SIGNAL_TYPE_RGB;
1971
1972 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
1973 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
1974 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
1975 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
1976 * Prefer DIG assignment is decided by board design.
1977 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
1978 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
1979 * By this, adding DIGG should not hurt DCE 8.0.
1980 * This will let DCE 8.1 share DCE 8.0 as much as possible
1981 */
1982
1983 enc110->link_regs = link_regs;
1984 enc110->aux_regs = aux_regs;
1985 enc110->hpd_regs = hpd_regs;
1986
1987 switch (enc110->base.transmitter) {
1988 case TRANSMITTER_UNIPHY_A:
1989 enc110->base.preferred_engine = ENGINE_ID_DIGA;
1990 break;
1991 case TRANSMITTER_UNIPHY_B:
1992 enc110->base.preferred_engine = ENGINE_ID_DIGB;
1993 break;
1994 case TRANSMITTER_UNIPHY_C:
1995 enc110->base.preferred_engine = ENGINE_ID_DIGC;
1996 break;
1997 case TRANSMITTER_UNIPHY_D:
1998 enc110->base.preferred_engine = ENGINE_ID_DIGD;
1999 break;
2000 case TRANSMITTER_UNIPHY_E:
2001 enc110->base.preferred_engine = ENGINE_ID_DIGE;
2002 break;
2003 case TRANSMITTER_UNIPHY_F:
2004 enc110->base.preferred_engine = ENGINE_ID_DIGF;
2005 break;
2006 case TRANSMITTER_UNIPHY_G:
2007 enc110->base.preferred_engine = ENGINE_ID_DIGG;
2008 break;
2009 default:
2010 if (init_data->analog_engine != ENGINE_ID_UNKNOWN) {
2011 /* The connector is analog-only, ie. VGA */
2012 enc110->base.preferred_engine = init_data->analog_engine;
2013 enc110->base.output_signals = SIGNAL_TYPE_RGB;
2014 enc110->base.transmitter = TRANSMITTER_UNKNOWN;
2015 break;
2016 }
2017 ASSERT_CRITICAL(false);
2018 enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
2019 }
2020
2021 /* default to one to mirror Windows behavior */
2022 enc110->base.features.flags.bits.HDMI_6GB_EN = 1;
2023
2024 result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios,
2025 enc110->base.id, &bp_cap_info);
2026
2027 /* Override features with DCE-specific values */
2028 if (result == BP_RESULT_OK) {
2029 enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
2030 bp_cap_info.DP_HBR2_EN;
2031 enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
2032 bp_cap_info.DP_HBR3_EN;
2033 enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
2034 } else if (result != BP_RESULT_NORECORD) {
2035 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
2036 __func__,
2037 result);
2038 }
2039 if (enc110->base.ctx->dc->debug.hdmi20_disable) {
2040 enc110->base.features.flags.bits.HDMI_6GB_EN = 0;
2041 }
2042 }
2043 #endif
2044