1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 #include <linux/acpi.h>
34 #include <linux/module.h>
35 #include <rdma/ib_addr.h>
36 #include <rdma/ib_smi.h>
37 #include <rdma/ib_user_verbs.h>
38 #include <rdma/ib_cache.h>
39 #include "hns_roce_common.h"
40 #include "hns_roce_device.h"
41 #include "hns_roce_hem.h"
42 #include "hns_roce_hw_v2.h"
43 #include "hns_roce_bond.h"
44
hns_roce_set_mac(struct hns_roce_dev * hr_dev,u32 port,const u8 * addr)45 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port,
46 const u8 *addr)
47 {
48 u8 phy_port;
49 u32 i;
50
51 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
52 return 0;
53
54 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
55 return 0;
56
57 for (i = 0; i < ETH_ALEN; i++)
58 hr_dev->dev_addr[port][i] = addr[i];
59
60 phy_port = hr_dev->iboe.phy_port[port];
61 return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
62 }
63
hns_roce_add_gid(const struct ib_gid_attr * attr,void ** context)64 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
65 {
66 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
67 u32 port = attr->port_num - 1;
68 int ret;
69
70 if (port >= hr_dev->caps.num_ports)
71 return -EINVAL;
72
73 ret = hr_dev->hw->set_gid(hr_dev, attr->index, &attr->gid, attr);
74
75 return ret;
76 }
77
hns_roce_del_gid(const struct ib_gid_attr * attr,void ** context)78 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
79 {
80 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
81 u32 port = attr->port_num - 1;
82 int ret;
83
84 if (port >= hr_dev->caps.num_ports)
85 return -EINVAL;
86
87 ret = hr_dev->hw->set_gid(hr_dev, attr->index, NULL, NULL);
88
89 return ret;
90 }
91
hns_roce_get_port_state(struct hns_roce_dev * hr_dev,u32 port_num,enum ib_port_state * state)92 static int hns_roce_get_port_state(struct hns_roce_dev *hr_dev, u32 port_num,
93 enum ib_port_state *state)
94 {
95 struct hns_roce_bond_group *bond_grp;
96 u8 bus_num = get_hr_bus_num(hr_dev);
97 struct net_device *net_dev;
98
99 net_dev = ib_device_get_netdev(&hr_dev->ib_dev, port_num);
100 if (!net_dev)
101 return -ENODEV;
102
103 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_BOND) {
104 bond_grp = hns_roce_get_bond_grp(net_dev, bus_num);
105 if (bond_grp) {
106 *state = ib_get_curr_port_state(bond_grp->upper_dev);
107 goto out;
108 }
109 }
110
111 *state = ib_get_curr_port_state(net_dev);
112 out:
113 dev_put(net_dev);
114 return 0;
115 }
116
handle_en_event(struct net_device * netdev,struct hns_roce_dev * hr_dev,u32 port,unsigned long event)117 static int handle_en_event(struct net_device *netdev,
118 struct hns_roce_dev *hr_dev,
119 u32 port, unsigned long event)
120 {
121 struct ib_device *ibdev = &hr_dev->ib_dev;
122 struct device *dev = hr_dev->dev;
123 enum ib_port_state curr_state;
124 struct ib_event ibevent;
125 int ret = 0;
126
127 if (!netdev) {
128 dev_err(dev, "can't find netdev on port(%u)!\n", port);
129 return -ENODEV;
130 }
131
132 switch (event) {
133 case NETDEV_REGISTER:
134 case NETDEV_CHANGEADDR:
135 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
136 break;
137 case NETDEV_UP:
138 case NETDEV_CHANGE:
139 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
140 if (ret)
141 return ret;
142 fallthrough;
143 case NETDEV_DOWN:
144 if (!netif_is_lag_master(netdev))
145 break;
146 curr_state = ib_get_curr_port_state(netdev);
147
148 write_lock_irq(&ibdev->cache_lock);
149 if (ibdev->port_data[port].cache.last_port_state == curr_state) {
150 write_unlock_irq(&ibdev->cache_lock);
151 return 0;
152 }
153 ibdev->port_data[port].cache.last_port_state = curr_state;
154 write_unlock_irq(&ibdev->cache_lock);
155
156 ibevent.event = (curr_state == IB_PORT_DOWN) ?
157 IB_EVENT_PORT_ERR : IB_EVENT_PORT_ACTIVE;
158 ibevent.device = ibdev;
159 ibevent.element.port_num = port + 1;
160 ib_dispatch_event(&ibevent);
161 break;
162 default:
163 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
164 break;
165 }
166
167 return ret;
168 }
169
hns_roce_netdev_event(struct notifier_block * self,unsigned long event,void * ptr)170 static int hns_roce_netdev_event(struct notifier_block *self,
171 unsigned long event, void *ptr)
172 {
173 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
174 struct hns_roce_bond_group *bond_grp;
175 struct hns_roce_ib_iboe *iboe = NULL;
176 struct hns_roce_dev *hr_dev = NULL;
177 struct net_device *upper = NULL;
178 int ret;
179 u32 port;
180
181 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
182 iboe = &hr_dev->iboe;
183 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_BOND) {
184 bond_grp = hns_roce_get_bond_grp(get_hr_netdev(hr_dev, 0),
185 get_hr_bus_num(hr_dev));
186 upper = bond_grp ? bond_grp->upper_dev : NULL;
187 }
188
189 for (port = 0; port < hr_dev->caps.num_ports; port++) {
190 if ((!upper && dev == iboe->netdevs[port]) ||
191 (upper && dev == upper)) {
192 ret = handle_en_event(dev, hr_dev, port, event);
193 if (ret)
194 return NOTIFY_DONE;
195 break;
196 }
197 }
198
199 return NOTIFY_DONE;
200 }
201
hns_roce_setup_mtu_mac(struct hns_roce_dev * hr_dev)202 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
203 {
204 struct net_device *net_dev;
205 int ret;
206 u8 i;
207
208 for (i = 0; i < hr_dev->caps.num_ports; i++) {
209 net_dev = get_hr_netdev(hr_dev, i);
210 ret = hns_roce_set_mac(hr_dev, i, net_dev->dev_addr);
211 if (ret)
212 return ret;
213 }
214
215 return 0;
216 }
217
hns_roce_query_device(struct ib_device * ib_dev,struct ib_device_attr * props,struct ib_udata * uhw)218 static int hns_roce_query_device(struct ib_device *ib_dev,
219 struct ib_device_attr *props,
220 struct ib_udata *uhw)
221 {
222 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
223
224 memset(props, 0, sizeof(*props));
225
226 props->fw_ver = hr_dev->caps.fw_ver;
227 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
228 props->max_mr_size = (u64)(~(0ULL));
229 props->page_size_cap = hr_dev->caps.page_size_cap;
230 props->vendor_id = hr_dev->vendor_id;
231 props->vendor_part_id = hr_dev->vendor_part_id;
232 props->hw_ver = hr_dev->hw_rev;
233 props->max_qp = hr_dev->caps.num_qps;
234 props->max_qp_wr = hr_dev->caps.max_wqes;
235 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
236 IB_DEVICE_RC_RNR_NAK_GEN;
237 props->max_send_sge = hr_dev->caps.max_sq_sg;
238 props->max_recv_sge = hr_dev->caps.max_rq_sg;
239 props->max_sge_rd = hr_dev->caps.max_sq_sg;
240 props->max_cq = hr_dev->caps.num_cqs;
241 props->max_cqe = hr_dev->caps.max_cqes;
242 props->max_mr = hr_dev->caps.num_mtpts;
243 props->max_pd = hr_dev->caps.num_pds;
244 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
245 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
246 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
247 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
248 props->max_pkeys = 1;
249 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
250 props->max_ah = INT_MAX;
251 props->cq_caps.max_cq_moderation_period = HNS_ROCE_MAX_CQ_PERIOD;
252 props->cq_caps.max_cq_moderation_count = HNS_ROCE_MAX_CQ_COUNT;
253 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
254 props->cq_caps.max_cq_moderation_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08;
255
256 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
257 props->max_srq = hr_dev->caps.num_srqs;
258 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
259 props->max_srq_sge = hr_dev->caps.max_srq_sges;
260 }
261
262 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_LIMIT_BANK) {
263 props->max_cq >>= 1;
264 props->max_qp >>= 1;
265 }
266
267 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR &&
268 hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
269 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
270 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
271 }
272
273 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
274 props->device_cap_flags |= IB_DEVICE_XRC;
275
276 return 0;
277 }
278
hns_roce_query_port(struct ib_device * ib_dev,u32 port_num,struct ib_port_attr * props)279 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num,
280 struct ib_port_attr *props)
281 {
282 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
283 struct net_device *net_dev;
284 enum ib_mtu mtu;
285 u32 port;
286 int ret;
287
288 port = port_num - 1;
289
290 /* props being zeroed by the caller, avoid zeroing it here */
291
292 props->max_mtu = hr_dev->caps.max_mtu;
293 props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
294 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
295 IB_PORT_VENDOR_CLASS_SUP |
296 IB_PORT_BOOT_MGMT_SUP;
297 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
298 props->pkey_tbl_len = 1;
299 ret = ib_get_eth_speed(ib_dev, port_num, &props->active_speed,
300 &props->active_width);
301 if (ret)
302 ibdev_warn(ib_dev, "failed to get speed, ret = %d.\n", ret);
303
304 net_dev = ib_device_get_netdev(ib_dev, port_num);
305 if (!net_dev) {
306 ibdev_err(ib_dev, "find netdev %u failed!\n", port);
307 return -EINVAL;
308 }
309
310 mtu = iboe_get_mtu(net_dev->mtu);
311 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
312
313 dev_put(net_dev);
314
315 ret = hns_roce_get_port_state(hr_dev, port_num, &props->state);
316 if (ret) {
317 ibdev_err(ib_dev, "failed to get port state.\n");
318 return ret;
319 }
320
321 props->phys_state = props->state == IB_PORT_ACTIVE ?
322 IB_PORT_PHYS_STATE_LINK_UP :
323 IB_PORT_PHYS_STATE_DISABLED;
324 return 0;
325 }
326
hns_roce_get_link_layer(struct ib_device * device,u32 port_num)327 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
328 u32 port_num)
329 {
330 return IB_LINK_LAYER_ETHERNET;
331 }
332
hns_roce_query_pkey(struct ib_device * ib_dev,u32 port,u16 index,u16 * pkey)333 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index,
334 u16 *pkey)
335 {
336 if (index > 0)
337 return -EINVAL;
338
339 *pkey = PKEY_ID;
340
341 return 0;
342 }
343
hns_roce_modify_device(struct ib_device * ib_dev,int mask,struct ib_device_modify * props)344 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
345 struct ib_device_modify *props)
346 {
347 unsigned long flags;
348
349 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
350 return -EOPNOTSUPP;
351
352 if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
353 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
354 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
355 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
356 }
357
358 return 0;
359 }
360
361 struct hns_user_mmap_entry *
hns_roce_user_mmap_entry_insert(struct ib_ucontext * ucontext,u64 address,size_t length,enum hns_roce_mmap_type mmap_type)362 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
363 size_t length,
364 enum hns_roce_mmap_type mmap_type)
365 {
366 struct hns_user_mmap_entry *entry;
367 int ret;
368
369 entry = kzalloc_obj(*entry);
370 if (!entry)
371 return NULL;
372
373 entry->address = address;
374 entry->mmap_type = mmap_type;
375
376 switch (mmap_type) {
377 /* pgoff 0 must be used by DB for compatibility */
378 case HNS_ROCE_MMAP_TYPE_DB:
379 ret = rdma_user_mmap_entry_insert_exact(
380 ucontext, &entry->rdma_entry, length, 0);
381 break;
382 case HNS_ROCE_MMAP_TYPE_DWQE:
383 ret = rdma_user_mmap_entry_insert_range(
384 ucontext, &entry->rdma_entry, length, 1,
385 U32_MAX);
386 break;
387 default:
388 ret = -EINVAL;
389 break;
390 }
391
392 if (ret) {
393 kfree(entry);
394 return NULL;
395 }
396
397 return entry;
398 }
399
hns_roce_dealloc_uar_entry(struct hns_roce_ucontext * context)400 static void hns_roce_dealloc_uar_entry(struct hns_roce_ucontext *context)
401 {
402 if (context->db_mmap_entry)
403 rdma_user_mmap_entry_remove(
404 &context->db_mmap_entry->rdma_entry);
405 }
406
hns_roce_alloc_uar_entry(struct ib_ucontext * uctx)407 static int hns_roce_alloc_uar_entry(struct ib_ucontext *uctx)
408 {
409 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
410 u64 address;
411
412 address = context->uar.pfn << PAGE_SHIFT;
413 context->db_mmap_entry = hns_roce_user_mmap_entry_insert(
414 uctx, address, PAGE_SIZE, HNS_ROCE_MMAP_TYPE_DB);
415 if (!context->db_mmap_entry)
416 return -ENOMEM;
417
418 return 0;
419 }
420
hns_roce_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)421 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
422 struct ib_udata *udata)
423 {
424 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
425 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
426 struct hns_roce_ib_alloc_ucontext_resp resp = {};
427 struct hns_roce_ib_alloc_ucontext ucmd = {};
428 int ret = -EAGAIN;
429
430 if (!hr_dev->active)
431 goto error_out;
432
433 resp.qp_tab_size = hr_dev->caps.num_qps;
434 resp.srq_tab_size = hr_dev->caps.num_srqs;
435
436 ret = ib_copy_from_udata(&ucmd, udata,
437 min(udata->inlen, sizeof(ucmd)));
438 if (ret)
439 goto error_out;
440
441 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
442 context->config = ucmd.config & HNS_ROCE_EXSGE_FLAGS;
443
444 if (context->config & HNS_ROCE_EXSGE_FLAGS) {
445 resp.config |= HNS_ROCE_RSP_EXSGE_FLAGS;
446 resp.max_inline_data = hr_dev->caps.max_sq_inline;
447 }
448
449 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
450 context->config |= ucmd.config & HNS_ROCE_RQ_INLINE_FLAGS;
451 if (context->config & HNS_ROCE_RQ_INLINE_FLAGS)
452 resp.config |= HNS_ROCE_RSP_RQ_INLINE_FLAGS;
453 }
454
455 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQE_INLINE) {
456 context->config |= ucmd.config & HNS_ROCE_CQE_INLINE_FLAGS;
457 if (context->config & HNS_ROCE_CQE_INLINE_FLAGS)
458 resp.config |= HNS_ROCE_RSP_CQE_INLINE_FLAGS;
459 }
460
461 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
462 resp.congest_type = hr_dev->caps.cong_cap;
463
464 ret = hns_roce_uar_alloc(hr_dev, &context->uar);
465 if (ret)
466 goto error_out;
467
468 ret = hns_roce_alloc_uar_entry(uctx);
469 if (ret)
470 goto error_fail_uar_entry;
471
472 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
473 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
474 INIT_LIST_HEAD(&context->page_list);
475 mutex_init(&context->page_mutex);
476 }
477
478 resp.cqe_size = hr_dev->caps.cqe_sz;
479
480 ret = ib_copy_to_udata(udata, &resp,
481 min(udata->outlen, sizeof(resp)));
482 if (ret)
483 goto error_fail_copy_to_udata;
484
485 hns_roce_get_cq_bankid_for_uctx(context);
486
487 return 0;
488
489 error_fail_copy_to_udata:
490 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
491 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB)
492 mutex_destroy(&context->page_mutex);
493 hns_roce_dealloc_uar_entry(context);
494
495 error_fail_uar_entry:
496 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
497
498 error_out:
499 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_UCTX_ALLOC_ERR_CNT]);
500
501 return ret;
502 }
503
hns_roce_dealloc_ucontext(struct ib_ucontext * ibcontext)504 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
505 {
506 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
507 struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device);
508
509 hns_roce_put_cq_bankid_for_uctx(context);
510
511 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
512 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB)
513 mutex_destroy(&context->page_mutex);
514
515 hns_roce_dealloc_uar_entry(context);
516
517 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
518 }
519
hns_roce_mmap(struct ib_ucontext * uctx,struct vm_area_struct * vma)520 static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma)
521 {
522 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
523 struct rdma_user_mmap_entry *rdma_entry;
524 struct hns_user_mmap_entry *entry;
525 phys_addr_t pfn;
526 pgprot_t prot;
527 int ret;
528
529 if (hr_dev->dis_db) {
530 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_MMAP_ERR_CNT]);
531 return -EPERM;
532 }
533
534 rdma_entry = rdma_user_mmap_entry_get_pgoff(uctx, vma->vm_pgoff);
535 if (!rdma_entry) {
536 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_MMAP_ERR_CNT]);
537 return -EINVAL;
538 }
539
540 entry = to_hns_mmap(rdma_entry);
541 pfn = entry->address >> PAGE_SHIFT;
542
543 switch (entry->mmap_type) {
544 case HNS_ROCE_MMAP_TYPE_DB:
545 case HNS_ROCE_MMAP_TYPE_DWQE:
546 prot = pgprot_device(vma->vm_page_prot);
547 break;
548 default:
549 ret = -EINVAL;
550 goto out;
551 }
552
553 ret = rdma_user_mmap_io(uctx, vma, pfn, rdma_entry->npages * PAGE_SIZE,
554 prot, rdma_entry);
555
556 out:
557 rdma_user_mmap_entry_put(rdma_entry);
558 if (ret)
559 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_MMAP_ERR_CNT]);
560
561 return ret;
562 }
563
hns_roce_free_mmap(struct rdma_user_mmap_entry * rdma_entry)564 static void hns_roce_free_mmap(struct rdma_user_mmap_entry *rdma_entry)
565 {
566 struct hns_user_mmap_entry *entry = to_hns_mmap(rdma_entry);
567
568 kfree(entry);
569 }
570
hns_roce_port_immutable(struct ib_device * ib_dev,u32 port_num,struct ib_port_immutable * immutable)571 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num,
572 struct ib_port_immutable *immutable)
573 {
574 struct ib_port_attr attr;
575 int ret;
576
577 ret = ib_query_port(ib_dev, port_num, &attr);
578 if (ret)
579 return ret;
580
581 immutable->pkey_tbl_len = attr.pkey_tbl_len;
582 immutable->gid_tbl_len = attr.gid_tbl_len;
583
584 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
585 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
586 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
587 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
588
589 return 0;
590 }
591
hns_roce_disassociate_ucontext(struct ib_ucontext * ibcontext)592 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
593 {
594 }
595
hns_roce_get_fw_ver(struct ib_device * device,char * str)596 static void hns_roce_get_fw_ver(struct ib_device *device, char *str)
597 {
598 u64 fw_ver = to_hr_dev(device)->caps.fw_ver;
599 unsigned int major, minor, sub_minor;
600
601 major = upper_32_bits(fw_ver);
602 minor = high_16_bits(lower_32_bits(fw_ver));
603 sub_minor = low_16_bits(fw_ver);
604
605 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor,
606 sub_minor);
607 }
608
609 #define HNS_ROCE_HW_CNT(ename, cname) \
610 [HNS_ROCE_HW_##ename##_CNT].name = cname
611
612 static const struct rdma_stat_desc hns_roce_port_stats_descs[] = {
613 HNS_ROCE_HW_CNT(RX_RC_PKT, "rx_rc_pkt"),
614 HNS_ROCE_HW_CNT(RX_UC_PKT, "rx_uc_pkt"),
615 HNS_ROCE_HW_CNT(RX_UD_PKT, "rx_ud_pkt"),
616 HNS_ROCE_HW_CNT(RX_XRC_PKT, "rx_xrc_pkt"),
617 HNS_ROCE_HW_CNT(RX_PKT, "rx_pkt"),
618 HNS_ROCE_HW_CNT(RX_ERR_PKT, "rx_err_pkt"),
619 HNS_ROCE_HW_CNT(RX_CNP_PKT, "rx_cnp_pkt"),
620 HNS_ROCE_HW_CNT(TX_RC_PKT, "tx_rc_pkt"),
621 HNS_ROCE_HW_CNT(TX_UC_PKT, "tx_uc_pkt"),
622 HNS_ROCE_HW_CNT(TX_UD_PKT, "tx_ud_pkt"),
623 HNS_ROCE_HW_CNT(TX_XRC_PKT, "tx_xrc_pkt"),
624 HNS_ROCE_HW_CNT(TX_PKT, "tx_pkt"),
625 HNS_ROCE_HW_CNT(TX_ERR_PKT, "tx_err_pkt"),
626 HNS_ROCE_HW_CNT(TX_CNP_PKT, "tx_cnp_pkt"),
627 HNS_ROCE_HW_CNT(TRP_GET_MPT_ERR_PKT, "trp_get_mpt_err_pkt"),
628 HNS_ROCE_HW_CNT(TRP_GET_IRRL_ERR_PKT, "trp_get_irrl_err_pkt"),
629 HNS_ROCE_HW_CNT(ECN_DB, "ecn_doorbell"),
630 HNS_ROCE_HW_CNT(RX_BUF, "rx_buffer"),
631 HNS_ROCE_HW_CNT(TRP_RX_SOF, "trp_rx_sof"),
632 HNS_ROCE_HW_CNT(CQ_CQE, "cq_cqe"),
633 HNS_ROCE_HW_CNT(CQ_POE, "cq_poe"),
634 HNS_ROCE_HW_CNT(CQ_NOTIFY, "cq_notify"),
635 };
636
hns_roce_alloc_hw_port_stats(struct ib_device * device,u32 port_num)637 static struct rdma_hw_stats *hns_roce_alloc_hw_port_stats(
638 struct ib_device *device, u32 port_num)
639 {
640 struct hns_roce_dev *hr_dev = to_hr_dev(device);
641
642 if (port_num > hr_dev->caps.num_ports) {
643 ibdev_err(device, "invalid port num.\n");
644 return NULL;
645 }
646
647 return rdma_alloc_hw_stats_struct(hns_roce_port_stats_descs,
648 ARRAY_SIZE(hns_roce_port_stats_descs),
649 RDMA_HW_STATS_DEFAULT_LIFESPAN);
650 }
651
hns_roce_get_hw_stats(struct ib_device * device,struct rdma_hw_stats * stats,u32 port,int index)652 static int hns_roce_get_hw_stats(struct ib_device *device,
653 struct rdma_hw_stats *stats,
654 u32 port, int index)
655 {
656 struct hns_roce_dev *hr_dev = to_hr_dev(device);
657 int num_counters = HNS_ROCE_HW_CNT_TOTAL;
658 int ret;
659
660 if (port == 0)
661 return 0;
662
663 if (port > hr_dev->caps.num_ports)
664 return -EINVAL;
665
666 ret = hr_dev->hw->query_hw_counter(hr_dev, stats->value, port,
667 &num_counters);
668 if (ret) {
669 ibdev_err(device, "failed to query hw counter, ret = %d\n",
670 ret);
671 return ret;
672 }
673
674 return num_counters;
675 }
676
677 static void
hns_roce_unregister_bond_cleanup(struct hns_roce_dev * hr_dev,struct hns_roce_bond_group * bond_grp)678 hns_roce_unregister_bond_cleanup(struct hns_roce_dev *hr_dev,
679 struct hns_roce_bond_group *bond_grp)
680 {
681 struct net_device *net_dev;
682 int i;
683
684 /* To avoid the loss of other slave devices when main_hr_dev
685 * is unregistered, re-initialize the remaining slaves before
686 * the bond resources cleanup.
687 */
688 bond_grp->bond_state = HNS_ROCE_BOND_NOT_BONDED;
689 for (i = 0; i < ROCE_BOND_FUNC_MAX; i++) {
690 net_dev = bond_grp->bond_func_info[i].net_dev;
691 if (net_dev && net_dev != get_hr_netdev(hr_dev, 0))
692 hns_roce_bond_init_client(bond_grp, i);
693 }
694
695 hns_roce_cleanup_bond(bond_grp);
696 }
697
hns_roce_unregister_device(struct hns_roce_dev * hr_dev,bool bond_cleanup)698 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev,
699 bool bond_cleanup)
700 {
701 struct net_device *net_dev = get_hr_netdev(hr_dev, 0);
702 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
703 struct hns_roce_bond_group *bond_grp;
704 u8 bus_num = get_hr_bus_num(hr_dev);
705
706 if (bond_cleanup && hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_BOND) {
707 bond_grp = hns_roce_get_bond_grp(net_dev, bus_num);
708 if (bond_grp)
709 hns_roce_unregister_bond_cleanup(hr_dev, bond_grp);
710 }
711
712 hr_dev->active = false;
713 unregister_netdevice_notifier(&iboe->nb);
714 ib_unregister_device(&hr_dev->ib_dev);
715 }
716
717 static const struct ib_device_ops hns_roce_dev_ops = {
718 .owner = THIS_MODULE,
719 .driver_id = RDMA_DRIVER_HNS,
720 .uverbs_abi_ver = 1,
721 .uverbs_no_driver_id_binding = 1,
722
723 .get_dev_fw_str = hns_roce_get_fw_ver,
724 .add_gid = hns_roce_add_gid,
725 .alloc_pd = hns_roce_alloc_pd,
726 .alloc_ucontext = hns_roce_alloc_ucontext,
727 .create_ah = hns_roce_create_ah,
728 .create_user_ah = hns_roce_create_ah,
729 .create_cq = hns_roce_create_cq,
730 .create_qp = hns_roce_create_qp,
731 .dealloc_pd = hns_roce_dealloc_pd,
732 .dealloc_ucontext = hns_roce_dealloc_ucontext,
733 .del_gid = hns_roce_del_gid,
734 .dereg_mr = hns_roce_dereg_mr,
735 .destroy_ah = hns_roce_destroy_ah,
736 .destroy_cq = hns_roce_destroy_cq,
737 .disassociate_ucontext = hns_roce_disassociate_ucontext,
738 .get_dma_mr = hns_roce_get_dma_mr,
739 .get_link_layer = hns_roce_get_link_layer,
740 .get_port_immutable = hns_roce_port_immutable,
741 .mmap = hns_roce_mmap,
742 .mmap_free = hns_roce_free_mmap,
743 .modify_device = hns_roce_modify_device,
744 .modify_qp = hns_roce_modify_qp,
745 .query_ah = hns_roce_query_ah,
746 .query_device = hns_roce_query_device,
747 .query_pkey = hns_roce_query_pkey,
748 .query_port = hns_roce_query_port,
749 .reg_user_mr = hns_roce_reg_user_mr,
750
751 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
752 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
753 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
754 INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp),
755 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
756 };
757
758 static const struct ib_device_ops hns_roce_dev_hw_stats_ops = {
759 .alloc_hw_port_stats = hns_roce_alloc_hw_port_stats,
760 .get_hw_stats = hns_roce_get_hw_stats,
761 };
762
763 static const struct ib_device_ops hns_roce_dev_mr_ops = {
764 .rereg_user_mr = hns_roce_rereg_user_mr,
765 };
766
767 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
768 .alloc_mr = hns_roce_alloc_mr,
769 .map_mr_sg = hns_roce_map_mr_sg,
770 };
771
772 static const struct ib_device_ops hns_roce_dev_srq_ops = {
773 .create_srq = hns_roce_create_srq,
774 .destroy_srq = hns_roce_destroy_srq,
775
776 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
777 };
778
779 static const struct ib_device_ops hns_roce_dev_xrcd_ops = {
780 .alloc_xrcd = hns_roce_alloc_xrcd,
781 .dealloc_xrcd = hns_roce_dealloc_xrcd,
782
783 INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd),
784 };
785
786 static const struct ib_device_ops hns_roce_dev_restrack_ops = {
787 .fill_res_cq_entry = hns_roce_fill_res_cq_entry,
788 .fill_res_cq_entry_raw = hns_roce_fill_res_cq_entry_raw,
789 .fill_res_qp_entry = hns_roce_fill_res_qp_entry,
790 .fill_res_qp_entry_raw = hns_roce_fill_res_qp_entry_raw,
791 .fill_res_mr_entry = hns_roce_fill_res_mr_entry,
792 .fill_res_mr_entry_raw = hns_roce_fill_res_mr_entry_raw,
793 .fill_res_srq_entry = hns_roce_fill_res_srq_entry,
794 .fill_res_srq_entry_raw = hns_roce_fill_res_srq_entry_raw,
795 };
796
hns_roce_register_device(struct hns_roce_dev * hr_dev)797 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
798 {
799 struct hns_roce_ib_iboe *iboe = NULL;
800 struct device *dev = hr_dev->dev;
801 struct ib_device *ib_dev = NULL;
802 struct net_device *net_dev;
803 unsigned int i;
804 int ret;
805
806 iboe = &hr_dev->iboe;
807 spin_lock_init(&iboe->lock);
808
809 ib_dev = &hr_dev->ib_dev;
810
811 ib_dev->node_type = RDMA_NODE_IB_CA;
812 ib_dev->dev.parent = dev;
813
814 ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
815 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
816 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
817
818 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR)
819 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
820
821 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
822 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
823
824 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
825 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
826 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
827 }
828
829 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
830 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops);
831
832 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09 &&
833 !hr_dev->is_vf)
834 ib_set_device_ops(ib_dev, &hns_roce_dev_hw_stats_ops);
835
836 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
837 ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
838 ib_set_device_ops(ib_dev, &hns_roce_dev_restrack_ops);
839
840 dma_set_max_seg_size(dev, SZ_2G);
841
842 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_BOND) {
843 ret = hns_roce_alloc_bond_grp(hr_dev);
844 if (ret) {
845 dev_err(dev, "failed to alloc bond_grp for bus %u, ret = %d\n",
846 get_hr_bus_num(hr_dev), ret);
847 return ret;
848 }
849 }
850
851 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_BOND &&
852 hns_roce_bond_is_active(hr_dev)) {
853 ret = hns_roce_bond_init(hr_dev);
854 if (ret) {
855 dev_err(dev, "failed to init bond!\n");
856 return ret;
857 }
858 ret = ib_register_device(ib_dev, "hns_bond_%d", dev);
859 } else {
860 for (i = 0; i < hr_dev->caps.num_ports; i++) {
861 net_dev = get_hr_netdev(hr_dev, i);
862 if (!net_dev)
863 continue;
864
865 ret = ib_device_set_netdev(ib_dev, net_dev, i + 1);
866 if (ret)
867 return ret;
868 }
869 ret = ib_register_device(ib_dev, "hns_%d", dev);
870 }
871 if (ret) {
872 dev_err(dev, "ib_register_device failed!\n");
873 return ret;
874 }
875
876 ret = hns_roce_setup_mtu_mac(hr_dev);
877 if (ret) {
878 dev_err(dev, "setup_mtu_mac failed!\n");
879 goto error_failed_setup_mtu_mac;
880 }
881
882 iboe->nb.notifier_call = hns_roce_netdev_event;
883 ret = register_netdevice_notifier(&iboe->nb);
884 if (ret) {
885 dev_err(dev, "register_netdevice_notifier failed!\n");
886 goto error_failed_setup_mtu_mac;
887 }
888
889 hr_dev->active = true;
890 return 0;
891
892 error_failed_setup_mtu_mac:
893 ib_unregister_device(ib_dev);
894
895 return ret;
896 }
897
hns_roce_init_hem(struct hns_roce_dev * hr_dev)898 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
899 {
900 struct device *dev = hr_dev->dev;
901 int ret;
902
903 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
904 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
905 hr_dev->caps.num_mtpts);
906 if (ret) {
907 dev_err(dev, "failed to init MTPT context memory, aborting.\n");
908 return ret;
909 }
910
911 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
912 HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
913 hr_dev->caps.num_qps);
914 if (ret) {
915 dev_err(dev, "failed to init QP context memory, aborting.\n");
916 goto err_unmap_dmpt;
917 }
918
919 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
920 HEM_TYPE_IRRL,
921 hr_dev->caps.irrl_entry_sz *
922 hr_dev->caps.max_qp_init_rdma,
923 hr_dev->caps.num_qps);
924 if (ret) {
925 dev_err(dev, "failed to init irrl_table memory, aborting.\n");
926 goto err_unmap_qp;
927 }
928
929 if (hr_dev->caps.trrl_entry_sz) {
930 ret = hns_roce_init_hem_table(hr_dev,
931 &hr_dev->qp_table.trrl_table,
932 HEM_TYPE_TRRL,
933 hr_dev->caps.trrl_entry_sz *
934 hr_dev->caps.max_qp_dest_rdma,
935 hr_dev->caps.num_qps);
936 if (ret) {
937 dev_err(dev,
938 "failed to init trrl_table memory, aborting.\n");
939 goto err_unmap_irrl;
940 }
941 }
942
943 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
944 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
945 hr_dev->caps.num_cqs);
946 if (ret) {
947 dev_err(dev, "failed to init CQ context memory, aborting.\n");
948 goto err_unmap_trrl;
949 }
950
951 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
952 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
953 HEM_TYPE_SRQC,
954 hr_dev->caps.srqc_entry_sz,
955 hr_dev->caps.num_srqs);
956 if (ret) {
957 dev_err(dev,
958 "failed to init SRQ context memory, aborting.\n");
959 goto err_unmap_cq;
960 }
961 }
962
963 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
964 ret = hns_roce_init_hem_table(hr_dev,
965 &hr_dev->qp_table.sccc_table,
966 HEM_TYPE_SCCC,
967 hr_dev->caps.sccc_sz,
968 hr_dev->caps.num_qps);
969 if (ret) {
970 dev_err(dev,
971 "failed to init SCC context memory, aborting.\n");
972 goto err_unmap_srq;
973 }
974 }
975
976 if (hr_dev->caps.qpc_timer_entry_sz) {
977 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
978 HEM_TYPE_QPC_TIMER,
979 hr_dev->caps.qpc_timer_entry_sz,
980 hr_dev->caps.qpc_timer_bt_num);
981 if (ret) {
982 dev_err(dev,
983 "failed to init QPC timer memory, aborting.\n");
984 goto err_unmap_ctx;
985 }
986 }
987
988 if (hr_dev->caps.cqc_timer_entry_sz) {
989 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
990 HEM_TYPE_CQC_TIMER,
991 hr_dev->caps.cqc_timer_entry_sz,
992 hr_dev->caps.cqc_timer_bt_num);
993 if (ret) {
994 dev_err(dev,
995 "failed to init CQC timer memory, aborting.\n");
996 goto err_unmap_qpc_timer;
997 }
998 }
999
1000 if (hr_dev->caps.gmv_entry_sz) {
1001 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table,
1002 HEM_TYPE_GMV,
1003 hr_dev->caps.gmv_entry_sz,
1004 hr_dev->caps.gmv_entry_num);
1005 if (ret) {
1006 dev_err(dev,
1007 "failed to init gmv table memory, ret = %d\n",
1008 ret);
1009 goto err_unmap_cqc_timer;
1010 }
1011 }
1012
1013 return 0;
1014
1015 err_unmap_cqc_timer:
1016 if (hr_dev->caps.cqc_timer_entry_sz)
1017 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table);
1018
1019 err_unmap_qpc_timer:
1020 if (hr_dev->caps.qpc_timer_entry_sz)
1021 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
1022
1023 err_unmap_ctx:
1024 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
1025 hns_roce_cleanup_hem_table(hr_dev,
1026 &hr_dev->qp_table.sccc_table);
1027 err_unmap_srq:
1028 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
1029 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
1030
1031 err_unmap_cq:
1032 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
1033
1034 err_unmap_trrl:
1035 if (hr_dev->caps.trrl_entry_sz)
1036 hns_roce_cleanup_hem_table(hr_dev,
1037 &hr_dev->qp_table.trrl_table);
1038
1039 err_unmap_irrl:
1040 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
1041
1042 err_unmap_qp:
1043 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
1044
1045 err_unmap_dmpt:
1046 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
1047
1048 return ret;
1049 }
1050
hns_roce_teardown_hca(struct hns_roce_dev * hr_dev)1051 static void hns_roce_teardown_hca(struct hns_roce_dev *hr_dev)
1052 {
1053 hns_roce_cleanup_bitmap(hr_dev);
1054 mutex_destroy(&hr_dev->pgdir_mutex);
1055 }
1056
1057 /**
1058 * hns_roce_setup_hca - setup host channel adapter
1059 * @hr_dev: pointer to hns roce device
1060 * Return : int
1061 */
hns_roce_setup_hca(struct hns_roce_dev * hr_dev)1062 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
1063 {
1064 struct device *dev = hr_dev->dev;
1065 int ret;
1066
1067 spin_lock_init(&hr_dev->sm_lock);
1068
1069 INIT_LIST_HEAD(&hr_dev->qp_list);
1070 spin_lock_init(&hr_dev->qp_list_lock);
1071
1072 INIT_LIST_HEAD(&hr_dev->pgdir_list);
1073 mutex_init(&hr_dev->pgdir_mutex);
1074
1075 hns_roce_init_uar_table(hr_dev);
1076
1077 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
1078 if (ret) {
1079 dev_err(dev, "failed to allocate priv_uar.\n");
1080 goto err_uar_table_free;
1081 }
1082
1083 ret = hns_roce_init_qp_table(hr_dev);
1084 if (ret) {
1085 dev_err(dev, "failed to init qp_table.\n");
1086 goto err_uar_table_free;
1087 }
1088
1089 hns_roce_init_pd_table(hr_dev);
1090
1091 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
1092 hns_roce_init_xrcd_table(hr_dev);
1093
1094 hns_roce_init_mr_table(hr_dev);
1095
1096 hns_roce_init_cq_table(hr_dev);
1097
1098 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
1099 hns_roce_init_srq_table(hr_dev);
1100
1101 return 0;
1102
1103 err_uar_table_free:
1104 ida_destroy(&hr_dev->uar_ida.ida);
1105 mutex_destroy(&hr_dev->pgdir_mutex);
1106
1107 return ret;
1108 }
1109
check_and_get_armed_cq(struct list_head * cq_list,struct ib_cq * cq)1110 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
1111 {
1112 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
1113 unsigned long flags;
1114
1115 spin_lock_irqsave(&hr_cq->lock, flags);
1116 if (cq->comp_handler) {
1117 if (!hr_cq->is_armed) {
1118 hr_cq->is_armed = 1;
1119 list_add_tail(&hr_cq->node, cq_list);
1120 }
1121 }
1122 spin_unlock_irqrestore(&hr_cq->lock, flags);
1123 }
1124
hns_roce_handle_device_err(struct hns_roce_dev * hr_dev)1125 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
1126 {
1127 struct hns_roce_qp *hr_qp;
1128 struct hns_roce_cq *hr_cq;
1129 struct list_head cq_list;
1130 unsigned long flags_qp;
1131 unsigned long flags;
1132
1133 INIT_LIST_HEAD(&cq_list);
1134
1135 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
1136 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
1137 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
1138 if (hr_qp->sq.tail != hr_qp->sq.head)
1139 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
1140 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
1141
1142 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
1143 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
1144 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
1145 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
1146 }
1147
1148 list_for_each_entry(hr_cq, &cq_list, node)
1149 hns_roce_cq_completion(hr_dev, hr_cq->cqn);
1150
1151 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
1152 }
1153
hns_roce_alloc_dfx_cnt(struct hns_roce_dev * hr_dev)1154 static int hns_roce_alloc_dfx_cnt(struct hns_roce_dev *hr_dev)
1155 {
1156 hr_dev->dfx_cnt = kvzalloc_objs(atomic64_t, HNS_ROCE_DFX_CNT_TOTAL);
1157 if (!hr_dev->dfx_cnt)
1158 return -ENOMEM;
1159
1160 return 0;
1161 }
1162
hns_roce_dealloc_dfx_cnt(struct hns_roce_dev * hr_dev)1163 static void hns_roce_dealloc_dfx_cnt(struct hns_roce_dev *hr_dev)
1164 {
1165 kvfree(hr_dev->dfx_cnt);
1166 }
1167
hns_roce_init(struct hns_roce_dev * hr_dev)1168 int hns_roce_init(struct hns_roce_dev *hr_dev)
1169 {
1170 struct device *dev = hr_dev->dev;
1171 int ret;
1172
1173 hr_dev->is_reset = false;
1174
1175 ret = hns_roce_alloc_dfx_cnt(hr_dev);
1176 if (ret)
1177 return ret;
1178
1179 if (hr_dev->hw->cmq_init) {
1180 ret = hr_dev->hw->cmq_init(hr_dev);
1181 if (ret) {
1182 dev_err(dev, "init RoCE Command Queue failed!\n");
1183 goto error_failed_alloc_dfx_cnt;
1184 }
1185 }
1186
1187 ret = hr_dev->hw->hw_profile(hr_dev);
1188 if (ret) {
1189 dev_err(dev, "get RoCE engine profile failed!\n");
1190 goto error_failed_cmd_init;
1191 }
1192
1193 ret = hns_roce_cmd_init(hr_dev);
1194 if (ret) {
1195 dev_err(dev, "cmd init failed!\n");
1196 goto error_failed_cmd_init;
1197 }
1198
1199 /* EQ depends on poll mode, event mode depends on EQ */
1200 ret = hr_dev->hw->init_eq(hr_dev);
1201 if (ret) {
1202 dev_err(dev, "eq init failed!\n");
1203 goto error_failed_eq_table;
1204 }
1205
1206 if (hr_dev->cmd_mod) {
1207 ret = hns_roce_cmd_use_events(hr_dev);
1208 if (ret)
1209 dev_warn(dev,
1210 "Cmd event mode failed, set back to poll!\n");
1211 }
1212
1213 ret = hns_roce_init_hem(hr_dev);
1214 if (ret) {
1215 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
1216 goto error_failed_init_hem;
1217 }
1218
1219 ret = hns_roce_setup_hca(hr_dev);
1220 if (ret) {
1221 dev_err(dev, "setup hca failed!\n");
1222 goto error_failed_setup_hca;
1223 }
1224
1225 if (hr_dev->hw->hw_init) {
1226 ret = hr_dev->hw->hw_init(hr_dev);
1227 if (ret) {
1228 dev_err(dev, "hw_init failed!\n");
1229 goto error_failed_engine_init;
1230 }
1231 }
1232
1233 ret = hns_roce_register_device(hr_dev);
1234 if (ret)
1235 goto error_failed_register_device;
1236
1237 hns_roce_register_debugfs(hr_dev);
1238
1239 return 0;
1240
1241 error_failed_register_device:
1242 if (hr_dev->hw->hw_exit)
1243 hr_dev->hw->hw_exit(hr_dev);
1244
1245 error_failed_engine_init:
1246 hns_roce_teardown_hca(hr_dev);
1247
1248 error_failed_setup_hca:
1249 hns_roce_cleanup_hem(hr_dev);
1250
1251 error_failed_init_hem:
1252 if (hr_dev->cmd_mod)
1253 hns_roce_cmd_use_polling(hr_dev);
1254 hr_dev->hw->cleanup_eq(hr_dev);
1255
1256 error_failed_eq_table:
1257 hns_roce_cmd_cleanup(hr_dev);
1258
1259 error_failed_cmd_init:
1260 if (hr_dev->hw->cmq_exit)
1261 hr_dev->hw->cmq_exit(hr_dev);
1262
1263 error_failed_alloc_dfx_cnt:
1264 hns_roce_dealloc_dfx_cnt(hr_dev);
1265
1266 return ret;
1267 }
1268
hns_roce_exit(struct hns_roce_dev * hr_dev,bool bond_cleanup)1269 void hns_roce_exit(struct hns_roce_dev *hr_dev, bool bond_cleanup)
1270 {
1271 hns_roce_unregister_debugfs(hr_dev);
1272 hns_roce_unregister_device(hr_dev, bond_cleanup);
1273
1274 if (hr_dev->hw->hw_exit)
1275 hr_dev->hw->hw_exit(hr_dev);
1276 hns_roce_teardown_hca(hr_dev);
1277 hns_roce_cleanup_hem(hr_dev);
1278
1279 if (hr_dev->cmd_mod)
1280 hns_roce_cmd_use_polling(hr_dev);
1281
1282 hr_dev->hw->cleanup_eq(hr_dev);
1283 hns_roce_cmd_cleanup(hr_dev);
1284 if (hr_dev->hw->cmq_exit)
1285 hr_dev->hw->cmq_exit(hr_dev);
1286 hns_roce_dealloc_dfx_cnt(hr_dev);
1287 }
1288
1289 MODULE_LICENSE("Dual BSD/GPL");
1290 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
1291 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
1292 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
1293 MODULE_DESCRIPTION("HNS RoCE Driver");
1294