1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
9 #endif
10 #include <linux/if_vlan.h>
11 #include <linux/irq.h>
12 #include <linux/ip.h>
13 #include <linux/ipv6.h>
14 #include <linux/iommu.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/skbuff.h>
18 #include <linux/sctp.h>
19 #include <net/gre.h>
20 #include <net/gro.h>
21 #include <net/ip6_checksum.h>
22 #include <net/page_pool/helpers.h>
23 #include <net/pkt_cls.h>
24 #include <net/pkt_sched.h>
25 #include <net/tcp.h>
26 #include <net/vxlan.h>
27 #include <net/geneve.h>
28
29 #include "hnae3.h"
30 #include "hns3_enet.h"
31 /* All hns3 tracepoints are defined by the include below, which
32 * must be included exactly once across the whole kernel with
33 * CREATE_TRACE_POINTS defined
34 */
35 #define CREATE_TRACE_POINTS
36 #include "hns3_trace.h"
37
38 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift))
39 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
40
41 #define hns3_rl_err(fmt, ...) \
42 do { \
43 if (net_ratelimit()) \
44 netdev_err(fmt, ##__VA_ARGS__); \
45 } while (0)
46
47 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
48
49 static const char hns3_driver_name[] = "hns3";
50 static const char hns3_driver_string[] =
51 "Hisilicon Ethernet Network Driver for Hip08 Family";
52 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
53 static struct hnae3_client client;
54
55 static int debug = -1;
56 module_param(debug, int, 0);
57 MODULE_PARM_DESC(debug, " Network interface message level setting");
58
59 static unsigned int tx_sgl = 1;
60 module_param(tx_sgl, uint, 0600);
61 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
62
63 static bool page_pool_enabled = true;
64 module_param(page_pool_enabled, bool, 0400);
65
66 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \
67 sizeof(struct sg_table))
68 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
69 dma_get_cache_alignment())
70
71 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
72 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
73
74 #define HNS3_INNER_VLAN_TAG 1
75 #define HNS3_OUTER_VLAN_TAG 2
76
77 #define HNS3_MIN_TX_LEN 33U
78 #define HNS3_MIN_TUN_PKT_LEN 65U
79
80 /* hns3_pci_tbl - PCI Device ID Table
81 *
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
87 static const struct pci_device_id hns3_pci_tbl[] = {
88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
90 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
91 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
92 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
93 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
94 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
95 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
96 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
97 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
98 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
99 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
100 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
101 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
102 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
103 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
104 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
105 /* required last entry */
106 {0,}
107 };
108 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
109
110 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t, h) \
111 { ptype, \
112 l, \
113 CHECKSUM_##s, \
114 HNS3_L3_TYPE_##t, \
115 1, \
116 h}
117
118 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
119 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0, \
120 PKT_HASH_TYPE_NONE }
121
122 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
123 HNS3_RX_PTYPE_UNUSED_ENTRY(0),
124 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP, PKT_HASH_TYPE_NONE),
125 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP, PKT_HASH_TYPE_NONE),
126 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP, PKT_HASH_TYPE_NONE),
127 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
128 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
129 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
130 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM, PKT_HASH_TYPE_NONE),
131 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
132 HNS3_RX_PTYPE_UNUSED_ENTRY(9),
133 HNS3_RX_PTYPE_UNUSED_ENTRY(10),
134 HNS3_RX_PTYPE_UNUSED_ENTRY(11),
135 HNS3_RX_PTYPE_UNUSED_ENTRY(12),
136 HNS3_RX_PTYPE_UNUSED_ENTRY(13),
137 HNS3_RX_PTYPE_UNUSED_ENTRY(14),
138 HNS3_RX_PTYPE_UNUSED_ENTRY(15),
139 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
140 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
141 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
142 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
143 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
144 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4, PKT_HASH_TYPE_NONE),
145 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
146 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
147 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
148 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
149 HNS3_RX_PTYPE_UNUSED_ENTRY(26),
150 HNS3_RX_PTYPE_UNUSED_ENTRY(27),
151 HNS3_RX_PTYPE_UNUSED_ENTRY(28),
152 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
153 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
154 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
155 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
156 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
157 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
158 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
159 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
160 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
161 HNS3_RX_PTYPE_UNUSED_ENTRY(38),
162 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
163 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
164 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
165 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
166 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
167 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
168 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
169 HNS3_RX_PTYPE_UNUSED_ENTRY(46),
170 HNS3_RX_PTYPE_UNUSED_ENTRY(47),
171 HNS3_RX_PTYPE_UNUSED_ENTRY(48),
172 HNS3_RX_PTYPE_UNUSED_ENTRY(49),
173 HNS3_RX_PTYPE_UNUSED_ENTRY(50),
174 HNS3_RX_PTYPE_UNUSED_ENTRY(51),
175 HNS3_RX_PTYPE_UNUSED_ENTRY(52),
176 HNS3_RX_PTYPE_UNUSED_ENTRY(53),
177 HNS3_RX_PTYPE_UNUSED_ENTRY(54),
178 HNS3_RX_PTYPE_UNUSED_ENTRY(55),
179 HNS3_RX_PTYPE_UNUSED_ENTRY(56),
180 HNS3_RX_PTYPE_UNUSED_ENTRY(57),
181 HNS3_RX_PTYPE_UNUSED_ENTRY(58),
182 HNS3_RX_PTYPE_UNUSED_ENTRY(59),
183 HNS3_RX_PTYPE_UNUSED_ENTRY(60),
184 HNS3_RX_PTYPE_UNUSED_ENTRY(61),
185 HNS3_RX_PTYPE_UNUSED_ENTRY(62),
186 HNS3_RX_PTYPE_UNUSED_ENTRY(63),
187 HNS3_RX_PTYPE_UNUSED_ENTRY(64),
188 HNS3_RX_PTYPE_UNUSED_ENTRY(65),
189 HNS3_RX_PTYPE_UNUSED_ENTRY(66),
190 HNS3_RX_PTYPE_UNUSED_ENTRY(67),
191 HNS3_RX_PTYPE_UNUSED_ENTRY(68),
192 HNS3_RX_PTYPE_UNUSED_ENTRY(69),
193 HNS3_RX_PTYPE_UNUSED_ENTRY(70),
194 HNS3_RX_PTYPE_UNUSED_ENTRY(71),
195 HNS3_RX_PTYPE_UNUSED_ENTRY(72),
196 HNS3_RX_PTYPE_UNUSED_ENTRY(73),
197 HNS3_RX_PTYPE_UNUSED_ENTRY(74),
198 HNS3_RX_PTYPE_UNUSED_ENTRY(75),
199 HNS3_RX_PTYPE_UNUSED_ENTRY(76),
200 HNS3_RX_PTYPE_UNUSED_ENTRY(77),
201 HNS3_RX_PTYPE_UNUSED_ENTRY(78),
202 HNS3_RX_PTYPE_UNUSED_ENTRY(79),
203 HNS3_RX_PTYPE_UNUSED_ENTRY(80),
204 HNS3_RX_PTYPE_UNUSED_ENTRY(81),
205 HNS3_RX_PTYPE_UNUSED_ENTRY(82),
206 HNS3_RX_PTYPE_UNUSED_ENTRY(83),
207 HNS3_RX_PTYPE_UNUSED_ENTRY(84),
208 HNS3_RX_PTYPE_UNUSED_ENTRY(85),
209 HNS3_RX_PTYPE_UNUSED_ENTRY(86),
210 HNS3_RX_PTYPE_UNUSED_ENTRY(87),
211 HNS3_RX_PTYPE_UNUSED_ENTRY(88),
212 HNS3_RX_PTYPE_UNUSED_ENTRY(89),
213 HNS3_RX_PTYPE_UNUSED_ENTRY(90),
214 HNS3_RX_PTYPE_UNUSED_ENTRY(91),
215 HNS3_RX_PTYPE_UNUSED_ENTRY(92),
216 HNS3_RX_PTYPE_UNUSED_ENTRY(93),
217 HNS3_RX_PTYPE_UNUSED_ENTRY(94),
218 HNS3_RX_PTYPE_UNUSED_ENTRY(95),
219 HNS3_RX_PTYPE_UNUSED_ENTRY(96),
220 HNS3_RX_PTYPE_UNUSED_ENTRY(97),
221 HNS3_RX_PTYPE_UNUSED_ENTRY(98),
222 HNS3_RX_PTYPE_UNUSED_ENTRY(99),
223 HNS3_RX_PTYPE_UNUSED_ENTRY(100),
224 HNS3_RX_PTYPE_UNUSED_ENTRY(101),
225 HNS3_RX_PTYPE_UNUSED_ENTRY(102),
226 HNS3_RX_PTYPE_UNUSED_ENTRY(103),
227 HNS3_RX_PTYPE_UNUSED_ENTRY(104),
228 HNS3_RX_PTYPE_UNUSED_ENTRY(105),
229 HNS3_RX_PTYPE_UNUSED_ENTRY(106),
230 HNS3_RX_PTYPE_UNUSED_ENTRY(107),
231 HNS3_RX_PTYPE_UNUSED_ENTRY(108),
232 HNS3_RX_PTYPE_UNUSED_ENTRY(109),
233 HNS3_RX_PTYPE_UNUSED_ENTRY(110),
234 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
235 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
236 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
237 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
238 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
239 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
240 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
241 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
242 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
243 HNS3_RX_PTYPE_UNUSED_ENTRY(120),
244 HNS3_RX_PTYPE_UNUSED_ENTRY(121),
245 HNS3_RX_PTYPE_UNUSED_ENTRY(122),
246 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
247 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
248 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
249 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
250 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
251 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
252 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
253 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
254 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
255 HNS3_RX_PTYPE_UNUSED_ENTRY(132),
256 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
257 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
258 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
259 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
260 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
261 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
262 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
263 HNS3_RX_PTYPE_UNUSED_ENTRY(140),
264 HNS3_RX_PTYPE_UNUSED_ENTRY(141),
265 HNS3_RX_PTYPE_UNUSED_ENTRY(142),
266 HNS3_RX_PTYPE_UNUSED_ENTRY(143),
267 HNS3_RX_PTYPE_UNUSED_ENTRY(144),
268 HNS3_RX_PTYPE_UNUSED_ENTRY(145),
269 HNS3_RX_PTYPE_UNUSED_ENTRY(146),
270 HNS3_RX_PTYPE_UNUSED_ENTRY(147),
271 HNS3_RX_PTYPE_UNUSED_ENTRY(148),
272 HNS3_RX_PTYPE_UNUSED_ENTRY(149),
273 HNS3_RX_PTYPE_UNUSED_ENTRY(150),
274 HNS3_RX_PTYPE_UNUSED_ENTRY(151),
275 HNS3_RX_PTYPE_UNUSED_ENTRY(152),
276 HNS3_RX_PTYPE_UNUSED_ENTRY(153),
277 HNS3_RX_PTYPE_UNUSED_ENTRY(154),
278 HNS3_RX_PTYPE_UNUSED_ENTRY(155),
279 HNS3_RX_PTYPE_UNUSED_ENTRY(156),
280 HNS3_RX_PTYPE_UNUSED_ENTRY(157),
281 HNS3_RX_PTYPE_UNUSED_ENTRY(158),
282 HNS3_RX_PTYPE_UNUSED_ENTRY(159),
283 HNS3_RX_PTYPE_UNUSED_ENTRY(160),
284 HNS3_RX_PTYPE_UNUSED_ENTRY(161),
285 HNS3_RX_PTYPE_UNUSED_ENTRY(162),
286 HNS3_RX_PTYPE_UNUSED_ENTRY(163),
287 HNS3_RX_PTYPE_UNUSED_ENTRY(164),
288 HNS3_RX_PTYPE_UNUSED_ENTRY(165),
289 HNS3_RX_PTYPE_UNUSED_ENTRY(166),
290 HNS3_RX_PTYPE_UNUSED_ENTRY(167),
291 HNS3_RX_PTYPE_UNUSED_ENTRY(168),
292 HNS3_RX_PTYPE_UNUSED_ENTRY(169),
293 HNS3_RX_PTYPE_UNUSED_ENTRY(170),
294 HNS3_RX_PTYPE_UNUSED_ENTRY(171),
295 HNS3_RX_PTYPE_UNUSED_ENTRY(172),
296 HNS3_RX_PTYPE_UNUSED_ENTRY(173),
297 HNS3_RX_PTYPE_UNUSED_ENTRY(174),
298 HNS3_RX_PTYPE_UNUSED_ENTRY(175),
299 HNS3_RX_PTYPE_UNUSED_ENTRY(176),
300 HNS3_RX_PTYPE_UNUSED_ENTRY(177),
301 HNS3_RX_PTYPE_UNUSED_ENTRY(178),
302 HNS3_RX_PTYPE_UNUSED_ENTRY(179),
303 HNS3_RX_PTYPE_UNUSED_ENTRY(180),
304 HNS3_RX_PTYPE_UNUSED_ENTRY(181),
305 HNS3_RX_PTYPE_UNUSED_ENTRY(182),
306 HNS3_RX_PTYPE_UNUSED_ENTRY(183),
307 HNS3_RX_PTYPE_UNUSED_ENTRY(184),
308 HNS3_RX_PTYPE_UNUSED_ENTRY(185),
309 HNS3_RX_PTYPE_UNUSED_ENTRY(186),
310 HNS3_RX_PTYPE_UNUSED_ENTRY(187),
311 HNS3_RX_PTYPE_UNUSED_ENTRY(188),
312 HNS3_RX_PTYPE_UNUSED_ENTRY(189),
313 HNS3_RX_PTYPE_UNUSED_ENTRY(190),
314 HNS3_RX_PTYPE_UNUSED_ENTRY(191),
315 HNS3_RX_PTYPE_UNUSED_ENTRY(192),
316 HNS3_RX_PTYPE_UNUSED_ENTRY(193),
317 HNS3_RX_PTYPE_UNUSED_ENTRY(194),
318 HNS3_RX_PTYPE_UNUSED_ENTRY(195),
319 HNS3_RX_PTYPE_UNUSED_ENTRY(196),
320 HNS3_RX_PTYPE_UNUSED_ENTRY(197),
321 HNS3_RX_PTYPE_UNUSED_ENTRY(198),
322 HNS3_RX_PTYPE_UNUSED_ENTRY(199),
323 HNS3_RX_PTYPE_UNUSED_ENTRY(200),
324 HNS3_RX_PTYPE_UNUSED_ENTRY(201),
325 HNS3_RX_PTYPE_UNUSED_ENTRY(202),
326 HNS3_RX_PTYPE_UNUSED_ENTRY(203),
327 HNS3_RX_PTYPE_UNUSED_ENTRY(204),
328 HNS3_RX_PTYPE_UNUSED_ENTRY(205),
329 HNS3_RX_PTYPE_UNUSED_ENTRY(206),
330 HNS3_RX_PTYPE_UNUSED_ENTRY(207),
331 HNS3_RX_PTYPE_UNUSED_ENTRY(208),
332 HNS3_RX_PTYPE_UNUSED_ENTRY(209),
333 HNS3_RX_PTYPE_UNUSED_ENTRY(210),
334 HNS3_RX_PTYPE_UNUSED_ENTRY(211),
335 HNS3_RX_PTYPE_UNUSED_ENTRY(212),
336 HNS3_RX_PTYPE_UNUSED_ENTRY(213),
337 HNS3_RX_PTYPE_UNUSED_ENTRY(214),
338 HNS3_RX_PTYPE_UNUSED_ENTRY(215),
339 HNS3_RX_PTYPE_UNUSED_ENTRY(216),
340 HNS3_RX_PTYPE_UNUSED_ENTRY(217),
341 HNS3_RX_PTYPE_UNUSED_ENTRY(218),
342 HNS3_RX_PTYPE_UNUSED_ENTRY(219),
343 HNS3_RX_PTYPE_UNUSED_ENTRY(220),
344 HNS3_RX_PTYPE_UNUSED_ENTRY(221),
345 HNS3_RX_PTYPE_UNUSED_ENTRY(222),
346 HNS3_RX_PTYPE_UNUSED_ENTRY(223),
347 HNS3_RX_PTYPE_UNUSED_ENTRY(224),
348 HNS3_RX_PTYPE_UNUSED_ENTRY(225),
349 HNS3_RX_PTYPE_UNUSED_ENTRY(226),
350 HNS3_RX_PTYPE_UNUSED_ENTRY(227),
351 HNS3_RX_PTYPE_UNUSED_ENTRY(228),
352 HNS3_RX_PTYPE_UNUSED_ENTRY(229),
353 HNS3_RX_PTYPE_UNUSED_ENTRY(230),
354 HNS3_RX_PTYPE_UNUSED_ENTRY(231),
355 HNS3_RX_PTYPE_UNUSED_ENTRY(232),
356 HNS3_RX_PTYPE_UNUSED_ENTRY(233),
357 HNS3_RX_PTYPE_UNUSED_ENTRY(234),
358 HNS3_RX_PTYPE_UNUSED_ENTRY(235),
359 HNS3_RX_PTYPE_UNUSED_ENTRY(236),
360 HNS3_RX_PTYPE_UNUSED_ENTRY(237),
361 HNS3_RX_PTYPE_UNUSED_ENTRY(238),
362 HNS3_RX_PTYPE_UNUSED_ENTRY(239),
363 HNS3_RX_PTYPE_UNUSED_ENTRY(240),
364 HNS3_RX_PTYPE_UNUSED_ENTRY(241),
365 HNS3_RX_PTYPE_UNUSED_ENTRY(242),
366 HNS3_RX_PTYPE_UNUSED_ENTRY(243),
367 HNS3_RX_PTYPE_UNUSED_ENTRY(244),
368 HNS3_RX_PTYPE_UNUSED_ENTRY(245),
369 HNS3_RX_PTYPE_UNUSED_ENTRY(246),
370 HNS3_RX_PTYPE_UNUSED_ENTRY(247),
371 HNS3_RX_PTYPE_UNUSED_ENTRY(248),
372 HNS3_RX_PTYPE_UNUSED_ENTRY(249),
373 HNS3_RX_PTYPE_UNUSED_ENTRY(250),
374 HNS3_RX_PTYPE_UNUSED_ENTRY(251),
375 HNS3_RX_PTYPE_UNUSED_ENTRY(252),
376 HNS3_RX_PTYPE_UNUSED_ENTRY(253),
377 HNS3_RX_PTYPE_UNUSED_ENTRY(254),
378 HNS3_RX_PTYPE_UNUSED_ENTRY(255),
379 };
380
381 #define HNS3_INVALID_PTYPE \
382 ARRAY_SIZE(hns3_rx_ptype_tbl)
383
hns3_dma_map_sync(struct device * dev,unsigned long iova)384 static void hns3_dma_map_sync(struct device *dev, unsigned long iova)
385 {
386 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
387 struct iommu_iotlb_gather iotlb_gather;
388 size_t granule;
389
390 if (!domain || !iommu_is_dma_domain(domain))
391 return;
392
393 granule = 1 << __ffs(domain->pgsize_bitmap);
394 iova = ALIGN_DOWN(iova, granule);
395 iotlb_gather.start = iova;
396 iotlb_gather.end = iova + granule - 1;
397 iotlb_gather.pgsize = granule;
398
399 iommu_iotlb_sync(domain, &iotlb_gather);
400 }
401
hns3_irq_handle(int irq,void * vector)402 static irqreturn_t hns3_irq_handle(int irq, void *vector)
403 {
404 struct hns3_enet_tqp_vector *tqp_vector = vector;
405
406 napi_schedule_irqoff(&tqp_vector->napi);
407 tqp_vector->event_cnt++;
408
409 return IRQ_HANDLED;
410 }
411
hns3_nic_uninit_irq(struct hns3_nic_priv * priv)412 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
413 {
414 struct hns3_enet_tqp_vector *tqp_vectors;
415 unsigned int i;
416
417 for (i = 0; i < priv->vector_num; i++) {
418 tqp_vectors = &priv->tqp_vector[i];
419
420 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
421 continue;
422
423 /* clear the affinity mask */
424 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
425
426 /* release the irq resource */
427 free_irq(tqp_vectors->vector_irq, tqp_vectors);
428 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
429 }
430 }
431
hns3_nic_init_irq(struct hns3_nic_priv * priv)432 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
433 {
434 struct hns3_enet_tqp_vector *tqp_vectors;
435 int txrx_int_idx = 0;
436 int rx_int_idx = 0;
437 int tx_int_idx = 0;
438 unsigned int i;
439 int ret;
440
441 for (i = 0; i < priv->vector_num; i++) {
442 tqp_vectors = &priv->tqp_vector[i];
443
444 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
445 continue;
446
447 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
448 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
449 "%s-%s-%s-%d", hns3_driver_name,
450 pci_name(priv->ae_handle->pdev),
451 "TxRx", txrx_int_idx++);
452 txrx_int_idx++;
453 } else if (tqp_vectors->rx_group.ring) {
454 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
455 "%s-%s-%s-%d", hns3_driver_name,
456 pci_name(priv->ae_handle->pdev),
457 "Rx", rx_int_idx++);
458 } else if (tqp_vectors->tx_group.ring) {
459 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
460 "%s-%s-%s-%d", hns3_driver_name,
461 pci_name(priv->ae_handle->pdev),
462 "Tx", tx_int_idx++);
463 } else {
464 /* Skip this unused q_vector */
465 continue;
466 }
467
468 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
469
470 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
471 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
472 tqp_vectors->name, tqp_vectors);
473 if (ret) {
474 netdev_err(priv->netdev, "request irq(%d) fail\n",
475 tqp_vectors->vector_irq);
476 hns3_nic_uninit_irq(priv);
477 return ret;
478 }
479
480 irq_set_affinity_hint(tqp_vectors->vector_irq,
481 &tqp_vectors->affinity_mask);
482
483 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
484 }
485
486 return 0;
487 }
488
hns3_mask_vector_irq(struct hns3_enet_tqp_vector * tqp_vector,u32 mask_en)489 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
490 u32 mask_en)
491 {
492 writel(mask_en, tqp_vector->mask_addr);
493 }
494
hns3_vector_enable(struct hns3_enet_tqp_vector * tqp_vector)495 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
496 {
497 napi_enable(&tqp_vector->napi);
498 enable_irq(tqp_vector->vector_irq);
499
500 /* enable vector */
501 hns3_mask_vector_irq(tqp_vector, 1);
502 }
503
hns3_vector_disable(struct hns3_enet_tqp_vector * tqp_vector)504 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
505 {
506 /* disable vector */
507 hns3_mask_vector_irq(tqp_vector, 0);
508
509 disable_irq(tqp_vector->vector_irq);
510 napi_disable(&tqp_vector->napi);
511 cancel_work_sync(&tqp_vector->rx_group.dim.work);
512 cancel_work_sync(&tqp_vector->tx_group.dim.work);
513 }
514
hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector * tqp_vector,u32 rl_value)515 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
516 u32 rl_value)
517 {
518 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
519
520 /* this defines the configuration for RL (Interrupt Rate Limiter).
521 * Rl defines rate of interrupts i.e. number of interrupts-per-second
522 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
523 */
524 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
525 !tqp_vector->rx_group.coal.adapt_enable)
526 /* According to the hardware, the range of rl_reg is
527 * 0-59 and the unit is 4.
528 */
529 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
530
531 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
532 }
533
hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)534 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
535 u32 gl_value)
536 {
537 u32 new_val;
538
539 if (tqp_vector->rx_group.coal.unit_1us)
540 new_val = gl_value | HNS3_INT_GL_1US;
541 else
542 new_val = hns3_gl_usec_to_reg(gl_value);
543
544 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
545 }
546
hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)547 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
548 u32 gl_value)
549 {
550 u32 new_val;
551
552 if (tqp_vector->tx_group.coal.unit_1us)
553 new_val = gl_value | HNS3_INT_GL_1US;
554 else
555 new_val = hns3_gl_usec_to_reg(gl_value);
556
557 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
558 }
559
hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)560 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
561 u32 ql_value)
562 {
563 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
564 }
565
hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)566 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
567 u32 ql_value)
568 {
569 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
570 }
571
hns3_vector_coalesce_init(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)572 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
573 struct hns3_nic_priv *priv)
574 {
575 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
576 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
577 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
578 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
579 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
580
581 tx_coal->adapt_enable = ptx_coal->adapt_enable;
582 rx_coal->adapt_enable = prx_coal->adapt_enable;
583
584 tx_coal->int_gl = ptx_coal->int_gl;
585 rx_coal->int_gl = prx_coal->int_gl;
586
587 rx_coal->flow_level = prx_coal->flow_level;
588 tx_coal->flow_level = ptx_coal->flow_level;
589
590 /* device version above V3(include V3), GL can configure 1us
591 * unit, so uses 1us unit.
592 */
593 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
594 tx_coal->unit_1us = 1;
595 rx_coal->unit_1us = 1;
596 }
597
598 if (ae_dev->dev_specs.int_ql_max) {
599 tx_coal->ql_enable = 1;
600 rx_coal->ql_enable = 1;
601 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
602 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
603 tx_coal->int_ql = ptx_coal->int_ql;
604 rx_coal->int_ql = prx_coal->int_ql;
605 }
606 }
607
608 static void
hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)609 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
610 struct hns3_nic_priv *priv)
611 {
612 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
613 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
614 struct hnae3_handle *h = priv->ae_handle;
615
616 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
617 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
618 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
619
620 if (tx_coal->ql_enable)
621 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
622
623 if (rx_coal->ql_enable)
624 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
625 }
626
hns3_nic_set_real_num_queue(struct net_device * netdev)627 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
628 {
629 struct hnae3_handle *h = hns3_get_handle(netdev);
630 struct hnae3_knic_private_info *kinfo = &h->kinfo;
631 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
632 unsigned int queue_size = kinfo->num_tqps;
633 int i, ret;
634
635 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
636 netdev_reset_tc(netdev);
637 } else {
638 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
639 if (ret) {
640 netdev_err(netdev,
641 "netdev_set_num_tc fail, ret=%d!\n", ret);
642 return ret;
643 }
644
645 for (i = 0; i < tc_info->num_tc; i++)
646 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
647 tc_info->tqp_offset[i]);
648 }
649
650 ret = netif_set_real_num_tx_queues(netdev, queue_size);
651 if (ret) {
652 netdev_err(netdev,
653 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
654 return ret;
655 }
656
657 ret = netif_set_real_num_rx_queues(netdev, queue_size);
658 if (ret) {
659 netdev_err(netdev,
660 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
661 return ret;
662 }
663
664 return 0;
665 }
666
hns3_get_max_available_channels(struct hnae3_handle * h)667 u16 hns3_get_max_available_channels(struct hnae3_handle *h)
668 {
669 u16 alloc_tqps, max_rss_size, rss_size;
670
671 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
672 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
673
674 return min_t(u16, rss_size, max_rss_size);
675 }
676
hns3_tqp_enable(struct hnae3_queue * tqp)677 static void hns3_tqp_enable(struct hnae3_queue *tqp)
678 {
679 u32 rcb_reg;
680
681 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
682 rcb_reg |= BIT(HNS3_RING_EN_B);
683 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
684 }
685
hns3_tqp_disable(struct hnae3_queue * tqp)686 static void hns3_tqp_disable(struct hnae3_queue *tqp)
687 {
688 u32 rcb_reg;
689
690 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
691 rcb_reg &= ~BIT(HNS3_RING_EN_B);
692 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
693 }
694
hns3_free_rx_cpu_rmap(struct net_device * netdev)695 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
696 {
697 #ifdef CONFIG_RFS_ACCEL
698 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
699 netdev->rx_cpu_rmap = NULL;
700 #endif
701 }
702
hns3_set_rx_cpu_rmap(struct net_device * netdev)703 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
704 {
705 #ifdef CONFIG_RFS_ACCEL
706 struct hns3_nic_priv *priv = netdev_priv(netdev);
707 struct hns3_enet_tqp_vector *tqp_vector;
708 int i, ret;
709
710 if (!netdev->rx_cpu_rmap) {
711 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
712 if (!netdev->rx_cpu_rmap)
713 return -ENOMEM;
714 }
715
716 for (i = 0; i < priv->vector_num; i++) {
717 tqp_vector = &priv->tqp_vector[i];
718 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
719 tqp_vector->vector_irq);
720 if (ret) {
721 hns3_free_rx_cpu_rmap(netdev);
722 return ret;
723 }
724 }
725 #endif
726 return 0;
727 }
728
hns3_nic_net_up(struct net_device * netdev)729 static int hns3_nic_net_up(struct net_device *netdev)
730 {
731 struct hns3_nic_priv *priv = netdev_priv(netdev);
732 struct hnae3_handle *h = priv->ae_handle;
733 int i, j;
734 int ret;
735
736 ret = hns3_nic_reset_all_ring(h);
737 if (ret)
738 return ret;
739
740 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
741
742 /* enable the vectors */
743 for (i = 0; i < priv->vector_num; i++)
744 hns3_vector_enable(&priv->tqp_vector[i]);
745
746 /* enable rcb */
747 for (j = 0; j < h->kinfo.num_tqps; j++)
748 hns3_tqp_enable(h->kinfo.tqp[j]);
749
750 /* start the ae_dev */
751 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
752 if (ret) {
753 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
754 while (j--)
755 hns3_tqp_disable(h->kinfo.tqp[j]);
756
757 for (j = i - 1; j >= 0; j--)
758 hns3_vector_disable(&priv->tqp_vector[j]);
759 }
760
761 return ret;
762 }
763
hns3_config_xps(struct hns3_nic_priv * priv)764 static void hns3_config_xps(struct hns3_nic_priv *priv)
765 {
766 int i;
767
768 for (i = 0; i < priv->vector_num; i++) {
769 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
770 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
771
772 while (ring) {
773 int ret;
774
775 ret = netif_set_xps_queue(priv->netdev,
776 &tqp_vector->affinity_mask,
777 ring->tqp->tqp_index);
778 if (ret)
779 netdev_warn(priv->netdev,
780 "set xps queue failed: %d", ret);
781
782 ring = ring->next;
783 }
784 }
785 }
786
hns3_nic_net_open(struct net_device * netdev)787 static int hns3_nic_net_open(struct net_device *netdev)
788 {
789 struct hns3_nic_priv *priv = netdev_priv(netdev);
790 struct hnae3_handle *h = hns3_get_handle(netdev);
791 struct hnae3_knic_private_info *kinfo;
792 int i, ret;
793
794 if (hns3_nic_resetting(netdev))
795 return -EBUSY;
796
797 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
798 netdev_warn(netdev, "net open repeatedly!\n");
799 return 0;
800 }
801
802 netif_carrier_off(netdev);
803
804 ret = hns3_nic_set_real_num_queue(netdev);
805 if (ret)
806 return ret;
807
808 ret = hns3_nic_net_up(netdev);
809 if (ret) {
810 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
811 return ret;
812 }
813
814 kinfo = &h->kinfo;
815 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
816 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
817
818 if (h->ae_algo->ops->set_timer_task)
819 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
820
821 hns3_config_xps(priv);
822
823 netif_dbg(h, drv, netdev, "net open\n");
824
825 return 0;
826 }
827
hns3_reset_tx_queue(struct hnae3_handle * h)828 static void hns3_reset_tx_queue(struct hnae3_handle *h)
829 {
830 struct net_device *ndev = h->kinfo.netdev;
831 struct hns3_nic_priv *priv = netdev_priv(ndev);
832 struct netdev_queue *dev_queue;
833 u32 i;
834
835 for (i = 0; i < h->kinfo.num_tqps; i++) {
836 dev_queue = netdev_get_tx_queue(ndev,
837 priv->ring[i].queue_index);
838 netdev_tx_reset_queue(dev_queue);
839 }
840 }
841
hns3_nic_net_down(struct net_device * netdev)842 static void hns3_nic_net_down(struct net_device *netdev)
843 {
844 struct hns3_nic_priv *priv = netdev_priv(netdev);
845 struct hnae3_handle *h = hns3_get_handle(netdev);
846 const struct hnae3_ae_ops *ops;
847 int i;
848
849 /* disable vectors */
850 for (i = 0; i < priv->vector_num; i++)
851 hns3_vector_disable(&priv->tqp_vector[i]);
852
853 /* disable rcb */
854 for (i = 0; i < h->kinfo.num_tqps; i++)
855 hns3_tqp_disable(h->kinfo.tqp[i]);
856
857 /* stop ae_dev */
858 ops = priv->ae_handle->ae_algo->ops;
859 if (ops->stop)
860 ops->stop(priv->ae_handle);
861
862 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
863 * during reset process, because driver may not be able
864 * to disable the ring through firmware when downing the netdev.
865 */
866 if (!hns3_nic_resetting(netdev))
867 hns3_clear_all_ring(priv->ae_handle, false);
868
869 hns3_reset_tx_queue(priv->ae_handle);
870 }
871
hns3_nic_net_stop(struct net_device * netdev)872 static int hns3_nic_net_stop(struct net_device *netdev)
873 {
874 struct hns3_nic_priv *priv = netdev_priv(netdev);
875 struct hnae3_handle *h = hns3_get_handle(netdev);
876
877 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
878 return 0;
879
880 netif_dbg(h, drv, netdev, "net stop\n");
881
882 if (h->ae_algo->ops->set_timer_task)
883 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
884
885 netif_carrier_off(netdev);
886 netif_tx_disable(netdev);
887
888 hns3_nic_net_down(netdev);
889
890 return 0;
891 }
892
hns3_nic_uc_sync(struct net_device * netdev,const unsigned char * addr)893 static int hns3_nic_uc_sync(struct net_device *netdev,
894 const unsigned char *addr)
895 {
896 struct hnae3_handle *h = hns3_get_handle(netdev);
897
898 if (h->ae_algo->ops->add_uc_addr)
899 return h->ae_algo->ops->add_uc_addr(h, addr);
900
901 return 0;
902 }
903
hns3_nic_uc_unsync(struct net_device * netdev,const unsigned char * addr)904 static int hns3_nic_uc_unsync(struct net_device *netdev,
905 const unsigned char *addr)
906 {
907 struct hnae3_handle *h = hns3_get_handle(netdev);
908
909 /* need ignore the request of removing device address, because
910 * we store the device address and other addresses of uc list
911 * in the function's mac filter list.
912 */
913 if (ether_addr_equal(addr, netdev->dev_addr))
914 return 0;
915
916 if (h->ae_algo->ops->rm_uc_addr)
917 return h->ae_algo->ops->rm_uc_addr(h, addr);
918
919 return 0;
920 }
921
hns3_nic_mc_sync(struct net_device * netdev,const unsigned char * addr)922 static int hns3_nic_mc_sync(struct net_device *netdev,
923 const unsigned char *addr)
924 {
925 struct hnae3_handle *h = hns3_get_handle(netdev);
926
927 if (h->ae_algo->ops->add_mc_addr)
928 return h->ae_algo->ops->add_mc_addr(h, addr);
929
930 return 0;
931 }
932
hns3_nic_mc_unsync(struct net_device * netdev,const unsigned char * addr)933 static int hns3_nic_mc_unsync(struct net_device *netdev,
934 const unsigned char *addr)
935 {
936 struct hnae3_handle *h = hns3_get_handle(netdev);
937
938 if (h->ae_algo->ops->rm_mc_addr)
939 return h->ae_algo->ops->rm_mc_addr(h, addr);
940
941 return 0;
942 }
943
hns3_get_netdev_flags(struct net_device * netdev)944 static u8 hns3_get_netdev_flags(struct net_device *netdev)
945 {
946 u8 flags = 0;
947
948 if (netdev->flags & IFF_PROMISC)
949 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
950 else if (netdev->flags & IFF_ALLMULTI)
951 flags = HNAE3_USER_MPE;
952
953 return flags;
954 }
955
hns3_nic_set_rx_mode(struct net_device * netdev)956 static void hns3_nic_set_rx_mode(struct net_device *netdev)
957 {
958 struct hnae3_handle *h = hns3_get_handle(netdev);
959 u8 new_flags;
960
961 new_flags = hns3_get_netdev_flags(netdev);
962
963 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
964 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
965
966 /* User mode Promisc mode enable and vlan filtering is disabled to
967 * let all packets in.
968 */
969 h->netdev_flags = new_flags;
970 hns3_request_update_promisc_mode(h);
971 }
972
hns3_request_update_promisc_mode(struct hnae3_handle * handle)973 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
974 {
975 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
976
977 if (ops->request_update_promisc_mode)
978 ops->request_update_promisc_mode(handle);
979 }
980
hns3_tx_spare_space(struct hns3_enet_ring * ring)981 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
982 {
983 struct hns3_tx_spare *tx_spare = ring->tx_spare;
984 u32 ntc, ntu;
985
986 /* This smp_load_acquire() pairs with smp_store_release() in
987 * hns3_tx_spare_update() called in tx desc cleaning process.
988 */
989 ntc = smp_load_acquire(&tx_spare->last_to_clean);
990 ntu = tx_spare->next_to_use;
991
992 if (ntc > ntu)
993 return ntc - ntu - 1;
994
995 /* The free tx buffer is divided into two part, so pick the
996 * larger one.
997 */
998 return max(ntc, tx_spare->len - ntu) - 1;
999 }
1000
hns3_tx_spare_update(struct hns3_enet_ring * ring)1001 static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
1002 {
1003 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1004
1005 if (!tx_spare ||
1006 tx_spare->last_to_clean == tx_spare->next_to_clean)
1007 return;
1008
1009 /* This smp_store_release() pairs with smp_load_acquire() in
1010 * hns3_tx_spare_space() called in xmit process.
1011 */
1012 smp_store_release(&tx_spare->last_to_clean,
1013 tx_spare->next_to_clean);
1014 }
1015
hns3_can_use_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1016 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
1017 struct sk_buff *skb,
1018 u32 space)
1019 {
1020 u32 len = skb->len <= ring->tx_copybreak ? skb->len :
1021 skb_headlen(skb);
1022
1023 if (len > ring->tx_copybreak)
1024 return false;
1025
1026 if (ALIGN(len, dma_get_cache_alignment()) > space) {
1027 hns3_ring_stats_update(ring, tx_spare_full);
1028 return false;
1029 }
1030
1031 return true;
1032 }
1033
hns3_can_use_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1034 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1035 struct sk_buff *skb,
1036 u32 space)
1037 {
1038 if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1039 (!skb_has_frag_list(skb) &&
1040 skb_shinfo(skb)->nr_frags < tx_sgl))
1041 return false;
1042
1043 if (space < HNS3_MAX_SGL_SIZE) {
1044 hns3_ring_stats_update(ring, tx_spare_full);
1045 return false;
1046 }
1047
1048 return true;
1049 }
1050
hns3_init_tx_spare_buffer(struct hns3_enet_ring * ring)1051 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1052 {
1053 u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
1054 struct net_device *netdev = ring_to_netdev(ring);
1055 struct hns3_nic_priv *priv = netdev_priv(netdev);
1056 struct hns3_tx_spare *tx_spare;
1057 struct page *page;
1058 dma_addr_t dma;
1059 int order;
1060
1061 if (!alloc_size)
1062 return;
1063
1064 order = get_order(alloc_size);
1065 if (order > MAX_PAGE_ORDER) {
1066 if (net_ratelimit())
1067 dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n");
1068 return;
1069 }
1070
1071 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1072 GFP_KERNEL);
1073 if (!tx_spare) {
1074 /* The driver still work without the tx spare buffer */
1075 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1076 goto devm_kzalloc_error;
1077 }
1078
1079 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1080 GFP_KERNEL, order);
1081 if (!page) {
1082 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1083 goto alloc_pages_error;
1084 }
1085
1086 dma = dma_map_page(ring_to_dev(ring), page, 0,
1087 PAGE_SIZE << order, DMA_TO_DEVICE);
1088 if (dma_mapping_error(ring_to_dev(ring), dma)) {
1089 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1090 goto dma_mapping_error;
1091 }
1092
1093 tx_spare->dma = dma;
1094 tx_spare->buf = page_address(page);
1095 tx_spare->len = PAGE_SIZE << order;
1096 ring->tx_spare = tx_spare;
1097 ring->tx_copybreak = priv->tx_copybreak;
1098 return;
1099
1100 dma_mapping_error:
1101 put_page(page);
1102 alloc_pages_error:
1103 devm_kfree(ring_to_dev(ring), tx_spare);
1104 devm_kzalloc_error:
1105 ring->tqp->handle->kinfo.tx_spare_buf_size = 0;
1106 }
1107
1108 /* Use hns3_tx_spare_space() to make sure there is enough buffer
1109 * before calling below function to allocate tx buffer.
1110 */
hns3_tx_spare_alloc(struct hns3_enet_ring * ring,unsigned int size,dma_addr_t * dma,u32 * cb_len)1111 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1112 unsigned int size, dma_addr_t *dma,
1113 u32 *cb_len)
1114 {
1115 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1116 u32 ntu = tx_spare->next_to_use;
1117
1118 size = ALIGN(size, dma_get_cache_alignment());
1119 *cb_len = size;
1120
1121 /* Tx spare buffer wraps back here because the end of
1122 * freed tx buffer is not enough.
1123 */
1124 if (ntu + size > tx_spare->len) {
1125 *cb_len += (tx_spare->len - ntu);
1126 ntu = 0;
1127 }
1128
1129 tx_spare->next_to_use = ntu + size;
1130 if (tx_spare->next_to_use == tx_spare->len)
1131 tx_spare->next_to_use = 0;
1132
1133 *dma = tx_spare->dma + ntu;
1134
1135 return tx_spare->buf + ntu;
1136 }
1137
hns3_tx_spare_rollback(struct hns3_enet_ring * ring,u32 len)1138 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1139 {
1140 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1141
1142 if (len > tx_spare->next_to_use) {
1143 len -= tx_spare->next_to_use;
1144 tx_spare->next_to_use = tx_spare->len - len;
1145 } else {
1146 tx_spare->next_to_use -= len;
1147 }
1148 }
1149
hns3_tx_spare_reclaim_cb(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1150 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1151 struct hns3_desc_cb *cb)
1152 {
1153 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1154 u32 ntc = tx_spare->next_to_clean;
1155 u32 len = cb->length;
1156
1157 tx_spare->next_to_clean += len;
1158
1159 if (tx_spare->next_to_clean >= tx_spare->len) {
1160 tx_spare->next_to_clean -= tx_spare->len;
1161
1162 if (tx_spare->next_to_clean) {
1163 ntc = 0;
1164 len = tx_spare->next_to_clean;
1165 }
1166 }
1167
1168 /* This tx spare buffer is only really reclaimed after calling
1169 * hns3_tx_spare_update(), so it is still safe to use the info in
1170 * the tx buffer to do the dma sync or sg unmapping after
1171 * tx_spare->next_to_clean is moved forword.
1172 */
1173 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1174 dma_addr_t dma = tx_spare->dma + ntc;
1175
1176 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1177 DMA_TO_DEVICE);
1178 } else {
1179 struct sg_table *sgt = tx_spare->buf + ntc;
1180
1181 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1182 DMA_TO_DEVICE);
1183 }
1184 }
1185
hns3_set_tso(struct sk_buff * skb,u32 * paylen_fdop_ol4cs,u16 * mss,u32 * type_cs_vlan_tso,u32 * send_bytes)1186 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
1187 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
1188 {
1189 u32 l4_offset, hdr_len;
1190 union l3_hdr_info l3;
1191 union l4_hdr_info l4;
1192 u32 l4_paylen;
1193 int ret;
1194
1195 if (!skb_is_gso(skb))
1196 return 0;
1197
1198 ret = skb_cow_head(skb, 0);
1199 if (unlikely(ret < 0))
1200 return ret;
1201
1202 l3.hdr = skb_network_header(skb);
1203 l4.hdr = skb_transport_header(skb);
1204
1205 /* Software should clear the IPv4's checksum field when tso is
1206 * needed.
1207 */
1208 if (l3.v4->version == 4)
1209 l3.v4->check = 0;
1210
1211 /* tunnel packet */
1212 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1213 SKB_GSO_GRE_CSUM |
1214 SKB_GSO_UDP_TUNNEL |
1215 SKB_GSO_UDP_TUNNEL_CSUM)) {
1216 /* reset l3&l4 pointers from outer to inner headers */
1217 l3.hdr = skb_inner_network_header(skb);
1218 l4.hdr = skb_inner_transport_header(skb);
1219
1220 /* Software should clear the IPv4's checksum field when
1221 * tso is needed.
1222 */
1223 if (l3.v4->version == 4)
1224 l3.v4->check = 0;
1225 }
1226
1227 /* normal or tunnel packet */
1228 l4_offset = l4.hdr - skb->data;
1229
1230 /* remove payload length from inner pseudo checksum when tso */
1231 l4_paylen = skb->len - l4_offset;
1232
1233 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1234 hdr_len = sizeof(*l4.udp) + l4_offset;
1235 csum_replace_by_diff(&l4.udp->check,
1236 (__force __wsum)htonl(l4_paylen));
1237 } else {
1238 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1239 csum_replace_by_diff(&l4.tcp->check,
1240 (__force __wsum)htonl(l4_paylen));
1241 }
1242
1243 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1244
1245 /* find the txbd field values */
1246 *paylen_fdop_ol4cs = skb->len - hdr_len;
1247 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
1248
1249 /* offload outer UDP header checksum */
1250 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1251 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1252
1253 /* get MSS for TSO */
1254 *mss = skb_shinfo(skb)->gso_size;
1255
1256 trace_hns3_tso(skb);
1257
1258 return 0;
1259 }
1260
hns3_get_l4_protocol(struct sk_buff * skb,u8 * ol4_proto,u8 * il4_proto)1261 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1262 u8 *il4_proto)
1263 {
1264 union l3_hdr_info l3;
1265 unsigned char *l4_hdr;
1266 unsigned char *exthdr;
1267 u8 l4_proto_tmp;
1268 __be16 frag_off;
1269
1270 /* find outer header point */
1271 l3.hdr = skb_network_header(skb);
1272 l4_hdr = skb_transport_header(skb);
1273
1274 if (skb->protocol == htons(ETH_P_IPV6)) {
1275 exthdr = l3.hdr + sizeof(*l3.v6);
1276 l4_proto_tmp = l3.v6->nexthdr;
1277 if (l4_hdr != exthdr)
1278 ipv6_skip_exthdr(skb, exthdr - skb->data,
1279 &l4_proto_tmp, &frag_off);
1280 } else if (skb->protocol == htons(ETH_P_IP)) {
1281 l4_proto_tmp = l3.v4->protocol;
1282 } else {
1283 return -EINVAL;
1284 }
1285
1286 *ol4_proto = l4_proto_tmp;
1287
1288 /* tunnel packet */
1289 if (!skb->encapsulation) {
1290 *il4_proto = 0;
1291 return 0;
1292 }
1293
1294 /* find inner header point */
1295 l3.hdr = skb_inner_network_header(skb);
1296 l4_hdr = skb_inner_transport_header(skb);
1297
1298 if (l3.v6->version == 6) {
1299 exthdr = l3.hdr + sizeof(*l3.v6);
1300 l4_proto_tmp = l3.v6->nexthdr;
1301 if (l4_hdr != exthdr)
1302 ipv6_skip_exthdr(skb, exthdr - skb->data,
1303 &l4_proto_tmp, &frag_off);
1304 } else if (l3.v4->version == 4) {
1305 l4_proto_tmp = l3.v4->protocol;
1306 }
1307
1308 *il4_proto = l4_proto_tmp;
1309
1310 return 0;
1311 }
1312
1313 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1314 * and it is udp packet, which has a dest port as the IANA assigned.
1315 * the hardware is expected to do the checksum offload, but the
1316 * hardware will not do the checksum offload when udp dest port is
1317 * 4789, 4790 or 6081.
1318 */
hns3_tunnel_csum_bug(struct sk_buff * skb)1319 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1320 {
1321 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1322 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1323 union l4_hdr_info l4;
1324
1325 /* device version above V3(include V3), the hardware can
1326 * do this checksum offload.
1327 */
1328 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1329 return false;
1330
1331 l4.hdr = skb_transport_header(skb);
1332
1333 if (!(!skb->encapsulation &&
1334 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
1335 l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1336 l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT))))
1337 return false;
1338
1339 return true;
1340 }
1341
hns3_set_outer_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u32 * ol_type_vlan_len_msec)1342 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1343 u32 *ol_type_vlan_len_msec)
1344 {
1345 u32 l2_len, l3_len, l4_len;
1346 unsigned char *il2_hdr;
1347 union l3_hdr_info l3;
1348 union l4_hdr_info l4;
1349
1350 l3.hdr = skb_network_header(skb);
1351 l4.hdr = skb_transport_header(skb);
1352
1353 /* compute OL2 header size, defined in 2 Bytes */
1354 l2_len = l3.hdr - skb->data;
1355 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1356
1357 /* compute OL3 header size, defined in 4 Bytes */
1358 l3_len = l4.hdr - l3.hdr;
1359 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
1360
1361 il2_hdr = skb_inner_mac_header(skb);
1362 /* compute OL4 header size, defined in 4 Bytes */
1363 l4_len = il2_hdr - l4.hdr;
1364 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1365
1366 /* define outer network header type */
1367 if (skb->protocol == htons(ETH_P_IP)) {
1368 if (skb_is_gso(skb))
1369 hns3_set_field(*ol_type_vlan_len_msec,
1370 HNS3_TXD_OL3T_S,
1371 HNS3_OL3T_IPV4_CSUM);
1372 else
1373 hns3_set_field(*ol_type_vlan_len_msec,
1374 HNS3_TXD_OL3T_S,
1375 HNS3_OL3T_IPV4_NO_CSUM);
1376 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1377 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1378 HNS3_OL3T_IPV6);
1379 }
1380
1381 if (ol4_proto == IPPROTO_UDP)
1382 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1383 HNS3_TUN_MAC_IN_UDP);
1384 else if (ol4_proto == IPPROTO_GRE)
1385 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1386 HNS3_TUN_NVGRE);
1387 }
1388
hns3_set_l3_type(struct sk_buff * skb,union l3_hdr_info l3,u32 * type_cs_vlan_tso)1389 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3,
1390 u32 *type_cs_vlan_tso)
1391 {
1392 if (l3.v4->version == 4) {
1393 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1394 HNS3_L3T_IPV4);
1395
1396 /* the stack computes the IP header already, the only time we
1397 * need the hardware to recompute it is in the case of TSO.
1398 */
1399 if (skb_is_gso(skb))
1400 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
1401 } else if (l3.v6->version == 6) {
1402 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1403 HNS3_L3T_IPV6);
1404 }
1405 }
1406
hns3_set_l4_csum_length(struct sk_buff * skb,union l4_hdr_info l4,u32 l4_proto,u32 * type_cs_vlan_tso)1407 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4,
1408 u32 l4_proto, u32 *type_cs_vlan_tso)
1409 {
1410 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
1411 switch (l4_proto) {
1412 case IPPROTO_TCP:
1413 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1414 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1415 HNS3_L4T_TCP);
1416 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1417 l4.tcp->doff);
1418 break;
1419 case IPPROTO_UDP:
1420 if (hns3_tunnel_csum_bug(skb)) {
1421 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN);
1422
1423 return ret ? ret : skb_checksum_help(skb);
1424 }
1425
1426 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1427 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1428 HNS3_L4T_UDP);
1429 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1430 (sizeof(struct udphdr) >> 2));
1431 break;
1432 case IPPROTO_SCTP:
1433 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1434 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1435 HNS3_L4T_SCTP);
1436 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1437 (sizeof(struct sctphdr) >> 2));
1438 break;
1439 default:
1440 /* drop the skb tunnel packet if hardware don't support,
1441 * because hardware can't calculate csum when TSO.
1442 */
1443 if (skb_is_gso(skb))
1444 return -EDOM;
1445
1446 /* the stack computes the IP header already,
1447 * driver calculate l4 checksum when not TSO.
1448 */
1449 return skb_checksum_help(skb);
1450 }
1451
1452 return 0;
1453 }
1454
hns3_set_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u8 il4_proto,u32 * type_cs_vlan_tso,u32 * ol_type_vlan_len_msec)1455 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1456 u8 il4_proto, u32 *type_cs_vlan_tso,
1457 u32 *ol_type_vlan_len_msec)
1458 {
1459 unsigned char *l2_hdr = skb->data;
1460 u32 l4_proto = ol4_proto;
1461 union l4_hdr_info l4;
1462 union l3_hdr_info l3;
1463 u32 l2_len, l3_len;
1464
1465 l4.hdr = skb_transport_header(skb);
1466 l3.hdr = skb_network_header(skb);
1467
1468 /* handle encapsulation skb */
1469 if (skb->encapsulation) {
1470 /* If this is a not UDP/GRE encapsulation skb */
1471 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
1472 /* drop the skb tunnel packet if hardware don't support,
1473 * because hardware can't calculate csum when TSO.
1474 */
1475 if (skb_is_gso(skb))
1476 return -EDOM;
1477
1478 /* the stack computes the IP header already,
1479 * driver calculate l4 checksum when not TSO.
1480 */
1481 return skb_checksum_help(skb);
1482 }
1483
1484 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1485
1486 /* switch to inner header */
1487 l2_hdr = skb_inner_mac_header(skb);
1488 l3.hdr = skb_inner_network_header(skb);
1489 l4.hdr = skb_inner_transport_header(skb);
1490 l4_proto = il4_proto;
1491 }
1492
1493 hns3_set_l3_type(skb, l3, type_cs_vlan_tso);
1494
1495 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1496 l2_len = l3.hdr - l2_hdr;
1497 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1498
1499 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1500 l3_len = l4.hdr - l3.hdr;
1501 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1502
1503 return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso);
1504 }
1505
hns3_handle_vtags(struct hns3_enet_ring * tx_ring,struct sk_buff * skb)1506 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1507 struct sk_buff *skb)
1508 {
1509 struct hnae3_handle *handle = tx_ring->tqp->handle;
1510 struct hnae3_ae_dev *ae_dev;
1511 struct vlan_ethhdr *vhdr;
1512 int rc;
1513
1514 if (!(skb->protocol == htons(ETH_P_8021Q) ||
1515 skb_vlan_tag_present(skb)))
1516 return 0;
1517
1518 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1519 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1520 * will cause RAS error.
1521 */
1522 ae_dev = pci_get_drvdata(handle->pdev);
1523 if (unlikely(skb_vlan_tagged_multi(skb) &&
1524 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
1525 handle->port_base_vlan_state ==
1526 HNAE3_PORT_BASE_VLAN_ENABLE))
1527 return -EINVAL;
1528
1529 if (skb->protocol == htons(ETH_P_8021Q) &&
1530 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1531 /* When HW VLAN acceleration is turned off, and the stack
1532 * sets the protocol to 802.1q, the driver just need to
1533 * set the protocol to the encapsulated ethertype.
1534 */
1535 skb->protocol = vlan_get_protocol(skb);
1536 return 0;
1537 }
1538
1539 if (skb_vlan_tag_present(skb)) {
1540 /* Based on hw strategy, use out_vtag in two layer tag case,
1541 * and use inner_vtag in one tag case.
1542 */
1543 if (skb->protocol == htons(ETH_P_8021Q) &&
1544 handle->port_base_vlan_state ==
1545 HNAE3_PORT_BASE_VLAN_DISABLE)
1546 rc = HNS3_OUTER_VLAN_TAG;
1547 else
1548 rc = HNS3_INNER_VLAN_TAG;
1549
1550 skb->protocol = vlan_get_protocol(skb);
1551 return rc;
1552 }
1553
1554 rc = skb_cow_head(skb, 0);
1555 if (unlikely(rc < 0))
1556 return rc;
1557
1558 vhdr = skb_vlan_eth_hdr(skb);
1559 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1560 & VLAN_PRIO_MASK);
1561
1562 skb->protocol = vlan_get_protocol(skb);
1563 return 0;
1564 }
1565
1566 /* check if the hardware is capable of checksum offloading */
hns3_check_hw_tx_csum(struct sk_buff * skb)1567 static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1568 {
1569 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1570
1571 /* Kindly note, due to backward compatibility of the TX descriptor,
1572 * HW checksum of the non-IP packets and GSO packets is handled at
1573 * different place in the following code
1574 */
1575 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
1576 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1577 return false;
1578
1579 return true;
1580 }
1581
1582 struct hns3_desc_param {
1583 u32 paylen_ol4cs;
1584 u32 ol_type_vlan_len_msec;
1585 u32 type_cs_vlan_tso;
1586 u16 mss_hw_csum;
1587 u16 inner_vtag;
1588 u16 out_vtag;
1589 };
1590
hns3_init_desc_data(struct sk_buff * skb,struct hns3_desc_param * pa)1591 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa)
1592 {
1593 pa->paylen_ol4cs = skb->len;
1594 pa->ol_type_vlan_len_msec = 0;
1595 pa->type_cs_vlan_tso = 0;
1596 pa->mss_hw_csum = 0;
1597 pa->inner_vtag = 0;
1598 pa->out_vtag = 0;
1599 }
1600
hns3_handle_vlan_info(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_param * param)1601 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring,
1602 struct sk_buff *skb,
1603 struct hns3_desc_param *param)
1604 {
1605 int ret;
1606
1607 ret = hns3_handle_vtags(ring, skb);
1608 if (unlikely(ret < 0)) {
1609 hns3_ring_stats_update(ring, tx_vlan_err);
1610 return ret;
1611 } else if (ret == HNS3_INNER_VLAN_TAG) {
1612 param->inner_vtag = skb_vlan_tag_get(skb);
1613 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1614 VLAN_PRIO_MASK;
1615 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1616 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1617 param->out_vtag = skb_vlan_tag_get(skb);
1618 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1619 VLAN_PRIO_MASK;
1620 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1621 1);
1622 }
1623 return 0;
1624 }
1625
hns3_handle_csum_partial(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,struct hns3_desc_param * param)1626 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring,
1627 struct sk_buff *skb,
1628 struct hns3_desc_cb *desc_cb,
1629 struct hns3_desc_param *param)
1630 {
1631 u8 ol4_proto, il4_proto;
1632 int ret;
1633
1634 if (hns3_check_hw_tx_csum(skb)) {
1635 /* set checksum start and offset, defined in 2 Bytes */
1636 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1637 skb_checksum_start_offset(skb) >> 1);
1638 hns3_set_field(param->ol_type_vlan_len_msec,
1639 HNS3_TXD_CSUM_OFFSET_S,
1640 skb->csum_offset >> 1);
1641 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1642 return 0;
1643 }
1644
1645 skb_reset_mac_len(skb);
1646
1647 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1648 if (unlikely(ret < 0)) {
1649 hns3_ring_stats_update(ring, tx_l4_proto_err);
1650 return ret;
1651 }
1652
1653 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1654 ¶m->type_cs_vlan_tso,
1655 ¶m->ol_type_vlan_len_msec);
1656 if (unlikely(ret < 0)) {
1657 hns3_ring_stats_update(ring, tx_l2l3l4_err);
1658 return ret;
1659 }
1660
1661 ret = hns3_set_tso(skb, ¶m->paylen_ol4cs, ¶m->mss_hw_csum,
1662 ¶m->type_cs_vlan_tso, &desc_cb->send_bytes);
1663 if (unlikely(ret < 0)) {
1664 hns3_ring_stats_update(ring, tx_tso_err);
1665 return ret;
1666 }
1667 return 0;
1668 }
1669
hns3_fill_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc * desc,struct hns3_desc_cb * desc_cb)1670 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1671 struct sk_buff *skb, struct hns3_desc *desc,
1672 struct hns3_desc_cb *desc_cb)
1673 {
1674 struct hns3_desc_param param;
1675 int ret;
1676
1677 hns3_init_desc_data(skb, ¶m);
1678 ret = hns3_handle_vlan_info(ring, skb, ¶m);
1679 if (unlikely(ret < 0))
1680 return ret;
1681
1682 desc_cb->send_bytes = skb->len;
1683
1684 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1685 ret = hns3_handle_csum_partial(ring, skb, desc_cb, ¶m);
1686 if (ret)
1687 return ret;
1688 }
1689
1690 /* Set txbd */
1691 desc->tx.ol_type_vlan_len_msec =
1692 cpu_to_le32(param.ol_type_vlan_len_msec);
1693 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso);
1694 desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs);
1695 desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum);
1696 desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag);
1697 desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag);
1698
1699 return 0;
1700 }
1701
hns3_fill_desc(struct hns3_enet_ring * ring,dma_addr_t dma,unsigned int size)1702 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1703 unsigned int size)
1704 {
1705 #define HNS3_LIKELY_BD_NUM 1
1706
1707 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1708 unsigned int frag_buf_num;
1709 int k, sizeoflast;
1710
1711 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1712 desc->addr = cpu_to_le64(dma);
1713 desc->tx.send_size = cpu_to_le16(size);
1714 desc->tx.bdtp_fe_sc_vld_ra_ri =
1715 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1716
1717 trace_hns3_tx_desc(ring, ring->next_to_use);
1718 ring_ptr_move_fw(ring, next_to_use);
1719 return HNS3_LIKELY_BD_NUM;
1720 }
1721
1722 frag_buf_num = hns3_tx_bd_count(size);
1723 sizeoflast = size % HNS3_MAX_BD_SIZE;
1724 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1725
1726 /* When frag size is bigger than hardware limit, split this frag */
1727 for (k = 0; k < frag_buf_num; k++) {
1728 /* now, fill the descriptor */
1729 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1730 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1731 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1732 desc->tx.bdtp_fe_sc_vld_ra_ri =
1733 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1734
1735 trace_hns3_tx_desc(ring, ring->next_to_use);
1736 /* move ring pointer to next */
1737 ring_ptr_move_fw(ring, next_to_use);
1738
1739 desc = &ring->desc[ring->next_to_use];
1740 }
1741
1742 return frag_buf_num;
1743 }
1744
hns3_map_and_fill_desc(struct hns3_enet_ring * ring,void * priv,unsigned int type)1745 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1746 unsigned int type)
1747 {
1748 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1749 struct hnae3_handle *handle = ring->tqp->handle;
1750 struct device *dev = ring_to_dev(ring);
1751 struct hnae3_ae_dev *ae_dev;
1752 unsigned int size;
1753 dma_addr_t dma;
1754
1755 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1756 struct sk_buff *skb = (struct sk_buff *)priv;
1757
1758 size = skb_headlen(skb);
1759 if (!size)
1760 return 0;
1761
1762 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1763 } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1764 /* Head data has been filled in hns3_handle_tx_bounce(),
1765 * just return 0 here.
1766 */
1767 return 0;
1768 } else {
1769 skb_frag_t *frag = (skb_frag_t *)priv;
1770
1771 size = skb_frag_size(frag);
1772 if (!size)
1773 return 0;
1774
1775 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1776 }
1777
1778 if (unlikely(dma_mapping_error(dev, dma))) {
1779 hns3_ring_stats_update(ring, sw_err_cnt);
1780 return -ENOMEM;
1781 }
1782
1783 /* Add a SYNC command to sync io-pgtale to avoid errors in pgtable
1784 * prefetch
1785 */
1786 ae_dev = hns3_get_ae_dev(handle);
1787 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1788 hns3_dma_map_sync(dev, dma);
1789
1790 desc_cb->priv = priv;
1791 desc_cb->length = size;
1792 desc_cb->dma = dma;
1793 desc_cb->type = type;
1794
1795 return hns3_fill_desc(ring, dma, size);
1796 }
1797
hns3_skb_bd_num(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num)1798 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1799 unsigned int bd_num)
1800 {
1801 unsigned int size;
1802 int i;
1803
1804 size = skb_headlen(skb);
1805 while (size > HNS3_MAX_BD_SIZE) {
1806 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1807 size -= HNS3_MAX_BD_SIZE;
1808
1809 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1810 return bd_num;
1811 }
1812
1813 if (size) {
1814 bd_size[bd_num++] = size;
1815 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1816 return bd_num;
1817 }
1818
1819 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1820 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1821 size = skb_frag_size(frag);
1822 if (!size)
1823 continue;
1824
1825 while (size > HNS3_MAX_BD_SIZE) {
1826 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1827 size -= HNS3_MAX_BD_SIZE;
1828
1829 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1830 return bd_num;
1831 }
1832
1833 bd_size[bd_num++] = size;
1834 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1835 return bd_num;
1836 }
1837
1838 return bd_num;
1839 }
1840
hns3_tx_bd_num(struct sk_buff * skb,unsigned int * bd_size,u8 max_non_tso_bd_num,unsigned int bd_num,unsigned int recursion_level)1841 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1842 u8 max_non_tso_bd_num, unsigned int bd_num,
1843 unsigned int recursion_level)
1844 {
1845 #define HNS3_MAX_RECURSION_LEVEL 24
1846
1847 struct sk_buff *frag_skb;
1848
1849 /* If the total len is within the max bd limit */
1850 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1851 !skb_has_frag_list(skb) &&
1852 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
1853 return skb_shinfo(skb)->nr_frags + 1U;
1854
1855 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1856 return UINT_MAX;
1857
1858 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1859 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1860 return bd_num;
1861
1862 skb_walk_frags(skb, frag_skb) {
1863 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1864 bd_num, recursion_level + 1);
1865 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1866 return bd_num;
1867 }
1868
1869 return bd_num;
1870 }
1871
hns3_gso_hdr_len(struct sk_buff * skb)1872 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1873 {
1874 if (!skb->encapsulation)
1875 return skb_tcp_all_headers(skb);
1876
1877 return skb_inner_tcp_all_headers(skb);
1878 }
1879
1880 /* HW need every continuous max_non_tso_bd_num buffer data to be larger
1881 * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1882 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1883 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1884 * than MSS except the last max_non_tso_bd_num - 1 frags.
1885 */
hns3_skb_need_linearized(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num,u8 max_non_tso_bd_num)1886 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1887 unsigned int bd_num, u8 max_non_tso_bd_num)
1888 {
1889 unsigned int tot_len = 0;
1890 int i;
1891
1892 for (i = 0; i < max_non_tso_bd_num - 1U; i++)
1893 tot_len += bd_size[i];
1894
1895 /* ensure the first max_non_tso_bd_num frags is greater than
1896 * mss + header
1897 */
1898 if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
1899 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1900 return true;
1901
1902 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1903 * than mss except the last one.
1904 */
1905 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
1906 tot_len -= bd_size[i];
1907 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
1908
1909 if (tot_len < skb_shinfo(skb)->gso_size)
1910 return true;
1911 }
1912
1913 return false;
1914 }
1915
hns3_shinfo_pack(struct skb_shared_info * shinfo,__u32 * size)1916 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1917 {
1918 int i;
1919
1920 for (i = 0; i < MAX_SKB_FRAGS; i++)
1921 size[i] = skb_frag_size(&shinfo->frags[i]);
1922 }
1923
hns3_skb_linearize(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int bd_num)1924 static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1925 struct sk_buff *skb,
1926 unsigned int bd_num)
1927 {
1928 /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1929 * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1930 */
1931 if (bd_num == UINT_MAX) {
1932 hns3_ring_stats_update(ring, over_max_recursion);
1933 return -ENOMEM;
1934 }
1935
1936 /* The skb->len has exceeded the hw limitation, linearization
1937 * will not help.
1938 */
1939 if (skb->len > HNS3_MAX_TSO_SIZE ||
1940 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) {
1941 hns3_ring_stats_update(ring, hw_limitation);
1942 return -ENOMEM;
1943 }
1944
1945 if (__skb_linearize(skb)) {
1946 hns3_ring_stats_update(ring, sw_err_cnt);
1947 return -ENOMEM;
1948 }
1949
1950 return 0;
1951 }
1952
hns3_nic_maybe_stop_tx(struct hns3_enet_ring * ring,struct net_device * netdev,struct sk_buff * skb)1953 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1954 struct net_device *netdev,
1955 struct sk_buff *skb)
1956 {
1957 struct hns3_nic_priv *priv = netdev_priv(netdev);
1958 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
1959 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1960 unsigned int bd_num;
1961
1962 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
1963 if (unlikely(bd_num > max_non_tso_bd_num)) {
1964 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1965 !hns3_skb_need_linearized(skb, bd_size, bd_num,
1966 max_non_tso_bd_num)) {
1967 trace_hns3_over_max_bd(skb);
1968 goto out;
1969 }
1970
1971 if (hns3_skb_linearize(ring, skb, bd_num))
1972 return -ENOMEM;
1973
1974 bd_num = hns3_tx_bd_count(skb->len);
1975
1976 hns3_ring_stats_update(ring, tx_copy);
1977 }
1978
1979 out:
1980 if (likely(ring_space(ring) >= bd_num))
1981 return bd_num;
1982
1983 netif_stop_subqueue(netdev, ring->queue_index);
1984 smp_mb(); /* Memory barrier before checking ring_space */
1985
1986 /* Start queue in case hns3_clean_tx_ring has just made room
1987 * available and has not seen the queue stopped state performed
1988 * by netif_stop_subqueue above.
1989 */
1990 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1991 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1992 netif_start_subqueue(netdev, ring->queue_index);
1993 return bd_num;
1994 }
1995
1996 hns3_ring_stats_update(ring, tx_busy);
1997
1998 return -EBUSY;
1999 }
2000
hns3_clear_desc(struct hns3_enet_ring * ring,int next_to_use_orig)2001 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
2002 {
2003 struct device *dev = ring_to_dev(ring);
2004 unsigned int i;
2005
2006 for (i = 0; i < ring->desc_num; i++) {
2007 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
2008 struct hns3_desc_cb *desc_cb;
2009
2010 memset(desc, 0, sizeof(*desc));
2011
2012 /* check if this is where we started */
2013 if (ring->next_to_use == next_to_use_orig)
2014 break;
2015
2016 /* rollback one */
2017 ring_ptr_move_bw(ring, next_to_use);
2018
2019 desc_cb = &ring->desc_cb[ring->next_to_use];
2020
2021 if (!desc_cb->dma)
2022 continue;
2023
2024 /* unmap the descriptor dma address */
2025 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
2026 dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
2027 DMA_TO_DEVICE);
2028 else if (desc_cb->type &
2029 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
2030 hns3_tx_spare_rollback(ring, desc_cb->length);
2031 else if (desc_cb->length)
2032 dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
2033 DMA_TO_DEVICE);
2034
2035 desc_cb->length = 0;
2036 desc_cb->dma = 0;
2037 desc_cb->type = DESC_TYPE_UNKNOWN;
2038 }
2039 }
2040
hns3_fill_skb_to_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int type)2041 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
2042 struct sk_buff *skb, unsigned int type)
2043 {
2044 struct sk_buff *frag_skb;
2045 int i, ret, bd_num = 0;
2046
2047 ret = hns3_map_and_fill_desc(ring, skb, type);
2048 if (unlikely(ret < 0))
2049 return ret;
2050
2051 bd_num += ret;
2052
2053 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2054 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2055
2056 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
2057 if (unlikely(ret < 0))
2058 return ret;
2059
2060 bd_num += ret;
2061 }
2062
2063 skb_walk_frags(skb, frag_skb) {
2064 ret = hns3_fill_skb_to_desc(ring, frag_skb,
2065 DESC_TYPE_FRAGLIST_SKB);
2066 if (unlikely(ret < 0))
2067 return ret;
2068
2069 bd_num += ret;
2070 }
2071
2072 return bd_num;
2073 }
2074
hns3_tx_push_bd(struct hns3_enet_ring * ring,int num)2075 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num)
2076 {
2077 #define HNS3_BYTES_PER_64BIT 8
2078
2079 struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {};
2080 int offset = 0;
2081
2082 /* make sure everything is visible to device before
2083 * excuting tx push or updating doorbell
2084 */
2085 dma_wmb();
2086
2087 do {
2088 int idx = (ring->next_to_use - num + ring->desc_num) %
2089 ring->desc_num;
2090
2091 u64_stats_update_begin(&ring->syncp);
2092 ring->stats.tx_push++;
2093 u64_stats_update_end(&ring->syncp);
2094 memcpy(&desc[offset], &ring->desc[idx],
2095 sizeof(struct hns3_desc));
2096 offset++;
2097 } while (--num);
2098
2099 __iowrite64_copy(ring->tqp->mem_base, desc,
2100 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) /
2101 HNS3_BYTES_PER_64BIT);
2102 }
2103
hns3_tx_mem_doorbell(struct hns3_enet_ring * ring)2104 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring)
2105 {
2106 #define HNS3_MEM_DOORBELL_OFFSET 64
2107
2108 __le64 bd_num = cpu_to_le64((u64)ring->pending_buf);
2109
2110 /* make sure everything is visible to device before
2111 * excuting tx push or updating doorbell
2112 */
2113 dma_wmb();
2114
2115 __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET,
2116 &bd_num, 1);
2117 u64_stats_update_begin(&ring->syncp);
2118 ring->stats.tx_mem_doorbell += ring->pending_buf;
2119 u64_stats_update_end(&ring->syncp);
2120 }
2121
hns3_tx_doorbell(struct hns3_enet_ring * ring,int num,bool doorbell)2122 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2123 bool doorbell)
2124 {
2125 struct net_device *netdev = ring_to_netdev(ring);
2126 struct hns3_nic_priv *priv = netdev_priv(netdev);
2127
2128 /* when tx push is enabled, the packet whose number of BD below
2129 * HNS3_MAX_PUSH_BD_NUM can be pushed directly.
2130 */
2131 if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num &&
2132 !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) {
2133 /* This smp_store_release() pairs with smp_load_aquire() in
2134 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit
2135 * is updated.
2136 */
2137 smp_store_release(&ring->last_to_use, ring->next_to_use);
2138 hns3_tx_push_bd(ring, num);
2139 return;
2140 }
2141
2142 ring->pending_buf += num;
2143
2144 if (!doorbell) {
2145 hns3_ring_stats_update(ring, tx_more);
2146 return;
2147 }
2148
2149 /* This smp_store_release() pairs with smp_load_aquire() in
2150 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit is updated.
2151 */
2152 smp_store_release(&ring->last_to_use, ring->next_to_use);
2153
2154 if (ring->tqp->mem_base)
2155 hns3_tx_mem_doorbell(ring);
2156 else
2157 writel(ring->pending_buf,
2158 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
2159
2160 ring->pending_buf = 0;
2161 }
2162
hns3_tsyn(struct net_device * netdev,struct sk_buff * skb,struct hns3_desc * desc)2163 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2164 struct hns3_desc *desc)
2165 {
2166 struct hnae3_handle *h = hns3_get_handle(netdev);
2167
2168 if (!(h->ae_algo->ops->set_tx_hwts_info &&
2169 h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2170 return;
2171
2172 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2173 }
2174
hns3_handle_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb)2175 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2176 struct sk_buff *skb)
2177 {
2178 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2179 unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2180 unsigned int size = skb_headlen(skb);
2181 dma_addr_t dma;
2182 int bd_num = 0;
2183 u32 cb_len;
2184 void *buf;
2185 int ret;
2186
2187 if (skb->len <= ring->tx_copybreak) {
2188 size = skb->len;
2189 type = DESC_TYPE_BOUNCE_ALL;
2190 }
2191
2192 /* hns3_can_use_tx_bounce() is called to ensure the below
2193 * function can always return the tx buffer.
2194 */
2195 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2196
2197 ret = skb_copy_bits(skb, 0, buf, size);
2198 if (unlikely(ret < 0)) {
2199 hns3_tx_spare_rollback(ring, cb_len);
2200 hns3_ring_stats_update(ring, copy_bits_err);
2201 return ret;
2202 }
2203
2204 desc_cb->priv = skb;
2205 desc_cb->length = cb_len;
2206 desc_cb->dma = dma;
2207 desc_cb->type = type;
2208
2209 bd_num += hns3_fill_desc(ring, dma, size);
2210
2211 if (type == DESC_TYPE_BOUNCE_HEAD) {
2212 ret = hns3_fill_skb_to_desc(ring, skb,
2213 DESC_TYPE_BOUNCE_HEAD);
2214 if (unlikely(ret < 0))
2215 return ret;
2216
2217 bd_num += ret;
2218 }
2219
2220 dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2221 DMA_TO_DEVICE);
2222
2223 hns3_ring_stats_update(ring, tx_bounce);
2224
2225 return bd_num;
2226 }
2227
hns3_handle_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb)2228 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2229 struct sk_buff *skb)
2230 {
2231 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2232 u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2233 struct sg_table *sgt;
2234 int i, bd_num = 0;
2235 dma_addr_t dma;
2236 u32 cb_len;
2237 int nents;
2238
2239 if (skb_has_frag_list(skb))
2240 nfrag = HNS3_MAX_TSO_BD_NUM;
2241
2242 /* hns3_can_use_tx_sgl() is called to ensure the below
2243 * function can always return the tx buffer.
2244 */
2245 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2246 &dma, &cb_len);
2247
2248 /* scatterlist follows by the sg table */
2249 sgt->sgl = (struct scatterlist *)(sgt + 1);
2250 sg_init_table(sgt->sgl, nfrag);
2251 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2252 if (unlikely(nents < 0)) {
2253 hns3_tx_spare_rollback(ring, cb_len);
2254 hns3_ring_stats_update(ring, skb2sgl_err);
2255 return -ENOMEM;
2256 }
2257
2258 sgt->orig_nents = nents;
2259 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2260 DMA_TO_DEVICE);
2261 if (unlikely(!sgt->nents)) {
2262 hns3_tx_spare_rollback(ring, cb_len);
2263 hns3_ring_stats_update(ring, map_sg_err);
2264 return -ENOMEM;
2265 }
2266
2267 desc_cb->priv = skb;
2268 desc_cb->length = cb_len;
2269 desc_cb->dma = dma;
2270 desc_cb->type = DESC_TYPE_SGL_SKB;
2271
2272 for (i = 0; i < sgt->nents; i++)
2273 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2274 sg_dma_len(sgt->sgl + i));
2275 hns3_ring_stats_update(ring, tx_sgl);
2276
2277 return bd_num;
2278 }
2279
hns3_handle_desc_filling(struct hns3_enet_ring * ring,struct sk_buff * skb)2280 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2281 struct sk_buff *skb)
2282 {
2283 u32 space;
2284
2285 if (!ring->tx_spare)
2286 goto out;
2287
2288 space = hns3_tx_spare_space(ring);
2289
2290 if (hns3_can_use_tx_sgl(ring, skb, space))
2291 return hns3_handle_tx_sgl(ring, skb);
2292
2293 if (hns3_can_use_tx_bounce(ring, skb, space))
2294 return hns3_handle_tx_bounce(ring, skb);
2295
2296 out:
2297 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2298 }
2299
hns3_handle_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,int next_to_use_head)2300 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring,
2301 struct sk_buff *skb,
2302 struct hns3_desc_cb *desc_cb,
2303 int next_to_use_head)
2304 {
2305 int ret;
2306
2307 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2308 desc_cb);
2309 if (unlikely(ret < 0))
2310 goto fill_err;
2311
2312 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2313 * zero, which is unlikely, and 'ret > 0' means how many tx desc
2314 * need to be notified to the hw.
2315 */
2316 ret = hns3_handle_desc_filling(ring, skb);
2317 if (likely(ret > 0))
2318 return ret;
2319
2320 fill_err:
2321 hns3_clear_desc(ring, next_to_use_head);
2322 return ret;
2323 }
2324
hns3_nic_net_xmit(struct sk_buff * skb,struct net_device * netdev)2325 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
2326 {
2327 struct hns3_nic_priv *priv = netdev_priv(netdev);
2328 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
2329 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2330 struct netdev_queue *dev_queue;
2331 int pre_ntu, ret;
2332 bool doorbell;
2333
2334 /* Hardware can only handle short frames above 32 bytes */
2335 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2336 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2337
2338 hns3_ring_stats_update(ring, sw_err_cnt);
2339
2340 return NETDEV_TX_OK;
2341 }
2342
2343 /* Prefetch the data used later */
2344 prefetch(skb->data);
2345
2346 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
2347 if (unlikely(ret <= 0)) {
2348 if (ret == -EBUSY) {
2349 hns3_tx_doorbell(ring, 0, true);
2350 return NETDEV_TX_BUSY;
2351 }
2352
2353 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
2354 goto out_err_tx_ok;
2355 }
2356
2357 ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use);
2358 if (unlikely(ret <= 0))
2359 goto out_err_tx_ok;
2360
2361 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2362 (ring->desc_num - 1);
2363
2364 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2365 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2366
2367 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2368 cpu_to_le16(BIT(HNS3_TXD_FE_B));
2369 trace_hns3_tx_desc(ring, pre_ntu);
2370
2371 skb_tx_timestamp(skb);
2372
2373 /* Complete translate all packets */
2374 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
2375 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
2376 netdev_xmit_more());
2377 hns3_tx_doorbell(ring, ret, doorbell);
2378
2379 return NETDEV_TX_OK;
2380
2381 out_err_tx_ok:
2382 dev_kfree_skb_any(skb);
2383 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2384 return NETDEV_TX_OK;
2385 }
2386
hns3_nic_net_set_mac_address(struct net_device * netdev,void * p)2387 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2388 {
2389 char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN];
2390 char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN];
2391 struct hnae3_handle *h = hns3_get_handle(netdev);
2392 struct sockaddr *mac_addr = p;
2393 int ret;
2394
2395 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2396 return -EADDRNOTAVAIL;
2397
2398 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2399 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2400 netdev_info(netdev, "already using mac address %s\n",
2401 format_mac_addr_sa);
2402 return 0;
2403 }
2404
2405 /* For VF device, if there is a perm_addr, then the user will not
2406 * be allowed to change the address.
2407 */
2408 if (!hns3_is_phys_func(h->pdev) &&
2409 !is_zero_ether_addr(netdev->perm_addr)) {
2410 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr);
2411 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2412 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n",
2413 format_mac_addr_perm, format_mac_addr_sa);
2414 return -EPERM;
2415 }
2416
2417 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
2418 if (ret) {
2419 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2420 return ret;
2421 }
2422
2423 eth_hw_addr_set(netdev, mac_addr->sa_data);
2424
2425 return 0;
2426 }
2427
hns3_nic_do_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2428 static int hns3_nic_do_ioctl(struct net_device *netdev,
2429 struct ifreq *ifr, int cmd)
2430 {
2431 struct hnae3_handle *h = hns3_get_handle(netdev);
2432
2433 if (!netif_running(netdev))
2434 return -EINVAL;
2435
2436 if (!h->ae_algo->ops->do_ioctl)
2437 return -EOPNOTSUPP;
2438
2439 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2440 }
2441
hns3_nic_set_features(struct net_device * netdev,netdev_features_t features)2442 static int hns3_nic_set_features(struct net_device *netdev,
2443 netdev_features_t features)
2444 {
2445 netdev_features_t changed = netdev->features ^ features;
2446 struct hns3_nic_priv *priv = netdev_priv(netdev);
2447 struct hnae3_handle *h = priv->ae_handle;
2448 bool enable;
2449 int ret;
2450
2451 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
2452 enable = !!(features & NETIF_F_GRO_HW);
2453 ret = h->ae_algo->ops->set_gro_en(h, enable);
2454 if (ret)
2455 return ret;
2456 }
2457
2458 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2459 h->ae_algo->ops->enable_hw_strip_rxvtag) {
2460 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2461 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
2462 if (ret)
2463 return ret;
2464 }
2465
2466 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
2467 enable = !!(features & NETIF_F_NTUPLE);
2468 h->ae_algo->ops->enable_fd(h, enable);
2469 }
2470
2471 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2472 h->ae_algo->ops->cls_flower_active(h)) {
2473 netdev_err(netdev,
2474 "there are offloaded TC filters active, cannot disable HW TC offload");
2475 return -EINVAL;
2476 }
2477
2478 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2479 h->ae_algo->ops->enable_vlan_filter) {
2480 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2481 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2482 if (ret)
2483 return ret;
2484 }
2485
2486 return 0;
2487 }
2488
hns3_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2489 static netdev_features_t hns3_features_check(struct sk_buff *skb,
2490 struct net_device *dev,
2491 netdev_features_t features)
2492 {
2493 #define HNS3_MAX_HDR_LEN 480U
2494 #define HNS3_MAX_L4_HDR_LEN 60U
2495
2496 size_t len;
2497
2498 if (skb->ip_summed != CHECKSUM_PARTIAL)
2499 return features;
2500
2501 if (skb->encapsulation)
2502 len = skb_inner_transport_offset(skb);
2503 else
2504 len = skb_transport_offset(skb);
2505
2506 /* Assume L4 is 60 byte as TCP is the only protocol with a
2507 * a flexible value, and it's max len is 60 bytes.
2508 */
2509 len += HNS3_MAX_L4_HDR_LEN;
2510
2511 /* Hardware only supports checksum on the skb with a max header
2512 * len of 480 bytes.
2513 */
2514 if (len > HNS3_MAX_HDR_LEN)
2515 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2516
2517 return features;
2518 }
2519
hns3_fetch_stats(struct rtnl_link_stats64 * stats,struct hns3_enet_ring * ring,bool is_tx)2520 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
2521 struct hns3_enet_ring *ring, bool is_tx)
2522 {
2523 unsigned int start;
2524
2525 do {
2526 start = u64_stats_fetch_begin(&ring->syncp);
2527 if (is_tx) {
2528 stats->tx_bytes += ring->stats.tx_bytes;
2529 stats->tx_packets += ring->stats.tx_pkts;
2530 stats->tx_dropped += ring->stats.sw_err_cnt;
2531 stats->tx_dropped += ring->stats.tx_vlan_err;
2532 stats->tx_dropped += ring->stats.tx_l4_proto_err;
2533 stats->tx_dropped += ring->stats.tx_l2l3l4_err;
2534 stats->tx_dropped += ring->stats.tx_tso_err;
2535 stats->tx_dropped += ring->stats.over_max_recursion;
2536 stats->tx_dropped += ring->stats.hw_limitation;
2537 stats->tx_dropped += ring->stats.copy_bits_err;
2538 stats->tx_dropped += ring->stats.skb2sgl_err;
2539 stats->tx_dropped += ring->stats.map_sg_err;
2540 stats->tx_errors += ring->stats.sw_err_cnt;
2541 stats->tx_errors += ring->stats.tx_vlan_err;
2542 stats->tx_errors += ring->stats.tx_l4_proto_err;
2543 stats->tx_errors += ring->stats.tx_l2l3l4_err;
2544 stats->tx_errors += ring->stats.tx_tso_err;
2545 stats->tx_errors += ring->stats.over_max_recursion;
2546 stats->tx_errors += ring->stats.hw_limitation;
2547 stats->tx_errors += ring->stats.copy_bits_err;
2548 stats->tx_errors += ring->stats.skb2sgl_err;
2549 stats->tx_errors += ring->stats.map_sg_err;
2550 } else {
2551 stats->rx_bytes += ring->stats.rx_bytes;
2552 stats->rx_packets += ring->stats.rx_pkts;
2553 stats->rx_dropped += ring->stats.l2_err;
2554 stats->rx_errors += ring->stats.l2_err;
2555 stats->rx_errors += ring->stats.l3l4_csum_err;
2556 stats->rx_crc_errors += ring->stats.l2_err;
2557 stats->multicast += ring->stats.rx_multicast;
2558 stats->rx_length_errors += ring->stats.err_pkt_len;
2559 }
2560 } while (u64_stats_fetch_retry(&ring->syncp, start));
2561 }
2562
hns3_nic_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)2563 static void hns3_nic_get_stats64(struct net_device *netdev,
2564 struct rtnl_link_stats64 *stats)
2565 {
2566 struct hns3_nic_priv *priv = netdev_priv(netdev);
2567 int queue_num = priv->ae_handle->kinfo.num_tqps;
2568 struct hnae3_handle *handle = priv->ae_handle;
2569 struct rtnl_link_stats64 ring_total_stats;
2570 struct hns3_enet_ring *ring;
2571 unsigned int idx;
2572
2573 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2574 return;
2575
2576 handle->ae_algo->ops->update_stats(handle);
2577
2578 memset(&ring_total_stats, 0, sizeof(ring_total_stats));
2579 for (idx = 0; idx < queue_num; idx++) {
2580 /* fetch the tx stats */
2581 ring = &priv->ring[idx];
2582 hns3_fetch_stats(&ring_total_stats, ring, true);
2583
2584 /* fetch the rx stats */
2585 ring = &priv->ring[idx + queue_num];
2586 hns3_fetch_stats(&ring_total_stats, ring, false);
2587 }
2588
2589 stats->tx_bytes = ring_total_stats.tx_bytes;
2590 stats->tx_packets = ring_total_stats.tx_packets;
2591 stats->rx_bytes = ring_total_stats.rx_bytes;
2592 stats->rx_packets = ring_total_stats.rx_packets;
2593
2594 stats->rx_errors = ring_total_stats.rx_errors;
2595 stats->multicast = ring_total_stats.multicast;
2596 stats->rx_length_errors = ring_total_stats.rx_length_errors;
2597 stats->rx_crc_errors = ring_total_stats.rx_crc_errors;
2598 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2599
2600 stats->tx_errors = ring_total_stats.tx_errors;
2601 stats->rx_dropped = ring_total_stats.rx_dropped;
2602 stats->tx_dropped = ring_total_stats.tx_dropped;
2603 stats->collisions = netdev->stats.collisions;
2604 stats->rx_over_errors = netdev->stats.rx_over_errors;
2605 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2606 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2607 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2608 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2609 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2610 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2611 stats->tx_window_errors = netdev->stats.tx_window_errors;
2612 stats->rx_compressed = netdev->stats.rx_compressed;
2613 stats->tx_compressed = netdev->stats.tx_compressed;
2614 }
2615
hns3_setup_tc(struct net_device * netdev,void * type_data)2616 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
2617 {
2618 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
2619 struct hnae3_knic_private_info *kinfo;
2620 u8 tc = mqprio_qopt->qopt.num_tc;
2621 u16 mode = mqprio_qopt->mode;
2622 u8 hw = mqprio_qopt->qopt.hw;
2623 struct hnae3_handle *h;
2624
2625 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2626 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2627 return -EOPNOTSUPP;
2628
2629 if (tc > HNAE3_MAX_TC)
2630 return -EINVAL;
2631
2632 if (!netdev)
2633 return -EINVAL;
2634
2635 h = hns3_get_handle(netdev);
2636 kinfo = &h->kinfo;
2637
2638 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2639
2640 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
2641 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
2642 }
2643
hns3_setup_tc_cls_flower(struct hns3_nic_priv * priv,struct flow_cls_offload * flow)2644 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2645 struct flow_cls_offload *flow)
2646 {
2647 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2648 struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2649
2650 switch (flow->command) {
2651 case FLOW_CLS_REPLACE:
2652 if (h->ae_algo->ops->add_cls_flower)
2653 return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2654 break;
2655 case FLOW_CLS_DESTROY:
2656 if (h->ae_algo->ops->del_cls_flower)
2657 return h->ae_algo->ops->del_cls_flower(h, flow);
2658 break;
2659 default:
2660 break;
2661 }
2662
2663 return -EOPNOTSUPP;
2664 }
2665
hns3_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2666 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2667 void *cb_priv)
2668 {
2669 struct hns3_nic_priv *priv = cb_priv;
2670
2671 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2672 return -EOPNOTSUPP;
2673
2674 switch (type) {
2675 case TC_SETUP_CLSFLOWER:
2676 return hns3_setup_tc_cls_flower(priv, type_data);
2677 default:
2678 return -EOPNOTSUPP;
2679 }
2680 }
2681
2682 static LIST_HEAD(hns3_block_cb_list);
2683
hns3_nic_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)2684 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
2685 void *type_data)
2686 {
2687 struct hns3_nic_priv *priv = netdev_priv(dev);
2688 int ret;
2689
2690 switch (type) {
2691 case TC_SETUP_QDISC_MQPRIO:
2692 ret = hns3_setup_tc(dev, type_data);
2693 break;
2694 case TC_SETUP_BLOCK:
2695 ret = flow_block_cb_setup_simple(type_data,
2696 &hns3_block_cb_list,
2697 hns3_setup_tc_block_cb,
2698 priv, priv, true);
2699 break;
2700 default:
2701 return -EOPNOTSUPP;
2702 }
2703
2704 return ret;
2705 }
2706
hns3_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2707 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2708 __be16 proto, u16 vid)
2709 {
2710 struct hnae3_handle *h = hns3_get_handle(netdev);
2711 int ret = -EIO;
2712
2713 if (h->ae_algo->ops->set_vlan_filter)
2714 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2715
2716 return ret;
2717 }
2718
hns3_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2719 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2720 __be16 proto, u16 vid)
2721 {
2722 struct hnae3_handle *h = hns3_get_handle(netdev);
2723 int ret = -EIO;
2724
2725 if (h->ae_algo->ops->set_vlan_filter)
2726 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2727
2728 return ret;
2729 }
2730
hns3_ndo_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)2731 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2732 u8 qos, __be16 vlan_proto)
2733 {
2734 struct hnae3_handle *h = hns3_get_handle(netdev);
2735 int ret = -EIO;
2736
2737 netif_dbg(h, drv, netdev,
2738 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2739 vf, vlan, qos, ntohs(vlan_proto));
2740
2741 if (h->ae_algo->ops->set_vf_vlan_filter)
2742 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
2743 qos, vlan_proto);
2744
2745 return ret;
2746 }
2747
hns3_set_vf_spoofchk(struct net_device * netdev,int vf,bool enable)2748 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2749 {
2750 struct hnae3_handle *handle = hns3_get_handle(netdev);
2751
2752 if (hns3_nic_resetting(netdev))
2753 return -EBUSY;
2754
2755 if (!handle->ae_algo->ops->set_vf_spoofchk)
2756 return -EOPNOTSUPP;
2757
2758 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2759 }
2760
hns3_set_vf_trust(struct net_device * netdev,int vf,bool enable)2761 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2762 {
2763 struct hnae3_handle *handle = hns3_get_handle(netdev);
2764
2765 if (!handle->ae_algo->ops->set_vf_trust)
2766 return -EOPNOTSUPP;
2767
2768 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2769 }
2770
hns3_nic_change_mtu(struct net_device * netdev,int new_mtu)2771 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2772 {
2773 struct hnae3_handle *h = hns3_get_handle(netdev);
2774 int ret;
2775
2776 if (hns3_nic_resetting(netdev))
2777 return -EBUSY;
2778
2779 if (!h->ae_algo->ops->set_mtu)
2780 return -EOPNOTSUPP;
2781
2782 netif_dbg(h, drv, netdev,
2783 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2784
2785 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
2786 if (ret)
2787 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2788 ret);
2789 else
2790 WRITE_ONCE(netdev->mtu, new_mtu);
2791
2792 return ret;
2793 }
2794
hns3_get_timeout_queue(struct net_device * ndev)2795 static int hns3_get_timeout_queue(struct net_device *ndev)
2796 {
2797 int i;
2798
2799 /* Find the stopped queue the same way the stack does */
2800 for (i = 0; i < ndev->num_tx_queues; i++) {
2801 struct netdev_queue *q;
2802 unsigned long trans_start;
2803
2804 q = netdev_get_tx_queue(ndev, i);
2805 trans_start = READ_ONCE(q->trans_start);
2806 if (netif_xmit_stopped(q) &&
2807 time_after(jiffies,
2808 (trans_start + ndev->watchdog_timeo))) {
2809 #ifdef CONFIG_BQL
2810 struct dql *dql = &q->dql;
2811
2812 netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n",
2813 dql->last_obj_cnt, dql->num_queued,
2814 dql->adj_limit, dql->num_completed);
2815 #endif
2816 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2817 q->state,
2818 jiffies_to_msecs(jiffies - trans_start));
2819 break;
2820 }
2821 }
2822
2823 return i;
2824 }
2825
hns3_dump_queue_stats(struct net_device * ndev,struct hns3_enet_ring * tx_ring,int timeout_queue)2826 static void hns3_dump_queue_stats(struct net_device *ndev,
2827 struct hns3_enet_ring *tx_ring,
2828 int timeout_queue)
2829 {
2830 struct napi_struct *napi = &tx_ring->tqp_vector->napi;
2831 struct hns3_nic_priv *priv = netdev_priv(ndev);
2832
2833 netdev_info(ndev,
2834 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2835 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2836 tx_ring->next_to_clean, napi->state);
2837
2838 netdev_info(ndev,
2839 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
2840 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
2841 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
2842
2843 netdev_info(ndev,
2844 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2845 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
2846 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2847
2848 netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n",
2849 tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell);
2850 }
2851
hns3_dump_queue_reg(struct net_device * ndev,struct hns3_enet_ring * tx_ring)2852 static void hns3_dump_queue_reg(struct net_device *ndev,
2853 struct hns3_enet_ring *tx_ring)
2854 {
2855 netdev_info(ndev,
2856 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2857 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG),
2858 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG),
2859 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG),
2860 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG),
2861 readl(tx_ring->tqp_vector->mask_addr));
2862 netdev_info(ndev,
2863 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2864 hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG),
2865 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG),
2866 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG),
2867 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG),
2868 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG),
2869 hns3_tqp_read_reg(tx_ring,
2870 HNS3_RING_TX_RING_EBD_OFFSET_REG));
2871 }
2872
hns3_get_tx_timeo_queue_info(struct net_device * ndev)2873 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2874 {
2875 struct hns3_nic_priv *priv = netdev_priv(ndev);
2876 struct hnae3_handle *h = hns3_get_handle(ndev);
2877 struct hns3_enet_ring *tx_ring;
2878 int timeout_queue;
2879
2880 timeout_queue = hns3_get_timeout_queue(ndev);
2881 if (timeout_queue >= ndev->num_tx_queues) {
2882 netdev_info(ndev,
2883 "no netdev TX timeout queue found, timeout count: %llu\n",
2884 priv->tx_timeout_count);
2885 return false;
2886 }
2887
2888 priv->tx_timeout_count++;
2889
2890 tx_ring = &priv->ring[timeout_queue];
2891 hns3_dump_queue_stats(ndev, tx_ring, timeout_queue);
2892
2893 /* When mac received many pause frames continuous, it's unable to send
2894 * packets, which may cause tx timeout
2895 */
2896 if (h->ae_algo->ops->get_mac_stats) {
2897 struct hns3_mac_stats mac_stats;
2898
2899 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
2900 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
2901 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
2902 }
2903
2904 hns3_dump_queue_reg(ndev, tx_ring);
2905
2906 return true;
2907 }
2908
hns3_nic_net_timeout(struct net_device * ndev,unsigned int txqueue)2909 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
2910 {
2911 struct hns3_nic_priv *priv = netdev_priv(ndev);
2912 struct hnae3_handle *h = priv->ae_handle;
2913
2914 if (!hns3_get_tx_timeo_queue_info(ndev))
2915 return;
2916
2917 /* request the reset, and let the hclge to determine
2918 * which reset level should be done
2919 */
2920 if (h->ae_algo->ops->reset_event)
2921 h->ae_algo->ops->reset_event(h->pdev, h);
2922 }
2923
2924 #ifdef CONFIG_RFS_ACCEL
hns3_rx_flow_steer(struct net_device * dev,const struct sk_buff * skb,u16 rxq_index,u32 flow_id)2925 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2926 u16 rxq_index, u32 flow_id)
2927 {
2928 struct hnae3_handle *h = hns3_get_handle(dev);
2929 struct flow_keys fkeys;
2930
2931 if (!h->ae_algo->ops->add_arfs_entry)
2932 return -EOPNOTSUPP;
2933
2934 if (skb->encapsulation)
2935 return -EPROTONOSUPPORT;
2936
2937 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2938 return -EPROTONOSUPPORT;
2939
2940 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2941 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2942 (fkeys.basic.ip_proto != IPPROTO_TCP &&
2943 fkeys.basic.ip_proto != IPPROTO_UDP))
2944 return -EPROTONOSUPPORT;
2945
2946 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2947 }
2948 #endif
2949
hns3_nic_get_vf_config(struct net_device * ndev,int vf,struct ifla_vf_info * ivf)2950 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2951 struct ifla_vf_info *ivf)
2952 {
2953 struct hnae3_handle *h = hns3_get_handle(ndev);
2954
2955 if (!h->ae_algo->ops->get_vf_config)
2956 return -EOPNOTSUPP;
2957
2958 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2959 }
2960
hns3_nic_set_vf_link_state(struct net_device * ndev,int vf,int link_state)2961 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2962 int link_state)
2963 {
2964 struct hnae3_handle *h = hns3_get_handle(ndev);
2965
2966 if (!h->ae_algo->ops->set_vf_link_state)
2967 return -EOPNOTSUPP;
2968
2969 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2970 }
2971
hns3_nic_set_vf_rate(struct net_device * ndev,int vf,int min_tx_rate,int max_tx_rate)2972 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2973 int min_tx_rate, int max_tx_rate)
2974 {
2975 struct hnae3_handle *h = hns3_get_handle(ndev);
2976
2977 if (!h->ae_algo->ops->set_vf_rate)
2978 return -EOPNOTSUPP;
2979
2980 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2981 false);
2982 }
2983
hns3_nic_set_vf_mac(struct net_device * netdev,int vf_id,u8 * mac)2984 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2985 {
2986 struct hnae3_handle *h = hns3_get_handle(netdev);
2987 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
2988
2989 if (!h->ae_algo->ops->set_vf_mac)
2990 return -EOPNOTSUPP;
2991
2992 if (is_multicast_ether_addr(mac)) {
2993 hnae3_format_mac_addr(format_mac_addr, mac);
2994 netdev_err(netdev,
2995 "Invalid MAC:%s specified. Could not set MAC\n",
2996 format_mac_addr);
2997 return -EINVAL;
2998 }
2999
3000 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
3001 }
3002
3003 #define HNS3_INVALID_DSCP 0xff
3004 #define HNS3_DSCP_SHIFT 2
3005
hns3_get_skb_dscp(struct sk_buff * skb)3006 static u8 hns3_get_skb_dscp(struct sk_buff *skb)
3007 {
3008 __be16 protocol = skb->protocol;
3009 u8 dscp = HNS3_INVALID_DSCP;
3010
3011 if (protocol == htons(ETH_P_8021Q))
3012 protocol = vlan_get_protocol(skb);
3013
3014 if (protocol == htons(ETH_P_IP))
3015 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT;
3016 else if (protocol == htons(ETH_P_IPV6))
3017 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT;
3018
3019 return dscp;
3020 }
3021
hns3_nic_select_queue(struct net_device * netdev,struct sk_buff * skb,struct net_device * sb_dev)3022 static u16 hns3_nic_select_queue(struct net_device *netdev,
3023 struct sk_buff *skb,
3024 struct net_device *sb_dev)
3025 {
3026 struct hnae3_handle *h = hns3_get_handle(netdev);
3027 u8 dscp;
3028
3029 if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP ||
3030 !h->ae_algo->ops->get_dscp_prio)
3031 goto out;
3032
3033 dscp = hns3_get_skb_dscp(skb);
3034 if (unlikely(dscp >= HNAE3_MAX_DSCP))
3035 goto out;
3036
3037 skb->priority = h->kinfo.dscp_prio[dscp];
3038 if (skb->priority == HNAE3_PRIO_ID_INVALID)
3039 skb->priority = 0;
3040
3041 out:
3042 return netdev_pick_tx(netdev, skb, sb_dev);
3043 }
3044
3045 static const struct net_device_ops hns3_nic_netdev_ops = {
3046 .ndo_open = hns3_nic_net_open,
3047 .ndo_stop = hns3_nic_net_stop,
3048 .ndo_start_xmit = hns3_nic_net_xmit,
3049 .ndo_tx_timeout = hns3_nic_net_timeout,
3050 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
3051 .ndo_eth_ioctl = hns3_nic_do_ioctl,
3052 .ndo_change_mtu = hns3_nic_change_mtu,
3053 .ndo_set_features = hns3_nic_set_features,
3054 .ndo_features_check = hns3_features_check,
3055 .ndo_get_stats64 = hns3_nic_get_stats64,
3056 .ndo_setup_tc = hns3_nic_setup_tc,
3057 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
3058 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
3059 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
3060 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
3061 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
3062 .ndo_set_vf_trust = hns3_set_vf_trust,
3063 #ifdef CONFIG_RFS_ACCEL
3064 .ndo_rx_flow_steer = hns3_rx_flow_steer,
3065 #endif
3066 .ndo_get_vf_config = hns3_nic_get_vf_config,
3067 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
3068 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
3069 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
3070 .ndo_select_queue = hns3_nic_select_queue,
3071 };
3072
hns3_is_phys_func(struct pci_dev * pdev)3073 bool hns3_is_phys_func(struct pci_dev *pdev)
3074 {
3075 u32 dev_id = pdev->device;
3076
3077 switch (dev_id) {
3078 case HNAE3_DEV_ID_GE:
3079 case HNAE3_DEV_ID_25GE:
3080 case HNAE3_DEV_ID_25GE_RDMA:
3081 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
3082 case HNAE3_DEV_ID_50GE_RDMA:
3083 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
3084 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
3085 case HNAE3_DEV_ID_200G_RDMA:
3086 return true;
3087 case HNAE3_DEV_ID_VF:
3088 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
3089 return false;
3090 default:
3091 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
3092 dev_id);
3093 }
3094
3095 return false;
3096 }
3097
hns3_disable_sriov(struct pci_dev * pdev)3098 static void hns3_disable_sriov(struct pci_dev *pdev)
3099 {
3100 /* If our VFs are assigned we cannot shut down SR-IOV
3101 * without causing issues, so just leave the hardware
3102 * available but disabled
3103 */
3104 if (pci_vfs_assigned(pdev)) {
3105 dev_warn(&pdev->dev,
3106 "disabling driver while VFs are assigned\n");
3107 return;
3108 }
3109
3110 pci_disable_sriov(pdev);
3111 }
3112
3113 /* hns3_probe - Device initialization routine
3114 * @pdev: PCI device information struct
3115 * @ent: entry in hns3_pci_tbl
3116 *
3117 * hns3_probe initializes a PF identified by a pci_dev structure.
3118 * The OS initialization, configuring of the PF private structure,
3119 * and a hardware reset occur.
3120 *
3121 * Returns 0 on success, negative on failure
3122 */
hns3_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3123 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3124 {
3125 struct hnae3_ae_dev *ae_dev;
3126 int ret;
3127
3128 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
3129 if (!ae_dev)
3130 return -ENOMEM;
3131
3132 ae_dev->pdev = pdev;
3133 ae_dev->flag = ent->driver_data;
3134 pci_set_drvdata(pdev, ae_dev);
3135
3136 ret = hnae3_register_ae_dev(ae_dev);
3137 if (ret)
3138 pci_set_drvdata(pdev, NULL);
3139
3140 return ret;
3141 }
3142
3143 /**
3144 * hns3_clean_vf_config
3145 * @pdev: pointer to a pci_dev structure
3146 * @num_vfs: number of VFs allocated
3147 *
3148 * Clean residual vf config after disable sriov
3149 **/
hns3_clean_vf_config(struct pci_dev * pdev,int num_vfs)3150 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs)
3151 {
3152 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3153
3154 if (ae_dev->ops->clean_vf_config)
3155 ae_dev->ops->clean_vf_config(ae_dev, num_vfs);
3156 }
3157
3158 /* hns3_remove - Device removal routine
3159 * @pdev: PCI device information struct
3160 */
hns3_remove(struct pci_dev * pdev)3161 static void hns3_remove(struct pci_dev *pdev)
3162 {
3163 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3164
3165 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
3166 hns3_disable_sriov(pdev);
3167
3168 hnae3_unregister_ae_dev(ae_dev);
3169 pci_set_drvdata(pdev, NULL);
3170 }
3171
3172 /**
3173 * hns3_pci_sriov_configure
3174 * @pdev: pointer to a pci_dev structure
3175 * @num_vfs: number of VFs to allocate
3176 *
3177 * Enable or change the number of VFs. Called when the user updates the number
3178 * of VFs in sysfs.
3179 **/
hns3_pci_sriov_configure(struct pci_dev * pdev,int num_vfs)3180 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
3181 {
3182 int ret;
3183
3184 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
3185 dev_warn(&pdev->dev, "Can not config SRIOV\n");
3186 return -EINVAL;
3187 }
3188
3189 if (num_vfs) {
3190 ret = pci_enable_sriov(pdev, num_vfs);
3191 if (ret)
3192 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
3193 else
3194 return num_vfs;
3195 } else if (!pci_vfs_assigned(pdev)) {
3196 int num_vfs_pre = pci_num_vf(pdev);
3197
3198 pci_disable_sriov(pdev);
3199 hns3_clean_vf_config(pdev, num_vfs_pre);
3200 } else {
3201 dev_warn(&pdev->dev,
3202 "Unable to free VFs because some are assigned to VMs.\n");
3203 }
3204
3205 return 0;
3206 }
3207
hns3_shutdown(struct pci_dev * pdev)3208 static void hns3_shutdown(struct pci_dev *pdev)
3209 {
3210 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3211
3212 hnae3_unregister_ae_dev(ae_dev);
3213 pci_set_drvdata(pdev, NULL);
3214
3215 if (system_state == SYSTEM_POWER_OFF)
3216 pci_set_power_state(pdev, PCI_D3hot);
3217 }
3218
hns3_suspend(struct device * dev)3219 static int __maybe_unused hns3_suspend(struct device *dev)
3220 {
3221 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3222
3223 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3224 dev_info(dev, "Begin to suspend.\n");
3225 if (ae_dev->ops && ae_dev->ops->reset_prepare)
3226 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3227 }
3228
3229 return 0;
3230 }
3231
hns3_resume(struct device * dev)3232 static int __maybe_unused hns3_resume(struct device *dev)
3233 {
3234 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3235
3236 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3237 dev_info(dev, "Begin to resume.\n");
3238 if (ae_dev->ops && ae_dev->ops->reset_done)
3239 ae_dev->ops->reset_done(ae_dev);
3240 }
3241
3242 return 0;
3243 }
3244
hns3_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3245 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3246 pci_channel_state_t state)
3247 {
3248 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3249 pci_ers_result_t ret;
3250
3251 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
3252
3253 if (state == pci_channel_io_perm_failure)
3254 return PCI_ERS_RESULT_DISCONNECT;
3255
3256 if (!ae_dev || !ae_dev->ops) {
3257 dev_err(&pdev->dev,
3258 "Can't recover - error happened before device initialized\n");
3259 return PCI_ERS_RESULT_NONE;
3260 }
3261
3262 if (ae_dev->ops->handle_hw_ras_error)
3263 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
3264 else
3265 return PCI_ERS_RESULT_NONE;
3266
3267 return ret;
3268 }
3269
hns3_slot_reset(struct pci_dev * pdev)3270 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3271 {
3272 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3273 const struct hnae3_ae_ops *ops;
3274 enum hnae3_reset_type reset_type;
3275 struct device *dev = &pdev->dev;
3276
3277 if (!ae_dev || !ae_dev->ops)
3278 return PCI_ERS_RESULT_NONE;
3279
3280 ops = ae_dev->ops;
3281 /* request the reset */
3282 if (ops->reset_event && ops->get_reset_level &&
3283 ops->set_default_reset_request) {
3284 if (ae_dev->hw_err_reset_req) {
3285 reset_type = ops->get_reset_level(ae_dev,
3286 &ae_dev->hw_err_reset_req);
3287 ops->set_default_reset_request(ae_dev, reset_type);
3288 dev_info(dev, "requesting reset due to PCI error\n");
3289 ops->reset_event(pdev, NULL);
3290 }
3291
3292 return PCI_ERS_RESULT_RECOVERED;
3293 }
3294
3295 return PCI_ERS_RESULT_DISCONNECT;
3296 }
3297
hns3_reset_prepare(struct pci_dev * pdev)3298 static void hns3_reset_prepare(struct pci_dev *pdev)
3299 {
3300 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3301
3302 dev_info(&pdev->dev, "FLR prepare\n");
3303 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3304 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
3305 }
3306
hns3_reset_done(struct pci_dev * pdev)3307 static void hns3_reset_done(struct pci_dev *pdev)
3308 {
3309 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3310
3311 dev_info(&pdev->dev, "FLR done\n");
3312 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3313 ae_dev->ops->reset_done(ae_dev);
3314 }
3315
3316 static const struct pci_error_handlers hns3_err_handler = {
3317 .error_detected = hns3_error_detected,
3318 .slot_reset = hns3_slot_reset,
3319 .reset_prepare = hns3_reset_prepare,
3320 .reset_done = hns3_reset_done,
3321 };
3322
3323 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3324
3325 static struct pci_driver hns3_driver = {
3326 .name = hns3_driver_name,
3327 .id_table = hns3_pci_tbl,
3328 .probe = hns3_probe,
3329 .remove = hns3_remove,
3330 .shutdown = hns3_shutdown,
3331 .driver.pm = &hns3_pm_ops,
3332 .sriov_configure = hns3_pci_sriov_configure,
3333 .err_handler = &hns3_err_handler,
3334 };
3335
3336 /* set default feature to hns3 */
hns3_set_default_feature(struct net_device * netdev)3337 static void hns3_set_default_feature(struct net_device *netdev)
3338 {
3339 struct hnae3_handle *h = hns3_get_handle(netdev);
3340 struct pci_dev *pdev = h->pdev;
3341 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3342
3343 netdev->priv_flags |= IFF_UNICAST_FLT;
3344
3345 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3346 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3347 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3348 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3349 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
3350 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3351
3352 if (hnae3_ae_dev_gro_supported(ae_dev))
3353 netdev->features |= NETIF_F_GRO_HW;
3354
3355 if (hnae3_ae_dev_fd_supported(ae_dev))
3356 netdev->features |= NETIF_F_NTUPLE;
3357
3358 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
3359 netdev->features |= NETIF_F_GSO_UDP_L4;
3360
3361 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
3362 netdev->features |= NETIF_F_HW_CSUM;
3363 else
3364 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3365
3366 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3367 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3368
3369 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
3370 netdev->features |= NETIF_F_HW_TC;
3371
3372 netdev->hw_features |= netdev->features;
3373 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3374 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3375
3376 netdev->vlan_features |= netdev->features &
3377 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3378 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3379 NETIF_F_HW_TC);
3380
3381 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
3382
3383 /* The device_version V3 hardware can't offload the checksum for IP in
3384 * GRE packets, but can do it for NvGRE. So default to disable the
3385 * checksum and GSO offload for GRE.
3386 */
3387 if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) {
3388 netdev->features &= ~NETIF_F_GSO_GRE;
3389 netdev->features &= ~NETIF_F_GSO_GRE_CSUM;
3390 }
3391 }
3392
hns3_alloc_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3393 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3394 struct hns3_desc_cb *cb)
3395 {
3396 unsigned int order = hns3_page_order(ring);
3397 struct page *p;
3398
3399 if (ring->page_pool) {
3400 p = page_pool_dev_alloc_frag(ring->page_pool,
3401 &cb->page_offset,
3402 hns3_buf_size(ring));
3403 if (unlikely(!p))
3404 return -ENOMEM;
3405
3406 cb->priv = p;
3407 cb->buf = page_address(p);
3408 cb->dma = page_pool_get_dma_addr(p);
3409 cb->type = DESC_TYPE_PP_FRAG;
3410 cb->reuse_flag = 0;
3411 return 0;
3412 }
3413
3414 p = dev_alloc_pages(order);
3415 if (!p)
3416 return -ENOMEM;
3417
3418 cb->priv = p;
3419 cb->page_offset = 0;
3420 cb->reuse_flag = 0;
3421 cb->buf = page_address(p);
3422 cb->length = hns3_page_size(ring);
3423 cb->type = DESC_TYPE_PAGE;
3424 page_ref_add(p, USHRT_MAX - 1);
3425 cb->pagecnt_bias = USHRT_MAX;
3426
3427 return 0;
3428 }
3429
hns3_free_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb,int budget)3430 static void hns3_free_buffer(struct hns3_enet_ring *ring,
3431 struct hns3_desc_cb *cb, int budget)
3432 {
3433 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
3434 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
3435 napi_consume_skb(cb->priv, budget);
3436 else if (!HNAE3_IS_TX_RING(ring)) {
3437 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3438 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3439 else if (cb->type & DESC_TYPE_PP_FRAG)
3440 page_pool_put_full_page(ring->page_pool, cb->priv,
3441 false);
3442 }
3443 memset(cb, 0, sizeof(*cb));
3444 }
3445
hns3_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3446 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3447 {
3448 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3449 cb->length, ring_to_dma_dir(ring));
3450
3451 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
3452 return -EIO;
3453
3454 return 0;
3455 }
3456
hns3_unmap_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3457 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3458 struct hns3_desc_cb *cb)
3459 {
3460 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
3461 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3462 ring_to_dma_dir(ring));
3463 else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
3464 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3465 ring_to_dma_dir(ring));
3466 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3467 DESC_TYPE_SGL_SKB))
3468 hns3_tx_spare_reclaim_cb(ring, cb);
3469 }
3470
hns3_buffer_detach(struct hns3_enet_ring * ring,int i)3471 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3472 {
3473 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3474 ring->desc[i].addr = 0;
3475 ring->desc_cb[i].refill = 0;
3476 }
3477
hns3_free_buffer_detach(struct hns3_enet_ring * ring,int i,int budget)3478 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3479 int budget)
3480 {
3481 struct hns3_desc_cb *cb = &ring->desc_cb[i];
3482
3483 if (!ring->desc_cb[i].dma)
3484 return;
3485
3486 hns3_buffer_detach(ring, i);
3487 hns3_free_buffer(ring, cb, budget);
3488 }
3489
hns3_free_buffers(struct hns3_enet_ring * ring)3490 static void hns3_free_buffers(struct hns3_enet_ring *ring)
3491 {
3492 int i;
3493
3494 for (i = 0; i < ring->desc_num; i++)
3495 hns3_free_buffer_detach(ring, i, 0);
3496 }
3497
3498 /* free desc along with its attached buffer */
hns3_free_desc(struct hns3_enet_ring * ring)3499 static void hns3_free_desc(struct hns3_enet_ring *ring)
3500 {
3501 int size = ring->desc_num * sizeof(ring->desc[0]);
3502
3503 hns3_free_buffers(ring);
3504
3505 if (ring->desc) {
3506 dma_free_coherent(ring_to_dev(ring), size,
3507 ring->desc, ring->desc_dma_addr);
3508 ring->desc = NULL;
3509 }
3510 }
3511
hns3_alloc_desc(struct hns3_enet_ring * ring)3512 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3513 {
3514 int size = ring->desc_num * sizeof(ring->desc[0]);
3515
3516 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3517 &ring->desc_dma_addr, GFP_KERNEL);
3518 if (!ring->desc)
3519 return -ENOMEM;
3520
3521 return 0;
3522 }
3523
hns3_alloc_and_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3524 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
3525 struct hns3_desc_cb *cb)
3526 {
3527 int ret;
3528
3529 ret = hns3_alloc_buffer(ring, cb);
3530 if (ret || ring->page_pool)
3531 goto out;
3532
3533 ret = hns3_map_buffer(ring, cb);
3534 if (ret)
3535 goto out_with_buf;
3536
3537 return 0;
3538
3539 out_with_buf:
3540 hns3_free_buffer(ring, cb, 0);
3541 out:
3542 return ret;
3543 }
3544
hns3_alloc_and_attach_buffer(struct hns3_enet_ring * ring,int i)3545 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
3546 {
3547 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
3548
3549 if (ret)
3550 return ret;
3551
3552 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3553 ring->desc_cb[i].page_offset);
3554 ring->desc_cb[i].refill = 1;
3555
3556 return 0;
3557 }
3558
3559 /* Allocate memory for raw pkg, and map with dma */
hns3_alloc_ring_buffers(struct hns3_enet_ring * ring)3560 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3561 {
3562 int i, j, ret;
3563
3564 for (i = 0; i < ring->desc_num; i++) {
3565 ret = hns3_alloc_and_attach_buffer(ring, i);
3566 if (ret)
3567 goto out_buffer_fail;
3568
3569 if (!(i % HNS3_RESCHED_BD_NUM))
3570 cond_resched();
3571 }
3572
3573 return 0;
3574
3575 out_buffer_fail:
3576 for (j = i - 1; j >= 0; j--)
3577 hns3_free_buffer_detach(ring, j, 0);
3578 return ret;
3579 }
3580
3581 /* detach a in-used buffer and replace with a reserved one */
hns3_replace_buffer(struct hns3_enet_ring * ring,int i,struct hns3_desc_cb * res_cb)3582 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3583 struct hns3_desc_cb *res_cb)
3584 {
3585 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3586 ring->desc_cb[i] = *res_cb;
3587 ring->desc_cb[i].refill = 1;
3588 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3589 ring->desc_cb[i].page_offset);
3590 ring->desc[i].rx.bd_base_info = 0;
3591 }
3592
hns3_reuse_buffer(struct hns3_enet_ring * ring,int i)3593 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3594 {
3595 ring->desc_cb[i].reuse_flag = 0;
3596 ring->desc_cb[i].refill = 1;
3597 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3598 ring->desc_cb[i].page_offset);
3599 ring->desc[i].rx.bd_base_info = 0;
3600
3601 dma_sync_single_for_device(ring_to_dev(ring),
3602 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3603 hns3_buf_size(ring),
3604 DMA_FROM_DEVICE);
3605 }
3606
hns3_nic_reclaim_desc(struct hns3_enet_ring * ring,int * bytes,int * pkts,int budget)3607 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
3608 int *bytes, int *pkts, int budget)
3609 {
3610 /* This smp_load_acquire() pairs with smp_store_release() in
3611 * hns3_tx_doorbell().
3612 */
3613 int ltu = smp_load_acquire(&ring->last_to_use);
3614 int ntc = ring->next_to_clean;
3615 struct hns3_desc_cb *desc_cb;
3616 bool reclaimed = false;
3617 struct hns3_desc *desc;
3618
3619 while (ltu != ntc) {
3620 desc = &ring->desc[ntc];
3621
3622 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3623 BIT(HNS3_TXD_VLD_B))
3624 break;
3625
3626 desc_cb = &ring->desc_cb[ntc];
3627
3628 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
3629 DESC_TYPE_BOUNCE_HEAD |
3630 DESC_TYPE_SGL_SKB)) {
3631 (*pkts)++;
3632 (*bytes) += desc_cb->send_bytes;
3633 }
3634
3635 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
3636 hns3_free_buffer_detach(ring, ntc, budget);
3637
3638 if (++ntc == ring->desc_num)
3639 ntc = 0;
3640
3641 /* Issue prefetch for next Tx descriptor */
3642 prefetch(&ring->desc_cb[ntc]);
3643 reclaimed = true;
3644 }
3645
3646 if (unlikely(!reclaimed))
3647 return false;
3648
3649 /* This smp_store_release() pairs with smp_load_acquire() in
3650 * ring_space called by hns3_nic_net_xmit.
3651 */
3652 smp_store_release(&ring->next_to_clean, ntc);
3653
3654 hns3_tx_spare_update(ring);
3655
3656 return true;
3657 }
3658
hns3_clean_tx_ring(struct hns3_enet_ring * ring,int budget)3659 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
3660 {
3661 struct net_device *netdev = ring_to_netdev(ring);
3662 struct hns3_nic_priv *priv = netdev_priv(netdev);
3663 struct netdev_queue *dev_queue;
3664 int bytes, pkts;
3665
3666 bytes = 0;
3667 pkts = 0;
3668
3669 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
3670 return;
3671
3672 ring->tqp_vector->tx_group.total_bytes += bytes;
3673 ring->tqp_vector->tx_group.total_packets += pkts;
3674
3675 u64_stats_update_begin(&ring->syncp);
3676 ring->stats.tx_bytes += bytes;
3677 ring->stats.tx_pkts += pkts;
3678 u64_stats_update_end(&ring->syncp);
3679
3680 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3681 netdev_tx_completed_queue(dev_queue, pkts, bytes);
3682
3683 if (unlikely(netif_carrier_ok(netdev) &&
3684 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
3685 /* Make sure that anybody stopping the queue after this
3686 * sees the new next_to_clean.
3687 */
3688 smp_mb();
3689 if (netif_tx_queue_stopped(dev_queue) &&
3690 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
3691 netif_tx_wake_queue(dev_queue);
3692 ring->stats.restart_queue++;
3693 }
3694 }
3695 }
3696
hns3_desc_unused(struct hns3_enet_ring * ring)3697 static int hns3_desc_unused(struct hns3_enet_ring *ring)
3698 {
3699 int ntc = ring->next_to_clean;
3700 int ntu = ring->next_to_use;
3701
3702 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill))
3703 return ring->desc_num;
3704
3705 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3706 }
3707
3708 /* Return true if there is any allocation failure */
hns3_nic_alloc_rx_buffers(struct hns3_enet_ring * ring,int cleand_count)3709 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3710 int cleand_count)
3711 {
3712 struct hns3_desc_cb *desc_cb;
3713 struct hns3_desc_cb res_cbs;
3714 int i, ret;
3715
3716 for (i = 0; i < cleand_count; i++) {
3717 desc_cb = &ring->desc_cb[ring->next_to_use];
3718 if (desc_cb->reuse_flag) {
3719 hns3_ring_stats_update(ring, reuse_pg_cnt);
3720
3721 hns3_reuse_buffer(ring, ring->next_to_use);
3722 } else {
3723 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
3724 if (ret) {
3725 hns3_ring_stats_update(ring, sw_err_cnt);
3726
3727 hns3_rl_err(ring_to_netdev(ring),
3728 "alloc rx buffer failed: %d\n",
3729 ret);
3730
3731 writel(i, ring->tqp->io_base +
3732 HNS3_RING_RX_RING_HEAD_REG);
3733 return true;
3734 }
3735 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
3736
3737 hns3_ring_stats_update(ring, non_reuse_pg);
3738 }
3739
3740 ring_ptr_move_fw(ring, next_to_use);
3741 }
3742
3743 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
3744 return false;
3745 }
3746
hns3_can_reuse_page(struct hns3_desc_cb * cb)3747 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3748 {
3749 return page_count(cb->priv) == cb->pagecnt_bias;
3750 }
3751
hns3_handle_rx_copybreak(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3752 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i,
3753 struct hns3_enet_ring *ring,
3754 int pull_len,
3755 struct hns3_desc_cb *desc_cb)
3756 {
3757 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3758 u32 frag_offset = desc_cb->page_offset + pull_len;
3759 int size = le16_to_cpu(desc->rx.size);
3760 u32 frag_size = size - pull_len;
3761 void *frag = napi_alloc_frag(frag_size);
3762
3763 if (unlikely(!frag)) {
3764 hns3_ring_stats_update(ring, frag_alloc_err);
3765
3766 hns3_rl_err(ring_to_netdev(ring),
3767 "failed to allocate rx frag\n");
3768 return -ENOMEM;
3769 }
3770
3771 desc_cb->reuse_flag = 1;
3772 memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3773 skb_add_rx_frag(skb, i, virt_to_page(frag),
3774 offset_in_page(frag), frag_size, frag_size);
3775
3776 hns3_ring_stats_update(ring, frag_alloc);
3777 return 0;
3778 }
3779
hns3_nic_reuse_page(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3780 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3781 struct hns3_enet_ring *ring, int pull_len,
3782 struct hns3_desc_cb *desc_cb)
3783 {
3784 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3785 u32 frag_offset = desc_cb->page_offset + pull_len;
3786 int size = le16_to_cpu(desc->rx.size);
3787 u32 truesize = hns3_buf_size(ring);
3788 u32 frag_size = size - pull_len;
3789 int ret = 0;
3790 bool reused;
3791
3792 if (ring->page_pool) {
3793 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3794 frag_size, truesize);
3795 return;
3796 }
3797
3798 /* Avoid re-using remote or pfmem page */
3799 if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3800 goto out;
3801
3802 reused = hns3_can_reuse_page(desc_cb);
3803
3804 /* Rx page can be reused when:
3805 * 1. Rx page is only owned by the driver when page_offset
3806 * is zero, which means 0 @ truesize will be used by
3807 * stack after skb_add_rx_frag() is called, and the rest
3808 * of rx page can be reused by driver.
3809 * Or
3810 * 2. Rx page is only owned by the driver when page_offset
3811 * is non-zero, which means page_offset @ truesize will
3812 * be used by stack after skb_add_rx_frag() is called,
3813 * and 0 @ truesize can be reused by driver.
3814 */
3815 if ((!desc_cb->page_offset && reused) ||
3816 ((desc_cb->page_offset + truesize + truesize) <=
3817 hns3_page_size(ring) && desc_cb->page_offset)) {
3818 desc_cb->page_offset += truesize;
3819 desc_cb->reuse_flag = 1;
3820 } else if (desc_cb->page_offset && reused) {
3821 desc_cb->page_offset = 0;
3822 desc_cb->reuse_flag = 1;
3823 } else if (frag_size <= ring->rx_copybreak) {
3824 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb);
3825 if (!ret)
3826 return;
3827 }
3828
3829 out:
3830 desc_cb->pagecnt_bias--;
3831
3832 if (unlikely(!desc_cb->pagecnt_bias)) {
3833 page_ref_add(desc_cb->priv, USHRT_MAX);
3834 desc_cb->pagecnt_bias = USHRT_MAX;
3835 }
3836
3837 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3838 frag_size, truesize);
3839
3840 if (unlikely(!desc_cb->reuse_flag))
3841 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
3842 }
3843
hns3_gro_complete(struct sk_buff * skb,u32 l234info)3844 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
3845 {
3846 __be16 type = skb->protocol;
3847 struct tcphdr *th;
3848 int depth = 0;
3849
3850 while (eth_type_vlan(type)) {
3851 struct vlan_hdr *vh;
3852
3853 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3854 return -EFAULT;
3855
3856 vh = (struct vlan_hdr *)(skb->data + depth);
3857 type = vh->h_vlan_encapsulated_proto;
3858 depth += VLAN_HLEN;
3859 }
3860
3861 skb_set_network_header(skb, depth);
3862
3863 if (type == htons(ETH_P_IP)) {
3864 const struct iphdr *iph = ip_hdr(skb);
3865
3866 depth += sizeof(struct iphdr);
3867 skb_set_transport_header(skb, depth);
3868 th = tcp_hdr(skb);
3869 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3870 iph->daddr, 0);
3871 } else if (type == htons(ETH_P_IPV6)) {
3872 const struct ipv6hdr *iph = ipv6_hdr(skb);
3873
3874 depth += sizeof(struct ipv6hdr);
3875 skb_set_transport_header(skb, depth);
3876 th = tcp_hdr(skb);
3877 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3878 &iph->daddr, 0);
3879 } else {
3880 hns3_rl_err(skb->dev,
3881 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3882 be16_to_cpu(type), depth);
3883 return -EFAULT;
3884 }
3885
3886 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3887 if (th->cwr)
3888 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3889
3890 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3891 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
3892
3893 skb->csum_start = (unsigned char *)th - skb->head;
3894 skb->csum_offset = offsetof(struct tcphdr, check);
3895 skb->ip_summed = CHECKSUM_PARTIAL;
3896
3897 trace_hns3_gro(skb);
3898
3899 return 0;
3900 }
3901
hns3_checksum_complete(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 ptype,u16 csum)3902 static void hns3_checksum_complete(struct hns3_enet_ring *ring,
3903 struct sk_buff *skb, u32 ptype, u16 csum)
3904 {
3905 if (ptype == HNS3_INVALID_PTYPE ||
3906 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3907 return;
3908
3909 hns3_ring_stats_update(ring, csum_complete);
3910 skb->ip_summed = CHECKSUM_COMPLETE;
3911 skb->csum = csum_unfold((__force __sum16)csum);
3912 }
3913
hns3_rx_handle_csum(struct sk_buff * skb,u32 l234info,u32 ol_info,u32 ptype)3914 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3915 u32 ol_info, u32 ptype)
3916 {
3917 int l3_type, l4_type;
3918 int ol4_type;
3919
3920 if (ptype != HNS3_INVALID_PTYPE) {
3921 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3922 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
3923
3924 return;
3925 }
3926
3927 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
3928 HNS3_RXD_OL4ID_S);
3929 switch (ol4_type) {
3930 case HNS3_OL4_TYPE_MAC_IN_UDP:
3931 case HNS3_OL4_TYPE_NVGRE:
3932 skb->csum_level = 1;
3933 fallthrough;
3934 case HNS3_OL4_TYPE_NO_TUN:
3935 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3936 HNS3_RXD_L3ID_S);
3937 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3938 HNS3_RXD_L4ID_S);
3939 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
3940 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3941 l3_type == HNS3_L3_TYPE_IPV6) &&
3942 (l4_type == HNS3_L4_TYPE_UDP ||
3943 l4_type == HNS3_L4_TYPE_TCP ||
3944 l4_type == HNS3_L4_TYPE_SCTP))
3945 skb->ip_summed = CHECKSUM_UNNECESSARY;
3946 break;
3947 default:
3948 break;
3949 }
3950 }
3951
hns3_rx_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)3952 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
3953 u32 l234info, u32 bd_base_info, u32 ol_info,
3954 u16 csum)
3955 {
3956 struct net_device *netdev = ring_to_netdev(ring);
3957 struct hns3_nic_priv *priv = netdev_priv(netdev);
3958 u32 ptype = HNS3_INVALID_PTYPE;
3959
3960 skb->ip_summed = CHECKSUM_NONE;
3961
3962 skb_checksum_none_assert(skb);
3963
3964 if (!(netdev->features & NETIF_F_RXCSUM))
3965 return;
3966
3967 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3968 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3969 HNS3_RXD_PTYPE_S);
3970
3971 hns3_checksum_complete(ring, skb, ptype, csum);
3972
3973 /* check if hardware has done checksum */
3974 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3975 return;
3976
3977 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3978 BIT(HNS3_RXD_OL3E_B) |
3979 BIT(HNS3_RXD_OL4E_B)))) {
3980 skb->ip_summed = CHECKSUM_NONE;
3981 hns3_ring_stats_update(ring, l3l4_csum_err);
3982
3983 return;
3984 }
3985
3986 hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
3987 }
3988
hns3_rx_skb(struct hns3_enet_ring * ring,struct sk_buff * skb)3989 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
3990 {
3991 if (skb_has_frag_list(skb))
3992 napi_gro_flush(&ring->tqp_vector->napi, false);
3993
3994 napi_gro_receive(&ring->tqp_vector->napi, skb);
3995 }
3996
hns3_parse_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,u32 l234info,u16 * vlan_tag)3997 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
3998 struct hns3_desc *desc, u32 l234info,
3999 u16 *vlan_tag)
4000 {
4001 struct hnae3_handle *handle = ring->tqp->handle;
4002 struct pci_dev *pdev = ring->tqp->handle->pdev;
4003 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
4004
4005 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
4006 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4007 if (!(*vlan_tag & VLAN_VID_MASK))
4008 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4009
4010 return (*vlan_tag != 0);
4011 }
4012
4013 #define HNS3_STRP_OUTER_VLAN 0x1
4014 #define HNS3_STRP_INNER_VLAN 0x2
4015 #define HNS3_STRP_BOTH 0x3
4016
4017 /* Hardware always insert VLAN tag into RX descriptor when
4018 * remove the tag from packet, driver needs to determine
4019 * reporting which tag to stack.
4020 */
4021 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
4022 HNS3_RXD_STRP_TAGP_S)) {
4023 case HNS3_STRP_OUTER_VLAN:
4024 if (handle->port_base_vlan_state !=
4025 HNAE3_PORT_BASE_VLAN_DISABLE)
4026 return false;
4027
4028 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4029 return true;
4030 case HNS3_STRP_INNER_VLAN:
4031 if (handle->port_base_vlan_state !=
4032 HNAE3_PORT_BASE_VLAN_DISABLE)
4033 return false;
4034
4035 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4036 return true;
4037 case HNS3_STRP_BOTH:
4038 if (handle->port_base_vlan_state ==
4039 HNAE3_PORT_BASE_VLAN_DISABLE)
4040 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4041 else
4042 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4043
4044 return true;
4045 default:
4046 return false;
4047 }
4048 }
4049
hns3_rx_ring_move_fw(struct hns3_enet_ring * ring)4050 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
4051 {
4052 ring->desc[ring->next_to_clean].rx.bd_base_info &=
4053 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
4054 ring->desc_cb[ring->next_to_clean].refill = 0;
4055 ring->next_to_clean += 1;
4056
4057 if (unlikely(ring->next_to_clean == ring->desc_num))
4058 ring->next_to_clean = 0;
4059 }
4060
hns3_alloc_skb(struct hns3_enet_ring * ring,unsigned int length,unsigned char * va)4061 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
4062 unsigned char *va)
4063 {
4064 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
4065 struct net_device *netdev = ring_to_netdev(ring);
4066 struct sk_buff *skb;
4067
4068 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
4069 skb = ring->skb;
4070 if (unlikely(!skb)) {
4071 hns3_rl_err(netdev, "alloc rx skb fail\n");
4072 hns3_ring_stats_update(ring, sw_err_cnt);
4073
4074 return -ENOMEM;
4075 }
4076
4077 trace_hns3_rx_desc(ring);
4078 prefetchw(skb->data);
4079
4080 ring->pending_buf = 1;
4081 ring->frag_num = 0;
4082 ring->tail_skb = NULL;
4083 if (length <= HNS3_RX_HEAD_SIZE) {
4084 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
4085
4086 /* We can reuse buffer as-is, just make sure it is reusable */
4087 if (dev_page_is_reusable(desc_cb->priv))
4088 desc_cb->reuse_flag = 1;
4089 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
4090 page_pool_put_full_page(ring->page_pool, desc_cb->priv,
4091 false);
4092 else /* This page cannot be reused so discard it */
4093 __page_frag_cache_drain(desc_cb->priv,
4094 desc_cb->pagecnt_bias);
4095
4096 hns3_rx_ring_move_fw(ring);
4097 return 0;
4098 }
4099
4100 if (ring->page_pool)
4101 skb_mark_for_recycle(skb);
4102
4103 hns3_ring_stats_update(ring, seg_pkt_cnt);
4104
4105 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
4106 __skb_put(skb, ring->pull_len);
4107 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
4108 desc_cb);
4109 hns3_rx_ring_move_fw(ring);
4110
4111 return 0;
4112 }
4113
hns3_add_frag(struct hns3_enet_ring * ring)4114 static int hns3_add_frag(struct hns3_enet_ring *ring)
4115 {
4116 struct sk_buff *skb = ring->skb;
4117 struct sk_buff *head_skb = skb;
4118 struct sk_buff *new_skb;
4119 struct hns3_desc_cb *desc_cb;
4120 struct hns3_desc *desc;
4121 u32 bd_base_info;
4122
4123 do {
4124 desc = &ring->desc[ring->next_to_clean];
4125 desc_cb = &ring->desc_cb[ring->next_to_clean];
4126 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4127 /* make sure HW write desc complete */
4128 dma_rmb();
4129 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
4130 return -ENXIO;
4131
4132 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
4133 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
4134 if (unlikely(!new_skb)) {
4135 hns3_rl_err(ring_to_netdev(ring),
4136 "alloc rx fraglist skb fail\n");
4137 return -ENXIO;
4138 }
4139
4140 if (ring->page_pool)
4141 skb_mark_for_recycle(new_skb);
4142
4143 ring->frag_num = 0;
4144
4145 if (ring->tail_skb) {
4146 ring->tail_skb->next = new_skb;
4147 ring->tail_skb = new_skb;
4148 } else {
4149 skb_shinfo(skb)->frag_list = new_skb;
4150 ring->tail_skb = new_skb;
4151 }
4152 }
4153
4154 if (ring->tail_skb) {
4155 head_skb->truesize += hns3_buf_size(ring);
4156 head_skb->data_len += le16_to_cpu(desc->rx.size);
4157 head_skb->len += le16_to_cpu(desc->rx.size);
4158 skb = ring->tail_skb;
4159 }
4160
4161 dma_sync_single_for_cpu(ring_to_dev(ring),
4162 desc_cb->dma + desc_cb->page_offset,
4163 hns3_buf_size(ring),
4164 DMA_FROM_DEVICE);
4165
4166 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
4167 trace_hns3_rx_desc(ring);
4168 hns3_rx_ring_move_fw(ring);
4169 ring->pending_buf++;
4170 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
4171
4172 return 0;
4173 }
4174
hns3_set_gro_and_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)4175 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
4176 struct sk_buff *skb, u32 l234info,
4177 u32 bd_base_info, u32 ol_info, u16 csum)
4178 {
4179 struct net_device *netdev = ring_to_netdev(ring);
4180 struct hns3_nic_priv *priv = netdev_priv(netdev);
4181 u32 l3_type;
4182
4183 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
4184 HNS3_RXD_GRO_SIZE_M,
4185 HNS3_RXD_GRO_SIZE_S);
4186 /* if there is no HW GRO, do not set gro params */
4187 if (!skb_shinfo(skb)->gso_size) {
4188 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
4189 csum);
4190 return 0;
4191 }
4192
4193 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
4194 HNS3_RXD_GRO_COUNT_M,
4195 HNS3_RXD_GRO_COUNT_S);
4196
4197 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4198 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4199 HNS3_RXD_PTYPE_S);
4200
4201 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
4202 } else {
4203 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4204 HNS3_RXD_L3ID_S);
4205 }
4206
4207 if (l3_type == HNS3_L3_TYPE_IPV4)
4208 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
4209 else if (l3_type == HNS3_L3_TYPE_IPV6)
4210 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
4211 else
4212 return -EFAULT;
4213
4214 return hns3_gro_complete(skb, l234info);
4215 }
4216
hns3_set_rx_skb_rss_type(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 rss_hash,u32 l234info,u32 ol_info)4217 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
4218 struct sk_buff *skb, u32 rss_hash,
4219 u32 l234info, u32 ol_info)
4220 {
4221 enum pkt_hash_types rss_type = PKT_HASH_TYPE_NONE;
4222 struct net_device *netdev = ring_to_netdev(ring);
4223 struct hns3_nic_priv *priv = netdev_priv(netdev);
4224
4225 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4226 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4227 HNS3_RXD_PTYPE_S);
4228
4229 rss_type = hns3_rx_ptype_tbl[ptype].hash_type;
4230 } else {
4231 int l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4232 HNS3_RXD_L3ID_S);
4233 int l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
4234 HNS3_RXD_L4ID_S);
4235
4236 if (l3_type == HNS3_L3_TYPE_IPV4 ||
4237 l3_type == HNS3_L3_TYPE_IPV6) {
4238 if (l4_type == HNS3_L4_TYPE_UDP ||
4239 l4_type == HNS3_L4_TYPE_TCP ||
4240 l4_type == HNS3_L4_TYPE_SCTP)
4241 rss_type = PKT_HASH_TYPE_L4;
4242 else if (l4_type == HNS3_L4_TYPE_IGMP ||
4243 l4_type == HNS3_L4_TYPE_ICMP)
4244 rss_type = PKT_HASH_TYPE_L3;
4245 }
4246 }
4247
4248 skb_set_hash(skb, rss_hash, rss_type);
4249 }
4250
hns3_handle_rx_ts_info(struct net_device * netdev,struct hns3_desc * desc,struct sk_buff * skb,u32 bd_base_info)4251 static void hns3_handle_rx_ts_info(struct net_device *netdev,
4252 struct hns3_desc *desc, struct sk_buff *skb,
4253 u32 bd_base_info)
4254 {
4255 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4256 struct hnae3_handle *h = hns3_get_handle(netdev);
4257 u32 nsec = le32_to_cpu(desc->ts_nsec);
4258 u32 sec = le32_to_cpu(desc->ts_sec);
4259
4260 if (h->ae_algo->ops->get_rx_hwts)
4261 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4262 }
4263 }
4264
hns3_handle_rx_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,struct sk_buff * skb,u32 l234info)4265 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring,
4266 struct hns3_desc *desc, struct sk_buff *skb,
4267 u32 l234info)
4268 {
4269 struct net_device *netdev = ring_to_netdev(ring);
4270
4271 /* Based on hw strategy, the tag offloaded will be stored at
4272 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4273 * in one layer tag case.
4274 */
4275 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4276 u16 vlan_tag;
4277
4278 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4279 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4280 vlan_tag);
4281 }
4282 }
4283
hns3_handle_bdinfo(struct hns3_enet_ring * ring,struct sk_buff * skb)4284 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
4285 {
4286 struct net_device *netdev = ring_to_netdev(ring);
4287 enum hns3_pkt_l2t_type l2_frame_type;
4288 u32 bd_base_info, l234info, ol_info;
4289 struct hns3_desc *desc;
4290 unsigned int len;
4291 int pre_ntc, ret;
4292 u16 csum;
4293
4294 /* bdinfo handled below is only valid on the last BD of the
4295 * current packet, and ring->next_to_clean indicates the first
4296 * descriptor of next packet, so need - 1 below.
4297 */
4298 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4299 (ring->desc_num - 1);
4300 desc = &ring->desc[pre_ntc];
4301 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4302 l234info = le32_to_cpu(desc->rx.l234_info);
4303 ol_info = le32_to_cpu(desc->rx.ol_info);
4304 csum = le16_to_cpu(desc->csum);
4305
4306 hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info);
4307
4308 hns3_handle_rx_vlan_tag(ring, desc, skb, l234info);
4309
4310 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4311 BIT(HNS3_RXD_L2E_B))))) {
4312 u64_stats_update_begin(&ring->syncp);
4313 if (l234info & BIT(HNS3_RXD_L2E_B))
4314 ring->stats.l2_err++;
4315 else
4316 ring->stats.err_pkt_len++;
4317 u64_stats_update_end(&ring->syncp);
4318
4319 return -EFAULT;
4320 }
4321
4322 len = skb->len;
4323
4324 /* Do update ip stack process */
4325 skb->protocol = eth_type_trans(skb, netdev);
4326
4327 /* This is needed in order to enable forwarding support */
4328 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
4329 bd_base_info, ol_info, csum);
4330 if (unlikely(ret)) {
4331 hns3_ring_stats_update(ring, rx_err_cnt);
4332 return ret;
4333 }
4334
4335 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4336 HNS3_RXD_DMAC_S);
4337
4338 u64_stats_update_begin(&ring->syncp);
4339 ring->stats.rx_pkts++;
4340 ring->stats.rx_bytes += len;
4341
4342 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4343 ring->stats.rx_multicast++;
4344
4345 u64_stats_update_end(&ring->syncp);
4346
4347 ring->tqp_vector->rx_group.total_bytes += len;
4348
4349 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash),
4350 l234info, ol_info);
4351 return 0;
4352 }
4353
hns3_handle_rx_bd(struct hns3_enet_ring * ring)4354 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
4355 {
4356 struct sk_buff *skb = ring->skb;
4357 struct hns3_desc_cb *desc_cb;
4358 struct hns3_desc *desc;
4359 unsigned int length;
4360 u32 bd_base_info;
4361 int ret;
4362
4363 desc = &ring->desc[ring->next_to_clean];
4364 desc_cb = &ring->desc_cb[ring->next_to_clean];
4365
4366 prefetch(desc);
4367
4368 if (!skb) {
4369 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4370 /* Check valid BD */
4371 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4372 return -ENXIO;
4373
4374 dma_rmb();
4375 length = le16_to_cpu(desc->rx.size);
4376
4377 ring->va = desc_cb->buf + desc_cb->page_offset;
4378
4379 dma_sync_single_for_cpu(ring_to_dev(ring),
4380 desc_cb->dma + desc_cb->page_offset,
4381 hns3_buf_size(ring),
4382 DMA_FROM_DEVICE);
4383
4384 /* Prefetch first cache line of first page.
4385 * Idea is to cache few bytes of the header of the packet.
4386 * Our L1 Cache line size is 64B so need to prefetch twice to make
4387 * it 128B. But in actual we can have greater size of caches with
4388 * 128B Level 1 cache lines. In such a case, single fetch would
4389 * suffice to cache in the relevant part of the header.
4390 */
4391 net_prefetch(ring->va);
4392
4393 ret = hns3_alloc_skb(ring, length, ring->va);
4394 skb = ring->skb;
4395
4396 if (ret < 0) /* alloc buffer fail */
4397 return ret;
4398 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4399 ret = hns3_add_frag(ring);
4400 if (ret)
4401 return ret;
4402 }
4403 } else {
4404 ret = hns3_add_frag(ring);
4405 if (ret)
4406 return ret;
4407 }
4408
4409 /* As the head data may be changed when GRO enable, copy
4410 * the head data in after other data rx completed
4411 */
4412 if (skb->len > HNS3_RX_HEAD_SIZE)
4413 memcpy(skb->data, ring->va,
4414 ALIGN(ring->pull_len, sizeof(long)));
4415
4416 ret = hns3_handle_bdinfo(ring, skb);
4417 if (unlikely(ret)) {
4418 dev_kfree_skb_any(skb);
4419 return ret;
4420 }
4421
4422 skb_record_rx_queue(skb, ring->tqp->tqp_index);
4423 return 0;
4424 }
4425
hns3_clean_rx_ring(struct hns3_enet_ring * ring,int budget,void (* rx_fn)(struct hns3_enet_ring *,struct sk_buff *))4426 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4427 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
4428 {
4429 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
4430 int unused_count = hns3_desc_unused(ring);
4431 bool failure = false;
4432 int recv_pkts = 0;
4433 int err;
4434
4435 unused_count -= ring->pending_buf;
4436
4437 while (recv_pkts < budget) {
4438 /* Reuse or realloc buffers */
4439 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4440 failure = failure ||
4441 hns3_nic_alloc_rx_buffers(ring, unused_count);
4442 unused_count = 0;
4443 }
4444
4445 /* Poll one pkt */
4446 err = hns3_handle_rx_bd(ring);
4447 /* Do not get FE for the packet or failed to alloc skb */
4448 if (unlikely(!ring->skb || err == -ENXIO)) {
4449 goto out;
4450 } else if (likely(!err)) {
4451 rx_fn(ring, ring->skb);
4452 recv_pkts++;
4453 }
4454
4455 unused_count += ring->pending_buf;
4456 ring->skb = NULL;
4457 ring->pending_buf = 0;
4458 }
4459
4460 out:
4461 /* sync head pointer before exiting, since hardware will calculate
4462 * FBD number with head pointer
4463 */
4464 if (unused_count > 0)
4465 failure = failure ||
4466 hns3_nic_alloc_rx_buffers(ring, unused_count);
4467
4468 return failure ? budget : recv_pkts;
4469 }
4470
hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4471 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4472 {
4473 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4474 struct dim_sample sample = {};
4475
4476 if (!rx_group->coal.adapt_enable)
4477 return;
4478
4479 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4480 rx_group->total_bytes, &sample);
4481 net_dim(&rx_group->dim, sample);
4482 }
4483
hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4484 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4485 {
4486 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
4487 struct dim_sample sample = {};
4488
4489 if (!tx_group->coal.adapt_enable)
4490 return;
4491
4492 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4493 tx_group->total_bytes, &sample);
4494 net_dim(&tx_group->dim, sample);
4495 }
4496
hns3_nic_common_poll(struct napi_struct * napi,int budget)4497 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4498 {
4499 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
4500 struct hns3_enet_ring *ring;
4501 int rx_pkt_total = 0;
4502
4503 struct hns3_enet_tqp_vector *tqp_vector =
4504 container_of(napi, struct hns3_enet_tqp_vector, napi);
4505 bool clean_complete = true;
4506 int rx_budget = budget;
4507
4508 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4509 napi_complete(napi);
4510 return 0;
4511 }
4512
4513 /* Since the actual Tx work is minimal, we can give the Tx a larger
4514 * budget and be more aggressive about cleaning up the Tx descriptors.
4515 */
4516 hns3_for_each_ring(ring, tqp_vector->tx_group)
4517 hns3_clean_tx_ring(ring, budget);
4518
4519 /* make sure rx ring budget not smaller than 1 */
4520 if (tqp_vector->num_tqps > 1)
4521 rx_budget = max(budget / tqp_vector->num_tqps, 1);
4522
4523 hns3_for_each_ring(ring, tqp_vector->rx_group) {
4524 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4525 hns3_rx_skb);
4526 if (rx_cleaned >= rx_budget)
4527 clean_complete = false;
4528
4529 rx_pkt_total += rx_cleaned;
4530 }
4531
4532 tqp_vector->rx_group.total_packets += rx_pkt_total;
4533
4534 if (!clean_complete)
4535 return budget;
4536
4537 if (napi_complete(napi) &&
4538 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4539 hns3_update_rx_int_coalesce(tqp_vector);
4540 hns3_update_tx_int_coalesce(tqp_vector);
4541
4542 hns3_mask_vector_irq(tqp_vector, 1);
4543 }
4544
4545 return rx_pkt_total;
4546 }
4547
hns3_create_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node ** head,bool is_tx)4548 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4549 struct hnae3_ring_chain_node **head,
4550 bool is_tx)
4551 {
4552 u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX;
4553 u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX;
4554 struct hnae3_ring_chain_node *cur_chain = *head;
4555 struct pci_dev *pdev = tqp_vector->handle->pdev;
4556 struct hnae3_ring_chain_node *chain;
4557 struct hns3_enet_ring *ring;
4558
4559 ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring;
4560
4561 if (cur_chain) {
4562 while (cur_chain->next)
4563 cur_chain = cur_chain->next;
4564 }
4565
4566 while (ring) {
4567 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4568 if (!chain)
4569 return -ENOMEM;
4570 if (cur_chain)
4571 cur_chain->next = chain;
4572 else
4573 *head = chain;
4574 chain->tqp_index = ring->tqp->tqp_index;
4575 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4576 bit_value);
4577 hnae3_set_field(chain->int_gl_idx,
4578 HNAE3_RING_GL_IDX_M,
4579 HNAE3_RING_GL_IDX_S, field_value);
4580
4581 cur_chain = chain;
4582
4583 ring = ring->next;
4584 }
4585
4586 return 0;
4587 }
4588
4589 static struct hnae3_ring_chain_node *
hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector)4590 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector)
4591 {
4592 struct pci_dev *pdev = tqp_vector->handle->pdev;
4593 struct hnae3_ring_chain_node *cur_chain = NULL;
4594 struct hnae3_ring_chain_node *chain;
4595
4596 if (hns3_create_ring_chain(tqp_vector, &cur_chain, true))
4597 goto err_free_chain;
4598
4599 if (hns3_create_ring_chain(tqp_vector, &cur_chain, false))
4600 goto err_free_chain;
4601
4602 return cur_chain;
4603
4604 err_free_chain:
4605 while (cur_chain) {
4606 chain = cur_chain->next;
4607 devm_kfree(&pdev->dev, cur_chain);
4608 cur_chain = chain;
4609 }
4610
4611 return NULL;
4612 }
4613
hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node * head)4614 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4615 struct hnae3_ring_chain_node *head)
4616 {
4617 struct pci_dev *pdev = tqp_vector->handle->pdev;
4618 struct hnae3_ring_chain_node *chain_tmp, *chain;
4619
4620 chain = head;
4621
4622 while (chain) {
4623 chain_tmp = chain->next;
4624 devm_kfree(&pdev->dev, chain);
4625 chain = chain_tmp;
4626 }
4627 }
4628
hns3_add_ring_to_group(struct hns3_enet_ring_group * group,struct hns3_enet_ring * ring)4629 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4630 struct hns3_enet_ring *ring)
4631 {
4632 ring->next = group->ring;
4633 group->ring = ring;
4634
4635 group->count++;
4636 }
4637
hns3_nic_set_cpumask(struct hns3_nic_priv * priv)4638 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4639 {
4640 struct pci_dev *pdev = priv->ae_handle->pdev;
4641 struct hns3_enet_tqp_vector *tqp_vector;
4642 int num_vectors = priv->vector_num;
4643 int numa_node;
4644 int vector_i;
4645
4646 numa_node = dev_to_node(&pdev->dev);
4647
4648 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4649 tqp_vector = &priv->tqp_vector[vector_i];
4650 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4651 &tqp_vector->affinity_mask);
4652 }
4653 }
4654
hns3_rx_dim_work(struct work_struct * work)4655 static void hns3_rx_dim_work(struct work_struct *work)
4656 {
4657 struct dim *dim = container_of(work, struct dim, work);
4658 struct hns3_enet_ring_group *group = container_of(dim,
4659 struct hns3_enet_ring_group, dim);
4660 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4661 struct dim_cq_moder cur_moder =
4662 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4663
4664 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4665 tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4666
4667 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4668 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4669 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4670 }
4671
4672 dim->state = DIM_START_MEASURE;
4673 }
4674
hns3_tx_dim_work(struct work_struct * work)4675 static void hns3_tx_dim_work(struct work_struct *work)
4676 {
4677 struct dim *dim = container_of(work, struct dim, work);
4678 struct hns3_enet_ring_group *group = container_of(dim,
4679 struct hns3_enet_ring_group, dim);
4680 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4681 struct dim_cq_moder cur_moder =
4682 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4683
4684 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4685 tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4686
4687 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4688 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4689 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4690 }
4691
4692 dim->state = DIM_START_MEASURE;
4693 }
4694
hns3_nic_init_dim(struct hns3_enet_tqp_vector * tqp_vector)4695 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4696 {
4697 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
4698 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
4699 }
4700
hns3_nic_init_vector_data(struct hns3_nic_priv * priv)4701 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4702 {
4703 struct hnae3_handle *h = priv->ae_handle;
4704 struct hns3_enet_tqp_vector *tqp_vector;
4705 int ret;
4706 int i;
4707
4708 hns3_nic_set_cpumask(priv);
4709
4710 for (i = 0; i < priv->vector_num; i++) {
4711 tqp_vector = &priv->tqp_vector[i];
4712 hns3_vector_coalesce_init_hw(tqp_vector, priv);
4713 tqp_vector->num_tqps = 0;
4714 hns3_nic_init_dim(tqp_vector);
4715 }
4716
4717 for (i = 0; i < h->kinfo.num_tqps; i++) {
4718 u16 vector_i = i % priv->vector_num;
4719 u16 tqp_num = h->kinfo.num_tqps;
4720
4721 tqp_vector = &priv->tqp_vector[vector_i];
4722
4723 hns3_add_ring_to_group(&tqp_vector->tx_group,
4724 &priv->ring[i]);
4725
4726 hns3_add_ring_to_group(&tqp_vector->rx_group,
4727 &priv->ring[i + tqp_num]);
4728
4729 priv->ring[i].tqp_vector = tqp_vector;
4730 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
4731 tqp_vector->num_tqps++;
4732 }
4733
4734 for (i = 0; i < priv->vector_num; i++) {
4735 struct hnae3_ring_chain_node *vector_ring_chain;
4736
4737 tqp_vector = &priv->tqp_vector[i];
4738
4739 tqp_vector->rx_group.total_bytes = 0;
4740 tqp_vector->rx_group.total_packets = 0;
4741 tqp_vector->tx_group.total_bytes = 0;
4742 tqp_vector->tx_group.total_packets = 0;
4743 tqp_vector->handle = h;
4744
4745 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4746 if (!vector_ring_chain) {
4747 ret = -ENOMEM;
4748 goto map_ring_fail;
4749 }
4750
4751 ret = h->ae_algo->ops->map_ring_to_vector(h,
4752 tqp_vector->vector_irq, vector_ring_chain);
4753
4754 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4755
4756 if (ret)
4757 goto map_ring_fail;
4758
4759 netif_napi_add(priv->netdev, &tqp_vector->napi,
4760 hns3_nic_common_poll);
4761 }
4762
4763 return 0;
4764
4765 map_ring_fail:
4766 while (i--)
4767 netif_napi_del(&priv->tqp_vector[i].napi);
4768
4769 return ret;
4770 }
4771
hns3_nic_init_coal_cfg(struct hns3_nic_priv * priv)4772 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4773 {
4774 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4775 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4776 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4777
4778 /* initialize the configuration for interrupt coalescing.
4779 * 1. GL (Interrupt Gap Limiter)
4780 * 2. RL (Interrupt Rate Limiter)
4781 * 3. QL (Interrupt Quantity Limiter)
4782 *
4783 * Default: enable interrupt coalescing self-adaptive and GL
4784 */
4785 tx_coal->adapt_enable = 1;
4786 rx_coal->adapt_enable = 1;
4787
4788 tx_coal->int_gl = HNS3_INT_GL_50K;
4789 rx_coal->int_gl = HNS3_INT_GL_50K;
4790
4791 rx_coal->flow_level = HNS3_FLOW_LOW;
4792 tx_coal->flow_level = HNS3_FLOW_LOW;
4793
4794 if (ae_dev->dev_specs.int_ql_max) {
4795 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4796 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4797 }
4798 }
4799
hns3_nic_alloc_vector_data(struct hns3_nic_priv * priv)4800 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4801 {
4802 struct hnae3_handle *h = priv->ae_handle;
4803 struct hns3_enet_tqp_vector *tqp_vector;
4804 struct hnae3_vector_info *vector;
4805 struct pci_dev *pdev = h->pdev;
4806 u16 tqp_num = h->kinfo.num_tqps;
4807 u16 vector_num;
4808 int ret = 0;
4809 u16 i;
4810
4811 /* RSS size, cpu online and vector_num should be the same */
4812 /* Should consider 2p/4p later */
4813 vector_num = min_t(u16, num_online_cpus(), tqp_num);
4814
4815 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4816 GFP_KERNEL);
4817 if (!vector)
4818 return -ENOMEM;
4819
4820 /* save the actual available vector number */
4821 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4822
4823 priv->vector_num = vector_num;
4824 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4825 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4826 GFP_KERNEL);
4827 if (!priv->tqp_vector) {
4828 ret = -ENOMEM;
4829 goto out;
4830 }
4831
4832 for (i = 0; i < priv->vector_num; i++) {
4833 tqp_vector = &priv->tqp_vector[i];
4834 tqp_vector->idx = i;
4835 tqp_vector->mask_addr = vector[i].io_addr;
4836 tqp_vector->vector_irq = vector[i].vector;
4837 hns3_vector_coalesce_init(tqp_vector, priv);
4838 }
4839
4840 out:
4841 devm_kfree(&pdev->dev, vector);
4842 return ret;
4843 }
4844
hns3_clear_ring_group(struct hns3_enet_ring_group * group)4845 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4846 {
4847 group->ring = NULL;
4848 group->count = 0;
4849 }
4850
hns3_nic_uninit_vector_data(struct hns3_nic_priv * priv)4851 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
4852 {
4853 struct hnae3_ring_chain_node *vector_ring_chain;
4854 struct hnae3_handle *h = priv->ae_handle;
4855 struct hns3_enet_tqp_vector *tqp_vector;
4856 int i;
4857
4858 for (i = 0; i < priv->vector_num; i++) {
4859 tqp_vector = &priv->tqp_vector[i];
4860
4861 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4862 continue;
4863
4864 /* Since the mapping can be overwritten, when fail to get the
4865 * chain between vector and ring, we should go on to deal with
4866 * the remaining options.
4867 */
4868 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4869 if (!vector_ring_chain)
4870 dev_warn(priv->dev, "failed to get ring chain\n");
4871
4872 h->ae_algo->ops->unmap_ring_from_vector(h,
4873 tqp_vector->vector_irq, vector_ring_chain);
4874
4875 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4876
4877 hns3_clear_ring_group(&tqp_vector->rx_group);
4878 hns3_clear_ring_group(&tqp_vector->tx_group);
4879 netif_napi_del(&priv->tqp_vector[i].napi);
4880 }
4881 }
4882
hns3_nic_dealloc_vector_data(struct hns3_nic_priv * priv)4883 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
4884 {
4885 struct hnae3_handle *h = priv->ae_handle;
4886 struct pci_dev *pdev = h->pdev;
4887 int i, ret;
4888
4889 for (i = 0; i < priv->vector_num; i++) {
4890 struct hns3_enet_tqp_vector *tqp_vector;
4891
4892 tqp_vector = &priv->tqp_vector[i];
4893 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4894 if (ret)
4895 return;
4896 }
4897
4898 devm_kfree(&pdev->dev, priv->tqp_vector);
4899 }
4900
hns3_update_tx_spare_buf_config(struct hns3_nic_priv * priv)4901 static void hns3_update_tx_spare_buf_config(struct hns3_nic_priv *priv)
4902 {
4903 #define HNS3_MIN_SPARE_BUF_SIZE (2 * 1024 * 1024)
4904 #define HNS3_MAX_PACKET_SIZE (64 * 1024)
4905
4906 struct iommu_domain *domain = iommu_get_domain_for_dev(priv->dev);
4907 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
4908 struct hnae3_handle *handle = priv->ae_handle;
4909
4910 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3)
4911 return;
4912
4913 if (!(domain && iommu_is_dma_domain(domain)))
4914 return;
4915
4916 priv->min_tx_copybreak = HNS3_MAX_PACKET_SIZE;
4917 priv->min_tx_spare_buf_size = HNS3_MIN_SPARE_BUF_SIZE;
4918
4919 if (priv->tx_copybreak < priv->min_tx_copybreak)
4920 priv->tx_copybreak = priv->min_tx_copybreak;
4921 if (handle->kinfo.tx_spare_buf_size < priv->min_tx_spare_buf_size)
4922 handle->kinfo.tx_spare_buf_size = priv->min_tx_spare_buf_size;
4923 }
4924
hns3_ring_get_cfg(struct hnae3_queue * q,struct hns3_nic_priv * priv,unsigned int ring_type)4925 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4926 unsigned int ring_type)
4927 {
4928 int queue_num = priv->ae_handle->kinfo.num_tqps;
4929 struct hns3_enet_ring *ring;
4930 int desc_num;
4931
4932 if (ring_type == HNAE3_RING_TYPE_TX) {
4933 ring = &priv->ring[q->tqp_index];
4934 desc_num = priv->ae_handle->kinfo.num_tx_desc;
4935 ring->queue_index = q->tqp_index;
4936 ring->tx_copybreak = priv->tx_copybreak;
4937 ring->last_to_use = 0;
4938 } else {
4939 ring = &priv->ring[q->tqp_index + queue_num];
4940 desc_num = priv->ae_handle->kinfo.num_rx_desc;
4941 ring->queue_index = q->tqp_index;
4942 ring->rx_copybreak = priv->rx_copybreak;
4943 }
4944
4945 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
4946
4947 ring->tqp = q;
4948 ring->desc = NULL;
4949 ring->desc_cb = NULL;
4950 ring->dev = priv->dev;
4951 ring->desc_dma_addr = 0;
4952 ring->buf_size = q->buf_size;
4953 ring->desc_num = desc_num;
4954 ring->next_to_use = 0;
4955 ring->next_to_clean = 0;
4956 }
4957
hns3_queue_to_ring(struct hnae3_queue * tqp,struct hns3_nic_priv * priv)4958 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4959 struct hns3_nic_priv *priv)
4960 {
4961 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4962 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
4963 }
4964
hns3_get_ring_config(struct hns3_nic_priv * priv)4965 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4966 {
4967 struct hnae3_handle *h = priv->ae_handle;
4968 struct pci_dev *pdev = h->pdev;
4969 int i;
4970
4971 priv->ring = devm_kzalloc(&pdev->dev,
4972 array3_size(h->kinfo.num_tqps,
4973 sizeof(*priv->ring), 2),
4974 GFP_KERNEL);
4975 if (!priv->ring)
4976 return -ENOMEM;
4977
4978 for (i = 0; i < h->kinfo.num_tqps; i++)
4979 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
4980
4981 return 0;
4982 }
4983
hns3_put_ring_config(struct hns3_nic_priv * priv)4984 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4985 {
4986 if (!priv->ring)
4987 return;
4988
4989 devm_kfree(priv->dev, priv->ring);
4990 priv->ring = NULL;
4991 }
4992
hns3_alloc_page_pool(struct hns3_enet_ring * ring)4993 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
4994 {
4995 struct page_pool_params pp_params = {
4996 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
4997 .order = hns3_page_order(ring),
4998 .pool_size = ring->desc_num * hns3_buf_size(ring) /
4999 (PAGE_SIZE << hns3_page_order(ring)),
5000 .nid = dev_to_node(ring_to_dev(ring)),
5001 .dev = ring_to_dev(ring),
5002 .dma_dir = DMA_FROM_DEVICE,
5003 .offset = 0,
5004 .max_len = PAGE_SIZE << hns3_page_order(ring),
5005 };
5006
5007 ring->page_pool = page_pool_create(&pp_params);
5008 if (IS_ERR(ring->page_pool)) {
5009 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
5010 PTR_ERR(ring->page_pool));
5011 ring->page_pool = NULL;
5012 }
5013 }
5014
hns3_alloc_ring_memory(struct hns3_enet_ring * ring)5015 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
5016 {
5017 int ret;
5018
5019 if (ring->desc_num <= 0 || ring->buf_size <= 0)
5020 return -EINVAL;
5021
5022 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
5023 sizeof(ring->desc_cb[0]), GFP_KERNEL);
5024 if (!ring->desc_cb) {
5025 ret = -ENOMEM;
5026 goto out;
5027 }
5028
5029 ret = hns3_alloc_desc(ring);
5030 if (ret)
5031 goto out_with_desc_cb;
5032
5033 if (!HNAE3_IS_TX_RING(ring)) {
5034 if (page_pool_enabled)
5035 hns3_alloc_page_pool(ring);
5036
5037 ret = hns3_alloc_ring_buffers(ring);
5038 if (ret)
5039 goto out_with_desc;
5040 } else {
5041 hns3_init_tx_spare_buffer(ring);
5042 }
5043
5044 return 0;
5045
5046 out_with_desc:
5047 hns3_free_desc(ring);
5048 out_with_desc_cb:
5049 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5050 ring->desc_cb = NULL;
5051 out:
5052 return ret;
5053 }
5054
hns3_fini_ring(struct hns3_enet_ring * ring)5055 void hns3_fini_ring(struct hns3_enet_ring *ring)
5056 {
5057 hns3_free_desc(ring);
5058 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5059 ring->desc_cb = NULL;
5060 ring->next_to_clean = 0;
5061 ring->next_to_use = 0;
5062 ring->last_to_use = 0;
5063 ring->pending_buf = 0;
5064 if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
5065 dev_kfree_skb_any(ring->skb);
5066 ring->skb = NULL;
5067 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
5068 struct hns3_tx_spare *tx_spare = ring->tx_spare;
5069
5070 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
5071 DMA_TO_DEVICE);
5072 free_pages((unsigned long)tx_spare->buf,
5073 get_order(tx_spare->len));
5074 devm_kfree(ring_to_dev(ring), tx_spare);
5075 ring->tx_spare = NULL;
5076 }
5077
5078 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
5079 page_pool_destroy(ring->page_pool);
5080 ring->page_pool = NULL;
5081 }
5082 }
5083
hns3_buf_size2type(u32 buf_size)5084 static int hns3_buf_size2type(u32 buf_size)
5085 {
5086 int bd_size_type;
5087
5088 switch (buf_size) {
5089 case 512:
5090 bd_size_type = HNS3_BD_SIZE_512_TYPE;
5091 break;
5092 case 1024:
5093 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
5094 break;
5095 case 2048:
5096 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5097 break;
5098 case 4096:
5099 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
5100 break;
5101 default:
5102 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5103 }
5104
5105 return bd_size_type;
5106 }
5107
hns3_init_ring_hw(struct hns3_enet_ring * ring)5108 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
5109 {
5110 dma_addr_t dma = ring->desc_dma_addr;
5111 struct hnae3_queue *q = ring->tqp;
5112
5113 if (!HNAE3_IS_TX_RING(ring)) {
5114 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
5115 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
5116 (u32)((dma >> 31) >> 1));
5117
5118 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
5119 hns3_buf_size2type(ring->buf_size));
5120 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
5121 ring->desc_num / 8 - 1);
5122 } else {
5123 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
5124 (u32)dma);
5125 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
5126 (u32)((dma >> 31) >> 1));
5127
5128 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
5129 ring->desc_num / 8 - 1);
5130 }
5131 }
5132
hns3_init_tx_ring_tc(struct hns3_nic_priv * priv)5133 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
5134 {
5135 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5136 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5137 int i;
5138
5139 for (i = 0; i < tc_info->num_tc; i++) {
5140 int j;
5141
5142 for (j = 0; j < tc_info->tqp_count[i]; j++) {
5143 struct hnae3_queue *q;
5144
5145 q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
5146 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
5147 }
5148 }
5149 }
5150
hns3_init_all_ring(struct hns3_nic_priv * priv)5151 int hns3_init_all_ring(struct hns3_nic_priv *priv)
5152 {
5153 struct hnae3_handle *h = priv->ae_handle;
5154 int ring_num = h->kinfo.num_tqps * 2;
5155 int i, j;
5156 int ret;
5157
5158 hns3_update_tx_spare_buf_config(priv);
5159 for (i = 0; i < ring_num; i++) {
5160 ret = hns3_alloc_ring_memory(&priv->ring[i]);
5161 if (ret) {
5162 dev_err(priv->dev,
5163 "Alloc ring memory fail! ret=%d\n", ret);
5164 goto out_when_alloc_ring_memory;
5165 }
5166
5167 u64_stats_init(&priv->ring[i].syncp);
5168 cond_resched();
5169 }
5170
5171 return 0;
5172
5173 out_when_alloc_ring_memory:
5174 for (j = i - 1; j >= 0; j--)
5175 hns3_fini_ring(&priv->ring[j]);
5176
5177 return -ENOMEM;
5178 }
5179
hns3_uninit_all_ring(struct hns3_nic_priv * priv)5180 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
5181 {
5182 struct hnae3_handle *h = priv->ae_handle;
5183 int i;
5184
5185 for (i = 0; i < h->kinfo.num_tqps; i++) {
5186 hns3_fini_ring(&priv->ring[i]);
5187 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
5188 }
5189 }
5190
5191 /* Set mac addr if it is configured. or leave it to the AE driver */
hns3_init_mac_addr(struct net_device * netdev)5192 static int hns3_init_mac_addr(struct net_device *netdev)
5193 {
5194 struct hns3_nic_priv *priv = netdev_priv(netdev);
5195 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5196 struct hnae3_handle *h = priv->ae_handle;
5197 u8 mac_addr_temp[ETH_ALEN] = {0};
5198 int ret = 0;
5199
5200 if (h->ae_algo->ops->get_mac_addr)
5201 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
5202
5203 /* Check if the MAC address is valid, if not get a random one */
5204 if (!is_valid_ether_addr(mac_addr_temp)) {
5205 eth_hw_addr_random(netdev);
5206 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr);
5207 dev_warn(priv->dev, "using random MAC address %s\n",
5208 format_mac_addr);
5209 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
5210 eth_hw_addr_set(netdev, mac_addr_temp);
5211 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
5212 } else {
5213 return 0;
5214 }
5215
5216 if (h->ae_algo->ops->set_mac_addr)
5217 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
5218
5219 return ret;
5220 }
5221
hns3_init_phy(struct net_device * netdev)5222 static int hns3_init_phy(struct net_device *netdev)
5223 {
5224 struct hnae3_handle *h = hns3_get_handle(netdev);
5225 int ret = 0;
5226
5227 if (h->ae_algo->ops->mac_connect_phy)
5228 ret = h->ae_algo->ops->mac_connect_phy(h);
5229
5230 return ret;
5231 }
5232
hns3_uninit_phy(struct net_device * netdev)5233 static void hns3_uninit_phy(struct net_device *netdev)
5234 {
5235 struct hnae3_handle *h = hns3_get_handle(netdev);
5236
5237 if (h->ae_algo->ops->mac_disconnect_phy)
5238 h->ae_algo->ops->mac_disconnect_phy(h);
5239 }
5240
hns3_client_start(struct hnae3_handle * handle)5241 static int hns3_client_start(struct hnae3_handle *handle)
5242 {
5243 if (!handle->ae_algo->ops->client_start)
5244 return 0;
5245
5246 return handle->ae_algo->ops->client_start(handle);
5247 }
5248
hns3_client_stop(struct hnae3_handle * handle)5249 static void hns3_client_stop(struct hnae3_handle *handle)
5250 {
5251 if (!handle->ae_algo->ops->client_stop)
5252 return;
5253
5254 handle->ae_algo->ops->client_stop(handle);
5255 }
5256
hns3_info_show(struct hns3_nic_priv * priv)5257 static void hns3_info_show(struct hns3_nic_priv *priv)
5258 {
5259 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5260 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5261
5262 hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr);
5263 dev_info(priv->dev, "MAC address: %s\n", format_mac_addr);
5264 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
5265 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
5266 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
5267 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
5268 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
5269 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
5270 dev_info(priv->dev, "Total number of enabled TCs: %u\n",
5271 kinfo->tc_info.num_tc);
5272 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
5273 }
5274
hns3_set_cq_period_mode(struct hns3_nic_priv * priv,enum dim_cq_period_mode mode,bool is_tx)5275 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
5276 enum dim_cq_period_mode mode, bool is_tx)
5277 {
5278 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
5279 struct hnae3_handle *handle = priv->ae_handle;
5280 int i;
5281
5282 if (is_tx) {
5283 priv->tx_cqe_mode = mode;
5284
5285 for (i = 0; i < priv->vector_num; i++)
5286 priv->tqp_vector[i].tx_group.dim.mode = mode;
5287 } else {
5288 priv->rx_cqe_mode = mode;
5289
5290 for (i = 0; i < priv->vector_num; i++)
5291 priv->tqp_vector[i].rx_group.dim.mode = mode;
5292 }
5293
5294 if (hnae3_ae_dev_cq_supported(ae_dev)) {
5295 u32 new_mode;
5296 u64 reg;
5297
5298 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5299 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5300 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5301
5302 writel(new_mode, handle->kinfo.io_base + reg);
5303 }
5304 }
5305
hns3_cq_period_mode_init(struct hns3_nic_priv * priv,enum dim_cq_period_mode tx_mode,enum dim_cq_period_mode rx_mode)5306 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5307 enum dim_cq_period_mode tx_mode,
5308 enum dim_cq_period_mode rx_mode)
5309 {
5310 hns3_set_cq_period_mode(priv, tx_mode, true);
5311 hns3_set_cq_period_mode(priv, rx_mode, false);
5312 }
5313
hns3_state_init(struct hnae3_handle * handle)5314 static void hns3_state_init(struct hnae3_handle *handle)
5315 {
5316 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
5317 struct net_device *netdev = handle->kinfo.netdev;
5318 struct hns3_nic_priv *priv = netdev_priv(netdev);
5319
5320 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5321
5322 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
5323 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state);
5324
5325 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5326 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5327
5328 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5329 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5330
5331 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5332 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5333 }
5334
hns3_state_uninit(struct hnae3_handle * handle)5335 static void hns3_state_uninit(struct hnae3_handle *handle)
5336 {
5337 struct hns3_nic_priv *priv = handle->priv;
5338
5339 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
5340 }
5341
hns3_client_init(struct hnae3_handle * handle)5342 static int hns3_client_init(struct hnae3_handle *handle)
5343 {
5344 struct pci_dev *pdev = handle->pdev;
5345 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5346 u16 alloc_tqps, max_rss_size;
5347 struct hns3_nic_priv *priv;
5348 struct net_device *netdev;
5349 int ret;
5350
5351 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5352 &max_rss_size);
5353 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
5354 if (!netdev)
5355 return -ENOMEM;
5356
5357 priv = netdev_priv(netdev);
5358 priv->dev = &pdev->dev;
5359 priv->netdev = netdev;
5360 priv->ae_handle = handle;
5361 priv->tx_timeout_count = 0;
5362 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
5363 priv->min_tx_copybreak = 0;
5364 priv->min_tx_spare_buf_size = 0;
5365 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5366
5367 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5368
5369 handle->kinfo.netdev = netdev;
5370 handle->priv = (void *)priv;
5371
5372 hns3_init_mac_addr(netdev);
5373
5374 hns3_set_default_feature(netdev);
5375
5376 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5377 netdev->priv_flags |= IFF_UNICAST_FLT;
5378 netdev->netdev_ops = &hns3_nic_netdev_ops;
5379 SET_NETDEV_DEV(netdev, &pdev->dev);
5380 hns3_ethtool_set_ops(netdev);
5381
5382 /* Carrier off reporting is important to ethtool even BEFORE open */
5383 netif_carrier_off(netdev);
5384
5385 ret = hns3_get_ring_config(priv);
5386 if (ret) {
5387 ret = -ENOMEM;
5388 goto out_get_ring_cfg;
5389 }
5390
5391 hns3_nic_init_coal_cfg(priv);
5392
5393 ret = hns3_nic_alloc_vector_data(priv);
5394 if (ret) {
5395 ret = -ENOMEM;
5396 goto out_alloc_vector_data;
5397 }
5398
5399 ret = hns3_nic_init_vector_data(priv);
5400 if (ret) {
5401 ret = -ENOMEM;
5402 goto out_init_vector_data;
5403 }
5404
5405 ret = hns3_init_all_ring(priv);
5406 if (ret) {
5407 ret = -ENOMEM;
5408 goto out_init_ring;
5409 }
5410
5411 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5412 DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5413
5414 ret = hns3_init_phy(netdev);
5415 if (ret)
5416 goto out_init_phy;
5417
5418 /* the device can work without cpu rmap, only aRFS needs it */
5419 ret = hns3_set_rx_cpu_rmap(netdev);
5420 if (ret)
5421 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5422
5423 ret = hns3_nic_init_irq(priv);
5424 if (ret) {
5425 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5426 hns3_free_rx_cpu_rmap(netdev);
5427 goto out_init_irq_fail;
5428 }
5429
5430 ret = hns3_client_start(handle);
5431 if (ret) {
5432 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5433 goto out_client_start;
5434 }
5435
5436 hns3_dcbnl_setup(handle);
5437
5438 ret = hns3_dbg_init(handle);
5439 if (ret) {
5440 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5441 ret);
5442 goto out_client_start;
5443 }
5444
5445 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
5446
5447 hns3_state_init(handle);
5448
5449 ret = register_netdev(netdev);
5450 if (ret) {
5451 dev_err(priv->dev, "probe register netdev fail!\n");
5452 goto out_reg_netdev_fail;
5453 }
5454
5455 if (netif_msg_drv(handle))
5456 hns3_info_show(priv);
5457
5458 return ret;
5459
5460 out_reg_netdev_fail:
5461 hns3_state_uninit(handle);
5462 hns3_dbg_uninit(handle);
5463 hns3_client_stop(handle);
5464 out_client_start:
5465 hns3_free_rx_cpu_rmap(netdev);
5466 hns3_nic_uninit_irq(priv);
5467 out_init_irq_fail:
5468 hns3_uninit_phy(netdev);
5469 out_init_phy:
5470 hns3_uninit_all_ring(priv);
5471 out_init_ring:
5472 hns3_nic_uninit_vector_data(priv);
5473 out_init_vector_data:
5474 hns3_nic_dealloc_vector_data(priv);
5475 out_alloc_vector_data:
5476 priv->ring = NULL;
5477 out_get_ring_cfg:
5478 priv->ae_handle = NULL;
5479 free_netdev(netdev);
5480 return ret;
5481 }
5482
hns3_client_uninit(struct hnae3_handle * handle,bool reset)5483 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5484 {
5485 struct net_device *netdev = handle->kinfo.netdev;
5486 struct hns3_nic_priv *priv = netdev_priv(netdev);
5487
5488 if (netdev->reg_state != NETREG_UNINITIALIZED)
5489 unregister_netdev(netdev);
5490
5491 hns3_client_stop(handle);
5492
5493 hns3_uninit_phy(netdev);
5494
5495 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5496 netdev_warn(netdev, "already uninitialized\n");
5497 goto out_netdev_free;
5498 }
5499
5500 hns3_free_rx_cpu_rmap(netdev);
5501
5502 hns3_nic_uninit_irq(priv);
5503
5504 hns3_clear_all_ring(handle, true);
5505
5506 hns3_nic_uninit_vector_data(priv);
5507
5508 hns3_nic_dealloc_vector_data(priv);
5509
5510 hns3_uninit_all_ring(priv);
5511
5512 hns3_put_ring_config(priv);
5513
5514 out_netdev_free:
5515 hns3_dbg_uninit(handle);
5516 free_netdev(netdev);
5517 }
5518
hns3_link_status_change(struct hnae3_handle * handle,bool linkup)5519 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5520 {
5521 struct net_device *netdev = handle->kinfo.netdev;
5522
5523 if (!netdev)
5524 return;
5525
5526 if (linkup) {
5527 netif_tx_wake_all_queues(netdev);
5528 netif_carrier_on(netdev);
5529 if (netif_msg_link(handle))
5530 netdev_info(netdev, "link up\n");
5531 } else {
5532 netif_carrier_off(netdev);
5533 netif_tx_stop_all_queues(netdev);
5534 if (netif_msg_link(handle))
5535 netdev_info(netdev, "link down\n");
5536 }
5537 }
5538
hns3_clear_tx_ring(struct hns3_enet_ring * ring)5539 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
5540 {
5541 while (ring->next_to_clean != ring->next_to_use) {
5542 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
5543 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
5544 ring_ptr_move_fw(ring, next_to_clean);
5545 }
5546
5547 ring->pending_buf = 0;
5548 }
5549
hns3_clear_rx_ring(struct hns3_enet_ring * ring)5550 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5551 {
5552 struct hns3_desc_cb res_cbs;
5553 int ret;
5554
5555 while (ring->next_to_use != ring->next_to_clean) {
5556 /* When a buffer is not reused, it's memory has been
5557 * freed in hns3_handle_rx_bd or will be freed by
5558 * stack, so we need to replace the buffer here.
5559 */
5560 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5561 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
5562 if (ret) {
5563 hns3_ring_stats_update(ring, sw_err_cnt);
5564 /* if alloc new buffer fail, exit directly
5565 * and reclear in up flow.
5566 */
5567 netdev_warn(ring_to_netdev(ring),
5568 "reserve buffer map failed, ret = %d\n",
5569 ret);
5570 return ret;
5571 }
5572 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
5573 }
5574 ring_ptr_move_fw(ring, next_to_use);
5575 }
5576
5577 /* Free the pending skb in rx ring */
5578 if (ring->skb) {
5579 dev_kfree_skb_any(ring->skb);
5580 ring->skb = NULL;
5581 ring->pending_buf = 0;
5582 }
5583
5584 return 0;
5585 }
5586
hns3_force_clear_rx_ring(struct hns3_enet_ring * ring)5587 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
5588 {
5589 while (ring->next_to_use != ring->next_to_clean) {
5590 /* When a buffer is not reused, it's memory has been
5591 * freed in hns3_handle_rx_bd or will be freed by
5592 * stack, so only need to unmap the buffer here.
5593 */
5594 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5595 hns3_unmap_buffer(ring,
5596 &ring->desc_cb[ring->next_to_use]);
5597 ring->desc_cb[ring->next_to_use].dma = 0;
5598 }
5599
5600 ring_ptr_move_fw(ring, next_to_use);
5601 }
5602 }
5603
hns3_clear_all_ring(struct hnae3_handle * h,bool force)5604 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
5605 {
5606 struct net_device *ndev = h->kinfo.netdev;
5607 struct hns3_nic_priv *priv = netdev_priv(ndev);
5608 u32 i;
5609
5610 for (i = 0; i < h->kinfo.num_tqps; i++) {
5611 struct hns3_enet_ring *ring;
5612
5613 ring = &priv->ring[i];
5614 hns3_clear_tx_ring(ring);
5615
5616 ring = &priv->ring[i + h->kinfo.num_tqps];
5617 /* Continue to clear other rings even if clearing some
5618 * rings failed.
5619 */
5620 if (force)
5621 hns3_force_clear_rx_ring(ring);
5622 else
5623 hns3_clear_rx_ring(ring);
5624 }
5625 }
5626
hns3_nic_reset_all_ring(struct hnae3_handle * h)5627 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5628 {
5629 struct net_device *ndev = h->kinfo.netdev;
5630 struct hns3_nic_priv *priv = netdev_priv(ndev);
5631 struct hns3_enet_ring *rx_ring;
5632 int i, j;
5633 int ret;
5634
5635 ret = h->ae_algo->ops->reset_queue(h);
5636 if (ret)
5637 return ret;
5638
5639 for (i = 0; i < h->kinfo.num_tqps; i++) {
5640 hns3_init_ring_hw(&priv->ring[i]);
5641
5642 /* We need to clear tx ring here because self test will
5643 * use the ring and will not run down before up
5644 */
5645 hns3_clear_tx_ring(&priv->ring[i]);
5646 priv->ring[i].next_to_clean = 0;
5647 priv->ring[i].next_to_use = 0;
5648 priv->ring[i].last_to_use = 0;
5649
5650 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
5651 hns3_init_ring_hw(rx_ring);
5652 ret = hns3_clear_rx_ring(rx_ring);
5653 if (ret)
5654 return ret;
5655
5656 /* We can not know the hardware head and tail when this
5657 * function is called in reset flow, so we reuse all desc.
5658 */
5659 for (j = 0; j < rx_ring->desc_num; j++)
5660 hns3_reuse_buffer(rx_ring, j);
5661
5662 rx_ring->next_to_clean = 0;
5663 rx_ring->next_to_use = 0;
5664 }
5665
5666 hns3_init_tx_ring_tc(priv);
5667
5668 return 0;
5669 }
5670
hns3_reset_notify_down_enet(struct hnae3_handle * handle)5671 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5672 {
5673 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5674 struct net_device *ndev = kinfo->netdev;
5675 struct hns3_nic_priv *priv = netdev_priv(ndev);
5676
5677 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5678 return 0;
5679
5680 if (!netif_running(ndev))
5681 return 0;
5682
5683 return hns3_nic_net_stop(ndev);
5684 }
5685
hns3_reset_notify_up_enet(struct hnae3_handle * handle)5686 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5687 {
5688 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5689 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
5690 int ret = 0;
5691
5692 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5693 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5694 return -EFAULT;
5695 }
5696
5697 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5698
5699 if (netif_running(kinfo->netdev)) {
5700 ret = hns3_nic_net_open(kinfo->netdev);
5701 if (ret) {
5702 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5703 netdev_err(kinfo->netdev,
5704 "net up fail, ret=%d!\n", ret);
5705 return ret;
5706 }
5707 }
5708
5709 return ret;
5710 }
5711
hns3_reset_notify_init_enet(struct hnae3_handle * handle)5712 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5713 {
5714 struct net_device *netdev = handle->kinfo.netdev;
5715 struct hns3_nic_priv *priv = netdev_priv(netdev);
5716 int ret;
5717
5718 /* Carrier off reporting is important to ethtool even BEFORE open */
5719 netif_carrier_off(netdev);
5720
5721 ret = hns3_get_ring_config(priv);
5722 if (ret)
5723 return ret;
5724
5725 ret = hns3_nic_alloc_vector_data(priv);
5726 if (ret)
5727 goto err_put_ring;
5728
5729 ret = hns3_nic_init_vector_data(priv);
5730 if (ret)
5731 goto err_dealloc_vector;
5732
5733 ret = hns3_init_all_ring(priv);
5734 if (ret)
5735 goto err_uninit_vector;
5736
5737 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5738
5739 /* the device can work without cpu rmap, only aRFS needs it */
5740 ret = hns3_set_rx_cpu_rmap(netdev);
5741 if (ret)
5742 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5743
5744 ret = hns3_nic_init_irq(priv);
5745 if (ret) {
5746 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5747 hns3_free_rx_cpu_rmap(netdev);
5748 goto err_init_irq_fail;
5749 }
5750
5751 if (!hns3_is_phys_func(handle->pdev))
5752 hns3_init_mac_addr(netdev);
5753
5754 ret = hns3_client_start(handle);
5755 if (ret) {
5756 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5757 goto err_client_start_fail;
5758 }
5759
5760 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5761
5762 return ret;
5763
5764 err_client_start_fail:
5765 hns3_free_rx_cpu_rmap(netdev);
5766 hns3_nic_uninit_irq(priv);
5767 err_init_irq_fail:
5768 hns3_uninit_all_ring(priv);
5769 err_uninit_vector:
5770 hns3_nic_uninit_vector_data(priv);
5771 err_dealloc_vector:
5772 hns3_nic_dealloc_vector_data(priv);
5773 err_put_ring:
5774 hns3_put_ring_config(priv);
5775
5776 return ret;
5777 }
5778
hns3_reset_notify_uninit_enet(struct hnae3_handle * handle)5779 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5780 {
5781 struct net_device *netdev = handle->kinfo.netdev;
5782 struct hns3_nic_priv *priv = netdev_priv(netdev);
5783
5784 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5785 hns3_nic_net_stop(netdev);
5786
5787 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5788 netdev_warn(netdev, "already uninitialized\n");
5789 return 0;
5790 }
5791
5792 hns3_free_rx_cpu_rmap(netdev);
5793 hns3_nic_uninit_irq(priv);
5794 hns3_clear_all_ring(handle, true);
5795 hns3_reset_tx_queue(priv->ae_handle);
5796
5797 hns3_nic_uninit_vector_data(priv);
5798
5799 hns3_nic_dealloc_vector_data(priv);
5800
5801 hns3_uninit_all_ring(priv);
5802
5803 hns3_put_ring_config(priv);
5804
5805 return 0;
5806 }
5807
hns3_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)5808 int hns3_reset_notify(struct hnae3_handle *handle,
5809 enum hnae3_reset_notify_type type)
5810 {
5811 int ret = 0;
5812
5813 switch (type) {
5814 case HNAE3_UP_CLIENT:
5815 ret = hns3_reset_notify_up_enet(handle);
5816 break;
5817 case HNAE3_DOWN_CLIENT:
5818 ret = hns3_reset_notify_down_enet(handle);
5819 break;
5820 case HNAE3_INIT_CLIENT:
5821 ret = hns3_reset_notify_init_enet(handle);
5822 break;
5823 case HNAE3_UNINIT_CLIENT:
5824 ret = hns3_reset_notify_uninit_enet(handle);
5825 break;
5826 default:
5827 break;
5828 }
5829
5830 return ret;
5831 }
5832
hns3_change_channels(struct hnae3_handle * handle,u32 new_tqp_num,bool rxfh_configured)5833 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5834 bool rxfh_configured)
5835 {
5836 int ret;
5837
5838 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5839 rxfh_configured);
5840 if (ret) {
5841 dev_err(&handle->pdev->dev,
5842 "Change tqp num(%u) fail.\n", new_tqp_num);
5843 return ret;
5844 }
5845
5846 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5847 if (ret)
5848 return ret;
5849
5850 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5851 if (ret)
5852 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5853
5854 return ret;
5855 }
5856
hns3_set_channels(struct net_device * netdev,struct ethtool_channels * ch)5857 int hns3_set_channels(struct net_device *netdev,
5858 struct ethtool_channels *ch)
5859 {
5860 struct hnae3_handle *h = hns3_get_handle(netdev);
5861 struct hnae3_knic_private_info *kinfo = &h->kinfo;
5862 bool rxfh_configured = netif_is_rxfh_configured(netdev);
5863 u32 new_tqp_num = ch->combined_count;
5864 u16 org_tqp_num;
5865 int ret;
5866
5867 if (hns3_nic_resetting(netdev))
5868 return -EBUSY;
5869
5870 if (ch->rx_count || ch->tx_count)
5871 return -EINVAL;
5872
5873 if (kinfo->tc_info.mqprio_active) {
5874 dev_err(&netdev->dev,
5875 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5876 return -EINVAL;
5877 }
5878
5879 if (new_tqp_num > hns3_get_max_available_channels(h) ||
5880 new_tqp_num < 1) {
5881 dev_err(&netdev->dev,
5882 "Change tqps fail, the tqp range is from 1 to %u",
5883 hns3_get_max_available_channels(h));
5884 return -EINVAL;
5885 }
5886
5887 if (kinfo->rss_size == new_tqp_num)
5888 return 0;
5889
5890 netif_dbg(h, drv, netdev,
5891 "set channels: tqp_num=%u, rxfh=%d\n",
5892 new_tqp_num, rxfh_configured);
5893
5894 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5895 if (ret)
5896 return ret;
5897
5898 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5899 if (ret)
5900 return ret;
5901
5902 org_tqp_num = h->kinfo.num_tqps;
5903 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
5904 if (ret) {
5905 int ret1;
5906
5907 netdev_warn(netdev,
5908 "Change channels fail, revert to old value\n");
5909 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5910 if (ret1) {
5911 netdev_err(netdev,
5912 "revert to old channel fail\n");
5913 return ret1;
5914 }
5915
5916 return ret;
5917 }
5918
5919 return 0;
5920 }
5921
hns3_external_lb_prepare(struct net_device * ndev,bool if_running)5922 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running)
5923 {
5924 struct hns3_nic_priv *priv = netdev_priv(ndev);
5925 struct hnae3_handle *h = priv->ae_handle;
5926 int i;
5927
5928 if (!if_running)
5929 return;
5930
5931 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5932 return;
5933
5934 netif_carrier_off(ndev);
5935 netif_tx_disable(ndev);
5936
5937 for (i = 0; i < priv->vector_num; i++)
5938 hns3_vector_disable(&priv->tqp_vector[i]);
5939
5940 for (i = 0; i < h->kinfo.num_tqps; i++)
5941 hns3_tqp_disable(h->kinfo.tqp[i]);
5942
5943 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
5944 * during reset process, because driver may not be able
5945 * to disable the ring through firmware when downing the netdev.
5946 */
5947 if (!hns3_nic_resetting(ndev))
5948 hns3_nic_reset_all_ring(priv->ae_handle);
5949
5950 hns3_reset_tx_queue(priv->ae_handle);
5951 }
5952
hns3_external_lb_restore(struct net_device * ndev,bool if_running)5953 void hns3_external_lb_restore(struct net_device *ndev, bool if_running)
5954 {
5955 struct hns3_nic_priv *priv = netdev_priv(ndev);
5956 struct hnae3_handle *h = priv->ae_handle;
5957 int i;
5958
5959 if (!if_running)
5960 return;
5961
5962 if (hns3_nic_resetting(ndev))
5963 return;
5964
5965 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5966 return;
5967
5968 if (hns3_nic_reset_all_ring(priv->ae_handle))
5969 return;
5970
5971 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5972
5973 for (i = 0; i < priv->vector_num; i++)
5974 hns3_vector_enable(&priv->tqp_vector[i]);
5975
5976 for (i = 0; i < h->kinfo.num_tqps; i++)
5977 hns3_tqp_enable(h->kinfo.tqp[i]);
5978
5979 netif_tx_wake_all_queues(ndev);
5980
5981 if (h->ae_algo->ops->get_status(h))
5982 netif_carrier_on(ndev);
5983 }
5984
5985 static const struct hns3_hw_error_info hns3_hw_err[] = {
5986 { .type = HNAE3_PPU_POISON_ERROR,
5987 .msg = "PPU poison" },
5988 { .type = HNAE3_CMDQ_ECC_ERROR,
5989 .msg = "IMP CMDQ error" },
5990 { .type = HNAE3_IMP_RD_POISON_ERROR,
5991 .msg = "IMP RD poison" },
5992 { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5993 .msg = "ROCEE AXI RESP error" },
5994 };
5995
hns3_process_hw_error(struct hnae3_handle * handle,enum hnae3_hw_error_type type)5996 static void hns3_process_hw_error(struct hnae3_handle *handle,
5997 enum hnae3_hw_error_type type)
5998 {
5999 int i;
6000
6001 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
6002 if (hns3_hw_err[i].type == type) {
6003 dev_err(&handle->pdev->dev, "Detected %s!\n",
6004 hns3_hw_err[i].msg);
6005 break;
6006 }
6007 }
6008 }
6009
6010 static const struct hnae3_client_ops client_ops = {
6011 .init_instance = hns3_client_init,
6012 .uninit_instance = hns3_client_uninit,
6013 .link_status_change = hns3_link_status_change,
6014 .reset_notify = hns3_reset_notify,
6015 .process_hw_error = hns3_process_hw_error,
6016 };
6017
6018 /* hns3_init_module - Driver registration routine
6019 * hns3_init_module is the first routine called when the driver is
6020 * loaded. All it does is register with the PCI subsystem.
6021 */
hns3_init_module(void)6022 static int __init hns3_init_module(void)
6023 {
6024 int ret;
6025
6026 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
6027 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
6028
6029 client.type = HNAE3_CLIENT_KNIC;
6030 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
6031 hns3_driver_name);
6032
6033 client.ops = &client_ops;
6034
6035 INIT_LIST_HEAD(&client.node);
6036
6037 hns3_dbg_register_debugfs(hns3_driver_name);
6038
6039 ret = hnae3_register_client(&client);
6040 if (ret)
6041 goto err_reg_client;
6042
6043 ret = pci_register_driver(&hns3_driver);
6044 if (ret)
6045 goto err_reg_driver;
6046
6047 return ret;
6048
6049 err_reg_driver:
6050 hnae3_unregister_client(&client);
6051 err_reg_client:
6052 hns3_dbg_unregister_debugfs();
6053 return ret;
6054 }
6055 module_init(hns3_init_module);
6056
6057 /* hns3_exit_module - Driver exit cleanup routine
6058 * hns3_exit_module is called just before the driver is removed
6059 * from memory.
6060 */
hns3_exit_module(void)6061 static void __exit hns3_exit_module(void)
6062 {
6063 pci_unregister_driver(&hns3_driver);
6064 hnae3_unregister_client(&client);
6065 hns3_dbg_unregister_debugfs();
6066 }
6067 module_exit(hns3_exit_module);
6068
6069 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
6070 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6071 MODULE_LICENSE("GPL");
6072 MODULE_ALIAS("pci:hns-nic");
6073