1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
9 #endif
10 #include <linux/if_vlan.h>
11 #include <linux/irq.h>
12 #include <linux/ip.h>
13 #include <linux/ipv6.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/skbuff.h>
17 #include <linux/sctp.h>
18 #include <net/gre.h>
19 #include <net/gro.h>
20 #include <net/ip6_checksum.h>
21 #include <net/page_pool/helpers.h>
22 #include <net/pkt_cls.h>
23 #include <net/pkt_sched.h>
24 #include <net/tcp.h>
25 #include <net/vxlan.h>
26 #include <net/geneve.h>
27
28 #include "hnae3.h"
29 #include "hns3_enet.h"
30 /* All hns3 tracepoints are defined by the include below, which
31 * must be included exactly once across the whole kernel with
32 * CREATE_TRACE_POINTS defined
33 */
34 #define CREATE_TRACE_POINTS
35 #include "hns3_trace.h"
36
37 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift))
38 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
39
40 #define hns3_rl_err(fmt, ...) \
41 do { \
42 if (net_ratelimit()) \
43 netdev_err(fmt, ##__VA_ARGS__); \
44 } while (0)
45
46 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
47
48 static const char hns3_driver_name[] = "hns3";
49 static const char hns3_driver_string[] =
50 "Hisilicon Ethernet Network Driver for Hip08 Family";
51 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
52 static struct hnae3_client client;
53
54 static int debug = -1;
55 module_param(debug, int, 0);
56 MODULE_PARM_DESC(debug, " Network interface message level setting");
57
58 static unsigned int tx_sgl = 1;
59 module_param(tx_sgl, uint, 0600);
60 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
61
62 static bool page_pool_enabled = true;
63 module_param(page_pool_enabled, bool, 0400);
64
65 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \
66 sizeof(struct sg_table))
67 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
68 dma_get_cache_alignment())
69
70 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
71 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
72
73 #define HNS3_INNER_VLAN_TAG 1
74 #define HNS3_OUTER_VLAN_TAG 2
75
76 #define HNS3_MIN_TX_LEN 33U
77 #define HNS3_MIN_TUN_PKT_LEN 65U
78
79 /* hns3_pci_tbl - PCI Device ID Table
80 *
81 * Last entry must be all 0s
82 *
83 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
84 * Class, Class Mask, private data (not used) }
85 */
86 static const struct pci_device_id hns3_pci_tbl[] = {
87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
90 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
91 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
92 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
93 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
94 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
95 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
96 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
97 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
98 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
99 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
100 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
101 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
102 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
103 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
104 /* required last entry */
105 {0,}
106 };
107 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
108
109 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t, h) \
110 { ptype, \
111 l, \
112 CHECKSUM_##s, \
113 HNS3_L3_TYPE_##t, \
114 1, \
115 h}
116
117 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
118 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0, \
119 PKT_HASH_TYPE_NONE }
120
121 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
122 HNS3_RX_PTYPE_UNUSED_ENTRY(0),
123 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP, PKT_HASH_TYPE_NONE),
124 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP, PKT_HASH_TYPE_NONE),
125 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP, PKT_HASH_TYPE_NONE),
126 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
127 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
128 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
129 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM, PKT_HASH_TYPE_NONE),
130 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
131 HNS3_RX_PTYPE_UNUSED_ENTRY(9),
132 HNS3_RX_PTYPE_UNUSED_ENTRY(10),
133 HNS3_RX_PTYPE_UNUSED_ENTRY(11),
134 HNS3_RX_PTYPE_UNUSED_ENTRY(12),
135 HNS3_RX_PTYPE_UNUSED_ENTRY(13),
136 HNS3_RX_PTYPE_UNUSED_ENTRY(14),
137 HNS3_RX_PTYPE_UNUSED_ENTRY(15),
138 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
139 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
140 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
141 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
142 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
143 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4, PKT_HASH_TYPE_NONE),
144 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
145 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
146 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
147 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
148 HNS3_RX_PTYPE_UNUSED_ENTRY(26),
149 HNS3_RX_PTYPE_UNUSED_ENTRY(27),
150 HNS3_RX_PTYPE_UNUSED_ENTRY(28),
151 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
152 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
153 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
154 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
155 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
156 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
157 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
158 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
159 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
160 HNS3_RX_PTYPE_UNUSED_ENTRY(38),
161 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
162 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
163 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
164 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
165 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
166 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
167 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
168 HNS3_RX_PTYPE_UNUSED_ENTRY(46),
169 HNS3_RX_PTYPE_UNUSED_ENTRY(47),
170 HNS3_RX_PTYPE_UNUSED_ENTRY(48),
171 HNS3_RX_PTYPE_UNUSED_ENTRY(49),
172 HNS3_RX_PTYPE_UNUSED_ENTRY(50),
173 HNS3_RX_PTYPE_UNUSED_ENTRY(51),
174 HNS3_RX_PTYPE_UNUSED_ENTRY(52),
175 HNS3_RX_PTYPE_UNUSED_ENTRY(53),
176 HNS3_RX_PTYPE_UNUSED_ENTRY(54),
177 HNS3_RX_PTYPE_UNUSED_ENTRY(55),
178 HNS3_RX_PTYPE_UNUSED_ENTRY(56),
179 HNS3_RX_PTYPE_UNUSED_ENTRY(57),
180 HNS3_RX_PTYPE_UNUSED_ENTRY(58),
181 HNS3_RX_PTYPE_UNUSED_ENTRY(59),
182 HNS3_RX_PTYPE_UNUSED_ENTRY(60),
183 HNS3_RX_PTYPE_UNUSED_ENTRY(61),
184 HNS3_RX_PTYPE_UNUSED_ENTRY(62),
185 HNS3_RX_PTYPE_UNUSED_ENTRY(63),
186 HNS3_RX_PTYPE_UNUSED_ENTRY(64),
187 HNS3_RX_PTYPE_UNUSED_ENTRY(65),
188 HNS3_RX_PTYPE_UNUSED_ENTRY(66),
189 HNS3_RX_PTYPE_UNUSED_ENTRY(67),
190 HNS3_RX_PTYPE_UNUSED_ENTRY(68),
191 HNS3_RX_PTYPE_UNUSED_ENTRY(69),
192 HNS3_RX_PTYPE_UNUSED_ENTRY(70),
193 HNS3_RX_PTYPE_UNUSED_ENTRY(71),
194 HNS3_RX_PTYPE_UNUSED_ENTRY(72),
195 HNS3_RX_PTYPE_UNUSED_ENTRY(73),
196 HNS3_RX_PTYPE_UNUSED_ENTRY(74),
197 HNS3_RX_PTYPE_UNUSED_ENTRY(75),
198 HNS3_RX_PTYPE_UNUSED_ENTRY(76),
199 HNS3_RX_PTYPE_UNUSED_ENTRY(77),
200 HNS3_RX_PTYPE_UNUSED_ENTRY(78),
201 HNS3_RX_PTYPE_UNUSED_ENTRY(79),
202 HNS3_RX_PTYPE_UNUSED_ENTRY(80),
203 HNS3_RX_PTYPE_UNUSED_ENTRY(81),
204 HNS3_RX_PTYPE_UNUSED_ENTRY(82),
205 HNS3_RX_PTYPE_UNUSED_ENTRY(83),
206 HNS3_RX_PTYPE_UNUSED_ENTRY(84),
207 HNS3_RX_PTYPE_UNUSED_ENTRY(85),
208 HNS3_RX_PTYPE_UNUSED_ENTRY(86),
209 HNS3_RX_PTYPE_UNUSED_ENTRY(87),
210 HNS3_RX_PTYPE_UNUSED_ENTRY(88),
211 HNS3_RX_PTYPE_UNUSED_ENTRY(89),
212 HNS3_RX_PTYPE_UNUSED_ENTRY(90),
213 HNS3_RX_PTYPE_UNUSED_ENTRY(91),
214 HNS3_RX_PTYPE_UNUSED_ENTRY(92),
215 HNS3_RX_PTYPE_UNUSED_ENTRY(93),
216 HNS3_RX_PTYPE_UNUSED_ENTRY(94),
217 HNS3_RX_PTYPE_UNUSED_ENTRY(95),
218 HNS3_RX_PTYPE_UNUSED_ENTRY(96),
219 HNS3_RX_PTYPE_UNUSED_ENTRY(97),
220 HNS3_RX_PTYPE_UNUSED_ENTRY(98),
221 HNS3_RX_PTYPE_UNUSED_ENTRY(99),
222 HNS3_RX_PTYPE_UNUSED_ENTRY(100),
223 HNS3_RX_PTYPE_UNUSED_ENTRY(101),
224 HNS3_RX_PTYPE_UNUSED_ENTRY(102),
225 HNS3_RX_PTYPE_UNUSED_ENTRY(103),
226 HNS3_RX_PTYPE_UNUSED_ENTRY(104),
227 HNS3_RX_PTYPE_UNUSED_ENTRY(105),
228 HNS3_RX_PTYPE_UNUSED_ENTRY(106),
229 HNS3_RX_PTYPE_UNUSED_ENTRY(107),
230 HNS3_RX_PTYPE_UNUSED_ENTRY(108),
231 HNS3_RX_PTYPE_UNUSED_ENTRY(109),
232 HNS3_RX_PTYPE_UNUSED_ENTRY(110),
233 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
234 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
235 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
236 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
237 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
238 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
239 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
240 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
241 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
242 HNS3_RX_PTYPE_UNUSED_ENTRY(120),
243 HNS3_RX_PTYPE_UNUSED_ENTRY(121),
244 HNS3_RX_PTYPE_UNUSED_ENTRY(122),
245 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
246 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
247 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
248 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
249 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
250 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
251 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
252 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
253 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
254 HNS3_RX_PTYPE_UNUSED_ENTRY(132),
255 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
256 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
257 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
258 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
259 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
260 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
261 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
262 HNS3_RX_PTYPE_UNUSED_ENTRY(140),
263 HNS3_RX_PTYPE_UNUSED_ENTRY(141),
264 HNS3_RX_PTYPE_UNUSED_ENTRY(142),
265 HNS3_RX_PTYPE_UNUSED_ENTRY(143),
266 HNS3_RX_PTYPE_UNUSED_ENTRY(144),
267 HNS3_RX_PTYPE_UNUSED_ENTRY(145),
268 HNS3_RX_PTYPE_UNUSED_ENTRY(146),
269 HNS3_RX_PTYPE_UNUSED_ENTRY(147),
270 HNS3_RX_PTYPE_UNUSED_ENTRY(148),
271 HNS3_RX_PTYPE_UNUSED_ENTRY(149),
272 HNS3_RX_PTYPE_UNUSED_ENTRY(150),
273 HNS3_RX_PTYPE_UNUSED_ENTRY(151),
274 HNS3_RX_PTYPE_UNUSED_ENTRY(152),
275 HNS3_RX_PTYPE_UNUSED_ENTRY(153),
276 HNS3_RX_PTYPE_UNUSED_ENTRY(154),
277 HNS3_RX_PTYPE_UNUSED_ENTRY(155),
278 HNS3_RX_PTYPE_UNUSED_ENTRY(156),
279 HNS3_RX_PTYPE_UNUSED_ENTRY(157),
280 HNS3_RX_PTYPE_UNUSED_ENTRY(158),
281 HNS3_RX_PTYPE_UNUSED_ENTRY(159),
282 HNS3_RX_PTYPE_UNUSED_ENTRY(160),
283 HNS3_RX_PTYPE_UNUSED_ENTRY(161),
284 HNS3_RX_PTYPE_UNUSED_ENTRY(162),
285 HNS3_RX_PTYPE_UNUSED_ENTRY(163),
286 HNS3_RX_PTYPE_UNUSED_ENTRY(164),
287 HNS3_RX_PTYPE_UNUSED_ENTRY(165),
288 HNS3_RX_PTYPE_UNUSED_ENTRY(166),
289 HNS3_RX_PTYPE_UNUSED_ENTRY(167),
290 HNS3_RX_PTYPE_UNUSED_ENTRY(168),
291 HNS3_RX_PTYPE_UNUSED_ENTRY(169),
292 HNS3_RX_PTYPE_UNUSED_ENTRY(170),
293 HNS3_RX_PTYPE_UNUSED_ENTRY(171),
294 HNS3_RX_PTYPE_UNUSED_ENTRY(172),
295 HNS3_RX_PTYPE_UNUSED_ENTRY(173),
296 HNS3_RX_PTYPE_UNUSED_ENTRY(174),
297 HNS3_RX_PTYPE_UNUSED_ENTRY(175),
298 HNS3_RX_PTYPE_UNUSED_ENTRY(176),
299 HNS3_RX_PTYPE_UNUSED_ENTRY(177),
300 HNS3_RX_PTYPE_UNUSED_ENTRY(178),
301 HNS3_RX_PTYPE_UNUSED_ENTRY(179),
302 HNS3_RX_PTYPE_UNUSED_ENTRY(180),
303 HNS3_RX_PTYPE_UNUSED_ENTRY(181),
304 HNS3_RX_PTYPE_UNUSED_ENTRY(182),
305 HNS3_RX_PTYPE_UNUSED_ENTRY(183),
306 HNS3_RX_PTYPE_UNUSED_ENTRY(184),
307 HNS3_RX_PTYPE_UNUSED_ENTRY(185),
308 HNS3_RX_PTYPE_UNUSED_ENTRY(186),
309 HNS3_RX_PTYPE_UNUSED_ENTRY(187),
310 HNS3_RX_PTYPE_UNUSED_ENTRY(188),
311 HNS3_RX_PTYPE_UNUSED_ENTRY(189),
312 HNS3_RX_PTYPE_UNUSED_ENTRY(190),
313 HNS3_RX_PTYPE_UNUSED_ENTRY(191),
314 HNS3_RX_PTYPE_UNUSED_ENTRY(192),
315 HNS3_RX_PTYPE_UNUSED_ENTRY(193),
316 HNS3_RX_PTYPE_UNUSED_ENTRY(194),
317 HNS3_RX_PTYPE_UNUSED_ENTRY(195),
318 HNS3_RX_PTYPE_UNUSED_ENTRY(196),
319 HNS3_RX_PTYPE_UNUSED_ENTRY(197),
320 HNS3_RX_PTYPE_UNUSED_ENTRY(198),
321 HNS3_RX_PTYPE_UNUSED_ENTRY(199),
322 HNS3_RX_PTYPE_UNUSED_ENTRY(200),
323 HNS3_RX_PTYPE_UNUSED_ENTRY(201),
324 HNS3_RX_PTYPE_UNUSED_ENTRY(202),
325 HNS3_RX_PTYPE_UNUSED_ENTRY(203),
326 HNS3_RX_PTYPE_UNUSED_ENTRY(204),
327 HNS3_RX_PTYPE_UNUSED_ENTRY(205),
328 HNS3_RX_PTYPE_UNUSED_ENTRY(206),
329 HNS3_RX_PTYPE_UNUSED_ENTRY(207),
330 HNS3_RX_PTYPE_UNUSED_ENTRY(208),
331 HNS3_RX_PTYPE_UNUSED_ENTRY(209),
332 HNS3_RX_PTYPE_UNUSED_ENTRY(210),
333 HNS3_RX_PTYPE_UNUSED_ENTRY(211),
334 HNS3_RX_PTYPE_UNUSED_ENTRY(212),
335 HNS3_RX_PTYPE_UNUSED_ENTRY(213),
336 HNS3_RX_PTYPE_UNUSED_ENTRY(214),
337 HNS3_RX_PTYPE_UNUSED_ENTRY(215),
338 HNS3_RX_PTYPE_UNUSED_ENTRY(216),
339 HNS3_RX_PTYPE_UNUSED_ENTRY(217),
340 HNS3_RX_PTYPE_UNUSED_ENTRY(218),
341 HNS3_RX_PTYPE_UNUSED_ENTRY(219),
342 HNS3_RX_PTYPE_UNUSED_ENTRY(220),
343 HNS3_RX_PTYPE_UNUSED_ENTRY(221),
344 HNS3_RX_PTYPE_UNUSED_ENTRY(222),
345 HNS3_RX_PTYPE_UNUSED_ENTRY(223),
346 HNS3_RX_PTYPE_UNUSED_ENTRY(224),
347 HNS3_RX_PTYPE_UNUSED_ENTRY(225),
348 HNS3_RX_PTYPE_UNUSED_ENTRY(226),
349 HNS3_RX_PTYPE_UNUSED_ENTRY(227),
350 HNS3_RX_PTYPE_UNUSED_ENTRY(228),
351 HNS3_RX_PTYPE_UNUSED_ENTRY(229),
352 HNS3_RX_PTYPE_UNUSED_ENTRY(230),
353 HNS3_RX_PTYPE_UNUSED_ENTRY(231),
354 HNS3_RX_PTYPE_UNUSED_ENTRY(232),
355 HNS3_RX_PTYPE_UNUSED_ENTRY(233),
356 HNS3_RX_PTYPE_UNUSED_ENTRY(234),
357 HNS3_RX_PTYPE_UNUSED_ENTRY(235),
358 HNS3_RX_PTYPE_UNUSED_ENTRY(236),
359 HNS3_RX_PTYPE_UNUSED_ENTRY(237),
360 HNS3_RX_PTYPE_UNUSED_ENTRY(238),
361 HNS3_RX_PTYPE_UNUSED_ENTRY(239),
362 HNS3_RX_PTYPE_UNUSED_ENTRY(240),
363 HNS3_RX_PTYPE_UNUSED_ENTRY(241),
364 HNS3_RX_PTYPE_UNUSED_ENTRY(242),
365 HNS3_RX_PTYPE_UNUSED_ENTRY(243),
366 HNS3_RX_PTYPE_UNUSED_ENTRY(244),
367 HNS3_RX_PTYPE_UNUSED_ENTRY(245),
368 HNS3_RX_PTYPE_UNUSED_ENTRY(246),
369 HNS3_RX_PTYPE_UNUSED_ENTRY(247),
370 HNS3_RX_PTYPE_UNUSED_ENTRY(248),
371 HNS3_RX_PTYPE_UNUSED_ENTRY(249),
372 HNS3_RX_PTYPE_UNUSED_ENTRY(250),
373 HNS3_RX_PTYPE_UNUSED_ENTRY(251),
374 HNS3_RX_PTYPE_UNUSED_ENTRY(252),
375 HNS3_RX_PTYPE_UNUSED_ENTRY(253),
376 HNS3_RX_PTYPE_UNUSED_ENTRY(254),
377 HNS3_RX_PTYPE_UNUSED_ENTRY(255),
378 };
379
380 #define HNS3_INVALID_PTYPE \
381 ARRAY_SIZE(hns3_rx_ptype_tbl)
382
hns3_irq_handle(int irq,void * vector)383 static irqreturn_t hns3_irq_handle(int irq, void *vector)
384 {
385 struct hns3_enet_tqp_vector *tqp_vector = vector;
386
387 napi_schedule_irqoff(&tqp_vector->napi);
388 tqp_vector->event_cnt++;
389
390 return IRQ_HANDLED;
391 }
392
hns3_nic_uninit_irq(struct hns3_nic_priv * priv)393 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
394 {
395 struct hns3_enet_tqp_vector *tqp_vectors;
396 unsigned int i;
397
398 for (i = 0; i < priv->vector_num; i++) {
399 tqp_vectors = &priv->tqp_vector[i];
400
401 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
402 continue;
403
404 /* clear the affinity mask */
405 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
406
407 /* release the irq resource */
408 free_irq(tqp_vectors->vector_irq, tqp_vectors);
409 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
410 }
411 }
412
hns3_nic_init_irq(struct hns3_nic_priv * priv)413 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
414 {
415 struct hns3_enet_tqp_vector *tqp_vectors;
416 int txrx_int_idx = 0;
417 int rx_int_idx = 0;
418 int tx_int_idx = 0;
419 unsigned int i;
420 int ret;
421
422 for (i = 0; i < priv->vector_num; i++) {
423 tqp_vectors = &priv->tqp_vector[i];
424
425 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
426 continue;
427
428 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
429 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
430 "%s-%s-%s-%d", hns3_driver_name,
431 pci_name(priv->ae_handle->pdev),
432 "TxRx", txrx_int_idx++);
433 txrx_int_idx++;
434 } else if (tqp_vectors->rx_group.ring) {
435 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
436 "%s-%s-%s-%d", hns3_driver_name,
437 pci_name(priv->ae_handle->pdev),
438 "Rx", rx_int_idx++);
439 } else if (tqp_vectors->tx_group.ring) {
440 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
441 "%s-%s-%s-%d", hns3_driver_name,
442 pci_name(priv->ae_handle->pdev),
443 "Tx", tx_int_idx++);
444 } else {
445 /* Skip this unused q_vector */
446 continue;
447 }
448
449 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
450
451 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
452 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
453 tqp_vectors->name, tqp_vectors);
454 if (ret) {
455 netdev_err(priv->netdev, "request irq(%d) fail\n",
456 tqp_vectors->vector_irq);
457 hns3_nic_uninit_irq(priv);
458 return ret;
459 }
460
461 irq_set_affinity_hint(tqp_vectors->vector_irq,
462 &tqp_vectors->affinity_mask);
463
464 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
465 }
466
467 return 0;
468 }
469
hns3_mask_vector_irq(struct hns3_enet_tqp_vector * tqp_vector,u32 mask_en)470 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
471 u32 mask_en)
472 {
473 writel(mask_en, tqp_vector->mask_addr);
474 }
475
hns3_irq_enable(struct hns3_enet_tqp_vector * tqp_vector)476 static void hns3_irq_enable(struct hns3_enet_tqp_vector *tqp_vector)
477 {
478 napi_enable(&tqp_vector->napi);
479 enable_irq(tqp_vector->vector_irq);
480 }
481
hns3_irq_disable(struct hns3_enet_tqp_vector * tqp_vector)482 static void hns3_irq_disable(struct hns3_enet_tqp_vector *tqp_vector)
483 {
484 disable_irq(tqp_vector->vector_irq);
485 napi_disable(&tqp_vector->napi);
486 cancel_work_sync(&tqp_vector->rx_group.dim.work);
487 cancel_work_sync(&tqp_vector->tx_group.dim.work);
488 }
489
hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector * tqp_vector,u32 rl_value)490 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
491 u32 rl_value)
492 {
493 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
494
495 /* this defines the configuration for RL (Interrupt Rate Limiter).
496 * Rl defines rate of interrupts i.e. number of interrupts-per-second
497 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
498 */
499 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
500 !tqp_vector->rx_group.coal.adapt_enable)
501 /* According to the hardware, the range of rl_reg is
502 * 0-59 and the unit is 4.
503 */
504 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
505
506 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
507 }
508
hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)509 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
510 u32 gl_value)
511 {
512 u32 new_val;
513
514 if (tqp_vector->rx_group.coal.unit_1us)
515 new_val = gl_value | HNS3_INT_GL_1US;
516 else
517 new_val = hns3_gl_usec_to_reg(gl_value);
518
519 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
520 }
521
hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)522 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
523 u32 gl_value)
524 {
525 u32 new_val;
526
527 if (tqp_vector->tx_group.coal.unit_1us)
528 new_val = gl_value | HNS3_INT_GL_1US;
529 else
530 new_val = hns3_gl_usec_to_reg(gl_value);
531
532 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
533 }
534
hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)535 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
536 u32 ql_value)
537 {
538 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
539 }
540
hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)541 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
542 u32 ql_value)
543 {
544 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
545 }
546
hns3_vector_coalesce_init(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)547 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
548 struct hns3_nic_priv *priv)
549 {
550 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
551 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
552 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
553 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
554 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
555
556 tx_coal->adapt_enable = ptx_coal->adapt_enable;
557 rx_coal->adapt_enable = prx_coal->adapt_enable;
558
559 tx_coal->int_gl = ptx_coal->int_gl;
560 rx_coal->int_gl = prx_coal->int_gl;
561
562 rx_coal->flow_level = prx_coal->flow_level;
563 tx_coal->flow_level = ptx_coal->flow_level;
564
565 /* device version above V3(include V3), GL can configure 1us
566 * unit, so uses 1us unit.
567 */
568 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
569 tx_coal->unit_1us = 1;
570 rx_coal->unit_1us = 1;
571 }
572
573 if (ae_dev->dev_specs.int_ql_max) {
574 tx_coal->ql_enable = 1;
575 rx_coal->ql_enable = 1;
576 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
577 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
578 tx_coal->int_ql = ptx_coal->int_ql;
579 rx_coal->int_ql = prx_coal->int_ql;
580 }
581 }
582
583 static void
hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)584 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
585 struct hns3_nic_priv *priv)
586 {
587 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
588 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
589 struct hnae3_handle *h = priv->ae_handle;
590
591 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
592 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
593 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
594
595 if (tx_coal->ql_enable)
596 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
597
598 if (rx_coal->ql_enable)
599 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
600 }
601
hns3_nic_set_real_num_queue(struct net_device * netdev)602 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
603 {
604 struct hnae3_handle *h = hns3_get_handle(netdev);
605 struct hnae3_knic_private_info *kinfo = &h->kinfo;
606 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
607 unsigned int queue_size = kinfo->num_tqps;
608 int i, ret;
609
610 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
611 netdev_reset_tc(netdev);
612 } else {
613 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
614 if (ret) {
615 netdev_err(netdev,
616 "netdev_set_num_tc fail, ret=%d!\n", ret);
617 return ret;
618 }
619
620 for (i = 0; i < tc_info->num_tc; i++)
621 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
622 tc_info->tqp_offset[i]);
623 }
624
625 ret = netif_set_real_num_tx_queues(netdev, queue_size);
626 if (ret) {
627 netdev_err(netdev,
628 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
629 return ret;
630 }
631
632 ret = netif_set_real_num_rx_queues(netdev, queue_size);
633 if (ret) {
634 netdev_err(netdev,
635 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
636 return ret;
637 }
638
639 return 0;
640 }
641
hns3_get_max_available_channels(struct hnae3_handle * h)642 u16 hns3_get_max_available_channels(struct hnae3_handle *h)
643 {
644 u16 alloc_tqps, max_rss_size, rss_size;
645
646 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
647 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
648
649 return min_t(u16, rss_size, max_rss_size);
650 }
651
hns3_tqp_enable(struct hnae3_queue * tqp)652 static void hns3_tqp_enable(struct hnae3_queue *tqp)
653 {
654 u32 rcb_reg;
655
656 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
657 rcb_reg |= BIT(HNS3_RING_EN_B);
658 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
659 }
660
hns3_tqp_disable(struct hnae3_queue * tqp)661 static void hns3_tqp_disable(struct hnae3_queue *tqp)
662 {
663 u32 rcb_reg;
664
665 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
666 rcb_reg &= ~BIT(HNS3_RING_EN_B);
667 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
668 }
669
hns3_free_rx_cpu_rmap(struct net_device * netdev)670 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
671 {
672 #ifdef CONFIG_RFS_ACCEL
673 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
674 netdev->rx_cpu_rmap = NULL;
675 #endif
676 }
677
hns3_set_rx_cpu_rmap(struct net_device * netdev)678 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
679 {
680 #ifdef CONFIG_RFS_ACCEL
681 struct hns3_nic_priv *priv = netdev_priv(netdev);
682 struct hns3_enet_tqp_vector *tqp_vector;
683 int i, ret;
684
685 if (!netdev->rx_cpu_rmap) {
686 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
687 if (!netdev->rx_cpu_rmap)
688 return -ENOMEM;
689 }
690
691 for (i = 0; i < priv->vector_num; i++) {
692 tqp_vector = &priv->tqp_vector[i];
693 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
694 tqp_vector->vector_irq);
695 if (ret) {
696 hns3_free_rx_cpu_rmap(netdev);
697 return ret;
698 }
699 }
700 #endif
701 return 0;
702 }
703
hns3_enable_irqs_and_tqps(struct net_device * netdev)704 static void hns3_enable_irqs_and_tqps(struct net_device *netdev)
705 {
706 struct hns3_nic_priv *priv = netdev_priv(netdev);
707 struct hnae3_handle *h = priv->ae_handle;
708 u16 i;
709
710 for (i = 0; i < priv->vector_num; i++)
711 hns3_irq_enable(&priv->tqp_vector[i]);
712
713 for (i = 0; i < priv->vector_num; i++)
714 hns3_mask_vector_irq(&priv->tqp_vector[i], 1);
715
716 for (i = 0; i < h->kinfo.num_tqps; i++)
717 hns3_tqp_enable(h->kinfo.tqp[i]);
718 }
719
hns3_disable_irqs_and_tqps(struct net_device * netdev)720 static void hns3_disable_irqs_and_tqps(struct net_device *netdev)
721 {
722 struct hns3_nic_priv *priv = netdev_priv(netdev);
723 struct hnae3_handle *h = priv->ae_handle;
724 u16 i;
725
726 for (i = 0; i < h->kinfo.num_tqps; i++)
727 hns3_tqp_disable(h->kinfo.tqp[i]);
728
729 for (i = 0; i < priv->vector_num; i++)
730 hns3_mask_vector_irq(&priv->tqp_vector[i], 0);
731
732 for (i = 0; i < priv->vector_num; i++)
733 hns3_irq_disable(&priv->tqp_vector[i]);
734 }
735
hns3_nic_net_up(struct net_device * netdev)736 static int hns3_nic_net_up(struct net_device *netdev)
737 {
738 struct hns3_nic_priv *priv = netdev_priv(netdev);
739 struct hnae3_handle *h = priv->ae_handle;
740 int ret;
741
742 ret = hns3_nic_reset_all_ring(h);
743 if (ret)
744 return ret;
745
746 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
747
748 hns3_enable_irqs_and_tqps(netdev);
749
750 /* start the ae_dev */
751 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
752 if (ret) {
753 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
754 hns3_disable_irqs_and_tqps(netdev);
755 }
756
757 return ret;
758 }
759
hns3_config_xps(struct hns3_nic_priv * priv)760 static void hns3_config_xps(struct hns3_nic_priv *priv)
761 {
762 int i;
763
764 for (i = 0; i < priv->vector_num; i++) {
765 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
766 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
767
768 while (ring) {
769 int ret;
770
771 ret = netif_set_xps_queue(priv->netdev,
772 &tqp_vector->affinity_mask,
773 ring->tqp->tqp_index);
774 if (ret)
775 netdev_warn(priv->netdev,
776 "set xps queue failed: %d", ret);
777
778 ring = ring->next;
779 }
780 }
781 }
782
hns3_nic_net_open(struct net_device * netdev)783 static int hns3_nic_net_open(struct net_device *netdev)
784 {
785 struct hns3_nic_priv *priv = netdev_priv(netdev);
786 struct hnae3_handle *h = hns3_get_handle(netdev);
787 struct hnae3_knic_private_info *kinfo;
788 int i, ret;
789
790 if (hns3_nic_resetting(netdev))
791 return -EBUSY;
792
793 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
794 netdev_warn(netdev, "net open repeatedly!\n");
795 return 0;
796 }
797
798 netif_carrier_off(netdev);
799
800 ret = hns3_nic_set_real_num_queue(netdev);
801 if (ret)
802 return ret;
803
804 ret = hns3_nic_net_up(netdev);
805 if (ret) {
806 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
807 return ret;
808 }
809
810 kinfo = &h->kinfo;
811 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
812 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
813
814 if (h->ae_algo->ops->set_timer_task)
815 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
816
817 hns3_config_xps(priv);
818
819 netif_dbg(h, drv, netdev, "net open\n");
820
821 return 0;
822 }
823
hns3_reset_tx_queue(struct hnae3_handle * h)824 static void hns3_reset_tx_queue(struct hnae3_handle *h)
825 {
826 struct net_device *ndev = h->kinfo.netdev;
827 struct hns3_nic_priv *priv = netdev_priv(ndev);
828 struct netdev_queue *dev_queue;
829 u32 i;
830
831 for (i = 0; i < h->kinfo.num_tqps; i++) {
832 dev_queue = netdev_get_tx_queue(ndev,
833 priv->ring[i].queue_index);
834 netdev_tx_reset_queue(dev_queue);
835 }
836 }
837
hns3_nic_net_down(struct net_device * netdev)838 static void hns3_nic_net_down(struct net_device *netdev)
839 {
840 struct hns3_nic_priv *priv = netdev_priv(netdev);
841 const struct hnae3_ae_ops *ops;
842
843 hns3_disable_irqs_and_tqps(netdev);
844
845 /* stop ae_dev */
846 ops = priv->ae_handle->ae_algo->ops;
847 if (ops->stop)
848 ops->stop(priv->ae_handle);
849
850 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
851 * during reset process, because driver may not be able
852 * to disable the ring through firmware when downing the netdev.
853 */
854 if (!hns3_nic_resetting(netdev))
855 hns3_clear_all_ring(priv->ae_handle, false);
856
857 hns3_reset_tx_queue(priv->ae_handle);
858 }
859
hns3_nic_net_stop(struct net_device * netdev)860 static int hns3_nic_net_stop(struct net_device *netdev)
861 {
862 struct hns3_nic_priv *priv = netdev_priv(netdev);
863 struct hnae3_handle *h = hns3_get_handle(netdev);
864
865 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
866 return 0;
867
868 netif_dbg(h, drv, netdev, "net stop\n");
869
870 if (h->ae_algo->ops->set_timer_task)
871 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
872
873 netif_carrier_off(netdev);
874 netif_tx_disable(netdev);
875
876 hns3_nic_net_down(netdev);
877
878 return 0;
879 }
880
hns3_nic_uc_sync(struct net_device * netdev,const unsigned char * addr)881 static int hns3_nic_uc_sync(struct net_device *netdev,
882 const unsigned char *addr)
883 {
884 struct hnae3_handle *h = hns3_get_handle(netdev);
885
886 if (h->ae_algo->ops->add_uc_addr)
887 return h->ae_algo->ops->add_uc_addr(h, addr);
888
889 return 0;
890 }
891
hns3_nic_uc_unsync(struct net_device * netdev,const unsigned char * addr)892 static int hns3_nic_uc_unsync(struct net_device *netdev,
893 const unsigned char *addr)
894 {
895 struct hnae3_handle *h = hns3_get_handle(netdev);
896
897 /* need ignore the request of removing device address, because
898 * we store the device address and other addresses of uc list
899 * in the function's mac filter list.
900 */
901 if (ether_addr_equal(addr, netdev->dev_addr))
902 return 0;
903
904 if (h->ae_algo->ops->rm_uc_addr)
905 return h->ae_algo->ops->rm_uc_addr(h, addr);
906
907 return 0;
908 }
909
hns3_nic_mc_sync(struct net_device * netdev,const unsigned char * addr)910 static int hns3_nic_mc_sync(struct net_device *netdev,
911 const unsigned char *addr)
912 {
913 struct hnae3_handle *h = hns3_get_handle(netdev);
914
915 if (h->ae_algo->ops->add_mc_addr)
916 return h->ae_algo->ops->add_mc_addr(h, addr);
917
918 return 0;
919 }
920
hns3_nic_mc_unsync(struct net_device * netdev,const unsigned char * addr)921 static int hns3_nic_mc_unsync(struct net_device *netdev,
922 const unsigned char *addr)
923 {
924 struct hnae3_handle *h = hns3_get_handle(netdev);
925
926 if (h->ae_algo->ops->rm_mc_addr)
927 return h->ae_algo->ops->rm_mc_addr(h, addr);
928
929 return 0;
930 }
931
hns3_get_netdev_flags(struct net_device * netdev)932 static u8 hns3_get_netdev_flags(struct net_device *netdev)
933 {
934 u8 flags = 0;
935
936 if (netdev->flags & IFF_PROMISC)
937 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
938 else if (netdev->flags & IFF_ALLMULTI)
939 flags = HNAE3_USER_MPE;
940
941 return flags;
942 }
943
hns3_nic_set_rx_mode(struct net_device * netdev)944 static void hns3_nic_set_rx_mode(struct net_device *netdev)
945 {
946 struct hnae3_handle *h = hns3_get_handle(netdev);
947 u8 new_flags;
948
949 new_flags = hns3_get_netdev_flags(netdev);
950
951 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
952 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
953
954 /* User mode Promisc mode enable and vlan filtering is disabled to
955 * let all packets in.
956 */
957 h->netdev_flags = new_flags;
958 hns3_request_update_promisc_mode(h);
959 }
960
hns3_request_update_promisc_mode(struct hnae3_handle * handle)961 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
962 {
963 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
964
965 if (ops->request_update_promisc_mode)
966 ops->request_update_promisc_mode(handle);
967 }
968
hns3_tx_spare_space(struct hns3_enet_ring * ring)969 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
970 {
971 struct hns3_tx_spare *tx_spare = ring->tx_spare;
972 u32 ntc, ntu;
973
974 /* This smp_load_acquire() pairs with smp_store_release() in
975 * hns3_tx_spare_update() called in tx desc cleaning process.
976 */
977 ntc = smp_load_acquire(&tx_spare->last_to_clean);
978 ntu = tx_spare->next_to_use;
979
980 if (ntc > ntu)
981 return ntc - ntu - 1;
982
983 /* The free tx buffer is divided into two part, so pick the
984 * larger one.
985 */
986 return max(ntc, tx_spare->len - ntu) - 1;
987 }
988
hns3_tx_spare_update(struct hns3_enet_ring * ring)989 static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
990 {
991 struct hns3_tx_spare *tx_spare = ring->tx_spare;
992
993 if (!tx_spare ||
994 tx_spare->last_to_clean == tx_spare->next_to_clean)
995 return;
996
997 /* This smp_store_release() pairs with smp_load_acquire() in
998 * hns3_tx_spare_space() called in xmit process.
999 */
1000 smp_store_release(&tx_spare->last_to_clean,
1001 tx_spare->next_to_clean);
1002 }
1003
hns3_can_use_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1004 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
1005 struct sk_buff *skb,
1006 u32 space)
1007 {
1008 u32 len = skb->len <= ring->tx_copybreak ? skb->len :
1009 skb_headlen(skb);
1010
1011 if (len > ring->tx_copybreak)
1012 return false;
1013
1014 if (ALIGN(len, dma_get_cache_alignment()) > space) {
1015 hns3_ring_stats_update(ring, tx_spare_full);
1016 return false;
1017 }
1018
1019 return true;
1020 }
1021
hns3_can_use_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1022 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1023 struct sk_buff *skb,
1024 u32 space)
1025 {
1026 if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1027 (!skb_has_frag_list(skb) &&
1028 skb_shinfo(skb)->nr_frags < tx_sgl))
1029 return false;
1030
1031 if (space < HNS3_MAX_SGL_SIZE) {
1032 hns3_ring_stats_update(ring, tx_spare_full);
1033 return false;
1034 }
1035
1036 return true;
1037 }
1038
hns3_init_tx_spare_buffer(struct hns3_enet_ring * ring)1039 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1040 {
1041 u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
1042 struct hns3_tx_spare *tx_spare;
1043 struct page *page;
1044 dma_addr_t dma;
1045 int order;
1046
1047 if (!alloc_size)
1048 return;
1049
1050 order = get_order(alloc_size);
1051 if (order > MAX_PAGE_ORDER) {
1052 if (net_ratelimit())
1053 dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n");
1054 return;
1055 }
1056
1057 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1058 GFP_KERNEL);
1059 if (!tx_spare) {
1060 /* The driver still work without the tx spare buffer */
1061 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1062 goto devm_kzalloc_error;
1063 }
1064
1065 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1066 GFP_KERNEL, order);
1067 if (!page) {
1068 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1069 goto alloc_pages_error;
1070 }
1071
1072 dma = dma_map_page(ring_to_dev(ring), page, 0,
1073 PAGE_SIZE << order, DMA_TO_DEVICE);
1074 if (dma_mapping_error(ring_to_dev(ring), dma)) {
1075 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1076 goto dma_mapping_error;
1077 }
1078
1079 tx_spare->dma = dma;
1080 tx_spare->buf = page_address(page);
1081 tx_spare->len = PAGE_SIZE << order;
1082 ring->tx_spare = tx_spare;
1083 return;
1084
1085 dma_mapping_error:
1086 put_page(page);
1087 alloc_pages_error:
1088 devm_kfree(ring_to_dev(ring), tx_spare);
1089 devm_kzalloc_error:
1090 ring->tqp->handle->kinfo.tx_spare_buf_size = 0;
1091 }
1092
1093 /* Use hns3_tx_spare_space() to make sure there is enough buffer
1094 * before calling below function to allocate tx buffer.
1095 */
hns3_tx_spare_alloc(struct hns3_enet_ring * ring,unsigned int size,dma_addr_t * dma,u32 * cb_len)1096 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1097 unsigned int size, dma_addr_t *dma,
1098 u32 *cb_len)
1099 {
1100 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1101 u32 ntu = tx_spare->next_to_use;
1102
1103 size = ALIGN(size, dma_get_cache_alignment());
1104 *cb_len = size;
1105
1106 /* Tx spare buffer wraps back here because the end of
1107 * freed tx buffer is not enough.
1108 */
1109 if (ntu + size > tx_spare->len) {
1110 *cb_len += (tx_spare->len - ntu);
1111 ntu = 0;
1112 }
1113
1114 tx_spare->next_to_use = ntu + size;
1115 if (tx_spare->next_to_use == tx_spare->len)
1116 tx_spare->next_to_use = 0;
1117
1118 *dma = tx_spare->dma + ntu;
1119
1120 return tx_spare->buf + ntu;
1121 }
1122
hns3_tx_spare_rollback(struct hns3_enet_ring * ring,u32 len)1123 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1124 {
1125 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1126
1127 if (len > tx_spare->next_to_use) {
1128 len -= tx_spare->next_to_use;
1129 tx_spare->next_to_use = tx_spare->len - len;
1130 } else {
1131 tx_spare->next_to_use -= len;
1132 }
1133 }
1134
hns3_tx_spare_reclaim_cb(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1135 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1136 struct hns3_desc_cb *cb)
1137 {
1138 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1139 u32 ntc = tx_spare->next_to_clean;
1140 u32 len = cb->length;
1141
1142 tx_spare->next_to_clean += len;
1143
1144 if (tx_spare->next_to_clean >= tx_spare->len) {
1145 tx_spare->next_to_clean -= tx_spare->len;
1146
1147 if (tx_spare->next_to_clean) {
1148 ntc = 0;
1149 len = tx_spare->next_to_clean;
1150 }
1151 }
1152
1153 /* This tx spare buffer is only really reclaimed after calling
1154 * hns3_tx_spare_update(), so it is still safe to use the info in
1155 * the tx buffer to do the dma sync or sg unmapping after
1156 * tx_spare->next_to_clean is moved forword.
1157 */
1158 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1159 dma_addr_t dma = tx_spare->dma + ntc;
1160
1161 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1162 DMA_TO_DEVICE);
1163 } else {
1164 struct sg_table *sgt = tx_spare->buf + ntc;
1165
1166 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1167 DMA_TO_DEVICE);
1168 }
1169 }
1170
hns3_set_tso(struct sk_buff * skb,u32 * paylen_fdop_ol4cs,u16 * mss,u32 * type_cs_vlan_tso,u32 * send_bytes)1171 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
1172 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
1173 {
1174 u32 l4_offset, hdr_len;
1175 union l3_hdr_info l3;
1176 union l4_hdr_info l4;
1177 u32 l4_paylen;
1178 int ret;
1179
1180 if (!skb_is_gso(skb))
1181 return 0;
1182
1183 ret = skb_cow_head(skb, 0);
1184 if (unlikely(ret < 0))
1185 return ret;
1186
1187 l3.hdr = skb_network_header(skb);
1188 l4.hdr = skb_transport_header(skb);
1189
1190 /* Software should clear the IPv4's checksum field when tso is
1191 * needed.
1192 */
1193 if (l3.v4->version == 4)
1194 l3.v4->check = 0;
1195
1196 /* tunnel packet */
1197 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1198 SKB_GSO_GRE_CSUM |
1199 SKB_GSO_UDP_TUNNEL |
1200 SKB_GSO_UDP_TUNNEL_CSUM)) {
1201 /* reset l3&l4 pointers from outer to inner headers */
1202 l3.hdr = skb_inner_network_header(skb);
1203 l4.hdr = skb_inner_transport_header(skb);
1204
1205 /* Software should clear the IPv4's checksum field when
1206 * tso is needed.
1207 */
1208 if (l3.v4->version == 4)
1209 l3.v4->check = 0;
1210 }
1211
1212 /* normal or tunnel packet */
1213 l4_offset = l4.hdr - skb->data;
1214
1215 /* remove payload length from inner pseudo checksum when tso */
1216 l4_paylen = skb->len - l4_offset;
1217
1218 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1219 hdr_len = sizeof(*l4.udp) + l4_offset;
1220 csum_replace_by_diff(&l4.udp->check,
1221 (__force __wsum)htonl(l4_paylen));
1222 } else {
1223 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1224 csum_replace_by_diff(&l4.tcp->check,
1225 (__force __wsum)htonl(l4_paylen));
1226 }
1227
1228 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1229
1230 /* find the txbd field values */
1231 *paylen_fdop_ol4cs = skb->len - hdr_len;
1232 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
1233
1234 /* offload outer UDP header checksum */
1235 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1236 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1237
1238 /* get MSS for TSO */
1239 *mss = skb_shinfo(skb)->gso_size;
1240
1241 trace_hns3_tso(skb);
1242
1243 return 0;
1244 }
1245
hns3_get_l4_protocol(struct sk_buff * skb,u8 * ol4_proto,u8 * il4_proto)1246 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1247 u8 *il4_proto)
1248 {
1249 union l3_hdr_info l3;
1250 unsigned char *l4_hdr;
1251 unsigned char *exthdr;
1252 u8 l4_proto_tmp;
1253 __be16 frag_off;
1254
1255 /* find outer header point */
1256 l3.hdr = skb_network_header(skb);
1257 l4_hdr = skb_transport_header(skb);
1258
1259 if (skb->protocol == htons(ETH_P_IPV6)) {
1260 exthdr = l3.hdr + sizeof(*l3.v6);
1261 l4_proto_tmp = l3.v6->nexthdr;
1262 if (l4_hdr != exthdr)
1263 ipv6_skip_exthdr(skb, exthdr - skb->data,
1264 &l4_proto_tmp, &frag_off);
1265 } else if (skb->protocol == htons(ETH_P_IP)) {
1266 l4_proto_tmp = l3.v4->protocol;
1267 } else {
1268 return -EINVAL;
1269 }
1270
1271 *ol4_proto = l4_proto_tmp;
1272
1273 /* tunnel packet */
1274 if (!skb->encapsulation) {
1275 *il4_proto = 0;
1276 return 0;
1277 }
1278
1279 /* find inner header point */
1280 l3.hdr = skb_inner_network_header(skb);
1281 l4_hdr = skb_inner_transport_header(skb);
1282
1283 if (l3.v6->version == 6) {
1284 exthdr = l3.hdr + sizeof(*l3.v6);
1285 l4_proto_tmp = l3.v6->nexthdr;
1286 if (l4_hdr != exthdr)
1287 ipv6_skip_exthdr(skb, exthdr - skb->data,
1288 &l4_proto_tmp, &frag_off);
1289 } else if (l3.v4->version == 4) {
1290 l4_proto_tmp = l3.v4->protocol;
1291 }
1292
1293 *il4_proto = l4_proto_tmp;
1294
1295 return 0;
1296 }
1297
1298 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1299 * and it is udp packet, which has a dest port as the IANA assigned.
1300 * the hardware is expected to do the checksum offload, but the
1301 * hardware will not do the checksum offload when udp dest port is
1302 * 4789, 4790 or 6081.
1303 */
hns3_tunnel_csum_bug(struct sk_buff * skb)1304 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1305 {
1306 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1307 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1308 union l4_hdr_info l4;
1309
1310 /* device version above V3(include V3), the hardware can
1311 * do this checksum offload.
1312 */
1313 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1314 return false;
1315
1316 l4.hdr = skb_transport_header(skb);
1317
1318 if (!(!skb->encapsulation &&
1319 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
1320 l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1321 l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT))))
1322 return false;
1323
1324 return true;
1325 }
1326
hns3_set_outer_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u32 * ol_type_vlan_len_msec)1327 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1328 u32 *ol_type_vlan_len_msec)
1329 {
1330 u32 l2_len, l3_len, l4_len;
1331 unsigned char *il2_hdr;
1332 union l3_hdr_info l3;
1333 union l4_hdr_info l4;
1334
1335 l3.hdr = skb_network_header(skb);
1336 l4.hdr = skb_transport_header(skb);
1337
1338 /* compute OL2 header size, defined in 2 Bytes */
1339 l2_len = l3.hdr - skb->data;
1340 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1341
1342 /* compute OL3 header size, defined in 4 Bytes */
1343 l3_len = l4.hdr - l3.hdr;
1344 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
1345
1346 il2_hdr = skb_inner_mac_header(skb);
1347 /* compute OL4 header size, defined in 4 Bytes */
1348 l4_len = il2_hdr - l4.hdr;
1349 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1350
1351 /* define outer network header type */
1352 if (skb->protocol == htons(ETH_P_IP)) {
1353 if (skb_is_gso(skb))
1354 hns3_set_field(*ol_type_vlan_len_msec,
1355 HNS3_TXD_OL3T_S,
1356 HNS3_OL3T_IPV4_CSUM);
1357 else
1358 hns3_set_field(*ol_type_vlan_len_msec,
1359 HNS3_TXD_OL3T_S,
1360 HNS3_OL3T_IPV4_NO_CSUM);
1361 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1362 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1363 HNS3_OL3T_IPV6);
1364 }
1365
1366 if (ol4_proto == IPPROTO_UDP)
1367 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1368 HNS3_TUN_MAC_IN_UDP);
1369 else if (ol4_proto == IPPROTO_GRE)
1370 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1371 HNS3_TUN_NVGRE);
1372 }
1373
hns3_set_l3_type(struct sk_buff * skb,union l3_hdr_info l3,u32 * type_cs_vlan_tso)1374 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3,
1375 u32 *type_cs_vlan_tso)
1376 {
1377 if (l3.v4->version == 4) {
1378 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1379 HNS3_L3T_IPV4);
1380
1381 /* the stack computes the IP header already, the only time we
1382 * need the hardware to recompute it is in the case of TSO.
1383 */
1384 if (skb_is_gso(skb))
1385 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
1386 } else if (l3.v6->version == 6) {
1387 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1388 HNS3_L3T_IPV6);
1389 }
1390 }
1391
hns3_set_l4_csum_length(struct sk_buff * skb,union l4_hdr_info l4,u32 l4_proto,u32 * type_cs_vlan_tso)1392 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4,
1393 u32 l4_proto, u32 *type_cs_vlan_tso)
1394 {
1395 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
1396 switch (l4_proto) {
1397 case IPPROTO_TCP:
1398 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1399 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1400 HNS3_L4T_TCP);
1401 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1402 l4.tcp->doff);
1403 break;
1404 case IPPROTO_UDP:
1405 if (hns3_tunnel_csum_bug(skb)) {
1406 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN);
1407
1408 return ret ? ret : skb_checksum_help(skb);
1409 }
1410
1411 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1412 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1413 HNS3_L4T_UDP);
1414 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1415 (sizeof(struct udphdr) >> 2));
1416 break;
1417 case IPPROTO_SCTP:
1418 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1419 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1420 HNS3_L4T_SCTP);
1421 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1422 (sizeof(struct sctphdr) >> 2));
1423 break;
1424 default:
1425 /* drop the skb tunnel packet if hardware don't support,
1426 * because hardware can't calculate csum when TSO.
1427 */
1428 if (skb_is_gso(skb))
1429 return -EDOM;
1430
1431 /* the stack computes the IP header already,
1432 * driver calculate l4 checksum when not TSO.
1433 */
1434 return skb_checksum_help(skb);
1435 }
1436
1437 return 0;
1438 }
1439
hns3_set_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u8 il4_proto,u32 * type_cs_vlan_tso,u32 * ol_type_vlan_len_msec)1440 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1441 u8 il4_proto, u32 *type_cs_vlan_tso,
1442 u32 *ol_type_vlan_len_msec)
1443 {
1444 unsigned char *l2_hdr = skb->data;
1445 u32 l4_proto = ol4_proto;
1446 union l4_hdr_info l4;
1447 union l3_hdr_info l3;
1448 u32 l2_len, l3_len;
1449
1450 l4.hdr = skb_transport_header(skb);
1451 l3.hdr = skb_network_header(skb);
1452
1453 /* handle encapsulation skb */
1454 if (skb->encapsulation) {
1455 /* If this is a not UDP/GRE encapsulation skb */
1456 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
1457 /* drop the skb tunnel packet if hardware don't support,
1458 * because hardware can't calculate csum when TSO.
1459 */
1460 if (skb_is_gso(skb))
1461 return -EDOM;
1462
1463 /* the stack computes the IP header already,
1464 * driver calculate l4 checksum when not TSO.
1465 */
1466 return skb_checksum_help(skb);
1467 }
1468
1469 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1470
1471 /* switch to inner header */
1472 l2_hdr = skb_inner_mac_header(skb);
1473 l3.hdr = skb_inner_network_header(skb);
1474 l4.hdr = skb_inner_transport_header(skb);
1475 l4_proto = il4_proto;
1476 }
1477
1478 hns3_set_l3_type(skb, l3, type_cs_vlan_tso);
1479
1480 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1481 l2_len = l3.hdr - l2_hdr;
1482 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1483
1484 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1485 l3_len = l4.hdr - l3.hdr;
1486 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1487
1488 return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso);
1489 }
1490
hns3_handle_vtags(struct hns3_enet_ring * tx_ring,struct sk_buff * skb)1491 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1492 struct sk_buff *skb)
1493 {
1494 struct hnae3_handle *handle = tx_ring->tqp->handle;
1495 struct hnae3_ae_dev *ae_dev;
1496 struct vlan_ethhdr *vhdr;
1497 int rc;
1498
1499 if (!(skb->protocol == htons(ETH_P_8021Q) ||
1500 skb_vlan_tag_present(skb)))
1501 return 0;
1502
1503 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1504 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1505 * will cause RAS error.
1506 */
1507 ae_dev = pci_get_drvdata(handle->pdev);
1508 if (unlikely(skb_vlan_tagged_multi(skb) &&
1509 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
1510 handle->port_base_vlan_state ==
1511 HNAE3_PORT_BASE_VLAN_ENABLE))
1512 return -EINVAL;
1513
1514 if (skb->protocol == htons(ETH_P_8021Q) &&
1515 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1516 /* When HW VLAN acceleration is turned off, and the stack
1517 * sets the protocol to 802.1q, the driver just need to
1518 * set the protocol to the encapsulated ethertype.
1519 */
1520 skb->protocol = vlan_get_protocol(skb);
1521 return 0;
1522 }
1523
1524 if (skb_vlan_tag_present(skb)) {
1525 /* Based on hw strategy, use out_vtag in two layer tag case,
1526 * and use inner_vtag in one tag case.
1527 */
1528 if (skb->protocol == htons(ETH_P_8021Q) &&
1529 handle->port_base_vlan_state ==
1530 HNAE3_PORT_BASE_VLAN_DISABLE)
1531 rc = HNS3_OUTER_VLAN_TAG;
1532 else
1533 rc = HNS3_INNER_VLAN_TAG;
1534
1535 skb->protocol = vlan_get_protocol(skb);
1536 return rc;
1537 }
1538
1539 rc = skb_cow_head(skb, 0);
1540 if (unlikely(rc < 0))
1541 return rc;
1542
1543 vhdr = skb_vlan_eth_hdr(skb);
1544 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1545 & VLAN_PRIO_MASK);
1546
1547 skb->protocol = vlan_get_protocol(skb);
1548 return 0;
1549 }
1550
1551 /* check if the hardware is capable of checksum offloading */
hns3_check_hw_tx_csum(struct sk_buff * skb)1552 static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1553 {
1554 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1555
1556 /* Kindly note, due to backward compatibility of the TX descriptor,
1557 * HW checksum of the non-IP packets and GSO packets is handled at
1558 * different place in the following code
1559 */
1560 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
1561 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1562 return false;
1563
1564 return true;
1565 }
1566
1567 struct hns3_desc_param {
1568 u32 paylen_ol4cs;
1569 u32 ol_type_vlan_len_msec;
1570 u32 type_cs_vlan_tso;
1571 u16 mss_hw_csum;
1572 u16 inner_vtag;
1573 u16 out_vtag;
1574 };
1575
hns3_init_desc_data(struct sk_buff * skb,struct hns3_desc_param * pa)1576 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa)
1577 {
1578 pa->paylen_ol4cs = skb->len;
1579 pa->ol_type_vlan_len_msec = 0;
1580 pa->type_cs_vlan_tso = 0;
1581 pa->mss_hw_csum = 0;
1582 pa->inner_vtag = 0;
1583 pa->out_vtag = 0;
1584 }
1585
hns3_handle_vlan_info(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_param * param)1586 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring,
1587 struct sk_buff *skb,
1588 struct hns3_desc_param *param)
1589 {
1590 int ret;
1591
1592 ret = hns3_handle_vtags(ring, skb);
1593 if (unlikely(ret < 0)) {
1594 hns3_ring_stats_update(ring, tx_vlan_err);
1595 return ret;
1596 } else if (ret == HNS3_INNER_VLAN_TAG) {
1597 param->inner_vtag = skb_vlan_tag_get(skb);
1598 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1599 VLAN_PRIO_MASK;
1600 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1601 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1602 param->out_vtag = skb_vlan_tag_get(skb);
1603 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1604 VLAN_PRIO_MASK;
1605 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1606 1);
1607 }
1608 return 0;
1609 }
1610
hns3_handle_csum_partial(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,struct hns3_desc_param * param)1611 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring,
1612 struct sk_buff *skb,
1613 struct hns3_desc_cb *desc_cb,
1614 struct hns3_desc_param *param)
1615 {
1616 u8 ol4_proto, il4_proto;
1617 int ret;
1618
1619 if (hns3_check_hw_tx_csum(skb)) {
1620 /* set checksum start and offset, defined in 2 Bytes */
1621 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1622 skb_checksum_start_offset(skb) >> 1);
1623 hns3_set_field(param->ol_type_vlan_len_msec,
1624 HNS3_TXD_CSUM_OFFSET_S,
1625 skb->csum_offset >> 1);
1626 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1627 return 0;
1628 }
1629
1630 skb_reset_mac_len(skb);
1631
1632 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1633 if (unlikely(ret < 0)) {
1634 hns3_ring_stats_update(ring, tx_l4_proto_err);
1635 return ret;
1636 }
1637
1638 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1639 ¶m->type_cs_vlan_tso,
1640 ¶m->ol_type_vlan_len_msec);
1641 if (unlikely(ret < 0)) {
1642 hns3_ring_stats_update(ring, tx_l2l3l4_err);
1643 return ret;
1644 }
1645
1646 ret = hns3_set_tso(skb, ¶m->paylen_ol4cs, ¶m->mss_hw_csum,
1647 ¶m->type_cs_vlan_tso, &desc_cb->send_bytes);
1648 if (unlikely(ret < 0)) {
1649 hns3_ring_stats_update(ring, tx_tso_err);
1650 return ret;
1651 }
1652 return 0;
1653 }
1654
hns3_fill_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc * desc,struct hns3_desc_cb * desc_cb)1655 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1656 struct sk_buff *skb, struct hns3_desc *desc,
1657 struct hns3_desc_cb *desc_cb)
1658 {
1659 struct hns3_desc_param param;
1660 int ret;
1661
1662 hns3_init_desc_data(skb, ¶m);
1663 ret = hns3_handle_vlan_info(ring, skb, ¶m);
1664 if (unlikely(ret < 0))
1665 return ret;
1666
1667 desc_cb->send_bytes = skb->len;
1668
1669 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1670 ret = hns3_handle_csum_partial(ring, skb, desc_cb, ¶m);
1671 if (ret)
1672 return ret;
1673 }
1674
1675 /* Set txbd */
1676 desc->tx.ol_type_vlan_len_msec =
1677 cpu_to_le32(param.ol_type_vlan_len_msec);
1678 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso);
1679 desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs);
1680 desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum);
1681 desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag);
1682 desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag);
1683
1684 return 0;
1685 }
1686
hns3_fill_desc(struct hns3_enet_ring * ring,dma_addr_t dma,unsigned int size)1687 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1688 unsigned int size)
1689 {
1690 #define HNS3_LIKELY_BD_NUM 1
1691
1692 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1693 unsigned int frag_buf_num;
1694 int k, sizeoflast;
1695
1696 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1697 desc->addr = cpu_to_le64(dma);
1698 desc->tx.send_size = cpu_to_le16(size);
1699 desc->tx.bdtp_fe_sc_vld_ra_ri =
1700 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1701
1702 trace_hns3_tx_desc(ring, ring->next_to_use);
1703 ring_ptr_move_fw(ring, next_to_use);
1704 return HNS3_LIKELY_BD_NUM;
1705 }
1706
1707 frag_buf_num = hns3_tx_bd_count(size);
1708 sizeoflast = size % HNS3_MAX_BD_SIZE;
1709 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1710
1711 /* When frag size is bigger than hardware limit, split this frag */
1712 for (k = 0; k < frag_buf_num; k++) {
1713 /* now, fill the descriptor */
1714 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1715 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1716 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1717 desc->tx.bdtp_fe_sc_vld_ra_ri =
1718 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1719
1720 trace_hns3_tx_desc(ring, ring->next_to_use);
1721 /* move ring pointer to next */
1722 ring_ptr_move_fw(ring, next_to_use);
1723
1724 desc = &ring->desc[ring->next_to_use];
1725 }
1726
1727 return frag_buf_num;
1728 }
1729
hns3_map_and_fill_desc(struct hns3_enet_ring * ring,void * priv,unsigned int type)1730 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1731 unsigned int type)
1732 {
1733 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1734 struct device *dev = ring_to_dev(ring);
1735 unsigned int size;
1736 dma_addr_t dma;
1737
1738 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1739 struct sk_buff *skb = (struct sk_buff *)priv;
1740
1741 size = skb_headlen(skb);
1742 if (!size)
1743 return 0;
1744
1745 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1746 } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1747 /* Head data has been filled in hns3_handle_tx_bounce(),
1748 * just return 0 here.
1749 */
1750 return 0;
1751 } else {
1752 skb_frag_t *frag = (skb_frag_t *)priv;
1753
1754 size = skb_frag_size(frag);
1755 if (!size)
1756 return 0;
1757
1758 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1759 }
1760
1761 if (unlikely(dma_mapping_error(dev, dma))) {
1762 hns3_ring_stats_update(ring, sw_err_cnt);
1763 return -ENOMEM;
1764 }
1765
1766 desc_cb->priv = priv;
1767 desc_cb->length = size;
1768 desc_cb->dma = dma;
1769 desc_cb->type = type;
1770
1771 return hns3_fill_desc(ring, dma, size);
1772 }
1773
hns3_skb_bd_num(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num)1774 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1775 unsigned int bd_num)
1776 {
1777 unsigned int size;
1778 int i;
1779
1780 size = skb_headlen(skb);
1781 while (size > HNS3_MAX_BD_SIZE) {
1782 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1783 size -= HNS3_MAX_BD_SIZE;
1784
1785 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1786 return bd_num;
1787 }
1788
1789 if (size) {
1790 bd_size[bd_num++] = size;
1791 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1792 return bd_num;
1793 }
1794
1795 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1796 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1797 size = skb_frag_size(frag);
1798 if (!size)
1799 continue;
1800
1801 while (size > HNS3_MAX_BD_SIZE) {
1802 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1803 size -= HNS3_MAX_BD_SIZE;
1804
1805 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1806 return bd_num;
1807 }
1808
1809 bd_size[bd_num++] = size;
1810 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1811 return bd_num;
1812 }
1813
1814 return bd_num;
1815 }
1816
hns3_tx_bd_num(struct sk_buff * skb,unsigned int * bd_size,u8 max_non_tso_bd_num,unsigned int bd_num,unsigned int recursion_level)1817 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1818 u8 max_non_tso_bd_num, unsigned int bd_num,
1819 unsigned int recursion_level)
1820 {
1821 #define HNS3_MAX_RECURSION_LEVEL 24
1822
1823 struct sk_buff *frag_skb;
1824
1825 /* If the total len is within the max bd limit */
1826 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1827 !skb_has_frag_list(skb) &&
1828 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
1829 return skb_shinfo(skb)->nr_frags + 1U;
1830
1831 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1832 return UINT_MAX;
1833
1834 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1835 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1836 return bd_num;
1837
1838 skb_walk_frags(skb, frag_skb) {
1839 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1840 bd_num, recursion_level + 1);
1841 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1842 return bd_num;
1843 }
1844
1845 return bd_num;
1846 }
1847
hns3_gso_hdr_len(struct sk_buff * skb)1848 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1849 {
1850 if (!skb->encapsulation)
1851 return skb_tcp_all_headers(skb);
1852
1853 return skb_inner_tcp_all_headers(skb);
1854 }
1855
1856 /* HW need every continuous max_non_tso_bd_num buffer data to be larger
1857 * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1858 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1859 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1860 * than MSS except the last max_non_tso_bd_num - 1 frags.
1861 */
hns3_skb_need_linearized(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num,u8 max_non_tso_bd_num)1862 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1863 unsigned int bd_num, u8 max_non_tso_bd_num)
1864 {
1865 unsigned int tot_len = 0;
1866 int i;
1867
1868 for (i = 0; i < max_non_tso_bd_num - 1U; i++)
1869 tot_len += bd_size[i];
1870
1871 /* ensure the first max_non_tso_bd_num frags is greater than
1872 * mss + header
1873 */
1874 if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
1875 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1876 return true;
1877
1878 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1879 * than mss except the last one.
1880 */
1881 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
1882 tot_len -= bd_size[i];
1883 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
1884
1885 if (tot_len < skb_shinfo(skb)->gso_size)
1886 return true;
1887 }
1888
1889 return false;
1890 }
1891
hns3_shinfo_pack(struct skb_shared_info * shinfo,__u32 * size)1892 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1893 {
1894 int i;
1895
1896 for (i = 0; i < MAX_SKB_FRAGS; i++)
1897 size[i] = skb_frag_size(&shinfo->frags[i]);
1898 }
1899
hns3_skb_linearize(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int bd_num)1900 static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1901 struct sk_buff *skb,
1902 unsigned int bd_num)
1903 {
1904 /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1905 * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1906 */
1907 if (bd_num == UINT_MAX) {
1908 hns3_ring_stats_update(ring, over_max_recursion);
1909 return -ENOMEM;
1910 }
1911
1912 /* The skb->len has exceeded the hw limitation, linearization
1913 * will not help.
1914 */
1915 if (skb->len > HNS3_MAX_TSO_SIZE ||
1916 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) {
1917 hns3_ring_stats_update(ring, hw_limitation);
1918 return -ENOMEM;
1919 }
1920
1921 if (__skb_linearize(skb)) {
1922 hns3_ring_stats_update(ring, sw_err_cnt);
1923 return -ENOMEM;
1924 }
1925
1926 return 0;
1927 }
1928
hns3_nic_maybe_stop_tx(struct hns3_enet_ring * ring,struct net_device * netdev,struct sk_buff * skb)1929 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1930 struct net_device *netdev,
1931 struct sk_buff *skb)
1932 {
1933 struct hns3_nic_priv *priv = netdev_priv(netdev);
1934 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
1935 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1936 unsigned int bd_num;
1937
1938 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
1939 if (unlikely(bd_num > max_non_tso_bd_num)) {
1940 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1941 !hns3_skb_need_linearized(skb, bd_size, bd_num,
1942 max_non_tso_bd_num)) {
1943 trace_hns3_over_max_bd(skb);
1944 goto out;
1945 }
1946
1947 if (hns3_skb_linearize(ring, skb, bd_num))
1948 return -ENOMEM;
1949
1950 bd_num = hns3_tx_bd_count(skb->len);
1951
1952 hns3_ring_stats_update(ring, tx_copy);
1953 }
1954
1955 out:
1956 if (likely(ring_space(ring) >= bd_num))
1957 return bd_num;
1958
1959 netif_stop_subqueue(netdev, ring->queue_index);
1960 smp_mb(); /* Memory barrier before checking ring_space */
1961
1962 /* Start queue in case hns3_clean_tx_ring has just made room
1963 * available and has not seen the queue stopped state performed
1964 * by netif_stop_subqueue above.
1965 */
1966 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1967 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1968 netif_start_subqueue(netdev, ring->queue_index);
1969 return bd_num;
1970 }
1971
1972 hns3_ring_stats_update(ring, tx_busy);
1973
1974 return -EBUSY;
1975 }
1976
hns3_clear_desc(struct hns3_enet_ring * ring,int next_to_use_orig)1977 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1978 {
1979 struct device *dev = ring_to_dev(ring);
1980 unsigned int i;
1981
1982 for (i = 0; i < ring->desc_num; i++) {
1983 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1984 struct hns3_desc_cb *desc_cb;
1985
1986 memset(desc, 0, sizeof(*desc));
1987
1988 /* check if this is where we started */
1989 if (ring->next_to_use == next_to_use_orig)
1990 break;
1991
1992 /* rollback one */
1993 ring_ptr_move_bw(ring, next_to_use);
1994
1995 desc_cb = &ring->desc_cb[ring->next_to_use];
1996
1997 if (!desc_cb->dma)
1998 continue;
1999
2000 /* unmap the descriptor dma address */
2001 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
2002 dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
2003 DMA_TO_DEVICE);
2004 else if (desc_cb->type &
2005 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
2006 hns3_tx_spare_rollback(ring, desc_cb->length);
2007 else if (desc_cb->length)
2008 dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
2009 DMA_TO_DEVICE);
2010
2011 desc_cb->length = 0;
2012 desc_cb->dma = 0;
2013 desc_cb->type = DESC_TYPE_UNKNOWN;
2014 }
2015 }
2016
hns3_fill_skb_to_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int type)2017 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
2018 struct sk_buff *skb, unsigned int type)
2019 {
2020 struct sk_buff *frag_skb;
2021 int i, ret, bd_num = 0;
2022
2023 ret = hns3_map_and_fill_desc(ring, skb, type);
2024 if (unlikely(ret < 0))
2025 return ret;
2026
2027 bd_num += ret;
2028
2029 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2030 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2031
2032 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
2033 if (unlikely(ret < 0))
2034 return ret;
2035
2036 bd_num += ret;
2037 }
2038
2039 skb_walk_frags(skb, frag_skb) {
2040 ret = hns3_fill_skb_to_desc(ring, frag_skb,
2041 DESC_TYPE_FRAGLIST_SKB);
2042 if (unlikely(ret < 0))
2043 return ret;
2044
2045 bd_num += ret;
2046 }
2047
2048 return bd_num;
2049 }
2050
hns3_tx_push_bd(struct hns3_enet_ring * ring,int num)2051 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num)
2052 {
2053 #define HNS3_BYTES_PER_64BIT 8
2054
2055 struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {};
2056 int offset = 0;
2057
2058 /* make sure everything is visible to device before
2059 * excuting tx push or updating doorbell
2060 */
2061 dma_wmb();
2062
2063 do {
2064 int idx = (ring->next_to_use - num + ring->desc_num) %
2065 ring->desc_num;
2066
2067 u64_stats_update_begin(&ring->syncp);
2068 ring->stats.tx_push++;
2069 u64_stats_update_end(&ring->syncp);
2070 memcpy(&desc[offset], &ring->desc[idx],
2071 sizeof(struct hns3_desc));
2072 offset++;
2073 } while (--num);
2074
2075 __iowrite64_copy(ring->tqp->mem_base, desc,
2076 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) /
2077 HNS3_BYTES_PER_64BIT);
2078 }
2079
hns3_tx_mem_doorbell(struct hns3_enet_ring * ring)2080 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring)
2081 {
2082 #define HNS3_MEM_DOORBELL_OFFSET 64
2083
2084 __le64 bd_num = cpu_to_le64((u64)ring->pending_buf);
2085
2086 /* make sure everything is visible to device before
2087 * excuting tx push or updating doorbell
2088 */
2089 dma_wmb();
2090
2091 __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET,
2092 &bd_num, 1);
2093 u64_stats_update_begin(&ring->syncp);
2094 ring->stats.tx_mem_doorbell += ring->pending_buf;
2095 u64_stats_update_end(&ring->syncp);
2096 }
2097
hns3_tx_doorbell(struct hns3_enet_ring * ring,int num,bool doorbell)2098 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2099 bool doorbell)
2100 {
2101 struct net_device *netdev = ring_to_netdev(ring);
2102 struct hns3_nic_priv *priv = netdev_priv(netdev);
2103
2104 /* when tx push is enabled, the packet whose number of BD below
2105 * HNS3_MAX_PUSH_BD_NUM can be pushed directly.
2106 */
2107 if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num &&
2108 !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) {
2109 /* This smp_store_release() pairs with smp_load_aquire() in
2110 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit
2111 * is updated.
2112 */
2113 smp_store_release(&ring->last_to_use, ring->next_to_use);
2114 hns3_tx_push_bd(ring, num);
2115 return;
2116 }
2117
2118 ring->pending_buf += num;
2119
2120 if (!doorbell) {
2121 hns3_ring_stats_update(ring, tx_more);
2122 return;
2123 }
2124
2125 /* This smp_store_release() pairs with smp_load_aquire() in
2126 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit is updated.
2127 */
2128 smp_store_release(&ring->last_to_use, ring->next_to_use);
2129
2130 if (ring->tqp->mem_base)
2131 hns3_tx_mem_doorbell(ring);
2132 else
2133 writel(ring->pending_buf,
2134 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
2135
2136 ring->pending_buf = 0;
2137 }
2138
hns3_tsyn(struct net_device * netdev,struct sk_buff * skb,struct hns3_desc * desc)2139 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2140 struct hns3_desc *desc)
2141 {
2142 struct hnae3_handle *h = hns3_get_handle(netdev);
2143
2144 if (!(h->ae_algo->ops->set_tx_hwts_info &&
2145 h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2146 return;
2147
2148 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2149 }
2150
hns3_handle_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb)2151 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2152 struct sk_buff *skb)
2153 {
2154 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2155 unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2156 unsigned int size = skb_headlen(skb);
2157 dma_addr_t dma;
2158 int bd_num = 0;
2159 u32 cb_len;
2160 void *buf;
2161 int ret;
2162
2163 if (skb->len <= ring->tx_copybreak) {
2164 size = skb->len;
2165 type = DESC_TYPE_BOUNCE_ALL;
2166 }
2167
2168 /* hns3_can_use_tx_bounce() is called to ensure the below
2169 * function can always return the tx buffer.
2170 */
2171 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2172
2173 ret = skb_copy_bits(skb, 0, buf, size);
2174 if (unlikely(ret < 0)) {
2175 hns3_tx_spare_rollback(ring, cb_len);
2176 hns3_ring_stats_update(ring, copy_bits_err);
2177 return ret;
2178 }
2179
2180 desc_cb->priv = skb;
2181 desc_cb->length = cb_len;
2182 desc_cb->dma = dma;
2183 desc_cb->type = type;
2184
2185 bd_num += hns3_fill_desc(ring, dma, size);
2186
2187 if (type == DESC_TYPE_BOUNCE_HEAD) {
2188 ret = hns3_fill_skb_to_desc(ring, skb,
2189 DESC_TYPE_BOUNCE_HEAD);
2190 if (unlikely(ret < 0))
2191 return ret;
2192
2193 bd_num += ret;
2194 }
2195
2196 dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2197 DMA_TO_DEVICE);
2198
2199 hns3_ring_stats_update(ring, tx_bounce);
2200
2201 return bd_num;
2202 }
2203
hns3_handle_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb)2204 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2205 struct sk_buff *skb)
2206 {
2207 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2208 u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2209 struct sg_table *sgt;
2210 int i, bd_num = 0;
2211 dma_addr_t dma;
2212 u32 cb_len;
2213 int nents;
2214
2215 if (skb_has_frag_list(skb))
2216 nfrag = HNS3_MAX_TSO_BD_NUM;
2217
2218 /* hns3_can_use_tx_sgl() is called to ensure the below
2219 * function can always return the tx buffer.
2220 */
2221 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2222 &dma, &cb_len);
2223
2224 /* scatterlist follows by the sg table */
2225 sgt->sgl = (struct scatterlist *)(sgt + 1);
2226 sg_init_table(sgt->sgl, nfrag);
2227 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2228 if (unlikely(nents < 0)) {
2229 hns3_tx_spare_rollback(ring, cb_len);
2230 hns3_ring_stats_update(ring, skb2sgl_err);
2231 return -ENOMEM;
2232 }
2233
2234 sgt->orig_nents = nents;
2235 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2236 DMA_TO_DEVICE);
2237 if (unlikely(!sgt->nents)) {
2238 hns3_tx_spare_rollback(ring, cb_len);
2239 hns3_ring_stats_update(ring, map_sg_err);
2240 return -ENOMEM;
2241 }
2242
2243 desc_cb->priv = skb;
2244 desc_cb->length = cb_len;
2245 desc_cb->dma = dma;
2246 desc_cb->type = DESC_TYPE_SGL_SKB;
2247
2248 for (i = 0; i < sgt->nents; i++)
2249 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2250 sg_dma_len(sgt->sgl + i));
2251 hns3_ring_stats_update(ring, tx_sgl);
2252
2253 return bd_num;
2254 }
2255
hns3_handle_desc_filling(struct hns3_enet_ring * ring,struct sk_buff * skb)2256 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2257 struct sk_buff *skb)
2258 {
2259 u32 space;
2260
2261 if (!ring->tx_spare)
2262 goto out;
2263
2264 space = hns3_tx_spare_space(ring);
2265
2266 if (hns3_can_use_tx_sgl(ring, skb, space))
2267 return hns3_handle_tx_sgl(ring, skb);
2268
2269 if (hns3_can_use_tx_bounce(ring, skb, space))
2270 return hns3_handle_tx_bounce(ring, skb);
2271
2272 out:
2273 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2274 }
2275
hns3_handle_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,int next_to_use_head)2276 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring,
2277 struct sk_buff *skb,
2278 struct hns3_desc_cb *desc_cb,
2279 int next_to_use_head)
2280 {
2281 int ret;
2282
2283 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2284 desc_cb);
2285 if (unlikely(ret < 0))
2286 goto fill_err;
2287
2288 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2289 * zero, which is unlikely, and 'ret > 0' means how many tx desc
2290 * need to be notified to the hw.
2291 */
2292 ret = hns3_handle_desc_filling(ring, skb);
2293 if (likely(ret > 0))
2294 return ret;
2295
2296 fill_err:
2297 hns3_clear_desc(ring, next_to_use_head);
2298 return ret;
2299 }
2300
hns3_nic_net_xmit(struct sk_buff * skb,struct net_device * netdev)2301 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
2302 {
2303 struct hns3_nic_priv *priv = netdev_priv(netdev);
2304 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
2305 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2306 struct netdev_queue *dev_queue;
2307 int pre_ntu, ret;
2308 bool doorbell;
2309
2310 /* Hardware can only handle short frames above 32 bytes */
2311 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2312 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2313
2314 hns3_ring_stats_update(ring, sw_err_cnt);
2315
2316 return NETDEV_TX_OK;
2317 }
2318
2319 /* Prefetch the data used later */
2320 prefetch(skb->data);
2321
2322 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
2323 if (unlikely(ret <= 0)) {
2324 if (ret == -EBUSY) {
2325 hns3_tx_doorbell(ring, 0, true);
2326 return NETDEV_TX_BUSY;
2327 }
2328
2329 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
2330 goto out_err_tx_ok;
2331 }
2332
2333 ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use);
2334 if (unlikely(ret <= 0))
2335 goto out_err_tx_ok;
2336
2337 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2338 (ring->desc_num - 1);
2339
2340 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2341 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2342
2343 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2344 cpu_to_le16(BIT(HNS3_TXD_FE_B));
2345 trace_hns3_tx_desc(ring, pre_ntu);
2346
2347 skb_tx_timestamp(skb);
2348
2349 /* Complete translate all packets */
2350 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
2351 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
2352 netdev_xmit_more());
2353 hns3_tx_doorbell(ring, ret, doorbell);
2354
2355 return NETDEV_TX_OK;
2356
2357 out_err_tx_ok:
2358 dev_kfree_skb_any(skb);
2359 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2360 return NETDEV_TX_OK;
2361 }
2362
hns3_nic_net_set_mac_address(struct net_device * netdev,void * p)2363 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2364 {
2365 char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN];
2366 char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN];
2367 struct hnae3_handle *h = hns3_get_handle(netdev);
2368 struct sockaddr *mac_addr = p;
2369 int ret;
2370
2371 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2372 return -EADDRNOTAVAIL;
2373
2374 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2375 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2376 netdev_info(netdev, "already using mac address %s\n",
2377 format_mac_addr_sa);
2378 return 0;
2379 }
2380
2381 /* For VF device, if there is a perm_addr, then the user will not
2382 * be allowed to change the address.
2383 */
2384 if (!hns3_is_phys_func(h->pdev) &&
2385 !is_zero_ether_addr(netdev->perm_addr)) {
2386 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr);
2387 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2388 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n",
2389 format_mac_addr_perm, format_mac_addr_sa);
2390 return -EPERM;
2391 }
2392
2393 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
2394 if (ret) {
2395 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2396 return ret;
2397 }
2398
2399 eth_hw_addr_set(netdev, mac_addr->sa_data);
2400
2401 return 0;
2402 }
2403
hns3_nic_do_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2404 static int hns3_nic_do_ioctl(struct net_device *netdev,
2405 struct ifreq *ifr, int cmd)
2406 {
2407 struct hnae3_handle *h = hns3_get_handle(netdev);
2408
2409 if (!netif_running(netdev))
2410 return -EINVAL;
2411
2412 if (!h->ae_algo->ops->do_ioctl)
2413 return -EOPNOTSUPP;
2414
2415 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2416 }
2417
hns3_nic_set_features(struct net_device * netdev,netdev_features_t features)2418 static int hns3_nic_set_features(struct net_device *netdev,
2419 netdev_features_t features)
2420 {
2421 netdev_features_t changed = netdev->features ^ features;
2422 struct hns3_nic_priv *priv = netdev_priv(netdev);
2423 struct hnae3_handle *h = priv->ae_handle;
2424 bool enable;
2425 int ret;
2426
2427 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
2428 enable = !!(features & NETIF_F_GRO_HW);
2429 ret = h->ae_algo->ops->set_gro_en(h, enable);
2430 if (ret)
2431 return ret;
2432 }
2433
2434 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2435 h->ae_algo->ops->enable_hw_strip_rxvtag) {
2436 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2437 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
2438 if (ret)
2439 return ret;
2440 }
2441
2442 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
2443 enable = !!(features & NETIF_F_NTUPLE);
2444 h->ae_algo->ops->enable_fd(h, enable);
2445 }
2446
2447 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2448 h->ae_algo->ops->cls_flower_active(h)) {
2449 netdev_err(netdev,
2450 "there are offloaded TC filters active, cannot disable HW TC offload");
2451 return -EINVAL;
2452 }
2453
2454 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2455 h->ae_algo->ops->enable_vlan_filter) {
2456 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2457 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2458 if (ret)
2459 return ret;
2460 }
2461
2462 return 0;
2463 }
2464
hns3_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2465 static netdev_features_t hns3_features_check(struct sk_buff *skb,
2466 struct net_device *dev,
2467 netdev_features_t features)
2468 {
2469 #define HNS3_MAX_HDR_LEN 480U
2470 #define HNS3_MAX_L4_HDR_LEN 60U
2471
2472 size_t len;
2473
2474 if (skb->ip_summed != CHECKSUM_PARTIAL)
2475 return features;
2476
2477 if (skb->encapsulation)
2478 len = skb_inner_transport_offset(skb);
2479 else
2480 len = skb_transport_offset(skb);
2481
2482 /* Assume L4 is 60 byte as TCP is the only protocol with a
2483 * a flexible value, and it's max len is 60 bytes.
2484 */
2485 len += HNS3_MAX_L4_HDR_LEN;
2486
2487 /* Hardware only supports checksum on the skb with a max header
2488 * len of 480 bytes.
2489 */
2490 if (len > HNS3_MAX_HDR_LEN)
2491 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2492
2493 return features;
2494 }
2495
hns3_fetch_stats(struct rtnl_link_stats64 * stats,struct hns3_enet_ring * ring,bool is_tx)2496 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
2497 struct hns3_enet_ring *ring, bool is_tx)
2498 {
2499 unsigned int start;
2500
2501 do {
2502 start = u64_stats_fetch_begin(&ring->syncp);
2503 if (is_tx) {
2504 stats->tx_bytes += ring->stats.tx_bytes;
2505 stats->tx_packets += ring->stats.tx_pkts;
2506 stats->tx_dropped += ring->stats.sw_err_cnt;
2507 stats->tx_dropped += ring->stats.tx_vlan_err;
2508 stats->tx_dropped += ring->stats.tx_l4_proto_err;
2509 stats->tx_dropped += ring->stats.tx_l2l3l4_err;
2510 stats->tx_dropped += ring->stats.tx_tso_err;
2511 stats->tx_dropped += ring->stats.over_max_recursion;
2512 stats->tx_dropped += ring->stats.hw_limitation;
2513 stats->tx_dropped += ring->stats.copy_bits_err;
2514 stats->tx_dropped += ring->stats.skb2sgl_err;
2515 stats->tx_dropped += ring->stats.map_sg_err;
2516 stats->tx_errors += ring->stats.sw_err_cnt;
2517 stats->tx_errors += ring->stats.tx_vlan_err;
2518 stats->tx_errors += ring->stats.tx_l4_proto_err;
2519 stats->tx_errors += ring->stats.tx_l2l3l4_err;
2520 stats->tx_errors += ring->stats.tx_tso_err;
2521 stats->tx_errors += ring->stats.over_max_recursion;
2522 stats->tx_errors += ring->stats.hw_limitation;
2523 stats->tx_errors += ring->stats.copy_bits_err;
2524 stats->tx_errors += ring->stats.skb2sgl_err;
2525 stats->tx_errors += ring->stats.map_sg_err;
2526 } else {
2527 stats->rx_bytes += ring->stats.rx_bytes;
2528 stats->rx_packets += ring->stats.rx_pkts;
2529 stats->rx_dropped += ring->stats.l2_err;
2530 stats->rx_errors += ring->stats.l2_err;
2531 stats->rx_errors += ring->stats.l3l4_csum_err;
2532 stats->rx_crc_errors += ring->stats.l2_err;
2533 stats->multicast += ring->stats.rx_multicast;
2534 stats->rx_length_errors += ring->stats.err_pkt_len;
2535 }
2536 } while (u64_stats_fetch_retry(&ring->syncp, start));
2537 }
2538
hns3_nic_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)2539 static void hns3_nic_get_stats64(struct net_device *netdev,
2540 struct rtnl_link_stats64 *stats)
2541 {
2542 struct hns3_nic_priv *priv = netdev_priv(netdev);
2543 int queue_num = priv->ae_handle->kinfo.num_tqps;
2544 struct hnae3_handle *handle = priv->ae_handle;
2545 struct rtnl_link_stats64 ring_total_stats;
2546 struct hns3_enet_ring *ring;
2547 unsigned int idx;
2548
2549 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2550 return;
2551
2552 handle->ae_algo->ops->update_stats(handle);
2553
2554 memset(&ring_total_stats, 0, sizeof(ring_total_stats));
2555 for (idx = 0; idx < queue_num; idx++) {
2556 /* fetch the tx stats */
2557 ring = &priv->ring[idx];
2558 hns3_fetch_stats(&ring_total_stats, ring, true);
2559
2560 /* fetch the rx stats */
2561 ring = &priv->ring[idx + queue_num];
2562 hns3_fetch_stats(&ring_total_stats, ring, false);
2563 }
2564
2565 stats->tx_bytes = ring_total_stats.tx_bytes;
2566 stats->tx_packets = ring_total_stats.tx_packets;
2567 stats->rx_bytes = ring_total_stats.rx_bytes;
2568 stats->rx_packets = ring_total_stats.rx_packets;
2569
2570 stats->rx_errors = ring_total_stats.rx_errors;
2571 stats->multicast = ring_total_stats.multicast;
2572 stats->rx_length_errors = ring_total_stats.rx_length_errors;
2573 stats->rx_crc_errors = ring_total_stats.rx_crc_errors;
2574 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2575
2576 stats->tx_errors = ring_total_stats.tx_errors;
2577 stats->rx_dropped = ring_total_stats.rx_dropped;
2578 stats->tx_dropped = ring_total_stats.tx_dropped;
2579 stats->collisions = netdev->stats.collisions;
2580 stats->rx_over_errors = netdev->stats.rx_over_errors;
2581 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2582 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2583 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2584 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2585 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2586 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2587 stats->tx_window_errors = netdev->stats.tx_window_errors;
2588 stats->rx_compressed = netdev->stats.rx_compressed;
2589 stats->tx_compressed = netdev->stats.tx_compressed;
2590 }
2591
hns3_setup_tc(struct net_device * netdev,void * type_data)2592 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
2593 {
2594 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
2595 struct hnae3_knic_private_info *kinfo;
2596 u8 tc = mqprio_qopt->qopt.num_tc;
2597 u16 mode = mqprio_qopt->mode;
2598 u8 hw = mqprio_qopt->qopt.hw;
2599 struct hnae3_handle *h;
2600
2601 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2602 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2603 return -EOPNOTSUPP;
2604
2605 if (tc > HNAE3_MAX_TC)
2606 return -EINVAL;
2607
2608 if (!netdev)
2609 return -EINVAL;
2610
2611 h = hns3_get_handle(netdev);
2612 kinfo = &h->kinfo;
2613
2614 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2615
2616 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
2617 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
2618 }
2619
hns3_setup_tc_cls_flower(struct hns3_nic_priv * priv,struct flow_cls_offload * flow)2620 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2621 struct flow_cls_offload *flow)
2622 {
2623 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2624 struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2625
2626 switch (flow->command) {
2627 case FLOW_CLS_REPLACE:
2628 if (h->ae_algo->ops->add_cls_flower)
2629 return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2630 break;
2631 case FLOW_CLS_DESTROY:
2632 if (h->ae_algo->ops->del_cls_flower)
2633 return h->ae_algo->ops->del_cls_flower(h, flow);
2634 break;
2635 default:
2636 break;
2637 }
2638
2639 return -EOPNOTSUPP;
2640 }
2641
hns3_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2642 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2643 void *cb_priv)
2644 {
2645 struct hns3_nic_priv *priv = cb_priv;
2646
2647 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2648 return -EOPNOTSUPP;
2649
2650 switch (type) {
2651 case TC_SETUP_CLSFLOWER:
2652 return hns3_setup_tc_cls_flower(priv, type_data);
2653 default:
2654 return -EOPNOTSUPP;
2655 }
2656 }
2657
2658 static LIST_HEAD(hns3_block_cb_list);
2659
hns3_nic_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)2660 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
2661 void *type_data)
2662 {
2663 struct hns3_nic_priv *priv = netdev_priv(dev);
2664 int ret;
2665
2666 switch (type) {
2667 case TC_SETUP_QDISC_MQPRIO:
2668 ret = hns3_setup_tc(dev, type_data);
2669 break;
2670 case TC_SETUP_BLOCK:
2671 ret = flow_block_cb_setup_simple(type_data,
2672 &hns3_block_cb_list,
2673 hns3_setup_tc_block_cb,
2674 priv, priv, true);
2675 break;
2676 default:
2677 return -EOPNOTSUPP;
2678 }
2679
2680 return ret;
2681 }
2682
hns3_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2683 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2684 __be16 proto, u16 vid)
2685 {
2686 struct hnae3_handle *h = hns3_get_handle(netdev);
2687 int ret = -EIO;
2688
2689 if (h->ae_algo->ops->set_vlan_filter)
2690 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2691
2692 return ret;
2693 }
2694
hns3_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2695 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2696 __be16 proto, u16 vid)
2697 {
2698 struct hnae3_handle *h = hns3_get_handle(netdev);
2699 int ret = -EIO;
2700
2701 if (h->ae_algo->ops->set_vlan_filter)
2702 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2703
2704 return ret;
2705 }
2706
hns3_ndo_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)2707 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2708 u8 qos, __be16 vlan_proto)
2709 {
2710 struct hnae3_handle *h = hns3_get_handle(netdev);
2711 int ret = -EIO;
2712
2713 netif_dbg(h, drv, netdev,
2714 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2715 vf, vlan, qos, ntohs(vlan_proto));
2716
2717 if (h->ae_algo->ops->set_vf_vlan_filter)
2718 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
2719 qos, vlan_proto);
2720
2721 return ret;
2722 }
2723
hns3_set_vf_spoofchk(struct net_device * netdev,int vf,bool enable)2724 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2725 {
2726 struct hnae3_handle *handle = hns3_get_handle(netdev);
2727
2728 if (hns3_nic_resetting(netdev))
2729 return -EBUSY;
2730
2731 if (!handle->ae_algo->ops->set_vf_spoofchk)
2732 return -EOPNOTSUPP;
2733
2734 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2735 }
2736
hns3_set_vf_trust(struct net_device * netdev,int vf,bool enable)2737 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2738 {
2739 struct hnae3_handle *handle = hns3_get_handle(netdev);
2740
2741 if (!handle->ae_algo->ops->set_vf_trust)
2742 return -EOPNOTSUPP;
2743
2744 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2745 }
2746
hns3_nic_change_mtu(struct net_device * netdev,int new_mtu)2747 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2748 {
2749 struct hnae3_handle *h = hns3_get_handle(netdev);
2750 int ret;
2751
2752 if (hns3_nic_resetting(netdev))
2753 return -EBUSY;
2754
2755 if (!h->ae_algo->ops->set_mtu)
2756 return -EOPNOTSUPP;
2757
2758 netif_dbg(h, drv, netdev,
2759 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2760
2761 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
2762 if (ret)
2763 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2764 ret);
2765 else
2766 WRITE_ONCE(netdev->mtu, new_mtu);
2767
2768 return ret;
2769 }
2770
hns3_get_timeout_queue(struct net_device * ndev)2771 static int hns3_get_timeout_queue(struct net_device *ndev)
2772 {
2773 int i;
2774
2775 /* Find the stopped queue the same way the stack does */
2776 for (i = 0; i < ndev->num_tx_queues; i++) {
2777 struct netdev_queue *q;
2778 unsigned long trans_start;
2779
2780 q = netdev_get_tx_queue(ndev, i);
2781 trans_start = READ_ONCE(q->trans_start);
2782 if (netif_xmit_stopped(q) &&
2783 time_after(jiffies,
2784 (trans_start + ndev->watchdog_timeo))) {
2785 #ifdef CONFIG_BQL
2786 struct dql *dql = &q->dql;
2787
2788 netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n",
2789 dql->last_obj_cnt, dql->num_queued,
2790 dql->adj_limit, dql->num_completed);
2791 #endif
2792 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2793 q->state,
2794 jiffies_to_msecs(jiffies - trans_start));
2795 break;
2796 }
2797 }
2798
2799 return i;
2800 }
2801
hns3_dump_queue_stats(struct net_device * ndev,struct hns3_enet_ring * tx_ring,int timeout_queue)2802 static void hns3_dump_queue_stats(struct net_device *ndev,
2803 struct hns3_enet_ring *tx_ring,
2804 int timeout_queue)
2805 {
2806 struct napi_struct *napi = &tx_ring->tqp_vector->napi;
2807 struct hns3_nic_priv *priv = netdev_priv(ndev);
2808
2809 netdev_info(ndev,
2810 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2811 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2812 tx_ring->next_to_clean, napi->state);
2813
2814 netdev_info(ndev,
2815 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
2816 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
2817 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
2818
2819 netdev_info(ndev,
2820 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2821 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
2822 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2823
2824 netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n",
2825 tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell);
2826 }
2827
hns3_dump_queue_reg(struct net_device * ndev,struct hns3_enet_ring * tx_ring)2828 static void hns3_dump_queue_reg(struct net_device *ndev,
2829 struct hns3_enet_ring *tx_ring)
2830 {
2831 netdev_info(ndev,
2832 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2833 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG),
2834 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG),
2835 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG),
2836 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG),
2837 readl(tx_ring->tqp_vector->mask_addr));
2838 netdev_info(ndev,
2839 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2840 hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG),
2841 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG),
2842 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG),
2843 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG),
2844 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG),
2845 hns3_tqp_read_reg(tx_ring,
2846 HNS3_RING_TX_RING_EBD_OFFSET_REG));
2847 }
2848
hns3_get_tx_timeo_queue_info(struct net_device * ndev)2849 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2850 {
2851 struct hns3_nic_priv *priv = netdev_priv(ndev);
2852 struct hnae3_handle *h = hns3_get_handle(ndev);
2853 struct hns3_enet_ring *tx_ring;
2854 int timeout_queue;
2855
2856 timeout_queue = hns3_get_timeout_queue(ndev);
2857 if (timeout_queue >= ndev->num_tx_queues) {
2858 netdev_info(ndev,
2859 "no netdev TX timeout queue found, timeout count: %llu\n",
2860 priv->tx_timeout_count);
2861 return false;
2862 }
2863
2864 priv->tx_timeout_count++;
2865
2866 tx_ring = &priv->ring[timeout_queue];
2867 hns3_dump_queue_stats(ndev, tx_ring, timeout_queue);
2868
2869 /* When mac received many pause frames continuous, it's unable to send
2870 * packets, which may cause tx timeout
2871 */
2872 if (h->ae_algo->ops->get_mac_stats) {
2873 struct hns3_mac_stats mac_stats;
2874
2875 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
2876 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
2877 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
2878 }
2879
2880 hns3_dump_queue_reg(ndev, tx_ring);
2881
2882 return true;
2883 }
2884
hns3_nic_net_timeout(struct net_device * ndev,unsigned int txqueue)2885 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
2886 {
2887 struct hns3_nic_priv *priv = netdev_priv(ndev);
2888 struct hnae3_handle *h = priv->ae_handle;
2889
2890 if (!hns3_get_tx_timeo_queue_info(ndev))
2891 return;
2892
2893 /* request the reset, and let the hclge to determine
2894 * which reset level should be done
2895 */
2896 if (h->ae_algo->ops->reset_event)
2897 h->ae_algo->ops->reset_event(h->pdev, h);
2898 }
2899
2900 #ifdef CONFIG_RFS_ACCEL
hns3_rx_flow_steer(struct net_device * dev,const struct sk_buff * skb,u16 rxq_index,u32 flow_id)2901 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2902 u16 rxq_index, u32 flow_id)
2903 {
2904 struct hnae3_handle *h = hns3_get_handle(dev);
2905 struct flow_keys fkeys;
2906
2907 if (!h->ae_algo->ops->add_arfs_entry)
2908 return -EOPNOTSUPP;
2909
2910 if (skb->encapsulation)
2911 return -EPROTONOSUPPORT;
2912
2913 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2914 return -EPROTONOSUPPORT;
2915
2916 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2917 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2918 (fkeys.basic.ip_proto != IPPROTO_TCP &&
2919 fkeys.basic.ip_proto != IPPROTO_UDP))
2920 return -EPROTONOSUPPORT;
2921
2922 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2923 }
2924 #endif
2925
hns3_nic_get_vf_config(struct net_device * ndev,int vf,struct ifla_vf_info * ivf)2926 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2927 struct ifla_vf_info *ivf)
2928 {
2929 struct hnae3_handle *h = hns3_get_handle(ndev);
2930
2931 if (!h->ae_algo->ops->get_vf_config)
2932 return -EOPNOTSUPP;
2933
2934 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2935 }
2936
hns3_nic_set_vf_link_state(struct net_device * ndev,int vf,int link_state)2937 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2938 int link_state)
2939 {
2940 struct hnae3_handle *h = hns3_get_handle(ndev);
2941
2942 if (!h->ae_algo->ops->set_vf_link_state)
2943 return -EOPNOTSUPP;
2944
2945 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2946 }
2947
hns3_nic_set_vf_rate(struct net_device * ndev,int vf,int min_tx_rate,int max_tx_rate)2948 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2949 int min_tx_rate, int max_tx_rate)
2950 {
2951 struct hnae3_handle *h = hns3_get_handle(ndev);
2952
2953 if (!h->ae_algo->ops->set_vf_rate)
2954 return -EOPNOTSUPP;
2955
2956 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2957 false);
2958 }
2959
hns3_nic_set_vf_mac(struct net_device * netdev,int vf_id,u8 * mac)2960 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2961 {
2962 struct hnae3_handle *h = hns3_get_handle(netdev);
2963 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
2964
2965 if (!h->ae_algo->ops->set_vf_mac)
2966 return -EOPNOTSUPP;
2967
2968 if (is_multicast_ether_addr(mac)) {
2969 hnae3_format_mac_addr(format_mac_addr, mac);
2970 netdev_err(netdev,
2971 "Invalid MAC:%s specified. Could not set MAC\n",
2972 format_mac_addr);
2973 return -EINVAL;
2974 }
2975
2976 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2977 }
2978
2979 #define HNS3_INVALID_DSCP 0xff
2980 #define HNS3_DSCP_SHIFT 2
2981
hns3_get_skb_dscp(struct sk_buff * skb)2982 static u8 hns3_get_skb_dscp(struct sk_buff *skb)
2983 {
2984 __be16 protocol = skb->protocol;
2985 u8 dscp = HNS3_INVALID_DSCP;
2986
2987 if (protocol == htons(ETH_P_8021Q))
2988 protocol = vlan_get_protocol(skb);
2989
2990 if (protocol == htons(ETH_P_IP))
2991 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT;
2992 else if (protocol == htons(ETH_P_IPV6))
2993 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT;
2994
2995 return dscp;
2996 }
2997
hns3_nic_select_queue(struct net_device * netdev,struct sk_buff * skb,struct net_device * sb_dev)2998 static u16 hns3_nic_select_queue(struct net_device *netdev,
2999 struct sk_buff *skb,
3000 struct net_device *sb_dev)
3001 {
3002 struct hnae3_handle *h = hns3_get_handle(netdev);
3003 u8 dscp;
3004
3005 if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP ||
3006 !h->ae_algo->ops->get_dscp_prio)
3007 goto out;
3008
3009 dscp = hns3_get_skb_dscp(skb);
3010 if (unlikely(dscp >= HNAE3_MAX_DSCP))
3011 goto out;
3012
3013 skb->priority = h->kinfo.dscp_prio[dscp];
3014 if (skb->priority == HNAE3_PRIO_ID_INVALID)
3015 skb->priority = 0;
3016
3017 out:
3018 return netdev_pick_tx(netdev, skb, sb_dev);
3019 }
3020
3021 static const struct net_device_ops hns3_nic_netdev_ops = {
3022 .ndo_open = hns3_nic_net_open,
3023 .ndo_stop = hns3_nic_net_stop,
3024 .ndo_start_xmit = hns3_nic_net_xmit,
3025 .ndo_tx_timeout = hns3_nic_net_timeout,
3026 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
3027 .ndo_eth_ioctl = hns3_nic_do_ioctl,
3028 .ndo_change_mtu = hns3_nic_change_mtu,
3029 .ndo_set_features = hns3_nic_set_features,
3030 .ndo_features_check = hns3_features_check,
3031 .ndo_get_stats64 = hns3_nic_get_stats64,
3032 .ndo_setup_tc = hns3_nic_setup_tc,
3033 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
3034 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
3035 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
3036 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
3037 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
3038 .ndo_set_vf_trust = hns3_set_vf_trust,
3039 #ifdef CONFIG_RFS_ACCEL
3040 .ndo_rx_flow_steer = hns3_rx_flow_steer,
3041 #endif
3042 .ndo_get_vf_config = hns3_nic_get_vf_config,
3043 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
3044 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
3045 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
3046 .ndo_select_queue = hns3_nic_select_queue,
3047 };
3048
hns3_is_phys_func(struct pci_dev * pdev)3049 bool hns3_is_phys_func(struct pci_dev *pdev)
3050 {
3051 u32 dev_id = pdev->device;
3052
3053 switch (dev_id) {
3054 case HNAE3_DEV_ID_GE:
3055 case HNAE3_DEV_ID_25GE:
3056 case HNAE3_DEV_ID_25GE_RDMA:
3057 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
3058 case HNAE3_DEV_ID_50GE_RDMA:
3059 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
3060 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
3061 case HNAE3_DEV_ID_200G_RDMA:
3062 return true;
3063 case HNAE3_DEV_ID_VF:
3064 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
3065 return false;
3066 default:
3067 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
3068 dev_id);
3069 }
3070
3071 return false;
3072 }
3073
hns3_disable_sriov(struct pci_dev * pdev)3074 static void hns3_disable_sriov(struct pci_dev *pdev)
3075 {
3076 /* If our VFs are assigned we cannot shut down SR-IOV
3077 * without causing issues, so just leave the hardware
3078 * available but disabled
3079 */
3080 if (pci_vfs_assigned(pdev)) {
3081 dev_warn(&pdev->dev,
3082 "disabling driver while VFs are assigned\n");
3083 return;
3084 }
3085
3086 pci_disable_sriov(pdev);
3087 }
3088
3089 /* hns3_probe - Device initialization routine
3090 * @pdev: PCI device information struct
3091 * @ent: entry in hns3_pci_tbl
3092 *
3093 * hns3_probe initializes a PF identified by a pci_dev structure.
3094 * The OS initialization, configuring of the PF private structure,
3095 * and a hardware reset occur.
3096 *
3097 * Returns 0 on success, negative on failure
3098 */
hns3_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3099 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3100 {
3101 struct hnae3_ae_dev *ae_dev;
3102 int ret;
3103
3104 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
3105 if (!ae_dev)
3106 return -ENOMEM;
3107
3108 ae_dev->pdev = pdev;
3109 ae_dev->flag = ent->driver_data;
3110 pci_set_drvdata(pdev, ae_dev);
3111
3112 ret = hnae3_register_ae_dev(ae_dev);
3113 if (ret)
3114 pci_set_drvdata(pdev, NULL);
3115
3116 return ret;
3117 }
3118
3119 /**
3120 * hns3_clean_vf_config
3121 * @pdev: pointer to a pci_dev structure
3122 * @num_vfs: number of VFs allocated
3123 *
3124 * Clean residual vf config after disable sriov
3125 **/
hns3_clean_vf_config(struct pci_dev * pdev,int num_vfs)3126 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs)
3127 {
3128 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3129
3130 if (ae_dev->ops->clean_vf_config)
3131 ae_dev->ops->clean_vf_config(ae_dev, num_vfs);
3132 }
3133
3134 /* hns3_remove - Device removal routine
3135 * @pdev: PCI device information struct
3136 */
hns3_remove(struct pci_dev * pdev)3137 static void hns3_remove(struct pci_dev *pdev)
3138 {
3139 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3140
3141 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
3142 hns3_disable_sriov(pdev);
3143
3144 hnae3_unregister_ae_dev(ae_dev);
3145 pci_set_drvdata(pdev, NULL);
3146 }
3147
3148 /**
3149 * hns3_pci_sriov_configure
3150 * @pdev: pointer to a pci_dev structure
3151 * @num_vfs: number of VFs to allocate
3152 *
3153 * Enable or change the number of VFs. Called when the user updates the number
3154 * of VFs in sysfs.
3155 **/
hns3_pci_sriov_configure(struct pci_dev * pdev,int num_vfs)3156 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
3157 {
3158 int ret;
3159
3160 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
3161 dev_warn(&pdev->dev, "Can not config SRIOV\n");
3162 return -EINVAL;
3163 }
3164
3165 if (num_vfs) {
3166 ret = pci_enable_sriov(pdev, num_vfs);
3167 if (ret)
3168 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
3169 else
3170 return num_vfs;
3171 } else if (!pci_vfs_assigned(pdev)) {
3172 int num_vfs_pre = pci_num_vf(pdev);
3173
3174 pci_disable_sriov(pdev);
3175 hns3_clean_vf_config(pdev, num_vfs_pre);
3176 } else {
3177 dev_warn(&pdev->dev,
3178 "Unable to free VFs because some are assigned to VMs.\n");
3179 }
3180
3181 return 0;
3182 }
3183
hns3_shutdown(struct pci_dev * pdev)3184 static void hns3_shutdown(struct pci_dev *pdev)
3185 {
3186 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3187
3188 hnae3_unregister_ae_dev(ae_dev);
3189 pci_set_drvdata(pdev, NULL);
3190
3191 if (system_state == SYSTEM_POWER_OFF)
3192 pci_set_power_state(pdev, PCI_D3hot);
3193 }
3194
hns3_suspend(struct device * dev)3195 static int __maybe_unused hns3_suspend(struct device *dev)
3196 {
3197 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3198
3199 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3200 dev_info(dev, "Begin to suspend.\n");
3201 if (ae_dev->ops && ae_dev->ops->reset_prepare)
3202 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3203 }
3204
3205 return 0;
3206 }
3207
hns3_resume(struct device * dev)3208 static int __maybe_unused hns3_resume(struct device *dev)
3209 {
3210 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3211
3212 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3213 dev_info(dev, "Begin to resume.\n");
3214 if (ae_dev->ops && ae_dev->ops->reset_done)
3215 ae_dev->ops->reset_done(ae_dev);
3216 }
3217
3218 return 0;
3219 }
3220
hns3_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3221 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3222 pci_channel_state_t state)
3223 {
3224 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3225 pci_ers_result_t ret;
3226
3227 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
3228
3229 if (state == pci_channel_io_perm_failure)
3230 return PCI_ERS_RESULT_DISCONNECT;
3231
3232 if (!ae_dev || !ae_dev->ops) {
3233 dev_err(&pdev->dev,
3234 "Can't recover - error happened before device initialized\n");
3235 return PCI_ERS_RESULT_NONE;
3236 }
3237
3238 if (ae_dev->ops->handle_hw_ras_error)
3239 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
3240 else
3241 return PCI_ERS_RESULT_NONE;
3242
3243 return ret;
3244 }
3245
hns3_slot_reset(struct pci_dev * pdev)3246 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3247 {
3248 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3249 const struct hnae3_ae_ops *ops;
3250 enum hnae3_reset_type reset_type;
3251 struct device *dev = &pdev->dev;
3252
3253 if (!ae_dev || !ae_dev->ops)
3254 return PCI_ERS_RESULT_NONE;
3255
3256 ops = ae_dev->ops;
3257 /* request the reset */
3258 if (ops->reset_event && ops->get_reset_level &&
3259 ops->set_default_reset_request) {
3260 if (ae_dev->hw_err_reset_req) {
3261 reset_type = ops->get_reset_level(ae_dev,
3262 &ae_dev->hw_err_reset_req);
3263 ops->set_default_reset_request(ae_dev, reset_type);
3264 dev_info(dev, "requesting reset due to PCI error\n");
3265 ops->reset_event(pdev, NULL);
3266 }
3267
3268 return PCI_ERS_RESULT_RECOVERED;
3269 }
3270
3271 return PCI_ERS_RESULT_DISCONNECT;
3272 }
3273
hns3_reset_prepare(struct pci_dev * pdev)3274 static void hns3_reset_prepare(struct pci_dev *pdev)
3275 {
3276 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3277
3278 dev_info(&pdev->dev, "FLR prepare\n");
3279 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3280 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
3281 }
3282
hns3_reset_done(struct pci_dev * pdev)3283 static void hns3_reset_done(struct pci_dev *pdev)
3284 {
3285 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3286
3287 dev_info(&pdev->dev, "FLR done\n");
3288 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3289 ae_dev->ops->reset_done(ae_dev);
3290 }
3291
3292 static const struct pci_error_handlers hns3_err_handler = {
3293 .error_detected = hns3_error_detected,
3294 .slot_reset = hns3_slot_reset,
3295 .reset_prepare = hns3_reset_prepare,
3296 .reset_done = hns3_reset_done,
3297 };
3298
3299 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3300
3301 static struct pci_driver hns3_driver = {
3302 .name = hns3_driver_name,
3303 .id_table = hns3_pci_tbl,
3304 .probe = hns3_probe,
3305 .remove = hns3_remove,
3306 .shutdown = hns3_shutdown,
3307 .driver.pm = &hns3_pm_ops,
3308 .sriov_configure = hns3_pci_sriov_configure,
3309 .err_handler = &hns3_err_handler,
3310 };
3311
3312 /* set default feature to hns3 */
hns3_set_default_feature(struct net_device * netdev)3313 static void hns3_set_default_feature(struct net_device *netdev)
3314 {
3315 struct hnae3_handle *h = hns3_get_handle(netdev);
3316 struct pci_dev *pdev = h->pdev;
3317 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3318
3319 netdev->priv_flags |= IFF_UNICAST_FLT;
3320
3321 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3322 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3323 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3324 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3325 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
3326 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3327
3328 if (hnae3_ae_dev_gro_supported(ae_dev))
3329 netdev->features |= NETIF_F_GRO_HW;
3330
3331 if (hnae3_ae_dev_fd_supported(ae_dev))
3332 netdev->features |= NETIF_F_NTUPLE;
3333
3334 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
3335 netdev->features |= NETIF_F_GSO_UDP_L4;
3336
3337 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
3338 netdev->features |= NETIF_F_HW_CSUM;
3339 else
3340 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3341
3342 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3343 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3344
3345 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
3346 netdev->features |= NETIF_F_HW_TC;
3347
3348 netdev->hw_features |= netdev->features;
3349 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3350 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3351
3352 netdev->vlan_features |= netdev->features &
3353 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3354 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3355 NETIF_F_HW_TC);
3356
3357 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
3358
3359 /* The device_version V3 hardware can't offload the checksum for IP in
3360 * GRE packets, but can do it for NvGRE. So default to disable the
3361 * checksum and GSO offload for GRE.
3362 */
3363 if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) {
3364 netdev->features &= ~NETIF_F_GSO_GRE;
3365 netdev->features &= ~NETIF_F_GSO_GRE_CSUM;
3366 }
3367 }
3368
hns3_alloc_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3369 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3370 struct hns3_desc_cb *cb)
3371 {
3372 unsigned int order = hns3_page_order(ring);
3373 struct page *p;
3374
3375 if (ring->page_pool) {
3376 p = page_pool_dev_alloc_frag(ring->page_pool,
3377 &cb->page_offset,
3378 hns3_buf_size(ring));
3379 if (unlikely(!p))
3380 return -ENOMEM;
3381
3382 cb->priv = p;
3383 cb->buf = page_address(p);
3384 cb->dma = page_pool_get_dma_addr(p);
3385 cb->type = DESC_TYPE_PP_FRAG;
3386 cb->reuse_flag = 0;
3387 return 0;
3388 }
3389
3390 p = dev_alloc_pages(order);
3391 if (!p)
3392 return -ENOMEM;
3393
3394 cb->priv = p;
3395 cb->page_offset = 0;
3396 cb->reuse_flag = 0;
3397 cb->buf = page_address(p);
3398 cb->length = hns3_page_size(ring);
3399 cb->type = DESC_TYPE_PAGE;
3400 page_ref_add(p, USHRT_MAX - 1);
3401 cb->pagecnt_bias = USHRT_MAX;
3402
3403 return 0;
3404 }
3405
hns3_free_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb,int budget)3406 static void hns3_free_buffer(struct hns3_enet_ring *ring,
3407 struct hns3_desc_cb *cb, int budget)
3408 {
3409 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
3410 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
3411 napi_consume_skb(cb->priv, budget);
3412 else if (!HNAE3_IS_TX_RING(ring)) {
3413 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3414 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3415 else if (cb->type & DESC_TYPE_PP_FRAG)
3416 page_pool_put_full_page(ring->page_pool, cb->priv,
3417 false);
3418 }
3419 memset(cb, 0, sizeof(*cb));
3420 }
3421
hns3_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3422 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3423 {
3424 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3425 cb->length, ring_to_dma_dir(ring));
3426
3427 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
3428 return -EIO;
3429
3430 return 0;
3431 }
3432
hns3_unmap_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3433 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3434 struct hns3_desc_cb *cb)
3435 {
3436 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
3437 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3438 ring_to_dma_dir(ring));
3439 else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
3440 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3441 ring_to_dma_dir(ring));
3442 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3443 DESC_TYPE_SGL_SKB))
3444 hns3_tx_spare_reclaim_cb(ring, cb);
3445 }
3446
hns3_buffer_detach(struct hns3_enet_ring * ring,int i)3447 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3448 {
3449 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3450 ring->desc[i].addr = 0;
3451 ring->desc_cb[i].refill = 0;
3452 }
3453
hns3_free_buffer_detach(struct hns3_enet_ring * ring,int i,int budget)3454 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3455 int budget)
3456 {
3457 struct hns3_desc_cb *cb = &ring->desc_cb[i];
3458
3459 if (!ring->desc_cb[i].dma)
3460 return;
3461
3462 hns3_buffer_detach(ring, i);
3463 hns3_free_buffer(ring, cb, budget);
3464 }
3465
hns3_free_buffers(struct hns3_enet_ring * ring)3466 static void hns3_free_buffers(struct hns3_enet_ring *ring)
3467 {
3468 int i;
3469
3470 for (i = 0; i < ring->desc_num; i++)
3471 hns3_free_buffer_detach(ring, i, 0);
3472 }
3473
3474 /* free desc along with its attached buffer */
hns3_free_desc(struct hns3_enet_ring * ring)3475 static void hns3_free_desc(struct hns3_enet_ring *ring)
3476 {
3477 int size = ring->desc_num * sizeof(ring->desc[0]);
3478
3479 hns3_free_buffers(ring);
3480
3481 if (ring->desc) {
3482 dma_free_coherent(ring_to_dev(ring), size,
3483 ring->desc, ring->desc_dma_addr);
3484 ring->desc = NULL;
3485 }
3486 }
3487
hns3_alloc_desc(struct hns3_enet_ring * ring)3488 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3489 {
3490 int size = ring->desc_num * sizeof(ring->desc[0]);
3491
3492 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3493 &ring->desc_dma_addr, GFP_KERNEL);
3494 if (!ring->desc)
3495 return -ENOMEM;
3496
3497 return 0;
3498 }
3499
hns3_alloc_and_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3500 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
3501 struct hns3_desc_cb *cb)
3502 {
3503 int ret;
3504
3505 ret = hns3_alloc_buffer(ring, cb);
3506 if (ret || ring->page_pool)
3507 goto out;
3508
3509 ret = hns3_map_buffer(ring, cb);
3510 if (ret)
3511 goto out_with_buf;
3512
3513 return 0;
3514
3515 out_with_buf:
3516 hns3_free_buffer(ring, cb, 0);
3517 out:
3518 return ret;
3519 }
3520
hns3_alloc_and_attach_buffer(struct hns3_enet_ring * ring,int i)3521 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
3522 {
3523 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
3524
3525 if (ret)
3526 return ret;
3527
3528 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3529 ring->desc_cb[i].page_offset);
3530 ring->desc_cb[i].refill = 1;
3531
3532 return 0;
3533 }
3534
3535 /* Allocate memory for raw pkg, and map with dma */
hns3_alloc_ring_buffers(struct hns3_enet_ring * ring)3536 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3537 {
3538 int i, j, ret;
3539
3540 for (i = 0; i < ring->desc_num; i++) {
3541 ret = hns3_alloc_and_attach_buffer(ring, i);
3542 if (ret)
3543 goto out_buffer_fail;
3544
3545 if (!(i % HNS3_RESCHED_BD_NUM))
3546 cond_resched();
3547 }
3548
3549 return 0;
3550
3551 out_buffer_fail:
3552 for (j = i - 1; j >= 0; j--)
3553 hns3_free_buffer_detach(ring, j, 0);
3554 return ret;
3555 }
3556
3557 /* detach a in-used buffer and replace with a reserved one */
hns3_replace_buffer(struct hns3_enet_ring * ring,int i,struct hns3_desc_cb * res_cb)3558 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3559 struct hns3_desc_cb *res_cb)
3560 {
3561 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3562 ring->desc_cb[i] = *res_cb;
3563 ring->desc_cb[i].refill = 1;
3564 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3565 ring->desc_cb[i].page_offset);
3566 ring->desc[i].rx.bd_base_info = 0;
3567 }
3568
hns3_reuse_buffer(struct hns3_enet_ring * ring,int i)3569 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3570 {
3571 ring->desc_cb[i].reuse_flag = 0;
3572 ring->desc_cb[i].refill = 1;
3573 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3574 ring->desc_cb[i].page_offset);
3575 ring->desc[i].rx.bd_base_info = 0;
3576
3577 dma_sync_single_for_device(ring_to_dev(ring),
3578 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3579 hns3_buf_size(ring),
3580 DMA_FROM_DEVICE);
3581 }
3582
hns3_nic_reclaim_desc(struct hns3_enet_ring * ring,int * bytes,int * pkts,int budget)3583 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
3584 int *bytes, int *pkts, int budget)
3585 {
3586 /* This smp_load_acquire() pairs with smp_store_release() in
3587 * hns3_tx_doorbell().
3588 */
3589 int ltu = smp_load_acquire(&ring->last_to_use);
3590 int ntc = ring->next_to_clean;
3591 struct hns3_desc_cb *desc_cb;
3592 bool reclaimed = false;
3593 struct hns3_desc *desc;
3594
3595 while (ltu != ntc) {
3596 desc = &ring->desc[ntc];
3597
3598 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3599 BIT(HNS3_TXD_VLD_B))
3600 break;
3601
3602 desc_cb = &ring->desc_cb[ntc];
3603
3604 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
3605 DESC_TYPE_BOUNCE_HEAD |
3606 DESC_TYPE_SGL_SKB)) {
3607 (*pkts)++;
3608 (*bytes) += desc_cb->send_bytes;
3609 }
3610
3611 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
3612 hns3_free_buffer_detach(ring, ntc, budget);
3613
3614 if (++ntc == ring->desc_num)
3615 ntc = 0;
3616
3617 /* Issue prefetch for next Tx descriptor */
3618 prefetch(&ring->desc_cb[ntc]);
3619 reclaimed = true;
3620 }
3621
3622 if (unlikely(!reclaimed))
3623 return false;
3624
3625 /* This smp_store_release() pairs with smp_load_acquire() in
3626 * ring_space called by hns3_nic_net_xmit.
3627 */
3628 smp_store_release(&ring->next_to_clean, ntc);
3629
3630 hns3_tx_spare_update(ring);
3631
3632 return true;
3633 }
3634
hns3_clean_tx_ring(struct hns3_enet_ring * ring,int budget)3635 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
3636 {
3637 struct net_device *netdev = ring_to_netdev(ring);
3638 struct hns3_nic_priv *priv = netdev_priv(netdev);
3639 struct netdev_queue *dev_queue;
3640 int bytes, pkts;
3641
3642 bytes = 0;
3643 pkts = 0;
3644
3645 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
3646 return;
3647
3648 ring->tqp_vector->tx_group.total_bytes += bytes;
3649 ring->tqp_vector->tx_group.total_packets += pkts;
3650
3651 u64_stats_update_begin(&ring->syncp);
3652 ring->stats.tx_bytes += bytes;
3653 ring->stats.tx_pkts += pkts;
3654 u64_stats_update_end(&ring->syncp);
3655
3656 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3657 netdev_tx_completed_queue(dev_queue, pkts, bytes);
3658
3659 if (unlikely(netif_carrier_ok(netdev) &&
3660 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
3661 /* Make sure that anybody stopping the queue after this
3662 * sees the new next_to_clean.
3663 */
3664 smp_mb();
3665 if (netif_tx_queue_stopped(dev_queue) &&
3666 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
3667 netif_tx_wake_queue(dev_queue);
3668 ring->stats.restart_queue++;
3669 }
3670 }
3671 }
3672
hns3_desc_unused(struct hns3_enet_ring * ring)3673 static int hns3_desc_unused(struct hns3_enet_ring *ring)
3674 {
3675 int ntc = ring->next_to_clean;
3676 int ntu = ring->next_to_use;
3677
3678 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill))
3679 return ring->desc_num;
3680
3681 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3682 }
3683
3684 /* Return true if there is any allocation failure */
hns3_nic_alloc_rx_buffers(struct hns3_enet_ring * ring,int cleand_count)3685 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3686 int cleand_count)
3687 {
3688 struct hns3_desc_cb *desc_cb;
3689 struct hns3_desc_cb res_cbs;
3690 int i, ret;
3691
3692 for (i = 0; i < cleand_count; i++) {
3693 desc_cb = &ring->desc_cb[ring->next_to_use];
3694 if (desc_cb->reuse_flag) {
3695 hns3_ring_stats_update(ring, reuse_pg_cnt);
3696
3697 hns3_reuse_buffer(ring, ring->next_to_use);
3698 } else {
3699 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
3700 if (ret) {
3701 hns3_ring_stats_update(ring, sw_err_cnt);
3702
3703 hns3_rl_err(ring_to_netdev(ring),
3704 "alloc rx buffer failed: %d\n",
3705 ret);
3706
3707 writel(i, ring->tqp->io_base +
3708 HNS3_RING_RX_RING_HEAD_REG);
3709 return true;
3710 }
3711 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
3712
3713 hns3_ring_stats_update(ring, non_reuse_pg);
3714 }
3715
3716 ring_ptr_move_fw(ring, next_to_use);
3717 }
3718
3719 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
3720 return false;
3721 }
3722
hns3_can_reuse_page(struct hns3_desc_cb * cb)3723 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3724 {
3725 return page_count(cb->priv) == cb->pagecnt_bias;
3726 }
3727
hns3_handle_rx_copybreak(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3728 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i,
3729 struct hns3_enet_ring *ring,
3730 int pull_len,
3731 struct hns3_desc_cb *desc_cb)
3732 {
3733 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3734 u32 frag_offset = desc_cb->page_offset + pull_len;
3735 int size = le16_to_cpu(desc->rx.size);
3736 u32 frag_size = size - pull_len;
3737 void *frag = napi_alloc_frag(frag_size);
3738
3739 if (unlikely(!frag)) {
3740 hns3_ring_stats_update(ring, frag_alloc_err);
3741
3742 hns3_rl_err(ring_to_netdev(ring),
3743 "failed to allocate rx frag\n");
3744 return -ENOMEM;
3745 }
3746
3747 desc_cb->reuse_flag = 1;
3748 memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3749 skb_add_rx_frag(skb, i, virt_to_page(frag),
3750 offset_in_page(frag), frag_size, frag_size);
3751
3752 hns3_ring_stats_update(ring, frag_alloc);
3753 return 0;
3754 }
3755
hns3_nic_reuse_page(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3756 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3757 struct hns3_enet_ring *ring, int pull_len,
3758 struct hns3_desc_cb *desc_cb)
3759 {
3760 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3761 u32 frag_offset = desc_cb->page_offset + pull_len;
3762 int size = le16_to_cpu(desc->rx.size);
3763 u32 truesize = hns3_buf_size(ring);
3764 u32 frag_size = size - pull_len;
3765 int ret = 0;
3766 bool reused;
3767
3768 if (ring->page_pool) {
3769 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3770 frag_size, truesize);
3771 return;
3772 }
3773
3774 /* Avoid re-using remote or pfmem page */
3775 if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3776 goto out;
3777
3778 reused = hns3_can_reuse_page(desc_cb);
3779
3780 /* Rx page can be reused when:
3781 * 1. Rx page is only owned by the driver when page_offset
3782 * is zero, which means 0 @ truesize will be used by
3783 * stack after skb_add_rx_frag() is called, and the rest
3784 * of rx page can be reused by driver.
3785 * Or
3786 * 2. Rx page is only owned by the driver when page_offset
3787 * is non-zero, which means page_offset @ truesize will
3788 * be used by stack after skb_add_rx_frag() is called,
3789 * and 0 @ truesize can be reused by driver.
3790 */
3791 if ((!desc_cb->page_offset && reused) ||
3792 ((desc_cb->page_offset + truesize + truesize) <=
3793 hns3_page_size(ring) && desc_cb->page_offset)) {
3794 desc_cb->page_offset += truesize;
3795 desc_cb->reuse_flag = 1;
3796 } else if (desc_cb->page_offset && reused) {
3797 desc_cb->page_offset = 0;
3798 desc_cb->reuse_flag = 1;
3799 } else if (frag_size <= ring->rx_copybreak) {
3800 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb);
3801 if (!ret)
3802 return;
3803 }
3804
3805 out:
3806 desc_cb->pagecnt_bias--;
3807
3808 if (unlikely(!desc_cb->pagecnt_bias)) {
3809 page_ref_add(desc_cb->priv, USHRT_MAX);
3810 desc_cb->pagecnt_bias = USHRT_MAX;
3811 }
3812
3813 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3814 frag_size, truesize);
3815
3816 if (unlikely(!desc_cb->reuse_flag))
3817 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
3818 }
3819
hns3_gro_complete(struct sk_buff * skb,u32 l234info)3820 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
3821 {
3822 __be16 type = skb->protocol;
3823 struct tcphdr *th;
3824 int depth = 0;
3825
3826 while (eth_type_vlan(type)) {
3827 struct vlan_hdr *vh;
3828
3829 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3830 return -EFAULT;
3831
3832 vh = (struct vlan_hdr *)(skb->data + depth);
3833 type = vh->h_vlan_encapsulated_proto;
3834 depth += VLAN_HLEN;
3835 }
3836
3837 skb_set_network_header(skb, depth);
3838
3839 if (type == htons(ETH_P_IP)) {
3840 const struct iphdr *iph = ip_hdr(skb);
3841
3842 depth += sizeof(struct iphdr);
3843 skb_set_transport_header(skb, depth);
3844 th = tcp_hdr(skb);
3845 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3846 iph->daddr, 0);
3847 } else if (type == htons(ETH_P_IPV6)) {
3848 const struct ipv6hdr *iph = ipv6_hdr(skb);
3849
3850 depth += sizeof(struct ipv6hdr);
3851 skb_set_transport_header(skb, depth);
3852 th = tcp_hdr(skb);
3853 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3854 &iph->daddr, 0);
3855 } else {
3856 hns3_rl_err(skb->dev,
3857 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3858 be16_to_cpu(type), depth);
3859 return -EFAULT;
3860 }
3861
3862 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3863 if (th->cwr)
3864 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3865
3866 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3867 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
3868
3869 skb->csum_start = (unsigned char *)th - skb->head;
3870 skb->csum_offset = offsetof(struct tcphdr, check);
3871 skb->ip_summed = CHECKSUM_PARTIAL;
3872
3873 trace_hns3_gro(skb);
3874
3875 return 0;
3876 }
3877
hns3_checksum_complete(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 ptype,u16 csum)3878 static void hns3_checksum_complete(struct hns3_enet_ring *ring,
3879 struct sk_buff *skb, u32 ptype, u16 csum)
3880 {
3881 if (ptype == HNS3_INVALID_PTYPE ||
3882 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3883 return;
3884
3885 hns3_ring_stats_update(ring, csum_complete);
3886 skb->ip_summed = CHECKSUM_COMPLETE;
3887 skb->csum = csum_unfold((__force __sum16)csum);
3888 }
3889
hns3_rx_handle_csum(struct sk_buff * skb,u32 l234info,u32 ol_info,u32 ptype)3890 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3891 u32 ol_info, u32 ptype)
3892 {
3893 int l3_type, l4_type;
3894 int ol4_type;
3895
3896 if (ptype != HNS3_INVALID_PTYPE) {
3897 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3898 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
3899
3900 return;
3901 }
3902
3903 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
3904 HNS3_RXD_OL4ID_S);
3905 switch (ol4_type) {
3906 case HNS3_OL4_TYPE_MAC_IN_UDP:
3907 case HNS3_OL4_TYPE_NVGRE:
3908 skb->csum_level = 1;
3909 fallthrough;
3910 case HNS3_OL4_TYPE_NO_TUN:
3911 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3912 HNS3_RXD_L3ID_S);
3913 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3914 HNS3_RXD_L4ID_S);
3915 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
3916 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3917 l3_type == HNS3_L3_TYPE_IPV6) &&
3918 (l4_type == HNS3_L4_TYPE_UDP ||
3919 l4_type == HNS3_L4_TYPE_TCP ||
3920 l4_type == HNS3_L4_TYPE_SCTP))
3921 skb->ip_summed = CHECKSUM_UNNECESSARY;
3922 break;
3923 default:
3924 break;
3925 }
3926 }
3927
hns3_rx_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)3928 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
3929 u32 l234info, u32 bd_base_info, u32 ol_info,
3930 u16 csum)
3931 {
3932 struct net_device *netdev = ring_to_netdev(ring);
3933 struct hns3_nic_priv *priv = netdev_priv(netdev);
3934 u32 ptype = HNS3_INVALID_PTYPE;
3935
3936 skb->ip_summed = CHECKSUM_NONE;
3937
3938 skb_checksum_none_assert(skb);
3939
3940 if (!(netdev->features & NETIF_F_RXCSUM))
3941 return;
3942
3943 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3944 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3945 HNS3_RXD_PTYPE_S);
3946
3947 hns3_checksum_complete(ring, skb, ptype, csum);
3948
3949 /* check if hardware has done checksum */
3950 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3951 return;
3952
3953 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3954 BIT(HNS3_RXD_OL3E_B) |
3955 BIT(HNS3_RXD_OL4E_B)))) {
3956 skb->ip_summed = CHECKSUM_NONE;
3957 hns3_ring_stats_update(ring, l3l4_csum_err);
3958
3959 return;
3960 }
3961
3962 hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
3963 }
3964
hns3_rx_skb(struct hns3_enet_ring * ring,struct sk_buff * skb)3965 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
3966 {
3967 if (skb_has_frag_list(skb))
3968 napi_gro_flush(&ring->tqp_vector->napi, false);
3969
3970 napi_gro_receive(&ring->tqp_vector->napi, skb);
3971 }
3972
hns3_parse_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,u32 l234info,u16 * vlan_tag)3973 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
3974 struct hns3_desc *desc, u32 l234info,
3975 u16 *vlan_tag)
3976 {
3977 struct hnae3_handle *handle = ring->tqp->handle;
3978 struct pci_dev *pdev = ring->tqp->handle->pdev;
3979 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3980
3981 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
3982 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3983 if (!(*vlan_tag & VLAN_VID_MASK))
3984 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3985
3986 return (*vlan_tag != 0);
3987 }
3988
3989 #define HNS3_STRP_OUTER_VLAN 0x1
3990 #define HNS3_STRP_INNER_VLAN 0x2
3991 #define HNS3_STRP_BOTH 0x3
3992
3993 /* Hardware always insert VLAN tag into RX descriptor when
3994 * remove the tag from packet, driver needs to determine
3995 * reporting which tag to stack.
3996 */
3997 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
3998 HNS3_RXD_STRP_TAGP_S)) {
3999 case HNS3_STRP_OUTER_VLAN:
4000 if (handle->port_base_vlan_state !=
4001 HNAE3_PORT_BASE_VLAN_DISABLE)
4002 return false;
4003
4004 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4005 return true;
4006 case HNS3_STRP_INNER_VLAN:
4007 if (handle->port_base_vlan_state !=
4008 HNAE3_PORT_BASE_VLAN_DISABLE)
4009 return false;
4010
4011 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4012 return true;
4013 case HNS3_STRP_BOTH:
4014 if (handle->port_base_vlan_state ==
4015 HNAE3_PORT_BASE_VLAN_DISABLE)
4016 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4017 else
4018 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4019
4020 return true;
4021 default:
4022 return false;
4023 }
4024 }
4025
hns3_rx_ring_move_fw(struct hns3_enet_ring * ring)4026 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
4027 {
4028 ring->desc[ring->next_to_clean].rx.bd_base_info &=
4029 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
4030 ring->desc_cb[ring->next_to_clean].refill = 0;
4031 ring->next_to_clean += 1;
4032
4033 if (unlikely(ring->next_to_clean == ring->desc_num))
4034 ring->next_to_clean = 0;
4035 }
4036
hns3_alloc_skb(struct hns3_enet_ring * ring,unsigned int length,unsigned char * va)4037 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
4038 unsigned char *va)
4039 {
4040 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
4041 struct net_device *netdev = ring_to_netdev(ring);
4042 struct sk_buff *skb;
4043
4044 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
4045 skb = ring->skb;
4046 if (unlikely(!skb)) {
4047 hns3_rl_err(netdev, "alloc rx skb fail\n");
4048 hns3_ring_stats_update(ring, sw_err_cnt);
4049
4050 return -ENOMEM;
4051 }
4052
4053 trace_hns3_rx_desc(ring);
4054 prefetchw(skb->data);
4055
4056 ring->pending_buf = 1;
4057 ring->frag_num = 0;
4058 ring->tail_skb = NULL;
4059 if (length <= HNS3_RX_HEAD_SIZE) {
4060 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
4061
4062 /* We can reuse buffer as-is, just make sure it is reusable */
4063 if (dev_page_is_reusable(desc_cb->priv))
4064 desc_cb->reuse_flag = 1;
4065 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
4066 page_pool_put_full_page(ring->page_pool, desc_cb->priv,
4067 false);
4068 else /* This page cannot be reused so discard it */
4069 __page_frag_cache_drain(desc_cb->priv,
4070 desc_cb->pagecnt_bias);
4071
4072 hns3_rx_ring_move_fw(ring);
4073 return 0;
4074 }
4075
4076 if (ring->page_pool)
4077 skb_mark_for_recycle(skb);
4078
4079 hns3_ring_stats_update(ring, seg_pkt_cnt);
4080
4081 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
4082 __skb_put(skb, ring->pull_len);
4083 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
4084 desc_cb);
4085 hns3_rx_ring_move_fw(ring);
4086
4087 return 0;
4088 }
4089
hns3_add_frag(struct hns3_enet_ring * ring)4090 static int hns3_add_frag(struct hns3_enet_ring *ring)
4091 {
4092 struct sk_buff *skb = ring->skb;
4093 struct sk_buff *head_skb = skb;
4094 struct sk_buff *new_skb;
4095 struct hns3_desc_cb *desc_cb;
4096 struct hns3_desc *desc;
4097 u32 bd_base_info;
4098
4099 do {
4100 desc = &ring->desc[ring->next_to_clean];
4101 desc_cb = &ring->desc_cb[ring->next_to_clean];
4102 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4103 /* make sure HW write desc complete */
4104 dma_rmb();
4105 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
4106 return -ENXIO;
4107
4108 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
4109 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
4110 if (unlikely(!new_skb)) {
4111 hns3_rl_err(ring_to_netdev(ring),
4112 "alloc rx fraglist skb fail\n");
4113 return -ENXIO;
4114 }
4115
4116 if (ring->page_pool)
4117 skb_mark_for_recycle(new_skb);
4118
4119 ring->frag_num = 0;
4120
4121 if (ring->tail_skb) {
4122 ring->tail_skb->next = new_skb;
4123 ring->tail_skb = new_skb;
4124 } else {
4125 skb_shinfo(skb)->frag_list = new_skb;
4126 ring->tail_skb = new_skb;
4127 }
4128 }
4129
4130 if (ring->tail_skb) {
4131 head_skb->truesize += hns3_buf_size(ring);
4132 head_skb->data_len += le16_to_cpu(desc->rx.size);
4133 head_skb->len += le16_to_cpu(desc->rx.size);
4134 skb = ring->tail_skb;
4135 }
4136
4137 dma_sync_single_for_cpu(ring_to_dev(ring),
4138 desc_cb->dma + desc_cb->page_offset,
4139 hns3_buf_size(ring),
4140 DMA_FROM_DEVICE);
4141
4142 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
4143 trace_hns3_rx_desc(ring);
4144 hns3_rx_ring_move_fw(ring);
4145 ring->pending_buf++;
4146 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
4147
4148 return 0;
4149 }
4150
hns3_set_gro_and_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)4151 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
4152 struct sk_buff *skb, u32 l234info,
4153 u32 bd_base_info, u32 ol_info, u16 csum)
4154 {
4155 struct net_device *netdev = ring_to_netdev(ring);
4156 struct hns3_nic_priv *priv = netdev_priv(netdev);
4157 u32 l3_type;
4158
4159 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
4160 HNS3_RXD_GRO_SIZE_M,
4161 HNS3_RXD_GRO_SIZE_S);
4162 /* if there is no HW GRO, do not set gro params */
4163 if (!skb_shinfo(skb)->gso_size) {
4164 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
4165 csum);
4166 return 0;
4167 }
4168
4169 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
4170 HNS3_RXD_GRO_COUNT_M,
4171 HNS3_RXD_GRO_COUNT_S);
4172
4173 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4174 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4175 HNS3_RXD_PTYPE_S);
4176
4177 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
4178 } else {
4179 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4180 HNS3_RXD_L3ID_S);
4181 }
4182
4183 if (l3_type == HNS3_L3_TYPE_IPV4)
4184 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
4185 else if (l3_type == HNS3_L3_TYPE_IPV6)
4186 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
4187 else
4188 return -EFAULT;
4189
4190 return hns3_gro_complete(skb, l234info);
4191 }
4192
hns3_set_rx_skb_rss_type(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 rss_hash,u32 l234info,u32 ol_info)4193 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
4194 struct sk_buff *skb, u32 rss_hash,
4195 u32 l234info, u32 ol_info)
4196 {
4197 enum pkt_hash_types rss_type = PKT_HASH_TYPE_NONE;
4198 struct net_device *netdev = ring_to_netdev(ring);
4199 struct hns3_nic_priv *priv = netdev_priv(netdev);
4200
4201 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4202 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4203 HNS3_RXD_PTYPE_S);
4204
4205 rss_type = hns3_rx_ptype_tbl[ptype].hash_type;
4206 } else {
4207 int l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4208 HNS3_RXD_L3ID_S);
4209 int l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
4210 HNS3_RXD_L4ID_S);
4211
4212 if (l3_type == HNS3_L3_TYPE_IPV4 ||
4213 l3_type == HNS3_L3_TYPE_IPV6) {
4214 if (l4_type == HNS3_L4_TYPE_UDP ||
4215 l4_type == HNS3_L4_TYPE_TCP ||
4216 l4_type == HNS3_L4_TYPE_SCTP)
4217 rss_type = PKT_HASH_TYPE_L4;
4218 else if (l4_type == HNS3_L4_TYPE_IGMP ||
4219 l4_type == HNS3_L4_TYPE_ICMP)
4220 rss_type = PKT_HASH_TYPE_L3;
4221 }
4222 }
4223
4224 skb_set_hash(skb, rss_hash, rss_type);
4225 }
4226
hns3_handle_rx_ts_info(struct net_device * netdev,struct hns3_desc * desc,struct sk_buff * skb,u32 bd_base_info)4227 static void hns3_handle_rx_ts_info(struct net_device *netdev,
4228 struct hns3_desc *desc, struct sk_buff *skb,
4229 u32 bd_base_info)
4230 {
4231 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4232 struct hnae3_handle *h = hns3_get_handle(netdev);
4233 u32 nsec = le32_to_cpu(desc->ts_nsec);
4234 u32 sec = le32_to_cpu(desc->ts_sec);
4235
4236 if (h->ae_algo->ops->get_rx_hwts)
4237 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4238 }
4239 }
4240
hns3_handle_rx_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,struct sk_buff * skb,u32 l234info)4241 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring,
4242 struct hns3_desc *desc, struct sk_buff *skb,
4243 u32 l234info)
4244 {
4245 struct net_device *netdev = ring_to_netdev(ring);
4246
4247 /* Based on hw strategy, the tag offloaded will be stored at
4248 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4249 * in one layer tag case.
4250 */
4251 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4252 u16 vlan_tag;
4253
4254 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4255 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4256 vlan_tag);
4257 }
4258 }
4259
hns3_handle_bdinfo(struct hns3_enet_ring * ring,struct sk_buff * skb)4260 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
4261 {
4262 struct net_device *netdev = ring_to_netdev(ring);
4263 enum hns3_pkt_l2t_type l2_frame_type;
4264 u32 bd_base_info, l234info, ol_info;
4265 struct hns3_desc *desc;
4266 unsigned int len;
4267 int pre_ntc, ret;
4268 u16 csum;
4269
4270 /* bdinfo handled below is only valid on the last BD of the
4271 * current packet, and ring->next_to_clean indicates the first
4272 * descriptor of next packet, so need - 1 below.
4273 */
4274 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4275 (ring->desc_num - 1);
4276 desc = &ring->desc[pre_ntc];
4277 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4278 l234info = le32_to_cpu(desc->rx.l234_info);
4279 ol_info = le32_to_cpu(desc->rx.ol_info);
4280 csum = le16_to_cpu(desc->csum);
4281
4282 hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info);
4283
4284 hns3_handle_rx_vlan_tag(ring, desc, skb, l234info);
4285
4286 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4287 BIT(HNS3_RXD_L2E_B))))) {
4288 u64_stats_update_begin(&ring->syncp);
4289 if (l234info & BIT(HNS3_RXD_L2E_B))
4290 ring->stats.l2_err++;
4291 else
4292 ring->stats.err_pkt_len++;
4293 u64_stats_update_end(&ring->syncp);
4294
4295 return -EFAULT;
4296 }
4297
4298 len = skb->len;
4299
4300 /* Do update ip stack process */
4301 skb->protocol = eth_type_trans(skb, netdev);
4302
4303 /* This is needed in order to enable forwarding support */
4304 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
4305 bd_base_info, ol_info, csum);
4306 if (unlikely(ret)) {
4307 hns3_ring_stats_update(ring, rx_err_cnt);
4308 return ret;
4309 }
4310
4311 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4312 HNS3_RXD_DMAC_S);
4313
4314 u64_stats_update_begin(&ring->syncp);
4315 ring->stats.rx_pkts++;
4316 ring->stats.rx_bytes += len;
4317
4318 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4319 ring->stats.rx_multicast++;
4320
4321 u64_stats_update_end(&ring->syncp);
4322
4323 ring->tqp_vector->rx_group.total_bytes += len;
4324
4325 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash),
4326 l234info, ol_info);
4327 return 0;
4328 }
4329
hns3_handle_rx_bd(struct hns3_enet_ring * ring)4330 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
4331 {
4332 struct sk_buff *skb = ring->skb;
4333 struct hns3_desc_cb *desc_cb;
4334 struct hns3_desc *desc;
4335 unsigned int length;
4336 u32 bd_base_info;
4337 int ret;
4338
4339 desc = &ring->desc[ring->next_to_clean];
4340 desc_cb = &ring->desc_cb[ring->next_to_clean];
4341
4342 prefetch(desc);
4343
4344 if (!skb) {
4345 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4346 /* Check valid BD */
4347 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4348 return -ENXIO;
4349
4350 dma_rmb();
4351 length = le16_to_cpu(desc->rx.size);
4352
4353 ring->va = desc_cb->buf + desc_cb->page_offset;
4354
4355 dma_sync_single_for_cpu(ring_to_dev(ring),
4356 desc_cb->dma + desc_cb->page_offset,
4357 hns3_buf_size(ring),
4358 DMA_FROM_DEVICE);
4359
4360 /* Prefetch first cache line of first page.
4361 * Idea is to cache few bytes of the header of the packet.
4362 * Our L1 Cache line size is 64B so need to prefetch twice to make
4363 * it 128B. But in actual we can have greater size of caches with
4364 * 128B Level 1 cache lines. In such a case, single fetch would
4365 * suffice to cache in the relevant part of the header.
4366 */
4367 net_prefetch(ring->va);
4368
4369 ret = hns3_alloc_skb(ring, length, ring->va);
4370 skb = ring->skb;
4371
4372 if (ret < 0) /* alloc buffer fail */
4373 return ret;
4374 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4375 ret = hns3_add_frag(ring);
4376 if (ret)
4377 return ret;
4378 }
4379 } else {
4380 ret = hns3_add_frag(ring);
4381 if (ret)
4382 return ret;
4383 }
4384
4385 /* As the head data may be changed when GRO enable, copy
4386 * the head data in after other data rx completed
4387 */
4388 if (skb->len > HNS3_RX_HEAD_SIZE)
4389 memcpy(skb->data, ring->va,
4390 ALIGN(ring->pull_len, sizeof(long)));
4391
4392 ret = hns3_handle_bdinfo(ring, skb);
4393 if (unlikely(ret)) {
4394 dev_kfree_skb_any(skb);
4395 return ret;
4396 }
4397
4398 skb_record_rx_queue(skb, ring->tqp->tqp_index);
4399 return 0;
4400 }
4401
hns3_clean_rx_ring(struct hns3_enet_ring * ring,int budget,void (* rx_fn)(struct hns3_enet_ring *,struct sk_buff *))4402 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4403 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
4404 {
4405 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
4406 int unused_count = hns3_desc_unused(ring);
4407 bool failure = false;
4408 int recv_pkts = 0;
4409 int err;
4410
4411 unused_count -= ring->pending_buf;
4412
4413 while (recv_pkts < budget) {
4414 /* Reuse or realloc buffers */
4415 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4416 failure = failure ||
4417 hns3_nic_alloc_rx_buffers(ring, unused_count);
4418 unused_count = 0;
4419 }
4420
4421 /* Poll one pkt */
4422 err = hns3_handle_rx_bd(ring);
4423 /* Do not get FE for the packet or failed to alloc skb */
4424 if (unlikely(!ring->skb || err == -ENXIO)) {
4425 goto out;
4426 } else if (likely(!err)) {
4427 rx_fn(ring, ring->skb);
4428 recv_pkts++;
4429 }
4430
4431 unused_count += ring->pending_buf;
4432 ring->skb = NULL;
4433 ring->pending_buf = 0;
4434 }
4435
4436 out:
4437 /* sync head pointer before exiting, since hardware will calculate
4438 * FBD number with head pointer
4439 */
4440 if (unused_count > 0)
4441 failure = failure ||
4442 hns3_nic_alloc_rx_buffers(ring, unused_count);
4443
4444 return failure ? budget : recv_pkts;
4445 }
4446
hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4447 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4448 {
4449 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4450 struct dim_sample sample = {};
4451
4452 if (!rx_group->coal.adapt_enable)
4453 return;
4454
4455 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4456 rx_group->total_bytes, &sample);
4457 net_dim(&rx_group->dim, &sample);
4458 }
4459
hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4460 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4461 {
4462 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
4463 struct dim_sample sample = {};
4464
4465 if (!tx_group->coal.adapt_enable)
4466 return;
4467
4468 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4469 tx_group->total_bytes, &sample);
4470 net_dim(&tx_group->dim, &sample);
4471 }
4472
hns3_nic_common_poll(struct napi_struct * napi,int budget)4473 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4474 {
4475 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
4476 struct hns3_enet_ring *ring;
4477 int rx_pkt_total = 0;
4478
4479 struct hns3_enet_tqp_vector *tqp_vector =
4480 container_of(napi, struct hns3_enet_tqp_vector, napi);
4481 bool clean_complete = true;
4482 int rx_budget = budget;
4483
4484 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4485 napi_complete(napi);
4486 return 0;
4487 }
4488
4489 /* Since the actual Tx work is minimal, we can give the Tx a larger
4490 * budget and be more aggressive about cleaning up the Tx descriptors.
4491 */
4492 hns3_for_each_ring(ring, tqp_vector->tx_group)
4493 hns3_clean_tx_ring(ring, budget);
4494
4495 /* make sure rx ring budget not smaller than 1 */
4496 if (tqp_vector->num_tqps > 1)
4497 rx_budget = max(budget / tqp_vector->num_tqps, 1);
4498
4499 hns3_for_each_ring(ring, tqp_vector->rx_group) {
4500 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4501 hns3_rx_skb);
4502 if (rx_cleaned >= rx_budget)
4503 clean_complete = false;
4504
4505 rx_pkt_total += rx_cleaned;
4506 }
4507
4508 tqp_vector->rx_group.total_packets += rx_pkt_total;
4509
4510 if (!clean_complete)
4511 return budget;
4512
4513 if (napi_complete(napi) &&
4514 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4515 hns3_update_rx_int_coalesce(tqp_vector);
4516 hns3_update_tx_int_coalesce(tqp_vector);
4517
4518 hns3_mask_vector_irq(tqp_vector, 1);
4519 }
4520
4521 return rx_pkt_total;
4522 }
4523
hns3_create_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node ** head,bool is_tx)4524 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4525 struct hnae3_ring_chain_node **head,
4526 bool is_tx)
4527 {
4528 u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX;
4529 u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX;
4530 struct hnae3_ring_chain_node *cur_chain = *head;
4531 struct pci_dev *pdev = tqp_vector->handle->pdev;
4532 struct hnae3_ring_chain_node *chain;
4533 struct hns3_enet_ring *ring;
4534
4535 ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring;
4536
4537 if (cur_chain) {
4538 while (cur_chain->next)
4539 cur_chain = cur_chain->next;
4540 }
4541
4542 while (ring) {
4543 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4544 if (!chain)
4545 return -ENOMEM;
4546 if (cur_chain)
4547 cur_chain->next = chain;
4548 else
4549 *head = chain;
4550 chain->tqp_index = ring->tqp->tqp_index;
4551 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4552 bit_value);
4553 hnae3_set_field(chain->int_gl_idx,
4554 HNAE3_RING_GL_IDX_M,
4555 HNAE3_RING_GL_IDX_S, field_value);
4556
4557 cur_chain = chain;
4558
4559 ring = ring->next;
4560 }
4561
4562 return 0;
4563 }
4564
4565 static struct hnae3_ring_chain_node *
hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector)4566 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector)
4567 {
4568 struct pci_dev *pdev = tqp_vector->handle->pdev;
4569 struct hnae3_ring_chain_node *cur_chain = NULL;
4570 struct hnae3_ring_chain_node *chain;
4571
4572 if (hns3_create_ring_chain(tqp_vector, &cur_chain, true))
4573 goto err_free_chain;
4574
4575 if (hns3_create_ring_chain(tqp_vector, &cur_chain, false))
4576 goto err_free_chain;
4577
4578 return cur_chain;
4579
4580 err_free_chain:
4581 while (cur_chain) {
4582 chain = cur_chain->next;
4583 devm_kfree(&pdev->dev, cur_chain);
4584 cur_chain = chain;
4585 }
4586
4587 return NULL;
4588 }
4589
hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node * head)4590 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4591 struct hnae3_ring_chain_node *head)
4592 {
4593 struct pci_dev *pdev = tqp_vector->handle->pdev;
4594 struct hnae3_ring_chain_node *chain_tmp, *chain;
4595
4596 chain = head;
4597
4598 while (chain) {
4599 chain_tmp = chain->next;
4600 devm_kfree(&pdev->dev, chain);
4601 chain = chain_tmp;
4602 }
4603 }
4604
hns3_add_ring_to_group(struct hns3_enet_ring_group * group,struct hns3_enet_ring * ring)4605 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4606 struct hns3_enet_ring *ring)
4607 {
4608 ring->next = group->ring;
4609 group->ring = ring;
4610
4611 group->count++;
4612 }
4613
hns3_nic_set_cpumask(struct hns3_nic_priv * priv)4614 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4615 {
4616 struct pci_dev *pdev = priv->ae_handle->pdev;
4617 struct hns3_enet_tqp_vector *tqp_vector;
4618 int num_vectors = priv->vector_num;
4619 int numa_node;
4620 int vector_i;
4621
4622 numa_node = dev_to_node(&pdev->dev);
4623
4624 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4625 tqp_vector = &priv->tqp_vector[vector_i];
4626 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4627 &tqp_vector->affinity_mask);
4628 }
4629 }
4630
hns3_rx_dim_work(struct work_struct * work)4631 static void hns3_rx_dim_work(struct work_struct *work)
4632 {
4633 struct dim *dim = container_of(work, struct dim, work);
4634 struct hns3_enet_ring_group *group = container_of(dim,
4635 struct hns3_enet_ring_group, dim);
4636 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4637 struct dim_cq_moder cur_moder =
4638 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4639
4640 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4641 tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4642
4643 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4644 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4645 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4646 }
4647
4648 dim->state = DIM_START_MEASURE;
4649 }
4650
hns3_tx_dim_work(struct work_struct * work)4651 static void hns3_tx_dim_work(struct work_struct *work)
4652 {
4653 struct dim *dim = container_of(work, struct dim, work);
4654 struct hns3_enet_ring_group *group = container_of(dim,
4655 struct hns3_enet_ring_group, dim);
4656 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4657 struct dim_cq_moder cur_moder =
4658 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4659
4660 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4661 tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4662
4663 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4664 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4665 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4666 }
4667
4668 dim->state = DIM_START_MEASURE;
4669 }
4670
hns3_nic_init_dim(struct hns3_enet_tqp_vector * tqp_vector)4671 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4672 {
4673 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
4674 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
4675 }
4676
hns3_nic_init_vector_data(struct hns3_nic_priv * priv)4677 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4678 {
4679 struct hnae3_handle *h = priv->ae_handle;
4680 struct hns3_enet_tqp_vector *tqp_vector;
4681 int ret;
4682 int i;
4683
4684 hns3_nic_set_cpumask(priv);
4685
4686 for (i = 0; i < priv->vector_num; i++) {
4687 tqp_vector = &priv->tqp_vector[i];
4688 hns3_vector_coalesce_init_hw(tqp_vector, priv);
4689 tqp_vector->num_tqps = 0;
4690 hns3_nic_init_dim(tqp_vector);
4691 }
4692
4693 for (i = 0; i < h->kinfo.num_tqps; i++) {
4694 u16 vector_i = i % priv->vector_num;
4695 u16 tqp_num = h->kinfo.num_tqps;
4696
4697 tqp_vector = &priv->tqp_vector[vector_i];
4698
4699 hns3_add_ring_to_group(&tqp_vector->tx_group,
4700 &priv->ring[i]);
4701
4702 hns3_add_ring_to_group(&tqp_vector->rx_group,
4703 &priv->ring[i + tqp_num]);
4704
4705 priv->ring[i].tqp_vector = tqp_vector;
4706 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
4707 tqp_vector->num_tqps++;
4708 }
4709
4710 for (i = 0; i < priv->vector_num; i++) {
4711 struct hnae3_ring_chain_node *vector_ring_chain;
4712
4713 tqp_vector = &priv->tqp_vector[i];
4714
4715 tqp_vector->rx_group.total_bytes = 0;
4716 tqp_vector->rx_group.total_packets = 0;
4717 tqp_vector->tx_group.total_bytes = 0;
4718 tqp_vector->tx_group.total_packets = 0;
4719 tqp_vector->handle = h;
4720
4721 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4722 if (!vector_ring_chain) {
4723 ret = -ENOMEM;
4724 goto map_ring_fail;
4725 }
4726
4727 ret = h->ae_algo->ops->map_ring_to_vector(h,
4728 tqp_vector->vector_irq, vector_ring_chain);
4729
4730 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4731
4732 if (ret)
4733 goto map_ring_fail;
4734
4735 netif_napi_add(priv->netdev, &tqp_vector->napi,
4736 hns3_nic_common_poll);
4737 }
4738
4739 return 0;
4740
4741 map_ring_fail:
4742 while (i--)
4743 netif_napi_del(&priv->tqp_vector[i].napi);
4744
4745 return ret;
4746 }
4747
hns3_nic_init_coal_cfg(struct hns3_nic_priv * priv)4748 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4749 {
4750 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4751 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4752 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4753
4754 /* initialize the configuration for interrupt coalescing.
4755 * 1. GL (Interrupt Gap Limiter)
4756 * 2. RL (Interrupt Rate Limiter)
4757 * 3. QL (Interrupt Quantity Limiter)
4758 *
4759 * Default: enable interrupt coalescing self-adaptive and GL
4760 */
4761 tx_coal->adapt_enable = 1;
4762 rx_coal->adapt_enable = 1;
4763
4764 tx_coal->int_gl = HNS3_INT_GL_50K;
4765 rx_coal->int_gl = HNS3_INT_GL_50K;
4766
4767 rx_coal->flow_level = HNS3_FLOW_LOW;
4768 tx_coal->flow_level = HNS3_FLOW_LOW;
4769
4770 if (ae_dev->dev_specs.int_ql_max) {
4771 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4772 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4773 }
4774 }
4775
hns3_nic_alloc_vector_data(struct hns3_nic_priv * priv)4776 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4777 {
4778 struct hnae3_handle *h = priv->ae_handle;
4779 struct hns3_enet_tqp_vector *tqp_vector;
4780 struct hnae3_vector_info *vector;
4781 struct pci_dev *pdev = h->pdev;
4782 u16 tqp_num = h->kinfo.num_tqps;
4783 u16 vector_num;
4784 int ret = 0;
4785 u16 i;
4786
4787 /* RSS size, cpu online and vector_num should be the same */
4788 /* Should consider 2p/4p later */
4789 vector_num = min_t(u16, num_online_cpus(), tqp_num);
4790
4791 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4792 GFP_KERNEL);
4793 if (!vector)
4794 return -ENOMEM;
4795
4796 /* save the actual available vector number */
4797 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4798
4799 priv->vector_num = vector_num;
4800 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4801 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4802 GFP_KERNEL);
4803 if (!priv->tqp_vector) {
4804 ret = -ENOMEM;
4805 goto out;
4806 }
4807
4808 for (i = 0; i < priv->vector_num; i++) {
4809 tqp_vector = &priv->tqp_vector[i];
4810 tqp_vector->idx = i;
4811 tqp_vector->mask_addr = vector[i].io_addr;
4812 tqp_vector->vector_irq = vector[i].vector;
4813 hns3_vector_coalesce_init(tqp_vector, priv);
4814 }
4815
4816 out:
4817 devm_kfree(&pdev->dev, vector);
4818 return ret;
4819 }
4820
hns3_clear_ring_group(struct hns3_enet_ring_group * group)4821 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4822 {
4823 group->ring = NULL;
4824 group->count = 0;
4825 }
4826
hns3_nic_uninit_vector_data(struct hns3_nic_priv * priv)4827 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
4828 {
4829 struct hnae3_ring_chain_node *vector_ring_chain;
4830 struct hnae3_handle *h = priv->ae_handle;
4831 struct hns3_enet_tqp_vector *tqp_vector;
4832 int i;
4833
4834 for (i = 0; i < priv->vector_num; i++) {
4835 tqp_vector = &priv->tqp_vector[i];
4836
4837 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4838 continue;
4839
4840 /* Since the mapping can be overwritten, when fail to get the
4841 * chain between vector and ring, we should go on to deal with
4842 * the remaining options.
4843 */
4844 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4845 if (!vector_ring_chain)
4846 dev_warn(priv->dev, "failed to get ring chain\n");
4847
4848 h->ae_algo->ops->unmap_ring_from_vector(h,
4849 tqp_vector->vector_irq, vector_ring_chain);
4850
4851 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4852
4853 hns3_clear_ring_group(&tqp_vector->rx_group);
4854 hns3_clear_ring_group(&tqp_vector->tx_group);
4855 netif_napi_del(&priv->tqp_vector[i].napi);
4856 }
4857 }
4858
hns3_nic_dealloc_vector_data(struct hns3_nic_priv * priv)4859 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
4860 {
4861 struct hnae3_handle *h = priv->ae_handle;
4862 struct pci_dev *pdev = h->pdev;
4863 int i, ret;
4864
4865 for (i = 0; i < priv->vector_num; i++) {
4866 struct hns3_enet_tqp_vector *tqp_vector;
4867
4868 tqp_vector = &priv->tqp_vector[i];
4869 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4870 if (ret)
4871 return;
4872 }
4873
4874 devm_kfree(&pdev->dev, priv->tqp_vector);
4875 }
4876
hns3_ring_get_cfg(struct hnae3_queue * q,struct hns3_nic_priv * priv,unsigned int ring_type)4877 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4878 unsigned int ring_type)
4879 {
4880 int queue_num = priv->ae_handle->kinfo.num_tqps;
4881 struct hns3_enet_ring *ring;
4882 int desc_num;
4883
4884 if (ring_type == HNAE3_RING_TYPE_TX) {
4885 ring = &priv->ring[q->tqp_index];
4886 desc_num = priv->ae_handle->kinfo.num_tx_desc;
4887 ring->queue_index = q->tqp_index;
4888 ring->tx_copybreak = priv->tx_copybreak;
4889 ring->last_to_use = 0;
4890 } else {
4891 ring = &priv->ring[q->tqp_index + queue_num];
4892 desc_num = priv->ae_handle->kinfo.num_rx_desc;
4893 ring->queue_index = q->tqp_index;
4894 ring->rx_copybreak = priv->rx_copybreak;
4895 }
4896
4897 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
4898
4899 ring->tqp = q;
4900 ring->desc = NULL;
4901 ring->desc_cb = NULL;
4902 ring->dev = priv->dev;
4903 ring->desc_dma_addr = 0;
4904 ring->buf_size = q->buf_size;
4905 ring->desc_num = desc_num;
4906 ring->next_to_use = 0;
4907 ring->next_to_clean = 0;
4908 }
4909
hns3_queue_to_ring(struct hnae3_queue * tqp,struct hns3_nic_priv * priv)4910 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4911 struct hns3_nic_priv *priv)
4912 {
4913 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4914 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
4915 }
4916
hns3_get_ring_config(struct hns3_nic_priv * priv)4917 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4918 {
4919 struct hnae3_handle *h = priv->ae_handle;
4920 struct pci_dev *pdev = h->pdev;
4921 int i;
4922
4923 priv->ring = devm_kzalloc(&pdev->dev,
4924 array3_size(h->kinfo.num_tqps,
4925 sizeof(*priv->ring), 2),
4926 GFP_KERNEL);
4927 if (!priv->ring)
4928 return -ENOMEM;
4929
4930 for (i = 0; i < h->kinfo.num_tqps; i++)
4931 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
4932
4933 return 0;
4934 }
4935
hns3_put_ring_config(struct hns3_nic_priv * priv)4936 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4937 {
4938 if (!priv->ring)
4939 return;
4940
4941 devm_kfree(priv->dev, priv->ring);
4942 priv->ring = NULL;
4943 }
4944
hns3_alloc_page_pool(struct hns3_enet_ring * ring)4945 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
4946 {
4947 struct page_pool_params pp_params = {
4948 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
4949 .order = hns3_page_order(ring),
4950 .pool_size = ring->desc_num * hns3_buf_size(ring) /
4951 (PAGE_SIZE << hns3_page_order(ring)),
4952 .nid = dev_to_node(ring_to_dev(ring)),
4953 .dev = ring_to_dev(ring),
4954 .dma_dir = DMA_FROM_DEVICE,
4955 .offset = 0,
4956 .max_len = PAGE_SIZE << hns3_page_order(ring),
4957 };
4958
4959 ring->page_pool = page_pool_create(&pp_params);
4960 if (IS_ERR(ring->page_pool)) {
4961 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
4962 PTR_ERR(ring->page_pool));
4963 ring->page_pool = NULL;
4964 }
4965 }
4966
hns3_alloc_ring_memory(struct hns3_enet_ring * ring)4967 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
4968 {
4969 int ret;
4970
4971 if (ring->desc_num <= 0 || ring->buf_size <= 0)
4972 return -EINVAL;
4973
4974 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
4975 sizeof(ring->desc_cb[0]), GFP_KERNEL);
4976 if (!ring->desc_cb) {
4977 ret = -ENOMEM;
4978 goto out;
4979 }
4980
4981 ret = hns3_alloc_desc(ring);
4982 if (ret)
4983 goto out_with_desc_cb;
4984
4985 if (!HNAE3_IS_TX_RING(ring)) {
4986 if (page_pool_enabled)
4987 hns3_alloc_page_pool(ring);
4988
4989 ret = hns3_alloc_ring_buffers(ring);
4990 if (ret)
4991 goto out_with_desc;
4992 } else {
4993 hns3_init_tx_spare_buffer(ring);
4994 }
4995
4996 return 0;
4997
4998 out_with_desc:
4999 hns3_free_desc(ring);
5000 out_with_desc_cb:
5001 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5002 ring->desc_cb = NULL;
5003 out:
5004 return ret;
5005 }
5006
hns3_fini_ring(struct hns3_enet_ring * ring)5007 void hns3_fini_ring(struct hns3_enet_ring *ring)
5008 {
5009 hns3_free_desc(ring);
5010 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5011 ring->desc_cb = NULL;
5012 ring->next_to_clean = 0;
5013 ring->next_to_use = 0;
5014 ring->last_to_use = 0;
5015 ring->pending_buf = 0;
5016 if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
5017 dev_kfree_skb_any(ring->skb);
5018 ring->skb = NULL;
5019 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
5020 struct hns3_tx_spare *tx_spare = ring->tx_spare;
5021
5022 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
5023 DMA_TO_DEVICE);
5024 free_pages((unsigned long)tx_spare->buf,
5025 get_order(tx_spare->len));
5026 devm_kfree(ring_to_dev(ring), tx_spare);
5027 ring->tx_spare = NULL;
5028 }
5029
5030 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
5031 page_pool_destroy(ring->page_pool);
5032 ring->page_pool = NULL;
5033 }
5034 }
5035
hns3_buf_size2type(u32 buf_size)5036 static int hns3_buf_size2type(u32 buf_size)
5037 {
5038 int bd_size_type;
5039
5040 switch (buf_size) {
5041 case 512:
5042 bd_size_type = HNS3_BD_SIZE_512_TYPE;
5043 break;
5044 case 1024:
5045 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
5046 break;
5047 case 2048:
5048 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5049 break;
5050 case 4096:
5051 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
5052 break;
5053 default:
5054 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5055 }
5056
5057 return bd_size_type;
5058 }
5059
hns3_init_ring_hw(struct hns3_enet_ring * ring)5060 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
5061 {
5062 dma_addr_t dma = ring->desc_dma_addr;
5063 struct hnae3_queue *q = ring->tqp;
5064
5065 if (!HNAE3_IS_TX_RING(ring)) {
5066 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
5067 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
5068 (u32)((dma >> 31) >> 1));
5069
5070 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
5071 hns3_buf_size2type(ring->buf_size));
5072 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
5073 ring->desc_num / 8 - 1);
5074 } else {
5075 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
5076 (u32)dma);
5077 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
5078 (u32)((dma >> 31) >> 1));
5079
5080 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
5081 ring->desc_num / 8 - 1);
5082 }
5083 }
5084
hns3_init_tx_ring_tc(struct hns3_nic_priv * priv)5085 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
5086 {
5087 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5088 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5089 int i;
5090
5091 for (i = 0; i < tc_info->num_tc; i++) {
5092 int j;
5093
5094 for (j = 0; j < tc_info->tqp_count[i]; j++) {
5095 struct hnae3_queue *q;
5096
5097 q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
5098 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
5099 }
5100 }
5101 }
5102
hns3_init_all_ring(struct hns3_nic_priv * priv)5103 int hns3_init_all_ring(struct hns3_nic_priv *priv)
5104 {
5105 struct hnae3_handle *h = priv->ae_handle;
5106 int ring_num = h->kinfo.num_tqps * 2;
5107 int i, j;
5108 int ret;
5109
5110 for (i = 0; i < ring_num; i++) {
5111 ret = hns3_alloc_ring_memory(&priv->ring[i]);
5112 if (ret) {
5113 dev_err(priv->dev,
5114 "Alloc ring memory fail! ret=%d\n", ret);
5115 goto out_when_alloc_ring_memory;
5116 }
5117
5118 u64_stats_init(&priv->ring[i].syncp);
5119 cond_resched();
5120 }
5121
5122 return 0;
5123
5124 out_when_alloc_ring_memory:
5125 for (j = i - 1; j >= 0; j--)
5126 hns3_fini_ring(&priv->ring[j]);
5127
5128 return -ENOMEM;
5129 }
5130
hns3_uninit_all_ring(struct hns3_nic_priv * priv)5131 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
5132 {
5133 struct hnae3_handle *h = priv->ae_handle;
5134 int i;
5135
5136 for (i = 0; i < h->kinfo.num_tqps; i++) {
5137 hns3_fini_ring(&priv->ring[i]);
5138 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
5139 }
5140 }
5141
5142 /* Set mac addr if it is configured. or leave it to the AE driver */
hns3_init_mac_addr(struct net_device * netdev)5143 static int hns3_init_mac_addr(struct net_device *netdev)
5144 {
5145 struct hns3_nic_priv *priv = netdev_priv(netdev);
5146 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5147 struct hnae3_handle *h = priv->ae_handle;
5148 u8 mac_addr_temp[ETH_ALEN] = {0};
5149 int ret = 0;
5150
5151 if (h->ae_algo->ops->get_mac_addr)
5152 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
5153
5154 /* Check if the MAC address is valid, if not get a random one */
5155 if (!is_valid_ether_addr(mac_addr_temp)) {
5156 eth_hw_addr_random(netdev);
5157 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr);
5158 dev_warn(priv->dev, "using random MAC address %s\n",
5159 format_mac_addr);
5160 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
5161 eth_hw_addr_set(netdev, mac_addr_temp);
5162 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
5163 } else {
5164 return 0;
5165 }
5166
5167 if (h->ae_algo->ops->set_mac_addr)
5168 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
5169
5170 return ret;
5171 }
5172
hns3_init_phy(struct net_device * netdev)5173 static int hns3_init_phy(struct net_device *netdev)
5174 {
5175 struct hnae3_handle *h = hns3_get_handle(netdev);
5176 int ret = 0;
5177
5178 if (h->ae_algo->ops->mac_connect_phy)
5179 ret = h->ae_algo->ops->mac_connect_phy(h);
5180
5181 return ret;
5182 }
5183
hns3_uninit_phy(struct net_device * netdev)5184 static void hns3_uninit_phy(struct net_device *netdev)
5185 {
5186 struct hnae3_handle *h = hns3_get_handle(netdev);
5187
5188 if (h->ae_algo->ops->mac_disconnect_phy)
5189 h->ae_algo->ops->mac_disconnect_phy(h);
5190 }
5191
hns3_client_start(struct hnae3_handle * handle)5192 static int hns3_client_start(struct hnae3_handle *handle)
5193 {
5194 if (!handle->ae_algo->ops->client_start)
5195 return 0;
5196
5197 return handle->ae_algo->ops->client_start(handle);
5198 }
5199
hns3_client_stop(struct hnae3_handle * handle)5200 static void hns3_client_stop(struct hnae3_handle *handle)
5201 {
5202 if (!handle->ae_algo->ops->client_stop)
5203 return;
5204
5205 handle->ae_algo->ops->client_stop(handle);
5206 }
5207
hns3_info_show(struct hns3_nic_priv * priv)5208 static void hns3_info_show(struct hns3_nic_priv *priv)
5209 {
5210 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5211 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5212
5213 hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr);
5214 dev_info(priv->dev, "MAC address: %s\n", format_mac_addr);
5215 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
5216 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
5217 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
5218 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
5219 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
5220 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
5221 dev_info(priv->dev, "Total number of enabled TCs: %u\n",
5222 kinfo->tc_info.num_tc);
5223 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
5224 }
5225
hns3_set_cq_period_mode(struct hns3_nic_priv * priv,enum dim_cq_period_mode mode,bool is_tx)5226 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
5227 enum dim_cq_period_mode mode, bool is_tx)
5228 {
5229 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
5230 struct hnae3_handle *handle = priv->ae_handle;
5231 int i;
5232
5233 if (is_tx) {
5234 priv->tx_cqe_mode = mode;
5235
5236 for (i = 0; i < priv->vector_num; i++)
5237 priv->tqp_vector[i].tx_group.dim.mode = mode;
5238 } else {
5239 priv->rx_cqe_mode = mode;
5240
5241 for (i = 0; i < priv->vector_num; i++)
5242 priv->tqp_vector[i].rx_group.dim.mode = mode;
5243 }
5244
5245 if (hnae3_ae_dev_cq_supported(ae_dev)) {
5246 u32 new_mode;
5247 u64 reg;
5248
5249 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5250 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5251 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5252
5253 writel(new_mode, handle->kinfo.io_base + reg);
5254 }
5255 }
5256
hns3_cq_period_mode_init(struct hns3_nic_priv * priv,enum dim_cq_period_mode tx_mode,enum dim_cq_period_mode rx_mode)5257 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5258 enum dim_cq_period_mode tx_mode,
5259 enum dim_cq_period_mode rx_mode)
5260 {
5261 hns3_set_cq_period_mode(priv, tx_mode, true);
5262 hns3_set_cq_period_mode(priv, rx_mode, false);
5263 }
5264
hns3_state_init(struct hnae3_handle * handle)5265 static void hns3_state_init(struct hnae3_handle *handle)
5266 {
5267 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
5268 struct net_device *netdev = handle->kinfo.netdev;
5269 struct hns3_nic_priv *priv = netdev_priv(netdev);
5270
5271 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5272
5273 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
5274 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state);
5275
5276 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5277 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5278
5279 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5280 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5281
5282 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5283 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5284 }
5285
hns3_state_uninit(struct hnae3_handle * handle)5286 static void hns3_state_uninit(struct hnae3_handle *handle)
5287 {
5288 struct hns3_nic_priv *priv = handle->priv;
5289
5290 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
5291 }
5292
hns3_client_init(struct hnae3_handle * handle)5293 static int hns3_client_init(struct hnae3_handle *handle)
5294 {
5295 struct pci_dev *pdev = handle->pdev;
5296 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5297 u16 alloc_tqps, max_rss_size;
5298 struct hns3_nic_priv *priv;
5299 struct net_device *netdev;
5300 int ret;
5301
5302 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5303 &max_rss_size);
5304 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
5305 if (!netdev)
5306 return -ENOMEM;
5307
5308 priv = netdev_priv(netdev);
5309 priv->dev = &pdev->dev;
5310 priv->netdev = netdev;
5311 priv->ae_handle = handle;
5312 priv->tx_timeout_count = 0;
5313 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
5314 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5315
5316 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5317
5318 handle->kinfo.netdev = netdev;
5319 handle->priv = (void *)priv;
5320
5321 hns3_init_mac_addr(netdev);
5322
5323 hns3_set_default_feature(netdev);
5324
5325 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5326 netdev->priv_flags |= IFF_UNICAST_FLT;
5327 netdev->netdev_ops = &hns3_nic_netdev_ops;
5328 SET_NETDEV_DEV(netdev, &pdev->dev);
5329 hns3_ethtool_set_ops(netdev);
5330
5331 /* Carrier off reporting is important to ethtool even BEFORE open */
5332 netif_carrier_off(netdev);
5333
5334 ret = hns3_get_ring_config(priv);
5335 if (ret) {
5336 ret = -ENOMEM;
5337 goto out_get_ring_cfg;
5338 }
5339
5340 hns3_nic_init_coal_cfg(priv);
5341
5342 ret = hns3_nic_alloc_vector_data(priv);
5343 if (ret) {
5344 ret = -ENOMEM;
5345 goto out_alloc_vector_data;
5346 }
5347
5348 ret = hns3_nic_init_vector_data(priv);
5349 if (ret) {
5350 ret = -ENOMEM;
5351 goto out_init_vector_data;
5352 }
5353
5354 ret = hns3_init_all_ring(priv);
5355 if (ret) {
5356 ret = -ENOMEM;
5357 goto out_init_ring;
5358 }
5359
5360 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5361 DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5362
5363 ret = hns3_init_phy(netdev);
5364 if (ret)
5365 goto out_init_phy;
5366
5367 /* the device can work without cpu rmap, only aRFS needs it */
5368 ret = hns3_set_rx_cpu_rmap(netdev);
5369 if (ret)
5370 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5371
5372 ret = hns3_nic_init_irq(priv);
5373 if (ret) {
5374 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5375 hns3_free_rx_cpu_rmap(netdev);
5376 goto out_init_irq_fail;
5377 }
5378
5379 ret = hns3_client_start(handle);
5380 if (ret) {
5381 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5382 goto out_client_start;
5383 }
5384
5385 hns3_dcbnl_setup(handle);
5386
5387 ret = hns3_dbg_init(handle);
5388 if (ret) {
5389 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5390 ret);
5391 goto out_client_start;
5392 }
5393
5394 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
5395
5396 hns3_state_init(handle);
5397
5398 ret = register_netdev(netdev);
5399 if (ret) {
5400 dev_err(priv->dev, "probe register netdev fail!\n");
5401 goto out_reg_netdev_fail;
5402 }
5403
5404 if (netif_msg_drv(handle))
5405 hns3_info_show(priv);
5406
5407 return ret;
5408
5409 out_reg_netdev_fail:
5410 hns3_state_uninit(handle);
5411 hns3_dbg_uninit(handle);
5412 hns3_client_stop(handle);
5413 out_client_start:
5414 hns3_free_rx_cpu_rmap(netdev);
5415 hns3_nic_uninit_irq(priv);
5416 out_init_irq_fail:
5417 hns3_uninit_phy(netdev);
5418 out_init_phy:
5419 hns3_uninit_all_ring(priv);
5420 out_init_ring:
5421 hns3_nic_uninit_vector_data(priv);
5422 out_init_vector_data:
5423 hns3_nic_dealloc_vector_data(priv);
5424 out_alloc_vector_data:
5425 priv->ring = NULL;
5426 out_get_ring_cfg:
5427 priv->ae_handle = NULL;
5428 free_netdev(netdev);
5429 return ret;
5430 }
5431
hns3_client_uninit(struct hnae3_handle * handle,bool reset)5432 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5433 {
5434 struct net_device *netdev = handle->kinfo.netdev;
5435 struct hns3_nic_priv *priv = netdev_priv(netdev);
5436
5437 if (netdev->reg_state != NETREG_UNINITIALIZED)
5438 unregister_netdev(netdev);
5439
5440 hns3_client_stop(handle);
5441
5442 hns3_uninit_phy(netdev);
5443
5444 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5445 netdev_warn(netdev, "already uninitialized\n");
5446 goto out_netdev_free;
5447 }
5448
5449 hns3_free_rx_cpu_rmap(netdev);
5450
5451 hns3_nic_uninit_irq(priv);
5452
5453 hns3_clear_all_ring(handle, true);
5454
5455 hns3_nic_uninit_vector_data(priv);
5456
5457 hns3_nic_dealloc_vector_data(priv);
5458
5459 hns3_uninit_all_ring(priv);
5460
5461 hns3_put_ring_config(priv);
5462
5463 out_netdev_free:
5464 hns3_dbg_uninit(handle);
5465 free_netdev(netdev);
5466 }
5467
hns3_link_status_change(struct hnae3_handle * handle,bool linkup)5468 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5469 {
5470 struct net_device *netdev = handle->kinfo.netdev;
5471
5472 if (!netdev)
5473 return;
5474
5475 if (linkup) {
5476 netif_tx_wake_all_queues(netdev);
5477 netif_carrier_on(netdev);
5478 if (netif_msg_link(handle))
5479 netdev_info(netdev, "link up\n");
5480 } else {
5481 netif_carrier_off(netdev);
5482 netif_tx_stop_all_queues(netdev);
5483 if (netif_msg_link(handle))
5484 netdev_info(netdev, "link down\n");
5485 }
5486 }
5487
hns3_clear_tx_ring(struct hns3_enet_ring * ring)5488 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
5489 {
5490 while (ring->next_to_clean != ring->next_to_use) {
5491 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
5492 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
5493 ring_ptr_move_fw(ring, next_to_clean);
5494 }
5495
5496 ring->pending_buf = 0;
5497 }
5498
hns3_clear_rx_ring(struct hns3_enet_ring * ring)5499 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5500 {
5501 struct hns3_desc_cb res_cbs;
5502 int ret;
5503
5504 while (ring->next_to_use != ring->next_to_clean) {
5505 /* When a buffer is not reused, it's memory has been
5506 * freed in hns3_handle_rx_bd or will be freed by
5507 * stack, so we need to replace the buffer here.
5508 */
5509 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5510 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
5511 if (ret) {
5512 hns3_ring_stats_update(ring, sw_err_cnt);
5513 /* if alloc new buffer fail, exit directly
5514 * and reclear in up flow.
5515 */
5516 netdev_warn(ring_to_netdev(ring),
5517 "reserve buffer map failed, ret = %d\n",
5518 ret);
5519 return ret;
5520 }
5521 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
5522 }
5523 ring_ptr_move_fw(ring, next_to_use);
5524 }
5525
5526 /* Free the pending skb in rx ring */
5527 if (ring->skb) {
5528 dev_kfree_skb_any(ring->skb);
5529 ring->skb = NULL;
5530 ring->pending_buf = 0;
5531 }
5532
5533 return 0;
5534 }
5535
hns3_force_clear_rx_ring(struct hns3_enet_ring * ring)5536 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
5537 {
5538 while (ring->next_to_use != ring->next_to_clean) {
5539 /* When a buffer is not reused, it's memory has been
5540 * freed in hns3_handle_rx_bd or will be freed by
5541 * stack, so only need to unmap the buffer here.
5542 */
5543 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5544 hns3_unmap_buffer(ring,
5545 &ring->desc_cb[ring->next_to_use]);
5546 ring->desc_cb[ring->next_to_use].dma = 0;
5547 }
5548
5549 ring_ptr_move_fw(ring, next_to_use);
5550 }
5551 }
5552
hns3_clear_all_ring(struct hnae3_handle * h,bool force)5553 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
5554 {
5555 struct net_device *ndev = h->kinfo.netdev;
5556 struct hns3_nic_priv *priv = netdev_priv(ndev);
5557 u32 i;
5558
5559 for (i = 0; i < h->kinfo.num_tqps; i++) {
5560 struct hns3_enet_ring *ring;
5561
5562 ring = &priv->ring[i];
5563 hns3_clear_tx_ring(ring);
5564
5565 ring = &priv->ring[i + h->kinfo.num_tqps];
5566 /* Continue to clear other rings even if clearing some
5567 * rings failed.
5568 */
5569 if (force)
5570 hns3_force_clear_rx_ring(ring);
5571 else
5572 hns3_clear_rx_ring(ring);
5573 }
5574 }
5575
hns3_nic_reset_all_ring(struct hnae3_handle * h)5576 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5577 {
5578 struct net_device *ndev = h->kinfo.netdev;
5579 struct hns3_nic_priv *priv = netdev_priv(ndev);
5580 struct hns3_enet_ring *rx_ring;
5581 int i, j;
5582 int ret;
5583
5584 ret = h->ae_algo->ops->reset_queue(h);
5585 if (ret)
5586 return ret;
5587
5588 for (i = 0; i < h->kinfo.num_tqps; i++) {
5589 hns3_init_ring_hw(&priv->ring[i]);
5590
5591 /* We need to clear tx ring here because self test will
5592 * use the ring and will not run down before up
5593 */
5594 hns3_clear_tx_ring(&priv->ring[i]);
5595 priv->ring[i].next_to_clean = 0;
5596 priv->ring[i].next_to_use = 0;
5597 priv->ring[i].last_to_use = 0;
5598
5599 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
5600 hns3_init_ring_hw(rx_ring);
5601 ret = hns3_clear_rx_ring(rx_ring);
5602 if (ret)
5603 return ret;
5604
5605 /* We can not know the hardware head and tail when this
5606 * function is called in reset flow, so we reuse all desc.
5607 */
5608 for (j = 0; j < rx_ring->desc_num; j++)
5609 hns3_reuse_buffer(rx_ring, j);
5610
5611 rx_ring->next_to_clean = 0;
5612 rx_ring->next_to_use = 0;
5613 }
5614
5615 hns3_init_tx_ring_tc(priv);
5616
5617 return 0;
5618 }
5619
hns3_reset_notify_down_enet(struct hnae3_handle * handle)5620 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5621 {
5622 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5623 struct net_device *ndev = kinfo->netdev;
5624 struct hns3_nic_priv *priv = netdev_priv(ndev);
5625
5626 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5627 return 0;
5628
5629 if (!netif_running(ndev))
5630 return 0;
5631
5632 return hns3_nic_net_stop(ndev);
5633 }
5634
hns3_reset_notify_up_enet(struct hnae3_handle * handle)5635 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5636 {
5637 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5638 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
5639 int ret = 0;
5640
5641 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5642 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5643 return -EFAULT;
5644 }
5645
5646 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5647
5648 if (netif_running(kinfo->netdev)) {
5649 ret = hns3_nic_net_open(kinfo->netdev);
5650 if (ret) {
5651 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5652 netdev_err(kinfo->netdev,
5653 "net up fail, ret=%d!\n", ret);
5654 return ret;
5655 }
5656 }
5657
5658 return ret;
5659 }
5660
hns3_reset_notify_init_enet(struct hnae3_handle * handle)5661 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5662 {
5663 struct net_device *netdev = handle->kinfo.netdev;
5664 struct hns3_nic_priv *priv = netdev_priv(netdev);
5665 int ret;
5666
5667 /* Carrier off reporting is important to ethtool even BEFORE open */
5668 netif_carrier_off(netdev);
5669
5670 ret = hns3_get_ring_config(priv);
5671 if (ret)
5672 return ret;
5673
5674 ret = hns3_nic_alloc_vector_data(priv);
5675 if (ret)
5676 goto err_put_ring;
5677
5678 ret = hns3_nic_init_vector_data(priv);
5679 if (ret)
5680 goto err_dealloc_vector;
5681
5682 ret = hns3_init_all_ring(priv);
5683 if (ret)
5684 goto err_uninit_vector;
5685
5686 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5687
5688 /* the device can work without cpu rmap, only aRFS needs it */
5689 ret = hns3_set_rx_cpu_rmap(netdev);
5690 if (ret)
5691 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5692
5693 ret = hns3_nic_init_irq(priv);
5694 if (ret) {
5695 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5696 hns3_free_rx_cpu_rmap(netdev);
5697 goto err_init_irq_fail;
5698 }
5699
5700 if (!hns3_is_phys_func(handle->pdev))
5701 hns3_init_mac_addr(netdev);
5702
5703 ret = hns3_client_start(handle);
5704 if (ret) {
5705 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5706 goto err_client_start_fail;
5707 }
5708
5709 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5710
5711 return ret;
5712
5713 err_client_start_fail:
5714 hns3_free_rx_cpu_rmap(netdev);
5715 hns3_nic_uninit_irq(priv);
5716 err_init_irq_fail:
5717 hns3_uninit_all_ring(priv);
5718 err_uninit_vector:
5719 hns3_nic_uninit_vector_data(priv);
5720 err_dealloc_vector:
5721 hns3_nic_dealloc_vector_data(priv);
5722 err_put_ring:
5723 hns3_put_ring_config(priv);
5724
5725 return ret;
5726 }
5727
hns3_reset_notify_uninit_enet(struct hnae3_handle * handle)5728 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5729 {
5730 struct net_device *netdev = handle->kinfo.netdev;
5731 struct hns3_nic_priv *priv = netdev_priv(netdev);
5732
5733 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5734 hns3_nic_net_stop(netdev);
5735
5736 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5737 netdev_warn(netdev, "already uninitialized\n");
5738 return 0;
5739 }
5740
5741 hns3_free_rx_cpu_rmap(netdev);
5742 hns3_nic_uninit_irq(priv);
5743 hns3_clear_all_ring(handle, true);
5744 hns3_reset_tx_queue(priv->ae_handle);
5745
5746 hns3_nic_uninit_vector_data(priv);
5747
5748 hns3_nic_dealloc_vector_data(priv);
5749
5750 hns3_uninit_all_ring(priv);
5751
5752 hns3_put_ring_config(priv);
5753
5754 return 0;
5755 }
5756
hns3_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)5757 int hns3_reset_notify(struct hnae3_handle *handle,
5758 enum hnae3_reset_notify_type type)
5759 {
5760 int ret = 0;
5761
5762 switch (type) {
5763 case HNAE3_UP_CLIENT:
5764 ret = hns3_reset_notify_up_enet(handle);
5765 break;
5766 case HNAE3_DOWN_CLIENT:
5767 ret = hns3_reset_notify_down_enet(handle);
5768 break;
5769 case HNAE3_INIT_CLIENT:
5770 ret = hns3_reset_notify_init_enet(handle);
5771 break;
5772 case HNAE3_UNINIT_CLIENT:
5773 ret = hns3_reset_notify_uninit_enet(handle);
5774 break;
5775 default:
5776 break;
5777 }
5778
5779 return ret;
5780 }
5781
hns3_change_channels(struct hnae3_handle * handle,u32 new_tqp_num,bool rxfh_configured)5782 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5783 bool rxfh_configured)
5784 {
5785 int ret;
5786
5787 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5788 rxfh_configured);
5789 if (ret) {
5790 dev_err(&handle->pdev->dev,
5791 "Change tqp num(%u) fail.\n", new_tqp_num);
5792 return ret;
5793 }
5794
5795 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5796 if (ret)
5797 return ret;
5798
5799 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5800 if (ret)
5801 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5802
5803 return ret;
5804 }
5805
hns3_set_channels(struct net_device * netdev,struct ethtool_channels * ch)5806 int hns3_set_channels(struct net_device *netdev,
5807 struct ethtool_channels *ch)
5808 {
5809 struct hnae3_handle *h = hns3_get_handle(netdev);
5810 struct hnae3_knic_private_info *kinfo = &h->kinfo;
5811 bool rxfh_configured = netif_is_rxfh_configured(netdev);
5812 u32 new_tqp_num = ch->combined_count;
5813 u16 org_tqp_num;
5814 int ret;
5815
5816 if (hns3_nic_resetting(netdev))
5817 return -EBUSY;
5818
5819 if (ch->rx_count || ch->tx_count)
5820 return -EINVAL;
5821
5822 if (kinfo->tc_info.mqprio_active) {
5823 dev_err(&netdev->dev,
5824 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5825 return -EINVAL;
5826 }
5827
5828 if (new_tqp_num > hns3_get_max_available_channels(h) ||
5829 new_tqp_num < 1) {
5830 dev_err(&netdev->dev,
5831 "Change tqps fail, the tqp range is from 1 to %u",
5832 hns3_get_max_available_channels(h));
5833 return -EINVAL;
5834 }
5835
5836 if (kinfo->rss_size == new_tqp_num)
5837 return 0;
5838
5839 netif_dbg(h, drv, netdev,
5840 "set channels: tqp_num=%u, rxfh=%d\n",
5841 new_tqp_num, rxfh_configured);
5842
5843 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5844 if (ret)
5845 return ret;
5846
5847 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5848 if (ret)
5849 return ret;
5850
5851 org_tqp_num = h->kinfo.num_tqps;
5852 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
5853 if (ret) {
5854 int ret1;
5855
5856 netdev_warn(netdev,
5857 "Change channels fail, revert to old value\n");
5858 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5859 if (ret1) {
5860 netdev_err(netdev,
5861 "revert to old channel fail\n");
5862 return ret1;
5863 }
5864
5865 return ret;
5866 }
5867
5868 return 0;
5869 }
5870
hns3_external_lb_prepare(struct net_device * ndev,bool if_running)5871 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running)
5872 {
5873 struct hns3_nic_priv *priv = netdev_priv(ndev);
5874
5875 if (!if_running)
5876 return;
5877
5878 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5879 return;
5880
5881 netif_carrier_off(ndev);
5882 netif_tx_disable(ndev);
5883
5884 hns3_disable_irqs_and_tqps(ndev);
5885
5886 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
5887 * during reset process, because driver may not be able
5888 * to disable the ring through firmware when downing the netdev.
5889 */
5890 if (!hns3_nic_resetting(ndev))
5891 hns3_nic_reset_all_ring(priv->ae_handle);
5892
5893 hns3_reset_tx_queue(priv->ae_handle);
5894 }
5895
hns3_external_lb_restore(struct net_device * ndev,bool if_running)5896 void hns3_external_lb_restore(struct net_device *ndev, bool if_running)
5897 {
5898 struct hns3_nic_priv *priv = netdev_priv(ndev);
5899 struct hnae3_handle *h = priv->ae_handle;
5900
5901 if (!if_running)
5902 return;
5903
5904 if (hns3_nic_resetting(ndev))
5905 return;
5906
5907 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5908 return;
5909
5910 if (hns3_nic_reset_all_ring(priv->ae_handle))
5911 return;
5912
5913 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5914
5915 hns3_enable_irqs_and_tqps(ndev);
5916
5917 netif_tx_wake_all_queues(ndev);
5918
5919 if (h->ae_algo->ops->get_status(h))
5920 netif_carrier_on(ndev);
5921 }
5922
5923 static const struct hns3_hw_error_info hns3_hw_err[] = {
5924 { .type = HNAE3_PPU_POISON_ERROR,
5925 .msg = "PPU poison" },
5926 { .type = HNAE3_CMDQ_ECC_ERROR,
5927 .msg = "IMP CMDQ error" },
5928 { .type = HNAE3_IMP_RD_POISON_ERROR,
5929 .msg = "IMP RD poison" },
5930 { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5931 .msg = "ROCEE AXI RESP error" },
5932 };
5933
hns3_process_hw_error(struct hnae3_handle * handle,enum hnae3_hw_error_type type)5934 static void hns3_process_hw_error(struct hnae3_handle *handle,
5935 enum hnae3_hw_error_type type)
5936 {
5937 int i;
5938
5939 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
5940 if (hns3_hw_err[i].type == type) {
5941 dev_err(&handle->pdev->dev, "Detected %s!\n",
5942 hns3_hw_err[i].msg);
5943 break;
5944 }
5945 }
5946 }
5947
5948 static const struct hnae3_client_ops client_ops = {
5949 .init_instance = hns3_client_init,
5950 .uninit_instance = hns3_client_uninit,
5951 .link_status_change = hns3_link_status_change,
5952 .reset_notify = hns3_reset_notify,
5953 .process_hw_error = hns3_process_hw_error,
5954 };
5955
5956 /* hns3_init_module - Driver registration routine
5957 * hns3_init_module is the first routine called when the driver is
5958 * loaded. All it does is register with the PCI subsystem.
5959 */
hns3_init_module(void)5960 static int __init hns3_init_module(void)
5961 {
5962 int ret;
5963
5964 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
5965 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
5966
5967 client.type = HNAE3_CLIENT_KNIC;
5968 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
5969 hns3_driver_name);
5970
5971 client.ops = &client_ops;
5972
5973 INIT_LIST_HEAD(&client.node);
5974
5975 hns3_dbg_register_debugfs(hns3_driver_name);
5976
5977 ret = hnae3_register_client(&client);
5978 if (ret)
5979 goto err_reg_client;
5980
5981 ret = pci_register_driver(&hns3_driver);
5982 if (ret)
5983 goto err_reg_driver;
5984
5985 return ret;
5986
5987 err_reg_driver:
5988 hnae3_unregister_client(&client);
5989 err_reg_client:
5990 hns3_dbg_unregister_debugfs();
5991 return ret;
5992 }
5993 module_init(hns3_init_module);
5994
5995 /* hns3_exit_module - Driver exit cleanup routine
5996 * hns3_exit_module is called just before the driver is removed
5997 * from memory.
5998 */
hns3_exit_module(void)5999 static void __exit hns3_exit_module(void)
6000 {
6001 hnae3_acquire_unload_lock();
6002 pci_unregister_driver(&hns3_driver);
6003 hnae3_unregister_client(&client);
6004 hns3_dbg_unregister_debugfs();
6005 hnae3_release_unload_lock();
6006 }
6007 module_exit(hns3_exit_module);
6008
6009 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
6010 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6011 MODULE_LICENSE("GPL");
6012 MODULE_ALIAS("pci:hns-nic");
6013