1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2021-2025 Intel Corporation 4 * 5 * Authors: Cezary Rojewski <cezary.rojewski@intel.com> 6 * Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com> 7 */ 8 9 #include <sound/hdaudio_ext.h> 10 #include "avs.h" 11 #include "debug.h" 12 #include "registers.h" 13 #include "trace.h" 14 15 #define MTL_HfDSSGBL_BASE 0x1000 16 #define MTL_REG_HfDSSCS (MTL_HfDSSGBL_BASE + 0x0) 17 #define MTL_HfDSSCS_SPA BIT(16) 18 #define MTL_HfDSSCS_CPA BIT(24) 19 20 #define MTL_DSPCS_BASE 0x178D00 21 #define MTL_REG_DSPCCTL (MTL_DSPCS_BASE + 0x4) 22 #define MTL_DSPCCTL_SPA BIT(0) 23 #define MTL_DSPCCTL_CPA BIT(8) 24 #define MTL_DSPCCTL_OSEL GENMASK(25, 24) 25 #define MTL_DSPCCTL_OSEL_HOST BIT(25) 26 27 #define MTL_HfINT_BASE 0x1100 28 #define MTL_REG_HfINTIPPTR (MTL_HfINT_BASE + 0x8) 29 #define MTL_REG_HfHIPCIE (MTL_HfINT_BASE + 0x40) 30 #define MTL_HfINTIPPTR_PTR GENMASK(20, 0) 31 #define MTL_HfHIPCIE_IE BIT(0) 32 33 #define MTL_DWICTL_INTENL_IE BIT(0) 34 #define MTL_DWICTL_FINALSTATUSL_IPC BIT(0) /* same as ADSPIS_IPC */ 35 36 static int avs_mtl_core_power_on(struct avs_dev *adev) 37 { 38 u32 reg; 39 int ret; 40 41 /* Power up DSP domain. */ 42 snd_hdac_adsp_updatel(adev, MTL_REG_HfDSSCS, MTL_HfDSSCS_SPA, MTL_HfDSSCS_SPA); 43 trace_avs_dsp_core_op(1, AVS_MAIN_CORE_MASK, "power dsp", true); 44 45 ret = snd_hdac_adsp_readl_poll(adev, MTL_REG_HfDSSCS, reg, 46 (reg & MTL_HfDSSCS_CPA) == MTL_HfDSSCS_CPA, 47 AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US); 48 if (ret) { 49 dev_err(adev->dev, "power on domain dsp failed: %d\n", ret); 50 return ret; 51 } 52 53 /* Prevent power gating of DSP domain. */ 54 snd_hdac_adsp_updatel(adev, MTL_REG_HfPWRCTL, MTL_HfPWRCTL_WPDSPHPxPG, 55 MTL_HfPWRCTL_WPDSPHPxPG); 56 trace_avs_dsp_core_op(1, AVS_MAIN_CORE_MASK, "prevent dsp PG", true); 57 58 ret = snd_hdac_adsp_readl_poll(adev, MTL_REG_HfPWRSTS, reg, 59 (reg & MTL_HfPWRSTS_DSPHPxPGS) == MTL_HfPWRSTS_DSPHPxPGS, 60 AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US); 61 62 /* Set ownership to HOST. */ 63 snd_hdac_adsp_updatel(adev, MTL_REG_DSPCCTL, MTL_DSPCCTL_OSEL, MTL_DSPCCTL_OSEL_HOST); 64 return ret; 65 } 66 67 static int avs_mtl_core_power_off(struct avs_dev *adev) 68 { 69 u32 reg; 70 71 /* Allow power gating of DSP domain. No STS polling as HOST is only one of its users. */ 72 snd_hdac_adsp_updatel(adev, MTL_REG_HfPWRCTL, MTL_HfPWRCTL_WPDSPHPxPG, 0); 73 trace_avs_dsp_core_op(0, AVS_MAIN_CORE_MASK, "allow dsp pg", false); 74 75 /* Power down DSP domain. */ 76 snd_hdac_adsp_updatel(adev, MTL_REG_HfDSSCS, MTL_HfDSSCS_SPA, 0); 77 trace_avs_dsp_core_op(0, AVS_MAIN_CORE_MASK, "power dsp", false); 78 79 return snd_hdac_adsp_readl_poll(adev, MTL_REG_HfDSSCS, reg, 80 (reg & MTL_HfDSSCS_CPA) == 0, 81 AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US); 82 } 83 84 int avs_mtl_core_power(struct avs_dev *adev, u32 core_mask, bool power) 85 { 86 core_mask &= AVS_MAIN_CORE_MASK; 87 if (!core_mask) 88 return 0; 89 90 if (power) 91 return avs_mtl_core_power_on(adev); 92 return avs_mtl_core_power_off(adev); 93 } 94 95 int avs_mtl_core_reset(struct avs_dev *adev, u32 core_mask, bool power) 96 { 97 /* No logical equivalent on ACE 1.x. */ 98 return 0; 99 } 100 101 int avs_mtl_core_stall(struct avs_dev *adev, u32 core_mask, bool stall) 102 { 103 u32 value, reg; 104 int ret; 105 106 core_mask &= AVS_MAIN_CORE_MASK; 107 if (!core_mask) 108 return 0; 109 110 value = snd_hdac_adsp_readl(adev, MTL_REG_DSPCCTL); 111 trace_avs_dsp_core_op(value, core_mask, "stall", stall); 112 if (value == UINT_MAX) 113 return 0; 114 115 value = stall ? 0 : MTL_DSPCCTL_SPA; 116 snd_hdac_adsp_updatel(adev, MTL_REG_DSPCCTL, MTL_DSPCCTL_SPA, value); 117 118 value = stall ? 0 : MTL_DSPCCTL_CPA; 119 ret = snd_hdac_adsp_readl_poll(adev, MTL_REG_DSPCCTL, 120 reg, (reg & MTL_DSPCCTL_CPA) == value, 121 AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US); 122 if (ret) 123 dev_err(adev->dev, "core_mask %d %sstall failed: %d\n", 124 core_mask, stall ? "" : "un", ret); 125 return ret; 126 } 127 128 static void avs_mtl_ipc_interrupt(struct avs_dev *adev) 129 { 130 const struct avs_spec *spec = adev->spec; 131 u32 hipc_ack, hipc_rsp; 132 133 snd_hdac_adsp_updatel(adev, spec->hipc->ctl_offset, 134 AVS_ADSP_HIPCCTL_DONE | AVS_ADSP_HIPCCTL_BUSY, 0); 135 136 hipc_ack = snd_hdac_adsp_readl(adev, spec->hipc->ack_offset); 137 hipc_rsp = snd_hdac_adsp_readl(adev, spec->hipc->rsp_offset); 138 139 /* DSP acked host's request. */ 140 if (hipc_ack & spec->hipc->ack_done_mask) { 141 complete(&adev->ipc->done_completion); 142 143 /* Tell DSP it has our attention. */ 144 snd_hdac_adsp_updatel(adev, spec->hipc->ack_offset, spec->hipc->ack_done_mask, 145 spec->hipc->ack_done_mask); 146 } 147 148 /* DSP sent new response to process. */ 149 if (hipc_rsp & spec->hipc->rsp_busy_mask) { 150 union avs_reply_msg msg; 151 152 msg.primary = snd_hdac_adsp_readl(adev, MTL_REG_HfIPCxTDR); 153 msg.ext.val = snd_hdac_adsp_readl(adev, MTL_REG_HfIPCxTDD); 154 155 avs_dsp_process_response(adev, msg.val); 156 157 /* Tell DSP we accepted its message. */ 158 snd_hdac_adsp_updatel(adev, MTL_REG_HfIPCxTDR, 159 MTL_HfIPCxTDR_BUSY, MTL_HfIPCxTDR_BUSY); 160 /* Ack this response. */ 161 snd_hdac_adsp_updatel(adev, MTL_REG_HfIPCxTDA, MTL_HfIPCxTDA_BUSY, 0); 162 } 163 164 snd_hdac_adsp_updatel(adev, spec->hipc->ctl_offset, 165 AVS_ADSP_HIPCCTL_DONE | AVS_ADSP_HIPCCTL_BUSY, 166 AVS_ADSP_HIPCCTL_DONE | AVS_ADSP_HIPCCTL_BUSY); 167 } 168 169 irqreturn_t avs_mtl_dsp_interrupt(struct avs_dev *adev) 170 { 171 u32 adspis = snd_hdac_adsp_readl(adev, MTL_DWICTL_REG_FINALSTATUSL); 172 irqreturn_t ret = IRQ_NONE; 173 174 if (adspis == UINT_MAX) 175 return ret; 176 177 if (adspis & MTL_DWICTL_FINALSTATUSL_IPC) { 178 avs_mtl_ipc_interrupt(adev); 179 ret = IRQ_HANDLED; 180 } 181 182 return ret; 183 } 184 185 void avs_mtl_interrupt_control(struct avs_dev *adev, bool enable) 186 { 187 if (enable) { 188 snd_hdac_adsp_updatel(adev, MTL_DWICTL_REG_INTENL, MTL_DWICTL_INTENL_IE, 189 MTL_DWICTL_INTENL_IE); 190 snd_hdac_adsp_updatew(adev, MTL_REG_HfHIPCIE, MTL_HfHIPCIE_IE, MTL_HfHIPCIE_IE); 191 snd_hdac_adsp_updatel(adev, MTL_REG_HfIPCxCTL, AVS_ADSP_HIPCCTL_DONE, 192 AVS_ADSP_HIPCCTL_DONE); 193 snd_hdac_adsp_updatel(adev, MTL_REG_HfIPCxCTL, AVS_ADSP_HIPCCTL_BUSY, 194 AVS_ADSP_HIPCCTL_BUSY); 195 } else { 196 snd_hdac_adsp_updatel(adev, MTL_REG_HfIPCxCTL, AVS_ADSP_HIPCCTL_BUSY, 0); 197 snd_hdac_adsp_updatel(adev, MTL_REG_HfIPCxCTL, AVS_ADSP_HIPCCTL_DONE, 0); 198 snd_hdac_adsp_updatew(adev, MTL_REG_HfHIPCIE, MTL_HfHIPCIE_IE, 0); 199 snd_hdac_adsp_updatel(adev, MTL_DWICTL_REG_INTENL, MTL_DWICTL_INTENL_IE, 0); 200 } 201 } 202