1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * SPI ADC driver for Analog Devices Inc. AD4695 and similar chips
4 *
5 * https://www.analog.com/en/products/ad4695.html
6 * https://www.analog.com/en/products/ad4696.html
7 * https://www.analog.com/en/products/ad4697.html
8 * https://www.analog.com/en/products/ad4698.html
9 *
10 * Copyright 2024 Analog Devices Inc.
11 * Copyright 2024 BayLibre, SAS
12 */
13
14 #include <linux/align.h>
15 #include <linux/bitfield.h>
16 #include <linux/bits.h>
17 #include <linux/compiler.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/err.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/iio/buffer-dmaengine.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/iio.h>
25 #include <linux/iio/triggered_buffer.h>
26 #include <linux/iio/trigger_consumer.h>
27 #include <linux/minmax.h>
28 #include <linux/mutex.h>
29 #include <linux/property.h>
30 #include <linux/pwm.h>
31 #include <linux/regmap.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/spi/offload/consumer.h>
34 #include <linux/spi/offload/provider.h>
35 #include <linux/spi/spi.h>
36 #include <linux/units.h>
37
38 #include <dt-bindings/iio/adc/adi,ad4695.h>
39
40 /* AD4695 registers */
41 #define AD4695_REG_SPI_CONFIG_A 0x0000
42 #define AD4695_REG_SPI_CONFIG_A_SW_RST (BIT(7) | BIT(0))
43 #define AD4695_REG_SPI_CONFIG_A_ADDR_DIR BIT(5)
44 #define AD4695_REG_SPI_CONFIG_B 0x0001
45 #define AD4695_REG_SPI_CONFIG_B_INST_MODE BIT(7)
46 #define AD4695_REG_DEVICE_TYPE 0x0003
47 #define AD4695_REG_SCRATCH_PAD 0x000A
48 #define AD4695_REG_VENDOR_L 0x000C
49 #define AD4695_REG_VENDOR_H 0x000D
50 #define AD4695_REG_LOOP_MODE 0x000E
51 #define AD4695_REG_SPI_CONFIG_C 0x0010
52 #define AD4695_REG_SPI_CONFIG_C_MB_STRICT BIT(7)
53 #define AD4695_REG_SPI_STATUS 0x0011
54 #define AD4695_REG_STATUS 0x0014
55 #define AD4695_REG_ALERT_STATUS1 0x0015
56 #define AD4695_REG_ALERT_STATUS2 0x0016
57 #define AD4695_REG_CLAMP_STATUS 0x001A
58 #define AD4695_REG_SETUP 0x0020
59 #define AD4695_REG_SETUP_LDO_EN BIT(4)
60 #define AD4695_REG_SETUP_SPI_MODE BIT(2)
61 #define AD4695_REG_SETUP_SPI_CYC_CTRL BIT(1)
62 #define AD4695_REG_REF_CTRL 0x0021
63 #define AD4695_REG_REF_CTRL_OV_MODE BIT(7)
64 #define AD4695_REG_REF_CTRL_VREF_SET GENMASK(4, 2)
65 #define AD4695_REG_REF_CTRL_REFHIZ_EN BIT(1)
66 #define AD4695_REG_REF_CTRL_REFBUF_EN BIT(0)
67 #define AD4695_REG_SEQ_CTRL 0x0022
68 #define AD4695_REG_SEQ_CTRL_STD_SEQ_EN BIT(7)
69 #define AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS GENMASK(6, 0)
70 #define AD4695_REG_AC_CTRL 0x0023
71 #define AD4695_REG_STD_SEQ_CONFIG 0x0024
72 #define AD4695_REG_GPIO_CTRL 0x0026
73 #define AD4695_REG_GP_MODE 0x0027
74 #define AD4695_REG_GP_MODE_BUSY_GP_SEL BIT(5)
75 #define AD4695_REG_GP_MODE_BUSY_GP_EN BIT(1)
76 #define AD4695_REG_TEMP_CTRL 0x0029
77 #define AD4695_REG_TEMP_CTRL_TEMP_EN BIT(0)
78 #define AD4695_REG_CONFIG_IN(n) (0x0030 | (n))
79 #define AD4695_REG_CONFIG_IN_MODE BIT(6)
80 #define AD4695_REG_CONFIG_IN_PAIR GENMASK(5, 4)
81 #define AD4695_REG_CONFIG_IN_AINHIGHZ_EN BIT(3)
82 #define AD4695_REG_CONFIG_IN_OSR_SET GENMASK(1, 0)
83 #define AD4695_REG_UPPER_IN(n) (0x0040 | (2 * (n)))
84 #define AD4695_REG_LOWER_IN(n) (0x0060 | (2 * (n)))
85 #define AD4695_REG_HYST_IN(n) (0x0080 | (2 * (n)))
86 #define AD4695_REG_OFFSET_IN(n) (0x00A0 | (2 * (n)))
87 #define AD4695_REG_GAIN_IN(n) (0x00C0 | (2 * (n)))
88 #define AD4695_REG_AS_SLOT(n) (0x0100 | (n))
89 #define AD4695_REG_AS_SLOT_INX GENMASK(3, 0)
90
91 /* Conversion mode commands */
92 #define AD4695_CMD_EXIT_CNV_MODE 0x0A
93 #define AD4695_CMD_TEMP_CHAN 0x0F
94 #define AD4695_CMD_VOLTAGE_CHAN(n) (0x10 | (n))
95
96 /* timing specs */
97 #define AD4695_T_CONVERT_NS 415
98 #define AD4695_T_WAKEUP_HW_MS 3
99 #define AD4695_T_WAKEUP_SW_MS 3
100 #define AD4695_T_REFBUF_MS 100
101 #define AD4695_T_REGCONFIG_NS 20
102 #define AD4695_T_SCK_CNV_DELAY_NS 80
103 #define AD4695_T_CNVL_NS 80
104 #define AD4695_T_CNVH_NS 10
105 #define AD4695_REG_ACCESS_SCLK_HZ (10 * MEGA)
106
107 /* Max number of voltage input channels. */
108 #define AD4695_MAX_VIN_CHANNELS 16
109
110 enum ad4695_in_pair {
111 AD4695_IN_PAIR_REFGND,
112 AD4695_IN_PAIR_COM,
113 AD4695_IN_PAIR_EVEN_ODD,
114 };
115
116 struct ad4695_chip_info {
117 const char *name;
118 int max_sample_rate;
119 u32 t_acq_ns;
120 u8 num_voltage_inputs;
121 };
122
123 struct ad4695_channel_config {
124 unsigned int channel;
125 bool highz_en;
126 bool bipolar;
127 enum ad4695_in_pair pin_pairing;
128 unsigned int common_mode_mv;
129 unsigned int oversampling_ratio;
130 };
131
132 struct ad4695_state {
133 struct spi_device *spi;
134 struct spi_offload *offload;
135 struct spi_offload_trigger *offload_trigger;
136 struct regmap *regmap;
137 struct regmap *regmap16;
138 struct gpio_desc *reset_gpio;
139 /* currently PWM CNV only supported with SPI offload use */
140 struct pwm_device *cnv_pwm;
141 /* protects against concurrent use of cnv_pwm */
142 struct mutex cnv_pwm_lock;
143 /* offload also requires separate gpio to manually control CNV */
144 struct gpio_desc *cnv_gpio;
145 /* voltages channels plus temperature and timestamp */
146 struct iio_chan_spec iio_chan[AD4695_MAX_VIN_CHANNELS + 2];
147 struct ad4695_channel_config channels_cfg[AD4695_MAX_VIN_CHANNELS];
148 const struct ad4695_chip_info *chip_info;
149 int sample_freq_range[3];
150 /* Reference voltage. */
151 unsigned int vref_mv;
152 /* Common mode input pin voltage. */
153 unsigned int com_mv;
154 /*
155 * 2 per voltage and temperature chan plus 1 xfer to trigger 1st
156 * CNV. Excluding the trigger xfer, every 2nd xfer only serves
157 * to control CS and add a delay between the last SCLK and next
158 * CNV rising edges.
159 */
160 struct spi_transfer buf_read_xfer[AD4695_MAX_VIN_CHANNELS * 2 + 3];
161 struct spi_message buf_read_msg;
162 /* Raw conversion data received. */
163 IIO_DECLARE_DMA_BUFFER_WITH_TS(u16, buf, AD4695_MAX_VIN_CHANNELS + 1);
164 u16 raw_data;
165 /* Commands to send for single conversion. */
166 u16 cnv_cmd;
167 u8 cnv_cmd2;
168 /* Buffer for storing data from regmap bus reads/writes */
169 u8 regmap_bus_data[4];
170 };
171
172 static const struct regmap_range ad4695_regmap_rd_ranges[] = {
173 regmap_reg_range(AD4695_REG_SPI_CONFIG_A, AD4695_REG_SPI_CONFIG_B),
174 regmap_reg_range(AD4695_REG_DEVICE_TYPE, AD4695_REG_DEVICE_TYPE),
175 regmap_reg_range(AD4695_REG_SCRATCH_PAD, AD4695_REG_SCRATCH_PAD),
176 regmap_reg_range(AD4695_REG_VENDOR_L, AD4695_REG_LOOP_MODE),
177 regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS),
178 regmap_reg_range(AD4695_REG_STATUS, AD4695_REG_ALERT_STATUS2),
179 regmap_reg_range(AD4695_REG_CLAMP_STATUS, AD4695_REG_CLAMP_STATUS),
180 regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_AC_CTRL),
181 regmap_reg_range(AD4695_REG_GPIO_CTRL, AD4695_REG_TEMP_CTRL),
182 regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_REG_CONFIG_IN(15)),
183 regmap_reg_range(AD4695_REG_AS_SLOT(0), AD4695_REG_AS_SLOT(127)),
184 };
185
186 static const struct regmap_access_table ad4695_regmap_rd_table = {
187 .yes_ranges = ad4695_regmap_rd_ranges,
188 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap_rd_ranges),
189 };
190
191 static const struct regmap_range ad4695_regmap_wr_ranges[] = {
192 regmap_reg_range(AD4695_REG_SPI_CONFIG_A, AD4695_REG_SPI_CONFIG_B),
193 regmap_reg_range(AD4695_REG_SCRATCH_PAD, AD4695_REG_SCRATCH_PAD),
194 regmap_reg_range(AD4695_REG_LOOP_MODE, AD4695_REG_LOOP_MODE),
195 regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS),
196 regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_AC_CTRL),
197 regmap_reg_range(AD4695_REG_GPIO_CTRL, AD4695_REG_TEMP_CTRL),
198 regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_REG_CONFIG_IN(15)),
199 regmap_reg_range(AD4695_REG_AS_SLOT(0), AD4695_REG_AS_SLOT(127)),
200 };
201
202 static const struct regmap_access_table ad4695_regmap_wr_table = {
203 .yes_ranges = ad4695_regmap_wr_ranges,
204 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap_wr_ranges),
205 };
206
207 static const struct regmap_config ad4695_regmap_config = {
208 .name = "ad4695-8",
209 .reg_bits = 16,
210 .val_bits = 8,
211 .max_register = AD4695_REG_AS_SLOT(127),
212 .rd_table = &ad4695_regmap_rd_table,
213 .wr_table = &ad4695_regmap_wr_table,
214 };
215
216 static const struct regmap_range ad4695_regmap16_rd_ranges[] = {
217 regmap_reg_range(AD4695_REG_STD_SEQ_CONFIG, AD4695_REG_STD_SEQ_CONFIG),
218 regmap_reg_range(AD4695_REG_UPPER_IN(0), AD4695_REG_GAIN_IN(15)),
219 };
220
221 static const struct regmap_access_table ad4695_regmap16_rd_table = {
222 .yes_ranges = ad4695_regmap16_rd_ranges,
223 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap16_rd_ranges),
224 };
225
226 static const struct regmap_range ad4695_regmap16_wr_ranges[] = {
227 regmap_reg_range(AD4695_REG_STD_SEQ_CONFIG, AD4695_REG_STD_SEQ_CONFIG),
228 regmap_reg_range(AD4695_REG_UPPER_IN(0), AD4695_REG_GAIN_IN(15)),
229 };
230
231 static const struct regmap_access_table ad4695_regmap16_wr_table = {
232 .yes_ranges = ad4695_regmap16_wr_ranges,
233 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap16_wr_ranges),
234 };
235
236 static const struct regmap_config ad4695_regmap16_config = {
237 .name = "ad4695-16",
238 .reg_bits = 16,
239 .reg_stride = 2,
240 .val_bits = 16,
241 .val_format_endian = REGMAP_ENDIAN_LITTLE,
242 .max_register = AD4695_REG_GAIN_IN(15),
243 .rd_table = &ad4695_regmap16_rd_table,
244 .wr_table = &ad4695_regmap16_wr_table,
245 };
246
ad4695_regmap_bus_reg_write(void * context,const void * data,size_t count)247 static int ad4695_regmap_bus_reg_write(void *context, const void *data,
248 size_t count)
249 {
250 struct ad4695_state *st = context;
251 struct spi_transfer xfer = {
252 .speed_hz = AD4695_REG_ACCESS_SCLK_HZ,
253 .len = count,
254 .tx_buf = st->regmap_bus_data,
255 };
256
257 if (count > ARRAY_SIZE(st->regmap_bus_data))
258 return -EINVAL;
259
260 memcpy(st->regmap_bus_data, data, count);
261
262 return spi_sync_transfer(st->spi, &xfer, 1);
263 }
264
ad4695_regmap_bus_reg_read(void * context,const void * reg,size_t reg_size,void * val,size_t val_size)265 static int ad4695_regmap_bus_reg_read(void *context, const void *reg,
266 size_t reg_size, void *val,
267 size_t val_size)
268 {
269 struct ad4695_state *st = context;
270 struct spi_transfer xfers[] = {
271 {
272 .speed_hz = AD4695_REG_ACCESS_SCLK_HZ,
273 .len = reg_size,
274 .tx_buf = &st->regmap_bus_data[0],
275 }, {
276 .speed_hz = AD4695_REG_ACCESS_SCLK_HZ,
277 .len = val_size,
278 .rx_buf = &st->regmap_bus_data[2],
279 },
280 };
281 int ret;
282
283 if (reg_size > 2)
284 return -EINVAL;
285
286 if (val_size > 2)
287 return -EINVAL;
288
289 memcpy(&st->regmap_bus_data[0], reg, reg_size);
290
291 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
292 if (ret)
293 return ret;
294
295 memcpy(val, &st->regmap_bus_data[2], val_size);
296
297 return 0;
298 }
299
300 static const struct regmap_bus ad4695_regmap_bus = {
301 .write = ad4695_regmap_bus_reg_write,
302 .read = ad4695_regmap_bus_reg_read,
303 .read_flag_mask = 0x80,
304 .reg_format_endian_default = REGMAP_ENDIAN_BIG,
305 .val_format_endian_default = REGMAP_ENDIAN_BIG,
306 };
307
308 enum {
309 AD4695_SCAN_TYPE_OSR_1,
310 AD4695_SCAN_TYPE_OSR_4,
311 AD4695_SCAN_TYPE_OSR_16,
312 AD4695_SCAN_TYPE_OSR_64,
313 };
314
315 static const struct iio_scan_type ad4695_scan_type_offload_u[] = {
316 [AD4695_SCAN_TYPE_OSR_1] = {
317 .sign = 'u',
318 .realbits = 16,
319 .shift = 3,
320 .storagebits = 32,
321 },
322 [AD4695_SCAN_TYPE_OSR_4] = {
323 .sign = 'u',
324 .realbits = 17,
325 .shift = 2,
326 .storagebits = 32,
327 },
328 [AD4695_SCAN_TYPE_OSR_16] = {
329 .sign = 'u',
330 .realbits = 18,
331 .shift = 1,
332 .storagebits = 32,
333 },
334 [AD4695_SCAN_TYPE_OSR_64] = {
335 .sign = 'u',
336 .realbits = 19,
337 .storagebits = 32,
338 },
339 };
340
341 static const struct iio_scan_type ad4695_scan_type_offload_s[] = {
342 [AD4695_SCAN_TYPE_OSR_1] = {
343 .sign = 's',
344 .realbits = 16,
345 .shift = 3,
346 .storagebits = 32,
347 },
348 [AD4695_SCAN_TYPE_OSR_4] = {
349 .sign = 's',
350 .realbits = 17,
351 .shift = 2,
352 .storagebits = 32,
353 },
354 [AD4695_SCAN_TYPE_OSR_16] = {
355 .sign = 's',
356 .realbits = 18,
357 .shift = 1,
358 .storagebits = 32,
359 },
360 [AD4695_SCAN_TYPE_OSR_64] = {
361 .sign = 's',
362 .realbits = 19,
363 .storagebits = 32,
364 },
365 };
366
367 static const struct iio_chan_spec ad4695_channel_template = {
368 .type = IIO_VOLTAGE,
369 .indexed = 1,
370 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
371 BIT(IIO_CHAN_INFO_SCALE) |
372 BIT(IIO_CHAN_INFO_OFFSET) |
373 BIT(IIO_CHAN_INFO_CALIBSCALE) |
374 BIT(IIO_CHAN_INFO_CALIBBIAS),
375 .info_mask_separate_available = BIT(IIO_CHAN_INFO_CALIBSCALE) |
376 BIT(IIO_CHAN_INFO_CALIBBIAS),
377 .scan_type = {
378 .sign = 'u',
379 .realbits = 16,
380 .storagebits = 16,
381 },
382 };
383
384 static const struct iio_chan_spec ad4695_temp_channel_template = {
385 .address = AD4695_CMD_TEMP_CHAN,
386 .type = IIO_TEMP,
387 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
388 BIT(IIO_CHAN_INFO_SCALE) |
389 BIT(IIO_CHAN_INFO_OFFSET),
390 .scan_type = {
391 .sign = 's',
392 .realbits = 16,
393 .storagebits = 16,
394 },
395 };
396
397 static const struct iio_chan_spec ad4695_soft_timestamp_channel_template =
398 IIO_CHAN_SOFT_TIMESTAMP(0);
399
400 static const char * const ad4695_power_supplies[] = {
401 "avdd", "vio"
402 };
403
404 static const int ad4695_oversampling_ratios[] = {
405 1, 4, 16, 64,
406 };
407
408 static const struct ad4695_chip_info ad4695_chip_info = {
409 .name = "ad4695",
410 .max_sample_rate = 500 * KILO,
411 .t_acq_ns = 1715,
412 .num_voltage_inputs = 16,
413 };
414
415 static const struct ad4695_chip_info ad4696_chip_info = {
416 .name = "ad4696",
417 .max_sample_rate = 1 * MEGA,
418 .t_acq_ns = 715,
419 .num_voltage_inputs = 16,
420 };
421
422 static const struct ad4695_chip_info ad4697_chip_info = {
423 .name = "ad4697",
424 .max_sample_rate = 500 * KILO,
425 .t_acq_ns = 1715,
426 .num_voltage_inputs = 8,
427 };
428
429 static const struct ad4695_chip_info ad4698_chip_info = {
430 .name = "ad4698",
431 .max_sample_rate = 1 * MEGA,
432 .t_acq_ns = 715,
433 .num_voltage_inputs = 8,
434 };
435
ad4695_cnv_manual_trigger(struct ad4695_state * st)436 static void ad4695_cnv_manual_trigger(struct ad4695_state *st)
437 {
438 gpiod_set_value_cansleep(st->cnv_gpio, 1);
439 ndelay(10);
440 gpiod_set_value_cansleep(st->cnv_gpio, 0);
441 }
442
443 /**
444 * ad4695_set_single_cycle_mode - Set the device in single cycle mode
445 * @st: The AD4695 state
446 * @channel: The first channel to read
447 *
448 * As per the datasheet, to enable single cycle mode, we need to set
449 * STD_SEQ_EN=0, NUM_SLOTS_AS=0 and CYC_CTRL=1 (Table 15). Setting SPI_MODE=1
450 * triggers the first conversion using the channel in AS_SLOT0.
451 *
452 * Context: can sleep, must be called with iio_device_claim_direct held
453 * Return: 0 on success, a negative error code on failure
454 */
ad4695_set_single_cycle_mode(struct ad4695_state * st,unsigned int channel)455 static int ad4695_set_single_cycle_mode(struct ad4695_state *st,
456 unsigned int channel)
457 {
458 int ret;
459
460 ret = regmap_clear_bits(st->regmap, AD4695_REG_SEQ_CTRL,
461 AD4695_REG_SEQ_CTRL_STD_SEQ_EN |
462 AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS);
463 if (ret)
464 return ret;
465
466 ret = regmap_write(st->regmap, AD4695_REG_AS_SLOT(0),
467 FIELD_PREP(AD4695_REG_AS_SLOT_INX, channel));
468 if (ret)
469 return ret;
470
471 return regmap_set_bits(st->regmap, AD4695_REG_SETUP,
472 AD4695_REG_SETUP_SPI_MODE |
473 AD4695_REG_SETUP_SPI_CYC_CTRL);
474 }
475
476 /**
477 * ad4695_enter_advanced_sequencer_mode - Put the ADC in advanced sequencer mode
478 * @st: The driver state
479 * @n: The number of slots to use - must be >= 2, <= 128
480 *
481 * As per the datasheet, to enable advanced sequencer, we need to set
482 * STD_SEQ_EN=0, NUM_SLOTS_AS=n-1 and CYC_CTRL=0 (Table 15). Setting SPI_MODE=1
483 * triggers the first conversion using the channel in AS_SLOT0.
484 *
485 * Return: 0 on success, a negative error code on failure
486 */
ad4695_enter_advanced_sequencer_mode(struct ad4695_state * st,u32 n)487 static int ad4695_enter_advanced_sequencer_mode(struct ad4695_state *st, u32 n)
488 {
489 int ret;
490
491 ret = regmap_update_bits(st->regmap, AD4695_REG_SEQ_CTRL,
492 AD4695_REG_SEQ_CTRL_STD_SEQ_EN |
493 AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS,
494 FIELD_PREP(AD4695_REG_SEQ_CTRL_STD_SEQ_EN, 0) |
495 FIELD_PREP(AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS, n - 1));
496 if (ret)
497 return ret;
498
499 return regmap_update_bits(st->regmap, AD4695_REG_SETUP,
500 AD4695_REG_SETUP_SPI_MODE | AD4695_REG_SETUP_SPI_CYC_CTRL,
501 FIELD_PREP(AD4695_REG_SETUP_SPI_MODE, 1) |
502 FIELD_PREP(AD4695_REG_SETUP_SPI_CYC_CTRL, 0));
503 }
504
505 /**
506 * ad4695_exit_conversion_mode - Exit conversion mode
507 * @st: The AD4695 state
508 *
509 * Sends SPI command to exit conversion mode.
510 *
511 * Return: 0 on success, a negative error code on failure
512 */
ad4695_exit_conversion_mode(struct ad4695_state * st)513 static int ad4695_exit_conversion_mode(struct ad4695_state *st)
514 {
515 /*
516 * An extra transfer is needed to trigger a conversion here so
517 * that we can be 100% sure the command will be processed by the
518 * ADC, rather than relying on it to be in the correct state
519 * when this function is called (this chip has a quirk where the
520 * command only works when reading a conversion, and if the
521 * previous conversion was already read then it won't work). The
522 * actual conversion command is then run at the slower
523 * AD4695_REG_ACCESS_SCLK_HZ speed to guarantee this works.
524 */
525 struct spi_transfer xfers[] = {
526 {
527 .delay.value = AD4695_T_CNVL_NS,
528 .delay.unit = SPI_DELAY_UNIT_NSECS,
529 .cs_change = 1,
530 .cs_change_delay.value = AD4695_T_CNVH_NS,
531 .cs_change_delay.unit = SPI_DELAY_UNIT_NSECS,
532 },
533 {
534 .speed_hz = AD4695_REG_ACCESS_SCLK_HZ,
535 .tx_buf = &st->cnv_cmd2,
536 .len = 1,
537 .delay.value = AD4695_T_REGCONFIG_NS,
538 .delay.unit = SPI_DELAY_UNIT_NSECS,
539 },
540 };
541
542 /*
543 * Technically, could do a 5-bit transfer, but shifting to start of
544 * 8 bits instead for better SPI controller support.
545 */
546 st->cnv_cmd2 = AD4695_CMD_EXIT_CNV_MODE << 3;
547
548 if (st->cnv_gpio) {
549 ad4695_cnv_manual_trigger(st);
550
551 /*
552 * In this case, CNV is not connected to CS, so we don't need
553 * the extra CS toggle to trigger the conversion and toggling
554 * CS would have no effect.
555 */
556 return spi_sync_transfer(st->spi, &xfers[1], 1);
557 }
558
559 return spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
560 }
561
ad4695_set_ref_voltage(struct ad4695_state * st,int vref_mv)562 static int ad4695_set_ref_voltage(struct ad4695_state *st, int vref_mv)
563 {
564 u8 val;
565
566 if (vref_mv >= 2400 && vref_mv <= 2750)
567 val = 0;
568 else if (vref_mv > 2750 && vref_mv <= 3250)
569 val = 1;
570 else if (vref_mv > 3250 && vref_mv <= 3750)
571 val = 2;
572 else if (vref_mv > 3750 && vref_mv <= 4500)
573 val = 3;
574 else if (vref_mv > 4500 && vref_mv <= 5100)
575 val = 4;
576 else
577 return -EINVAL;
578
579 return regmap_update_bits(st->regmap, AD4695_REG_REF_CTRL,
580 AD4695_REG_REF_CTRL_VREF_SET,
581 FIELD_PREP(AD4695_REG_REF_CTRL_VREF_SET, val));
582 }
583
584 /**
585 * ad4695_osr_to_regval - convert ratio to OSR register value
586 * @ratio: ratio to check
587 *
588 * Check if ratio is present in the list of available ratios and return
589 * the corresponding value that needs to be written to the register to
590 * select that ratio.
591 *
592 * Returns: register value (0 to 3) or -EINVAL if there is not an exact
593 * match
594 */
ad4695_osr_to_regval(int ratio)595 static int ad4695_osr_to_regval(int ratio)
596 {
597 int i;
598
599 for (i = 0; i < ARRAY_SIZE(ad4695_oversampling_ratios); i++) {
600 if (ratio == ad4695_oversampling_ratios[i])
601 return i;
602 }
603
604 return -EINVAL;
605 }
606
ad4695_write_chn_cfg(struct ad4695_state * st,struct ad4695_channel_config * cfg)607 static int ad4695_write_chn_cfg(struct ad4695_state *st,
608 struct ad4695_channel_config *cfg)
609 {
610 u32 mask, val;
611
612 mask = AD4695_REG_CONFIG_IN_MODE;
613 val = FIELD_PREP(AD4695_REG_CONFIG_IN_MODE, cfg->bipolar ? 1 : 0);
614
615 mask |= AD4695_REG_CONFIG_IN_PAIR;
616 val |= FIELD_PREP(AD4695_REG_CONFIG_IN_PAIR, cfg->pin_pairing);
617
618 mask |= AD4695_REG_CONFIG_IN_AINHIGHZ_EN;
619 val |= FIELD_PREP(AD4695_REG_CONFIG_IN_AINHIGHZ_EN,
620 cfg->highz_en ? 1 : 0);
621
622 return regmap_update_bits(st->regmap,
623 AD4695_REG_CONFIG_IN(cfg->channel),
624 mask, val);
625 }
626
ad4695_buffer_preenable(struct iio_dev * indio_dev)627 static int ad4695_buffer_preenable(struct iio_dev *indio_dev)
628 {
629 struct ad4695_state *st = iio_priv(indio_dev);
630 struct spi_transfer *xfer;
631 u8 temp_chan_bit = st->chip_info->num_voltage_inputs;
632 u32 bit, num_xfer, num_slots;
633 u32 temp_en = 0;
634 int ret, rx_buf_offset = 0;
635
636 /*
637 * We are using the advanced sequencer since it is the only way to read
638 * multiple channels that allows individual configuration of each
639 * voltage input channel. Slot 0 in the advanced sequencer is used to
640 * account for the gap between trigger polls - we don't read data from
641 * this slot. Each enabled voltage channel is assigned a slot starting
642 * with slot 1.
643 */
644 num_slots = 1;
645
646 memset(st->buf_read_xfer, 0, sizeof(st->buf_read_xfer));
647
648 /* First xfer is only to trigger conversion of slot 1, so no rx. */
649 xfer = &st->buf_read_xfer[0];
650 xfer->cs_change = 1;
651 xfer->delay.value = st->chip_info->t_acq_ns;
652 xfer->delay.unit = SPI_DELAY_UNIT_NSECS;
653 xfer->cs_change_delay.value = AD4695_T_CONVERT_NS;
654 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
655 num_xfer = 1;
656
657 iio_for_each_active_channel(indio_dev, bit) {
658 xfer = &st->buf_read_xfer[num_xfer];
659 xfer->bits_per_word = 16;
660 xfer->rx_buf = &st->buf[rx_buf_offset++];
661 xfer->len = 2;
662
663 if (bit == temp_chan_bit) {
664 temp_en = 1;
665 } else {
666 ret = regmap_write(st->regmap,
667 AD4695_REG_AS_SLOT(num_slots),
668 FIELD_PREP(AD4695_REG_AS_SLOT_INX, bit));
669 if (ret)
670 return ret;
671
672 num_slots++;
673 }
674
675 num_xfer++;
676
677 /*
678 * We need to add a blank xfer in data reads, to meet the timing
679 * requirement of a minimum delay between the last SCLK rising
680 * edge and the CS deassert.
681 */
682 xfer = &st->buf_read_xfer[num_xfer];
683 xfer->delay.value = AD4695_T_SCK_CNV_DELAY_NS;
684 xfer->delay.unit = SPI_DELAY_UNIT_NSECS;
685 xfer->cs_change = 1;
686 xfer->cs_change_delay.value = AD4695_T_CONVERT_NS;
687 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
688
689 num_xfer++;
690 }
691
692 /*
693 * The advanced sequencer requires that at least 2 slots are enabled.
694 * Since slot 0 is always used for other purposes, we need only 1
695 * enabled voltage channel to meet this requirement. If the temperature
696 * channel is the only enabled channel, we need to add one more slot in
697 * the sequence but not read from it. This is because the temperature
698 * sensor is sampled at the end of the channel sequence in advanced
699 * sequencer mode (see datasheet page 38).
700 *
701 * From the iio_for_each_active_channel() block above, we now have an
702 * xfer with data followed by a blank xfer to allow us to meet the
703 * timing spec, so move both of those up before adding an extra to
704 * handle the temperature-only case.
705 */
706 if (num_slots < 2) {
707 /* Move last two xfers */
708 st->buf_read_xfer[num_xfer] = st->buf_read_xfer[num_xfer - 1];
709 st->buf_read_xfer[num_xfer - 1] = st->buf_read_xfer[num_xfer - 2];
710 num_xfer++;
711
712 /* Modify inserted xfer for extra slot. */
713 xfer = &st->buf_read_xfer[num_xfer - 3];
714 memset(xfer, 0, sizeof(*xfer));
715 xfer->cs_change = 1;
716 xfer->delay.value = st->chip_info->t_acq_ns;
717 xfer->delay.unit = SPI_DELAY_UNIT_NSECS;
718 xfer->cs_change_delay.value = AD4695_T_CONVERT_NS;
719 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
720 xfer++;
721
722 /* and add the extra slot in the sequencer */
723 ret = regmap_write(st->regmap,
724 AD4695_REG_AS_SLOT(num_slots),
725 FIELD_PREP(AD4695_REG_AS_SLOT_INX, 0));
726 if (ret)
727 return ret;
728
729 num_slots++;
730
731 /*
732 * We still want to point at the last xfer when finished, so
733 * update the pointer.
734 */
735 xfer = &st->buf_read_xfer[num_xfer - 1];
736 }
737
738 /*
739 * Don't keep CS asserted after last xfer. Also triggers conversion of
740 * slot 0.
741 */
742 xfer->cs_change = 0;
743
744 /*
745 * Temperature channel isn't included in the sequence, but rather
746 * controlled by setting a bit in the TEMP_CTRL register.
747 */
748
749 ret = regmap_update_bits(st->regmap, AD4695_REG_TEMP_CTRL,
750 AD4695_REG_TEMP_CTRL_TEMP_EN,
751 FIELD_PREP(AD4695_REG_TEMP_CTRL_TEMP_EN, temp_en));
752 if (ret)
753 return ret;
754
755 spi_message_init_with_transfers(&st->buf_read_msg, st->buf_read_xfer,
756 num_xfer);
757
758 ret = spi_optimize_message(st->spi, &st->buf_read_msg);
759 if (ret)
760 return ret;
761
762 /* This triggers conversion of slot 0. */
763 ret = ad4695_enter_advanced_sequencer_mode(st, num_slots);
764 if (ret)
765 spi_unoptimize_message(&st->buf_read_msg);
766
767 return ret;
768 }
769
ad4695_buffer_postdisable(struct iio_dev * indio_dev)770 static int ad4695_buffer_postdisable(struct iio_dev *indio_dev)
771 {
772 struct ad4695_state *st = iio_priv(indio_dev);
773 int ret;
774
775 ret = ad4695_exit_conversion_mode(st);
776 if (ret)
777 return ret;
778
779 spi_unoptimize_message(&st->buf_read_msg);
780
781 return 0;
782 }
783
784 static const struct iio_buffer_setup_ops ad4695_buffer_setup_ops = {
785 .preenable = ad4695_buffer_preenable,
786 .postdisable = ad4695_buffer_postdisable,
787 };
788
ad4695_trigger_handler(int irq,void * p)789 static irqreturn_t ad4695_trigger_handler(int irq, void *p)
790 {
791 struct iio_poll_func *pf = p;
792 struct iio_dev *indio_dev = pf->indio_dev;
793 struct ad4695_state *st = iio_priv(indio_dev);
794 int ret;
795
796 ret = spi_sync(st->spi, &st->buf_read_msg);
797 if (ret)
798 goto out;
799
800 iio_push_to_buffers_with_ts(indio_dev, st->buf, sizeof(st->buf),
801 pf->timestamp);
802
803 out:
804 iio_trigger_notify_done(indio_dev->trig);
805
806 return IRQ_HANDLED;
807 }
808
ad4695_offload_buffer_postenable(struct iio_dev * indio_dev)809 static int ad4695_offload_buffer_postenable(struct iio_dev *indio_dev)
810 {
811 struct ad4695_state *st = iio_priv(indio_dev);
812 struct spi_offload_trigger_config config = {
813 .type = SPI_OFFLOAD_TRIGGER_DATA_READY,
814 };
815 struct spi_transfer *xfer = &st->buf_read_xfer[0];
816 struct pwm_state state;
817 u8 temp_chan_bit = st->chip_info->num_voltage_inputs;
818 u8 num_slots = 0;
819 u8 temp_en = 0;
820 unsigned int bit;
821 int ret;
822
823 iio_for_each_active_channel(indio_dev, bit) {
824 if (bit == temp_chan_bit) {
825 temp_en = 1;
826 continue;
827 }
828
829 ret = regmap_write(st->regmap, AD4695_REG_AS_SLOT(num_slots),
830 FIELD_PREP(AD4695_REG_AS_SLOT_INX, bit));
831 if (ret)
832 return ret;
833
834 num_slots++;
835 }
836
837 /*
838 * For non-offload, we could discard data to work around this
839 * restriction, but with offload, that is not possible.
840 */
841 if (num_slots < 2) {
842 dev_err(&st->spi->dev,
843 "At least two voltage channels must be enabled.\n");
844 return -EINVAL;
845 }
846
847 ret = regmap_update_bits(st->regmap, AD4695_REG_TEMP_CTRL,
848 AD4695_REG_TEMP_CTRL_TEMP_EN,
849 FIELD_PREP(AD4695_REG_TEMP_CTRL_TEMP_EN,
850 temp_en));
851 if (ret)
852 return ret;
853
854 /* Each BUSY event means just one sample for one channel is ready. */
855 memset(xfer, 0, sizeof(*xfer));
856 xfer->offload_flags = SPI_OFFLOAD_XFER_RX_STREAM;
857 /* Using 19 bits per word to allow for possible oversampling */
858 xfer->bits_per_word = 19;
859 xfer->len = 4;
860
861 spi_message_init_with_transfers(&st->buf_read_msg, xfer, 1);
862 st->buf_read_msg.offload = st->offload;
863
864 ret = spi_optimize_message(st->spi, &st->buf_read_msg);
865 if (ret)
866 return ret;
867
868 /*
869 * NB: technically, this is part the SPI offload trigger enable, but it
870 * doesn't work to call it from the offload trigger enable callback
871 * because it requires accessing the SPI bus. Calling it from the
872 * trigger enable callback could cause a deadlock.
873 */
874 ret = regmap_set_bits(st->regmap, AD4695_REG_GP_MODE,
875 AD4695_REG_GP_MODE_BUSY_GP_EN);
876 if (ret)
877 goto err_unoptimize_message;
878
879 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger,
880 &config);
881 if (ret)
882 goto err_disable_busy_output;
883
884 ret = ad4695_enter_advanced_sequencer_mode(st, num_slots);
885 if (ret)
886 goto err_offload_trigger_disable;
887
888 mutex_lock(&st->cnv_pwm_lock);
889 pwm_get_state(st->cnv_pwm, &state);
890 /*
891 * PWM subsystem generally rounds down, so requesting 2x minimum high
892 * time ensures that we meet the minimum high time in any case.
893 */
894 state.duty_cycle = AD4695_T_CNVH_NS * 2;
895 ret = pwm_apply_might_sleep(st->cnv_pwm, &state);
896 mutex_unlock(&st->cnv_pwm_lock);
897 if (ret)
898 goto err_offload_exit_conversion_mode;
899
900 return 0;
901
902 err_offload_exit_conversion_mode:
903 /*
904 * We have to unwind in a different order to avoid triggering offload.
905 * ad4695_exit_conversion_mode() triggers a conversion, so it has to be
906 * done after spi_offload_trigger_disable().
907 */
908 spi_offload_trigger_disable(st->offload, st->offload_trigger);
909 ad4695_exit_conversion_mode(st);
910 goto err_disable_busy_output;
911
912 err_offload_trigger_disable:
913 spi_offload_trigger_disable(st->offload, st->offload_trigger);
914
915 err_disable_busy_output:
916 regmap_clear_bits(st->regmap, AD4695_REG_GP_MODE,
917 AD4695_REG_GP_MODE_BUSY_GP_EN);
918
919 err_unoptimize_message:
920 spi_unoptimize_message(&st->buf_read_msg);
921
922 return ret;
923 }
924
ad4695_offload_buffer_predisable(struct iio_dev * indio_dev)925 static int ad4695_offload_buffer_predisable(struct iio_dev *indio_dev)
926 {
927 struct ad4695_state *st = iio_priv(indio_dev);
928 struct pwm_state state;
929 int ret;
930
931 scoped_guard(mutex, &st->cnv_pwm_lock) {
932 pwm_get_state(st->cnv_pwm, &state);
933 state.duty_cycle = 0;
934 ret = pwm_apply_might_sleep(st->cnv_pwm, &state);
935 if (ret)
936 return ret;
937 }
938
939 spi_offload_trigger_disable(st->offload, st->offload_trigger);
940
941 /*
942 * ad4695_exit_conversion_mode() triggers a conversion, so it has to be
943 * done after spi_offload_trigger_disable().
944 */
945 ret = ad4695_exit_conversion_mode(st);
946 if (ret)
947 return ret;
948
949 ret = regmap_clear_bits(st->regmap, AD4695_REG_GP_MODE,
950 AD4695_REG_GP_MODE_BUSY_GP_EN);
951 if (ret)
952 return ret;
953
954 spi_unoptimize_message(&st->buf_read_msg);
955
956 return 0;
957 }
958
959 static const struct iio_buffer_setup_ops ad4695_offload_buffer_setup_ops = {
960 .postenable = ad4695_offload_buffer_postenable,
961 .predisable = ad4695_offload_buffer_predisable,
962 };
963
964 /**
965 * ad4695_read_one_sample - Read a single sample using single-cycle mode
966 * @st: The AD4695 state
967 * @address: The address of the channel to read
968 *
969 * Upon successful return, the sample will be stored in `st->raw_data`.
970 *
971 * Context: can sleep, must be called with iio_device_claim_direct held
972 * Return: 0 on success, a negative error code on failure
973 */
ad4695_read_one_sample(struct ad4695_state * st,unsigned int address)974 static int ad4695_read_one_sample(struct ad4695_state *st, unsigned int address)
975 {
976 struct spi_transfer xfers[2] = {
977 {
978 .speed_hz = AD4695_REG_ACCESS_SCLK_HZ,
979 .bits_per_word = 16,
980 .tx_buf = &st->cnv_cmd,
981 .len = 2,
982 },
983 {
984 /* Required delay between last SCLK and CNV/CS */
985 .delay.value = AD4695_T_SCK_CNV_DELAY_NS,
986 .delay.unit = SPI_DELAY_UNIT_NSECS,
987 }
988 };
989 int ret;
990
991 ret = ad4695_set_single_cycle_mode(st, address);
992 if (ret)
993 return ret;
994
995 /*
996 * If CNV is connected to CS, the previous function will have triggered
997 * the conversion, otherwise, we do it manually.
998 */
999 if (st->cnv_gpio)
1000 ad4695_cnv_manual_trigger(st);
1001
1002 /*
1003 * Setting the first channel to the temperature channel isn't supported
1004 * in single-cycle mode, so we have to do an extra conversion to read
1005 * the temperature.
1006 */
1007 if (address == AD4695_CMD_TEMP_CHAN) {
1008 st->cnv_cmd = AD4695_CMD_TEMP_CHAN << 11;
1009
1010 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
1011 if (ret)
1012 return ret;
1013
1014 /*
1015 * If CNV is connected to CS, the previous function will have
1016 * triggered the conversion, otherwise, we do it manually.
1017 */
1018 if (st->cnv_gpio)
1019 ad4695_cnv_manual_trigger(st);
1020 }
1021
1022 /* Then read the result and exit conversion mode. */
1023 st->cnv_cmd = AD4695_CMD_EXIT_CNV_MODE << 11;
1024 xfers[0].rx_buf = &st->raw_data;
1025
1026 return spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
1027 }
1028
__ad4695_read_info_raw(struct ad4695_state * st,struct iio_chan_spec const * chan,int * val)1029 static int __ad4695_read_info_raw(struct ad4695_state *st,
1030 struct iio_chan_spec const *chan,
1031 int *val)
1032 {
1033 u8 realbits = chan->scan_type.realbits;
1034 int ret;
1035
1036 ret = ad4695_read_one_sample(st, chan->address);
1037 if (ret)
1038 return ret;
1039
1040 if (chan->scan_type.sign == 's')
1041 *val = sign_extend32(st->raw_data, realbits - 1);
1042 else
1043 *val = st->raw_data;
1044
1045 return IIO_VAL_INT;
1046 }
1047
ad4695_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)1048 static int ad4695_read_raw(struct iio_dev *indio_dev,
1049 struct iio_chan_spec const *chan,
1050 int *val, int *val2, long mask)
1051 {
1052 struct ad4695_state *st = iio_priv(indio_dev);
1053 const struct iio_scan_type *scan_type;
1054 struct ad4695_channel_config *cfg;
1055 unsigned int reg_val;
1056 int ret, tmp;
1057 u8 realbits;
1058
1059 if (chan->type == IIO_VOLTAGE)
1060 cfg = &st->channels_cfg[chan->scan_index];
1061
1062 scan_type = iio_get_current_scan_type(indio_dev, chan);
1063 if (IS_ERR(scan_type))
1064 return PTR_ERR(scan_type);
1065
1066 realbits = scan_type->realbits;
1067
1068 switch (mask) {
1069 case IIO_CHAN_INFO_RAW:
1070 if (!iio_device_claim_direct(indio_dev))
1071 return -EBUSY;
1072
1073 ret = __ad4695_read_info_raw(st, chan, val);
1074 iio_device_release_direct(indio_dev);
1075 return ret;
1076 case IIO_CHAN_INFO_SCALE:
1077 switch (chan->type) {
1078 case IIO_VOLTAGE:
1079 *val = st->vref_mv;
1080 *val2 = realbits;
1081 return IIO_VAL_FRACTIONAL_LOG2;
1082 case IIO_TEMP:
1083 /* T_scale (°C) = raw * V_REF (mV) / (-1.8 mV/°C * 2^16) */
1084 *val = st->vref_mv * -556;
1085 *val2 = 16;
1086 return IIO_VAL_FRACTIONAL_LOG2;
1087 default:
1088 return -EINVAL;
1089 }
1090 case IIO_CHAN_INFO_OFFSET:
1091 switch (chan->type) {
1092 case IIO_VOLTAGE:
1093 if (cfg->pin_pairing == AD4695_IN_PAIR_COM)
1094 *val = st->com_mv * (1 << realbits) / st->vref_mv;
1095 else if (cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD)
1096 *val = cfg->common_mode_mv * (1 << realbits) / st->vref_mv;
1097 else
1098 *val = 0;
1099
1100 return IIO_VAL_INT;
1101 case IIO_TEMP:
1102 /* T_offset (°C) = -725 mV / (-1.8 mV/°C) */
1103 /* T_offset (raw) = T_offset (°C) * (-1.8 mV/°C) * 2^16 / V_REF (mV) */
1104 *val = -47513600;
1105 *val2 = st->vref_mv;
1106 return IIO_VAL_FRACTIONAL;
1107 default:
1108 return -EINVAL;
1109 }
1110 case IIO_CHAN_INFO_CALIBSCALE:
1111 switch (chan->type) {
1112 case IIO_VOLTAGE:
1113 if (!iio_device_claim_direct(indio_dev))
1114 return -EBUSY;
1115 ret = regmap_read(st->regmap16,
1116 AD4695_REG_GAIN_IN(chan->scan_index),
1117 ®_val);
1118 iio_device_release_direct(indio_dev);
1119 if (ret)
1120 return ret;
1121 *val = reg_val;
1122 *val2 = 15;
1123
1124 return IIO_VAL_FRACTIONAL_LOG2;
1125 default:
1126 return -EINVAL;
1127 }
1128 case IIO_CHAN_INFO_CALIBBIAS:
1129 switch (chan->type)
1130 case IIO_VOLTAGE: {
1131 if (!iio_device_claim_direct(indio_dev))
1132 return -EBUSY;
1133 ret = regmap_read(st->regmap16,
1134 AD4695_REG_OFFSET_IN(chan->scan_index),
1135 ®_val);
1136 iio_device_release_direct(indio_dev);
1137 if (ret)
1138 return ret;
1139
1140 tmp = sign_extend32(reg_val, 15);
1141
1142 switch (cfg->oversampling_ratio) {
1143 case 1:
1144 *val = tmp / 4;
1145 *val2 = abs(tmp) % 4 * MICRO / 4;
1146 break;
1147 case 4:
1148 *val = tmp / 2;
1149 *val2 = abs(tmp) % 2 * MICRO / 2;
1150 break;
1151 case 16:
1152 *val = tmp;
1153 *val2 = 0;
1154 break;
1155 case 64:
1156 *val = tmp * 2;
1157 *val2 = 0;
1158 break;
1159 default:
1160 return -EINVAL;
1161 }
1162
1163 if (tmp < 0 && *val2) {
1164 *val *= -1;
1165 *val2 *= -1;
1166 }
1167
1168 return IIO_VAL_INT_PLUS_MICRO;
1169 default:
1170 return -EINVAL;
1171 }
1172 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1173 switch (chan->type) {
1174 case IIO_VOLTAGE:
1175 *val = cfg->oversampling_ratio;
1176 return IIO_VAL_INT;
1177 default:
1178 return -EINVAL;
1179 }
1180 case IIO_CHAN_INFO_SAMP_FREQ: {
1181 struct pwm_state state;
1182 unsigned int osr = 1;
1183
1184 if (chan->type == IIO_VOLTAGE)
1185 osr = cfg->oversampling_ratio;
1186
1187 ret = pwm_get_state_hw(st->cnv_pwm, &state);
1188 if (ret)
1189 return ret;
1190
1191 /*
1192 * The effective sampling frequency for a channel is the input
1193 * frequency divided by the channel's OSR value.
1194 */
1195 *val = DIV_ROUND_UP_ULL(NSEC_PER_SEC, state.period * osr);
1196
1197 return IIO_VAL_INT;
1198 }
1199 default:
1200 return -EINVAL;
1201 }
1202 }
1203
ad4695_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)1204 static int ad4695_write_raw_get_fmt(struct iio_dev *indio_dev,
1205 struct iio_chan_spec const *chan,
1206 long mask)
1207 {
1208 switch (mask) {
1209 case IIO_CHAN_INFO_SAMP_FREQ:
1210 return IIO_VAL_INT;
1211 default:
1212 return IIO_VAL_INT_PLUS_MICRO;
1213 }
1214 }
1215
ad4695_set_osr_val(struct ad4695_state * st,struct iio_chan_spec const * chan,int val)1216 static int ad4695_set_osr_val(struct ad4695_state *st,
1217 struct iio_chan_spec const *chan,
1218 int val)
1219 {
1220 int osr = ad4695_osr_to_regval(val);
1221
1222 if (osr < 0)
1223 return osr;
1224
1225 switch (chan->type) {
1226 case IIO_VOLTAGE:
1227 st->channels_cfg[chan->scan_index].oversampling_ratio = val;
1228 return regmap_update_bits(st->regmap,
1229 AD4695_REG_CONFIG_IN(chan->scan_index),
1230 AD4695_REG_CONFIG_IN_OSR_SET,
1231 FIELD_PREP(AD4695_REG_CONFIG_IN_OSR_SET, osr));
1232 default:
1233 return -EINVAL;
1234 }
1235 }
1236
ad4695_get_calibbias(int val,int val2,int osr)1237 static unsigned int ad4695_get_calibbias(int val, int val2, int osr)
1238 {
1239 int val_calc, scale;
1240
1241 switch (osr) {
1242 case 4:
1243 scale = 4;
1244 break;
1245 case 16:
1246 scale = 2;
1247 break;
1248 case 64:
1249 scale = 1;
1250 break;
1251 default:
1252 scale = 8;
1253 break;
1254 }
1255
1256 val = clamp_t(int, val, S32_MIN / 8, S32_MAX / 8);
1257
1258 /* val2 range is (-MICRO, MICRO) if val == 0, otherwise [0, MICRO) */
1259 if (val < 0)
1260 val_calc = val * scale - val2 * scale / MICRO;
1261 else if (val2 < 0)
1262 /* if val2 < 0 then val == 0 */
1263 val_calc = val2 * scale / (int)MICRO;
1264 else
1265 val_calc = val * scale + val2 * scale / MICRO;
1266
1267 val_calc /= 2;
1268
1269 return clamp_t(int, val_calc, S16_MIN, S16_MAX);
1270 }
1271
__ad4695_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)1272 static int __ad4695_write_raw(struct iio_dev *indio_dev,
1273 struct iio_chan_spec const *chan,
1274 int val, int val2, long mask)
1275 {
1276 struct ad4695_state *st = iio_priv(indio_dev);
1277 unsigned int reg_val;
1278 unsigned int osr = 1;
1279
1280 if (chan->type == IIO_VOLTAGE)
1281 osr = st->channels_cfg[chan->scan_index].oversampling_ratio;
1282
1283 switch (mask) {
1284 case IIO_CHAN_INFO_CALIBSCALE:
1285 switch (chan->type) {
1286 case IIO_VOLTAGE:
1287 if (val < 0 || val2 < 0)
1288 reg_val = 0;
1289 else if (val > 1)
1290 reg_val = U16_MAX;
1291 else
1292 reg_val = (val * (1 << 16) +
1293 mul_u64_u32_div(val2, 1 << 16,
1294 MICRO)) / 2;
1295
1296 return regmap_write(st->regmap16,
1297 AD4695_REG_GAIN_IN(chan->scan_index),
1298 reg_val);
1299 default:
1300 return -EINVAL;
1301 }
1302 case IIO_CHAN_INFO_CALIBBIAS:
1303 switch (chan->type) {
1304 case IIO_VOLTAGE:
1305 reg_val = ad4695_get_calibbias(val, val2, osr);
1306 return regmap_write(st->regmap16,
1307 AD4695_REG_OFFSET_IN(chan->scan_index),
1308 reg_val);
1309 default:
1310 return -EINVAL;
1311 }
1312 case IIO_CHAN_INFO_SAMP_FREQ: {
1313 struct pwm_state state;
1314 /*
1315 * Limit the maximum acceptable sample rate according to
1316 * the channel's oversampling ratio.
1317 */
1318 u64 max_osr_rate = DIV_ROUND_UP_ULL(st->chip_info->max_sample_rate,
1319 osr);
1320
1321 if (val <= 0 || val > max_osr_rate)
1322 return -EINVAL;
1323
1324 guard(mutex)(&st->cnv_pwm_lock);
1325 pwm_get_state(st->cnv_pwm, &state);
1326 /*
1327 * The required sample frequency for a given OSR is the
1328 * input frequency multiplied by it.
1329 */
1330 state.period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, val * osr);
1331 return pwm_apply_might_sleep(st->cnv_pwm, &state);
1332 }
1333 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1334 return ad4695_set_osr_val(st, chan, val);
1335 default:
1336 return -EINVAL;
1337 }
1338 }
1339
ad4695_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)1340 static int ad4695_write_raw(struct iio_dev *indio_dev,
1341 struct iio_chan_spec const *chan,
1342 int val, int val2, long mask)
1343 {
1344 int ret;
1345
1346 if (!iio_device_claim_direct(indio_dev))
1347 return -EBUSY;
1348 ret = __ad4695_write_raw(indio_dev, chan, val, val2, mask);
1349 iio_device_release_direct(indio_dev);
1350
1351 return ret;
1352 }
1353
ad4695_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)1354 static int ad4695_read_avail(struct iio_dev *indio_dev,
1355 struct iio_chan_spec const *chan,
1356 const int **vals, int *type, int *length,
1357 long mask)
1358 {
1359 int ret;
1360 static const int ad4695_calibscale_available[6] = {
1361 /* Range of 0 (inclusive) to 2 (exclusive) */
1362 0, 15, 1, 15, U16_MAX, 15
1363 };
1364 static const int ad4695_calibbias_available[4][6] = {
1365 /*
1366 * Datasheet says FSR/8 which translates to signed/4. The step
1367 * depends on oversampling ratio, so we need four different
1368 * ranges to select from.
1369 */
1370 {
1371 S16_MIN / 4, 0,
1372 0, MICRO / 4,
1373 S16_MAX / 4, S16_MAX % 4 * MICRO / 4
1374 },
1375 {
1376 S16_MIN / 2, 0,
1377 0, MICRO / 2,
1378 S16_MAX / 2, S16_MAX % 2 * MICRO / 2,
1379 },
1380 {
1381 S16_MIN, 0,
1382 1, 0,
1383 S16_MAX, 0,
1384 },
1385 {
1386 S16_MIN * 2, 0,
1387 2, 0,
1388 S16_MAX * 2, 0,
1389 },
1390 };
1391 struct ad4695_state *st = iio_priv(indio_dev);
1392 unsigned int osr = 1;
1393
1394 if (chan->type == IIO_VOLTAGE)
1395 osr = st->channels_cfg[chan->scan_index].oversampling_ratio;
1396
1397 switch (mask) {
1398 case IIO_CHAN_INFO_CALIBSCALE:
1399 switch (chan->type) {
1400 case IIO_VOLTAGE:
1401 *vals = ad4695_calibscale_available;
1402 *type = IIO_VAL_FRACTIONAL_LOG2;
1403 return IIO_AVAIL_RANGE;
1404 default:
1405 return -EINVAL;
1406 }
1407 case IIO_CHAN_INFO_CALIBBIAS:
1408 switch (chan->type) {
1409 case IIO_VOLTAGE:
1410 ret = ad4695_osr_to_regval(osr);
1411 if (ret < 0)
1412 return ret;
1413 /*
1414 * Select the appropriate calibbias array based on the
1415 * OSR value in the register.
1416 */
1417 *vals = ad4695_calibbias_available[ret];
1418 *type = IIO_VAL_INT_PLUS_MICRO;
1419 return IIO_AVAIL_RANGE;
1420 default:
1421 return -EINVAL;
1422 }
1423 case IIO_CHAN_INFO_SAMP_FREQ:
1424 /* Max sample rate for the channel depends on OSR */
1425 st->sample_freq_range[2] =
1426 DIV_ROUND_UP_ULL(st->chip_info->max_sample_rate, osr);
1427 *vals = st->sample_freq_range;
1428 *type = IIO_VAL_INT;
1429 return IIO_AVAIL_RANGE;
1430 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1431 switch (chan->type) {
1432 case IIO_VOLTAGE:
1433 *vals = ad4695_oversampling_ratios;
1434 *length = ARRAY_SIZE(ad4695_oversampling_ratios);
1435 *type = IIO_VAL_INT;
1436 return IIO_AVAIL_LIST;
1437 default:
1438 return -EINVAL;
1439 }
1440 default:
1441 return -EINVAL;
1442 }
1443 }
1444
ad4695_debugfs_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1445 static int ad4695_debugfs_reg_access(struct iio_dev *indio_dev,
1446 unsigned int reg,
1447 unsigned int writeval,
1448 unsigned int *readval)
1449 {
1450 struct ad4695_state *st = iio_priv(indio_dev);
1451 int ret = -EINVAL;
1452
1453 if (!iio_device_claim_direct(indio_dev))
1454 return -EBUSY;
1455
1456 if (readval) {
1457 if (regmap_check_range_table(st->regmap, reg,
1458 &ad4695_regmap_rd_table))
1459 ret = regmap_read(st->regmap, reg, readval);
1460 if (regmap_check_range_table(st->regmap16, reg,
1461 &ad4695_regmap16_rd_table))
1462 ret = regmap_read(st->regmap16, reg, readval);
1463 } else {
1464 if (regmap_check_range_table(st->regmap, reg,
1465 &ad4695_regmap_wr_table))
1466 ret = regmap_write(st->regmap, reg, writeval);
1467 if (regmap_check_range_table(st->regmap16, reg,
1468 &ad4695_regmap16_wr_table))
1469 ret = regmap_write(st->regmap16, reg, writeval);
1470 }
1471 iio_device_release_direct(indio_dev);
1472
1473 return ret;
1474 }
1475
ad4695_get_current_scan_type(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)1476 static int ad4695_get_current_scan_type(const struct iio_dev *indio_dev,
1477 const struct iio_chan_spec *chan)
1478 {
1479 struct ad4695_state *st = iio_priv(indio_dev);
1480 unsigned int osr = st->channels_cfg[chan->scan_index].oversampling_ratio;
1481
1482 switch (osr) {
1483 case 1:
1484 return AD4695_SCAN_TYPE_OSR_1;
1485 case 4:
1486 return AD4695_SCAN_TYPE_OSR_4;
1487 case 16:
1488 return AD4695_SCAN_TYPE_OSR_16;
1489 case 64:
1490 return AD4695_SCAN_TYPE_OSR_64;
1491 default:
1492 return -EINVAL;
1493 }
1494 }
1495
1496 static const struct iio_info ad4695_info = {
1497 .read_raw = &ad4695_read_raw,
1498 .write_raw_get_fmt = &ad4695_write_raw_get_fmt,
1499 .write_raw = &ad4695_write_raw,
1500 .read_avail = &ad4695_read_avail,
1501 .debugfs_reg_access = &ad4695_debugfs_reg_access,
1502 };
1503
1504 static const struct iio_info ad4695_offload_info = {
1505 .read_raw = &ad4695_read_raw,
1506 .write_raw_get_fmt = &ad4695_write_raw_get_fmt,
1507 .write_raw = &ad4695_write_raw,
1508 .get_current_scan_type = &ad4695_get_current_scan_type,
1509 .read_avail = &ad4695_read_avail,
1510 .debugfs_reg_access = &ad4695_debugfs_reg_access,
1511 };
1512
ad4695_parse_channel_cfg(struct ad4695_state * st)1513 static int ad4695_parse_channel_cfg(struct ad4695_state *st)
1514 {
1515 struct device *dev = &st->spi->dev;
1516 struct ad4695_channel_config *chan_cfg;
1517 struct iio_chan_spec *iio_chan;
1518 int ret, i;
1519
1520 /* populate defaults */
1521 for (i = 0; i < st->chip_info->num_voltage_inputs; i++) {
1522 chan_cfg = &st->channels_cfg[i];
1523 iio_chan = &st->iio_chan[i];
1524
1525 chan_cfg->highz_en = true;
1526 chan_cfg->channel = i;
1527
1528 /* This is the default OSR after reset */
1529 chan_cfg->oversampling_ratio = 1;
1530
1531 *iio_chan = ad4695_channel_template;
1532 iio_chan->channel = i;
1533 iio_chan->scan_index = i;
1534 iio_chan->address = AD4695_CMD_VOLTAGE_CHAN(i);
1535 }
1536
1537 /* modify based on firmware description */
1538 device_for_each_child_node_scoped(dev, child) {
1539 u32 reg, val;
1540
1541 ret = fwnode_property_read_u32(child, "reg", ®);
1542 if (ret)
1543 return dev_err_probe(dev, ret,
1544 "failed to read reg property (%s)\n",
1545 fwnode_get_name(child));
1546
1547 if (reg >= st->chip_info->num_voltage_inputs)
1548 return dev_err_probe(dev, -EINVAL,
1549 "reg out of range (%s)\n",
1550 fwnode_get_name(child));
1551
1552 iio_chan = &st->iio_chan[reg];
1553 chan_cfg = &st->channels_cfg[reg];
1554
1555 chan_cfg->highz_en =
1556 !fwnode_property_read_bool(child, "adi,no-high-z");
1557 chan_cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
1558
1559 ret = fwnode_property_read_u32(child, "common-mode-channel",
1560 &val);
1561 if (ret && ret != -EINVAL)
1562 return dev_err_probe(dev, ret,
1563 "failed to read common-mode-channel (%s)\n",
1564 fwnode_get_name(child));
1565
1566 if (ret == -EINVAL || val == AD4695_COMMON_MODE_REFGND)
1567 chan_cfg->pin_pairing = AD4695_IN_PAIR_REFGND;
1568 else if (val == AD4695_COMMON_MODE_COM)
1569 chan_cfg->pin_pairing = AD4695_IN_PAIR_COM;
1570 else
1571 chan_cfg->pin_pairing = AD4695_IN_PAIR_EVEN_ODD;
1572
1573 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD &&
1574 val % 2 == 0)
1575 return dev_err_probe(dev, -EINVAL,
1576 "common-mode-channel must be odd number (%s)\n",
1577 fwnode_get_name(child));
1578
1579 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD &&
1580 val != reg + 1)
1581 return dev_err_probe(dev, -EINVAL,
1582 "common-mode-channel must be next consecutive channel (%s)\n",
1583 fwnode_get_name(child));
1584
1585 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD) {
1586 char name[5];
1587
1588 snprintf(name, sizeof(name), "in%d", reg + 1);
1589
1590 ret = devm_regulator_get_enable_read_voltage(dev, name);
1591 if (ret < 0)
1592 return dev_err_probe(dev, ret,
1593 "failed to get %s voltage (%s)\n",
1594 name, fwnode_get_name(child));
1595
1596 chan_cfg->common_mode_mv = ret / 1000;
1597 }
1598
1599 if (chan_cfg->bipolar &&
1600 chan_cfg->pin_pairing == AD4695_IN_PAIR_REFGND)
1601 return dev_err_probe(dev, -EINVAL,
1602 "bipolar mode is not available for inputs paired with REFGND (%s).\n",
1603 fwnode_get_name(child));
1604
1605 if (chan_cfg->bipolar)
1606 iio_chan->scan_type.sign = 's';
1607
1608 ret = ad4695_write_chn_cfg(st, chan_cfg);
1609 if (ret)
1610 return ret;
1611 }
1612
1613 /* Temperature channel must be next scan index after voltage channels. */
1614 st->iio_chan[i] = ad4695_temp_channel_template;
1615 st->iio_chan[i].scan_index = i;
1616 i++;
1617
1618 st->iio_chan[i] = ad4695_soft_timestamp_channel_template;
1619 st->iio_chan[i].scan_index = i;
1620
1621 return 0;
1622 }
1623
ad4695_offload_trigger_match(struct spi_offload_trigger * trigger,enum spi_offload_trigger_type type,u64 * args,u32 nargs)1624 static bool ad4695_offload_trigger_match(struct spi_offload_trigger *trigger,
1625 enum spi_offload_trigger_type type,
1626 u64 *args, u32 nargs)
1627 {
1628 if (type != SPI_OFFLOAD_TRIGGER_DATA_READY)
1629 return false;
1630
1631 /*
1632 * Requires 2 args:
1633 * args[0] is the trigger event.
1634 * args[1] is the GPIO pin number.
1635 */
1636 if (nargs != 2 || args[0] != AD4695_TRIGGER_EVENT_BUSY)
1637 return false;
1638
1639 return true;
1640 }
1641
ad4695_offload_trigger_request(struct spi_offload_trigger * trigger,enum spi_offload_trigger_type type,u64 * args,u32 nargs)1642 static int ad4695_offload_trigger_request(struct spi_offload_trigger *trigger,
1643 enum spi_offload_trigger_type type,
1644 u64 *args, u32 nargs)
1645 {
1646 struct ad4695_state *st = spi_offload_trigger_get_priv(trigger);
1647
1648 /* Should already be validated by match, but just in case. */
1649 if (nargs != 2)
1650 return -EINVAL;
1651
1652 /* DT tells us if BUSY event uses GP0 or GP3. */
1653 if (args[1] == AD4695_TRIGGER_PIN_GP3)
1654 return regmap_set_bits(st->regmap, AD4695_REG_GP_MODE,
1655 AD4695_REG_GP_MODE_BUSY_GP_SEL);
1656
1657 return regmap_clear_bits(st->regmap, AD4695_REG_GP_MODE,
1658 AD4695_REG_GP_MODE_BUSY_GP_SEL);
1659 }
1660
1661 static int
ad4695_offload_trigger_validate(struct spi_offload_trigger * trigger,struct spi_offload_trigger_config * config)1662 ad4695_offload_trigger_validate(struct spi_offload_trigger *trigger,
1663 struct spi_offload_trigger_config *config)
1664 {
1665 if (config->type != SPI_OFFLOAD_TRIGGER_DATA_READY)
1666 return -EINVAL;
1667
1668 return 0;
1669 }
1670
1671 /*
1672 * NB: There are no enable/disable callbacks here due to requiring a SPI
1673 * message to enable or disable the BUSY output on the ADC.
1674 */
1675 static const struct spi_offload_trigger_ops ad4695_offload_trigger_ops = {
1676 .match = ad4695_offload_trigger_match,
1677 .request = ad4695_offload_trigger_request,
1678 .validate = ad4695_offload_trigger_validate,
1679 };
1680
ad4695_pwm_disable(void * pwm)1681 static void ad4695_pwm_disable(void *pwm)
1682 {
1683 pwm_disable(pwm);
1684 }
1685
ad4695_probe_spi_offload(struct iio_dev * indio_dev,struct ad4695_state * st)1686 static int ad4695_probe_spi_offload(struct iio_dev *indio_dev,
1687 struct ad4695_state *st)
1688 {
1689 struct device *dev = &st->spi->dev;
1690 struct spi_offload_trigger_info trigger_info = {
1691 .fwnode = dev_fwnode(dev),
1692 .ops = &ad4695_offload_trigger_ops,
1693 .priv = st,
1694 };
1695 struct pwm_state pwm_state;
1696 struct dma_chan *rx_dma;
1697 int ret, i;
1698
1699 indio_dev->info = &ad4695_offload_info;
1700 indio_dev->num_channels = st->chip_info->num_voltage_inputs + 1;
1701 indio_dev->setup_ops = &ad4695_offload_buffer_setup_ops;
1702
1703 if (!st->cnv_gpio)
1704 return dev_err_probe(dev, -ENODEV,
1705 "CNV GPIO is required for SPI offload\n");
1706
1707 ret = devm_spi_offload_trigger_register(dev, &trigger_info);
1708 if (ret)
1709 return dev_err_probe(dev, ret,
1710 "failed to register offload trigger\n");
1711
1712 st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload,
1713 SPI_OFFLOAD_TRIGGER_DATA_READY);
1714 if (IS_ERR(st->offload_trigger))
1715 return dev_err_probe(dev, PTR_ERR(st->offload_trigger),
1716 "failed to get offload trigger\n");
1717
1718 ret = devm_mutex_init(dev, &st->cnv_pwm_lock);
1719 if (ret)
1720 return ret;
1721
1722 st->cnv_pwm = devm_pwm_get(dev, NULL);
1723 if (IS_ERR(st->cnv_pwm))
1724 return dev_err_probe(dev, PTR_ERR(st->cnv_pwm),
1725 "failed to get CNV PWM\n");
1726
1727 pwm_init_state(st->cnv_pwm, &pwm_state);
1728
1729 /* If firmware didn't provide default rate, use 10kHz (arbitrary). */
1730 if (pwm_state.period == 0)
1731 pwm_state.period = 100 * MILLI;
1732
1733 pwm_state.enabled = true;
1734
1735 ret = pwm_apply_might_sleep(st->cnv_pwm, &pwm_state);
1736 if (ret)
1737 return dev_err_probe(dev, ret, "failed to apply CNV PWM\n");
1738
1739 ret = devm_add_action_or_reset(dev, ad4695_pwm_disable, st->cnv_pwm);
1740 if (ret)
1741 return ret;
1742
1743 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload);
1744 if (IS_ERR(rx_dma))
1745 return dev_err_probe(dev, PTR_ERR(rx_dma),
1746 "failed to get offload RX DMA\n");
1747
1748 for (i = 0; i < indio_dev->num_channels; i++) {
1749 struct iio_chan_spec *chan = &st->iio_chan[i];
1750 struct ad4695_channel_config *cfg;
1751
1752 /*
1753 * NB: When using offload support, all channels need to have the
1754 * same bits_per_word because they all use the same SPI message
1755 * for reading one sample. In order to prevent breaking
1756 * userspace in the future when oversampling support is added,
1757 * all channels are set read 19 bits with a shift of 3 to mask
1758 * out the extra bits even though we currently only support 16
1759 * bit samples (oversampling ratio == 1).
1760 */
1761 chan->scan_type.shift = 3;
1762 chan->scan_type.storagebits = 32;
1763 /* add sample frequency for PWM CNV trigger */
1764 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_SAMP_FREQ);
1765 chan->info_mask_separate_available |= BIT(IIO_CHAN_INFO_SAMP_FREQ);
1766
1767 /* Add the oversampling properties only for voltage channels */
1768 if (chan->type != IIO_VOLTAGE)
1769 continue;
1770
1771 cfg = &st->channels_cfg[i];
1772
1773 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
1774 chan->info_mask_separate_available |=
1775 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
1776 chan->has_ext_scan_type = 1;
1777 if (cfg->bipolar) {
1778 chan->ext_scan_type = ad4695_scan_type_offload_s;
1779 chan->num_ext_scan_type =
1780 ARRAY_SIZE(ad4695_scan_type_offload_s);
1781 } else {
1782 chan->ext_scan_type = ad4695_scan_type_offload_u;
1783 chan->num_ext_scan_type =
1784 ARRAY_SIZE(ad4695_scan_type_offload_u);
1785 }
1786 }
1787
1788 return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev,
1789 rx_dma, IIO_BUFFER_DIRECTION_IN);
1790 }
1791
1792 static const struct spi_offload_config ad4695_spi_offload_config = {
1793 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER |
1794 SPI_OFFLOAD_CAP_RX_STREAM_DMA,
1795 };
1796
ad4695_probe(struct spi_device * spi)1797 static int ad4695_probe(struct spi_device *spi)
1798 {
1799 struct device *dev = &spi->dev;
1800 struct ad4695_state *st;
1801 struct iio_dev *indio_dev;
1802 bool use_internal_ldo_supply;
1803 bool use_internal_ref_buffer;
1804 int ret;
1805
1806 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1807 if (!indio_dev)
1808 return -ENOMEM;
1809
1810 st = iio_priv(indio_dev);
1811 st->spi = spi;
1812
1813 st->chip_info = spi_get_device_match_data(spi);
1814 if (!st->chip_info)
1815 return -EINVAL;
1816
1817 st->sample_freq_range[0] = 1; /* min */
1818 st->sample_freq_range[1] = 1; /* step */
1819 st->sample_freq_range[2] = st->chip_info->max_sample_rate; /* max */
1820
1821 st->regmap = devm_regmap_init(dev, &ad4695_regmap_bus, st,
1822 &ad4695_regmap_config);
1823 if (IS_ERR(st->regmap))
1824 return dev_err_probe(dev, PTR_ERR(st->regmap),
1825 "Failed to initialize regmap\n");
1826
1827 st->regmap16 = devm_regmap_init(dev, &ad4695_regmap_bus, st,
1828 &ad4695_regmap16_config);
1829 if (IS_ERR(st->regmap16))
1830 return dev_err_probe(dev, PTR_ERR(st->regmap16),
1831 "Failed to initialize regmap16\n");
1832
1833 st->cnv_gpio = devm_gpiod_get_optional(dev, "cnv", GPIOD_OUT_LOW);
1834 if (IS_ERR(st->cnv_gpio))
1835 return dev_err_probe(dev, PTR_ERR(st->cnv_gpio),
1836 "Failed to get CNV GPIO\n");
1837
1838 ret = devm_regulator_bulk_get_enable(dev,
1839 ARRAY_SIZE(ad4695_power_supplies),
1840 ad4695_power_supplies);
1841 if (ret)
1842 return dev_err_probe(dev, ret,
1843 "Failed to enable power supplies\n");
1844
1845 /* If LDO_IN supply is present, then we are using internal LDO. */
1846 ret = devm_regulator_get_enable_optional(dev, "ldo-in");
1847 if (ret < 0 && ret != -ENODEV)
1848 return dev_err_probe(dev, ret,
1849 "Failed to enable LDO_IN supply\n");
1850
1851 use_internal_ldo_supply = ret == 0;
1852
1853 if (!use_internal_ldo_supply) {
1854 /* Otherwise we need an external VDD supply. */
1855 ret = devm_regulator_get_enable(dev, "vdd");
1856 if (ret < 0)
1857 return dev_err_probe(dev, ret,
1858 "Failed to enable VDD supply\n");
1859 }
1860
1861 /* If REFIN supply is given, then we are using internal buffer */
1862 ret = devm_regulator_get_enable_read_voltage(dev, "refin");
1863 if (ret < 0 && ret != -ENODEV)
1864 return dev_err_probe(dev, ret, "Failed to get REFIN voltage\n");
1865
1866 if (ret != -ENODEV) {
1867 st->vref_mv = ret / 1000;
1868 use_internal_ref_buffer = true;
1869 } else {
1870 /* Otherwise, we need an external reference. */
1871 ret = devm_regulator_get_enable_read_voltage(dev, "ref");
1872 if (ret < 0)
1873 return dev_err_probe(dev, ret,
1874 "Failed to get REF voltage\n");
1875
1876 st->vref_mv = ret / 1000;
1877 use_internal_ref_buffer = false;
1878 }
1879
1880 ret = devm_regulator_get_enable_read_voltage(dev, "com");
1881 if (ret < 0 && ret != -ENODEV)
1882 return dev_err_probe(dev, ret, "Failed to get COM voltage\n");
1883
1884 st->com_mv = ret == -ENODEV ? 0 : ret / 1000;
1885
1886 /*
1887 * Reset the device using hardware reset if available or fall back to
1888 * software reset.
1889 */
1890
1891 st->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1892 if (IS_ERR(st->reset_gpio))
1893 return PTR_ERR(st->reset_gpio);
1894
1895 if (st->reset_gpio) {
1896 gpiod_set_value(st->reset_gpio, 0);
1897 msleep(AD4695_T_WAKEUP_HW_MS);
1898 } else {
1899 ret = regmap_write(st->regmap, AD4695_REG_SPI_CONFIG_A,
1900 AD4695_REG_SPI_CONFIG_A_SW_RST);
1901 if (ret)
1902 return ret;
1903
1904 msleep(AD4695_T_WAKEUP_SW_MS);
1905 }
1906
1907 /* Needed for regmap16 to be able to work correctly. */
1908 ret = regmap_set_bits(st->regmap, AD4695_REG_SPI_CONFIG_A,
1909 AD4695_REG_SPI_CONFIG_A_ADDR_DIR);
1910 if (ret)
1911 return ret;
1912
1913 /* Disable internal LDO if it isn't needed. */
1914 ret = regmap_update_bits(st->regmap, AD4695_REG_SETUP,
1915 AD4695_REG_SETUP_LDO_EN,
1916 FIELD_PREP(AD4695_REG_SETUP_LDO_EN,
1917 use_internal_ldo_supply ? 1 : 0));
1918 if (ret)
1919 return ret;
1920
1921 /* configure reference supply */
1922
1923 if (device_property_present(dev, "adi,no-ref-current-limit")) {
1924 ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL,
1925 AD4695_REG_REF_CTRL_OV_MODE);
1926 if (ret)
1927 return ret;
1928 }
1929
1930 if (device_property_present(dev, "adi,no-ref-high-z")) {
1931 if (use_internal_ref_buffer)
1932 return dev_err_probe(dev, -EINVAL,
1933 "Cannot disable high-Z mode for internal reference buffer\n");
1934
1935 ret = regmap_clear_bits(st->regmap, AD4695_REG_REF_CTRL,
1936 AD4695_REG_REF_CTRL_REFHIZ_EN);
1937 if (ret)
1938 return ret;
1939 }
1940
1941 ret = ad4695_set_ref_voltage(st, st->vref_mv);
1942 if (ret)
1943 return ret;
1944
1945 if (use_internal_ref_buffer) {
1946 ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL,
1947 AD4695_REG_REF_CTRL_REFBUF_EN);
1948 if (ret)
1949 return ret;
1950
1951 /* Give the capacitor some time to charge up. */
1952 msleep(AD4695_T_REFBUF_MS);
1953 }
1954
1955 ret = ad4695_parse_channel_cfg(st);
1956 if (ret)
1957 return ret;
1958
1959 indio_dev->name = st->chip_info->name;
1960 indio_dev->info = &ad4695_info;
1961 indio_dev->modes = INDIO_DIRECT_MODE;
1962 indio_dev->channels = st->iio_chan;
1963 indio_dev->num_channels = st->chip_info->num_voltage_inputs + 2;
1964
1965 st->offload = devm_spi_offload_get(dev, spi, &ad4695_spi_offload_config);
1966 ret = PTR_ERR_OR_ZERO(st->offload);
1967 if (ret && ret != -ENODEV)
1968 return dev_err_probe(dev, ret, "failed to get SPI offload\n");
1969
1970 /* If no SPI offload, fall back to low speed usage. */
1971 if (ret == -ENODEV) {
1972 /* Driver currently requires CNV pin to be connected to SPI CS */
1973 if (st->cnv_gpio)
1974 return dev_err_probe(dev, -EINVAL,
1975 "CNV GPIO is not supported\n");
1976
1977 indio_dev->num_channels = st->chip_info->num_voltage_inputs + 2;
1978
1979 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1980 iio_pollfunc_store_time,
1981 ad4695_trigger_handler,
1982 &ad4695_buffer_setup_ops);
1983 if (ret)
1984 return ret;
1985 } else {
1986 ret = ad4695_probe_spi_offload(indio_dev, st);
1987 if (ret)
1988 return ret;
1989 }
1990
1991 return devm_iio_device_register(dev, indio_dev);
1992 }
1993
1994 static const struct spi_device_id ad4695_spi_id_table[] = {
1995 { .name = "ad4695", .driver_data = (kernel_ulong_t)&ad4695_chip_info },
1996 { .name = "ad4696", .driver_data = (kernel_ulong_t)&ad4696_chip_info },
1997 { .name = "ad4697", .driver_data = (kernel_ulong_t)&ad4697_chip_info },
1998 { .name = "ad4698", .driver_data = (kernel_ulong_t)&ad4698_chip_info },
1999 { }
2000 };
2001 MODULE_DEVICE_TABLE(spi, ad4695_spi_id_table);
2002
2003 static const struct of_device_id ad4695_of_match_table[] = {
2004 { .compatible = "adi,ad4695", .data = &ad4695_chip_info, },
2005 { .compatible = "adi,ad4696", .data = &ad4696_chip_info, },
2006 { .compatible = "adi,ad4697", .data = &ad4697_chip_info, },
2007 { .compatible = "adi,ad4698", .data = &ad4698_chip_info, },
2008 { }
2009 };
2010 MODULE_DEVICE_TABLE(of, ad4695_of_match_table);
2011
2012 static struct spi_driver ad4695_driver = {
2013 .driver = {
2014 .name = "ad4695",
2015 .of_match_table = ad4695_of_match_table,
2016 },
2017 .probe = ad4695_probe,
2018 .id_table = ad4695_spi_id_table,
2019 };
2020 module_spi_driver(ad4695_driver);
2021
2022 MODULE_AUTHOR("Ramona Gradinariu <ramona.gradinariu@analog.com>");
2023 MODULE_AUTHOR("David Lechner <dlechner@baylibre.com>");
2024 MODULE_DESCRIPTION("Analog Devices AD4695 ADC driver");
2025 MODULE_LICENSE("GPL");
2026 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");
2027