1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2015-2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 /* The caprices of the preprocessor require that this be declared right here */ 28 #define CREATE_TRACE_POINTS 29 30 #include "dm_services_types.h" 31 #include "dc.h" 32 #include "link_enc_cfg.h" 33 #include "dc/inc/core_types.h" 34 #include "dal_asic_id.h" 35 #include "dmub/dmub_srv.h" 36 #include "dc/inc/hw/dmcu.h" 37 #include "dc/inc/hw/abm.h" 38 #include "dc/dc_dmub_srv.h" 39 #include "dc/dc_stat.h" 40 #include "dc/dc_state.h" 41 #include "amdgpu_dm_trace.h" 42 #include "link/protocols/link_dpcd.h" 43 #include "link_service_types.h" 44 #include "link/protocols/link_dp_capability.h" 45 #include "link/protocols/link_ddc.h" 46 47 #include "amdgpu.h" 48 #include "amdgpu_display.h" 49 #include "amdgpu_ucode.h" 50 #include "atom.h" 51 #include "amdgpu_dm.h" 52 #include "amdgpu_dm_plane.h" 53 #include "amdgpu_dm_crtc.h" 54 #include "amdgpu_dm_hdcp.h" 55 #include <drm/display/drm_hdcp_helper.h> 56 #include "amdgpu_dm_wb.h" 57 #include "amdgpu_atombios.h" 58 59 #include "amd_shared.h" 60 #include "amdgpu_dm_irq.h" 61 #include "dm_helpers.h" 62 #include "amdgpu_dm_mst_types.h" 63 #if defined(CONFIG_DEBUG_FS) 64 #include "amdgpu_dm_debugfs.h" 65 #endif 66 #include "amdgpu_dm_psr.h" 67 #include "amdgpu_dm_replay.h" 68 #include "amdgpu_dm_backlight.h" 69 #include "amdgpu_dm_audio.h" 70 #include "amdgpu_dm_dmub.h" 71 #include "amdgpu_dm_connector.h" 72 #include "amdgpu_dm_pp_smu.h" 73 #include "amdgpu_dm_freesync.h" 74 #include "amdgpu_dm_cursor.h" 75 76 #include "ivsrcid/ivsrcid_vislands30.h" 77 78 #include <linux/backlight.h> 79 #include <linux/module.h> 80 #include <linux/moduleparam.h> 81 #include <linux/types.h> 82 #include <linux/pm_runtime.h> 83 #include <linux/pci.h> 84 #include <linux/power_supply.h> 85 #include <linux/firmware.h> 86 #include <linux/component.h> 87 #include <linux/sort.h> 88 89 #include <drm/drm_privacy_screen_consumer.h> 90 #include <drm/display/drm_dp_mst_helper.h> 91 #include <drm/display/drm_hdmi_helper.h> 92 #include <drm/drm_atomic.h> 93 #include <drm/drm_atomic_uapi.h> 94 #include <drm/drm_atomic_helper.h> 95 #include <drm/drm_blend.h> 96 #include <drm/drm_fixed.h> 97 #include <drm/drm_fourcc.h> 98 #include <drm/drm_edid.h> 99 #include <drm/drm_eld.h> 100 #include <drm/drm_mode.h> 101 #include <drm/drm_vblank.h> 102 #include <drm/drm_colorop.h> 103 #include <drm/drm_gem_atomic_helper.h> 104 105 #include <media/cec-notifier.h> 106 #include <acpi/video.h> 107 108 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 109 110 #include "modules/inc/mod_freesync.h" 111 #include "modules/inc/mod_power.h" 112 #include "modules/power/power_helpers.h" 113 114 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 115 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 116 117 /** 118 * DOC: overview 119 * 120 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 121 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 122 * requests into DC requests, and DC responses into DRM responses. 123 * 124 * The root control structure is &struct amdgpu_display_manager. 125 */ 126 127 /* basic init/fini API */ 128 static int amdgpu_dm_init(struct amdgpu_device *adev); 129 static void amdgpu_dm_fini(struct amdgpu_device *adev); 130 131 /* 132 * initializes drm_device display related structures, based on the information 133 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 134 * drm_encoder, drm_mode_config 135 * 136 * Returns 0 on success 137 */ 138 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 139 /* removes and deallocates the drm structures, created by the above function */ 140 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 141 142 STATIC_IFN_KUNIT int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state); 143 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state); 144 STATIC_IFN_KUNIT void dm_enable_per_frame_crtc_master_sync(struct dc_state *context); 145 146 #if !IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST) 147 static int amdgpu_dm_atomic_check(struct drm_device *dev, 148 struct drm_atomic_commit *state); 149 #endif 150 151 static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) 152 { 153 if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter) 154 dc_exit_ips_for_hw_access(dc); 155 } 156 157 /* 158 * dm_vblank_get_counter 159 * 160 * @brief 161 * Get counter for number of vertical blanks 162 * 163 * @param 164 * struct amdgpu_device *adev - [in] desired amdgpu device 165 * int disp_idx - [in] which CRTC to get the counter from 166 * 167 * @return 168 * Counter for vertical blanks 169 */ 170 STATIC_IFN_KUNIT u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 171 { 172 struct amdgpu_crtc *acrtc = NULL; 173 174 if (crtc >= adev->mode_info.num_crtc) 175 return 0; 176 177 acrtc = adev->mode_info.crtcs[crtc]; 178 179 if (!acrtc->dm_irq_params.stream) { 180 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 181 crtc); 182 return 0; 183 } 184 185 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 186 } 187 EXPORT_IF_KUNIT(dm_vblank_get_counter); 188 189 STATIC_IFN_KUNIT int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 190 u32 *vbl, u32 *position) 191 { 192 u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0; 193 struct amdgpu_crtc *acrtc = NULL; 194 struct dc *dc = adev->dm.dc; 195 196 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 197 return -EINVAL; 198 199 acrtc = adev->mode_info.crtcs[crtc]; 200 201 if (!acrtc->dm_irq_params.stream) { 202 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 203 crtc); 204 return 0; 205 } 206 207 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) 208 dc_allow_idle_optimizations(dc, false); 209 210 /* 211 * TODO rework base driver to use values directly. 212 * for now parse it back into reg-format 213 */ 214 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 215 &v_blank_start, 216 &v_blank_end, 217 &h_position, 218 &v_position); 219 220 *position = v_position | (h_position << 16); 221 *vbl = v_blank_start | (v_blank_end << 16); 222 223 return 0; 224 } 225 EXPORT_IF_KUNIT(dm_crtc_get_scanoutpos); 226 227 STATIC_IFN_KUNIT int dm_wait_for_idle(struct amdgpu_ip_block *ip_block) 228 { 229 /* XXX todo */ 230 return 0; 231 } 232 EXPORT_IF_KUNIT(dm_wait_for_idle); 233 234 /* 235 * DC will program planes with their z-order determined by their ordering 236 * in the dc_surface_updates array. This comparator is used to sort them 237 * by descending zpos. 238 */ 239 STATIC_IFN_KUNIT int dm_plane_layer_index_cmp(const void *a, const void *b) 240 { 241 const struct dc_surface_update *sa = (struct dc_surface_update *)a; 242 const struct dc_surface_update *sb = (struct dc_surface_update *)b; 243 244 /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */ 245 return sb->surface->layer_index - sa->surface->layer_index; 246 } 247 EXPORT_IF_KUNIT(dm_plane_layer_index_cmp); 248 249 #if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST) 250 static const struct amdgpu_dm_kunit_ops *amdgpu_dm_ops; 251 252 #define dm_post_update_surfaces_to_stream amdgpu_dm_ops->post_update_surfaces_to_stream 253 #define dm_update_planes_and_stream amdgpu_dm_ops->update_planes_and_stream 254 #else 255 #define dm_post_update_surfaces_to_stream dc_post_update_surfaces_to_stream 256 #define dm_update_planes_and_stream dc_update_planes_and_stream 257 #endif 258 259 /** 260 * update_planes_and_stream_adapter() - Send planes to be updated in DC 261 * 262 * DC has a generic way to update planes and stream via 263 * dc_update_planes_and_stream function; however, DM might need some 264 * adjustments and preparation before calling it. This function is a wrapper 265 * for the dc_update_planes_and_stream that does any required configuration 266 * before passing control to DC. 267 * 268 * @dc: Display Core control structure 269 * @planes_count: planes count to update 270 * @stream: stream state 271 * @stream_update: stream update 272 * @array_of_surface_update: dc surface update pointer 273 * 274 */ 275 STATIC_IFN_KUNIT INLINE_IFN_KUNIT 276 bool update_planes_and_stream_adapter(struct dc *dc, 277 int planes_count, 278 struct dc_stream_state *stream, 279 struct dc_stream_update *stream_update, 280 struct dc_surface_update *array_of_surface_update) 281 { 282 sort(array_of_surface_update, planes_count, 283 sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL); 284 285 /* 286 * Previous frame finished and HW is ready for optimization. 287 */ 288 dm_post_update_surfaces_to_stream(dc); 289 290 return dm_update_planes_and_stream(dc, 291 array_of_surface_update, 292 planes_count, 293 stream, 294 stream_update); 295 } 296 EXPORT_IF_KUNIT(update_planes_and_stream_adapter); 297 298 STATIC_IFN_KUNIT int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 299 enum amd_clockgating_state state) 300 { 301 return 0; 302 } 303 EXPORT_IF_KUNIT(dm_set_clockgating_state); 304 305 STATIC_IFN_KUNIT int dm_set_powergating_state(struct amdgpu_ip_block *ip_block, 306 enum amd_powergating_state state) 307 { 308 return 0; 309 } 310 EXPORT_IF_KUNIT(dm_set_powergating_state); 311 312 /* Prototypes of private functions */ 313 STATIC_IFN_KUNIT int dm_early_init(struct amdgpu_ip_block *ip_block); 314 315 #if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST) 316 static const struct amdgpu_dm_kunit_ops amdgpu_dm_default_ops = { 317 .gmc_pd_addr = amdgpu_gmc_pd_addr, 318 .post_update_surfaces_to_stream = dc_post_update_surfaces_to_stream, 319 .update_planes_and_stream = dc_update_planes_and_stream, 320 .atomic_helper_suspend = drm_atomic_helper_suspend, 321 }; 322 323 static const struct amdgpu_dm_kunit_ops *amdgpu_dm_ops = &amdgpu_dm_default_ops; 324 325 void amdgpu_dm_kunit_set_ops(const struct amdgpu_dm_kunit_ops *ops) 326 { 327 amdgpu_dm_ops = ops ? ops : &amdgpu_dm_default_ops; 328 } 329 EXPORT_IF_KUNIT(amdgpu_dm_kunit_set_ops); 330 331 #define dm_gmc_pd_addr amdgpu_dm_ops->gmc_pd_addr 332 #define dm_atomic_helper_suspend amdgpu_dm_ops->atomic_helper_suspend 333 #else 334 #define dm_gmc_pd_addr amdgpu_gmc_pd_addr 335 #define dm_atomic_helper_suspend drm_atomic_helper_suspend 336 #endif 337 338 /* Allocate memory for FBC compressed data */ 339 STATIC_IFN_KUNIT void mmhub_read_system_context(struct amdgpu_device *adev, 340 struct dc_phy_addr_space_config *pa_config) 341 { 342 u64 pt_base; 343 u32 logical_addr_low; 344 u32 logical_addr_high; 345 u32 agp_base, agp_bot, agp_top; 346 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 347 348 memset(pa_config, 0, sizeof(*pa_config)); 349 350 agp_base = 0; 351 agp_bot = adev->gmc.agp_start >> 24; 352 agp_top = adev->gmc.agp_end >> 24; 353 354 /* AGP aperture is disabled */ 355 if (agp_bot > agp_top) { 356 logical_addr_low = adev->gmc.fb_start >> 18; 357 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 358 AMD_APU_IS_RENOIR | 359 AMD_APU_IS_GREEN_SARDINE)) 360 /* 361 * Raven2 has a HW issue that it is unable to use the vram which 362 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 363 * workaround that increase system aperture high address (add 1) 364 * to get rid of the VM fault and hardware hang. 365 */ 366 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 367 else 368 logical_addr_high = adev->gmc.fb_end >> 18; 369 } else { 370 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 371 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 372 AMD_APU_IS_RENOIR | 373 AMD_APU_IS_GREEN_SARDINE)) 374 /* 375 * Raven2 has a HW issue that it is unable to use the vram which 376 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 377 * workaround that increase system aperture high address (add 1) 378 * to get rid of the VM fault and hardware hang. 379 */ 380 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 381 else 382 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 383 } 384 385 pt_base = dm_gmc_pd_addr(adev->gart.bo); 386 387 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 388 AMDGPU_GPU_PAGE_SHIFT); 389 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 390 AMDGPU_GPU_PAGE_SHIFT); 391 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 392 AMDGPU_GPU_PAGE_SHIFT); 393 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 394 AMDGPU_GPU_PAGE_SHIFT); 395 page_table_base.high_part = upper_32_bits(pt_base); 396 page_table_base.low_part = lower_32_bits(pt_base); 397 398 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 399 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 400 401 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 402 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 403 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 404 405 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 406 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 407 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 408 409 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 410 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 411 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 412 413 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 414 415 } 416 EXPORT_IF_KUNIT(mmhub_read_system_context); 417 418 STATIC_IFN_KUNIT int amdgpu_dm_init_power_module(struct amdgpu_display_manager *dm) 419 { 420 struct mod_power_init_params init_data[MAX_NUM_EDP]; 421 422 if (dm->num_of_edps == 0) { 423 drm_dbg_driver( 424 dm->ddev, 425 "amdgpu: No eDP detected, skip initializing power module\n"); 426 return 0; 427 } 428 429 /* Initialize all the power module parameters */ 430 for (int i = 0; i < dm->num_of_edps; i++) { 431 init_data[i].allow_psr_smu_optimizations = 432 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT); 433 init_data[i].allow_psr_multi_disp_optimizations = 434 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); 435 /* See dm_late_init */ 436 init_data[i].backlight_ramping_override = false; 437 init_data[i].backlight_ramping_start = 0xCCCC; 438 init_data[i].backlight_ramping_reduction = 0xCCCCCCCC; 439 init_data[i].def_varibright_level = 0; 440 init_data[i].abm_config_setting = 0; 441 init_data[i].num_backlight_levels = 101; 442 init_data[i].use_nits_based_brightness = false; 443 init_data[i].panel_max_millinits = 0; 444 init_data[i].panel_min_millinits = 0; 445 init_data[i].disable_fractional_pwm = 446 !(amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK); 447 init_data[i].use_custom_backlight_caps = false; 448 init_data[i].custom_backlight_caps_config_no = 0; 449 init_data[i].use_linear_backlight_curve = false; 450 if (amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE) 451 init_data[i].use_linear_backlight_curve = true; 452 init_data[i].def_varibright_enable = 0; 453 init_data[i].varibright_level = 0; 454 /* 455 * Power module uses 16-bit backlight levels (0xFFFF max) rather 456 * than 8-bit(0XFF max) 457 */ 458 init_data[i].min_backlight_pwm = 459 dm->backlight_caps[i].min_input_signal * 0x101; 460 init_data[i].max_backlight_pwm = 461 dm->backlight_caps[i].max_input_signal * 0x101; 462 init_data[i].min_abm_backlight = 463 dm->backlight_caps[i].min_input_signal * 0x101; 464 465 /* Min backlight level after ABM reduction, Don't allow below 1% 466 * 0xFFFF x 0.01 = 0x28F 467 */ 468 init_data[i].min_abm_backlight = (init_data[i].min_abm_backlight < 0x28F) ? 469 0x28F : init_data[i].min_abm_backlight; 470 } 471 472 dm->power_module = mod_power_create(dm->dc, init_data, dm->num_of_edps); 473 if (!dm->power_module) { 474 drm_err(dm->ddev, "amdgpu: Error allocating memory for power module\n"); 475 return -ENOMEM; 476 } 477 478 mod_power_hw_init(dm->power_module); 479 drm_dbg_driver(dm->ddev, "amdgpu: Power module init done\n"); 480 481 return 0; 482 } 483 EXPORT_IF_KUNIT(amdgpu_dm_init_power_module); 484 485 static int amdgpu_dm_init(struct amdgpu_device *adev) 486 { 487 struct dc_init_data init_data; 488 struct dc_callback_init init_params; 489 int r; 490 491 adev->dm.ddev = adev_to_drm(adev); 492 adev->dm.adev = adev; 493 494 /* Zero all the fields */ 495 memset(&init_data, 0, sizeof(init_data)); 496 memset(&init_params, 0, sizeof(init_params)); 497 498 mutex_init(&adev->dm.dpia_aux_lock); 499 mutex_init(&adev->dm.dc_lock); 500 mutex_init(&adev->dm.audio_lock); 501 502 spin_lock_init(&adev->dm.dmub_lock); 503 504 if (amdgpu_dm_irq_init(adev)) { 505 drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); 506 goto error; 507 } 508 509 /* special handling for early revisions of GC 11.5.4 */ 510 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4)) 511 init_data.asic_id.chip_family = AMDGPU_FAMILY_GC_11_5_4; 512 else 513 init_data.asic_id.chip_family = adev->family; 514 515 init_data.asic_id.pci_revision_id = adev->pdev->revision; 516 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 517 init_data.asic_id.chip_id = adev->pdev->device; 518 519 init_data.asic_id.vram_width = adev->gmc.vram_width; 520 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 521 init_data.asic_id.atombios_base_address = 522 adev->mode_info.atom_context->bios; 523 524 init_data.driver = adev; 525 526 /* cgs_device was created in dm_sw_init() */ 527 init_data.cgs_device = adev->dm.cgs_device; 528 529 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 530 531 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 532 case IP_VERSION(2, 1, 0): 533 switch (adev->dm.dmcub_fw_version) { 534 case 0: /* development */ 535 case 0x1: /* linux-firmware.git hash 6d9f399 */ 536 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 537 init_data.flags.disable_dmcu = false; 538 break; 539 default: 540 init_data.flags.disable_dmcu = true; 541 } 542 break; 543 case IP_VERSION(2, 0, 3): 544 init_data.flags.disable_dmcu = true; 545 break; 546 default: 547 break; 548 } 549 550 /* APU support S/G display by default except: 551 * ASICs before Carrizo, 552 * RAVEN1 (Users reported stability issue) 553 */ 554 555 if (adev->asic_type < CHIP_CARRIZO) { 556 init_data.flags.gpu_vm_support = false; 557 } else if (adev->asic_type == CHIP_RAVEN) { 558 if (adev->apu_flags & AMD_APU_IS_RAVEN) 559 init_data.flags.gpu_vm_support = false; 560 else 561 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); 562 } else { 563 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(2, 0, 3)) 564 init_data.flags.gpu_vm_support = (amdgpu_sg_display == 1); 565 else 566 init_data.flags.gpu_vm_support = 567 (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); 568 } 569 570 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; 571 572 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 573 init_data.flags.fbc_support = true; 574 575 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 576 init_data.flags.multi_mon_pp_mclk_switch = true; 577 578 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 579 init_data.flags.disable_fractional_pwm = true; 580 581 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 582 init_data.flags.edp_no_power_sequencing = true; 583 584 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 585 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 586 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 587 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 588 589 if (amdgpu_dc_feature_mask & DC_FRL_MASK) 590 init_data.flags.enable_frl = true; 591 592 init_data.flags.seamless_boot_edp_requested = false; 593 594 if (amdgpu_device_seamless_boot_supported(adev)) { 595 init_data.flags.seamless_boot_edp_requested = true; 596 init_data.flags.allow_seamless_boot_optimization = true; 597 drm_dbg(adev->dm.ddev, "Seamless boot requested\n"); 598 } 599 600 init_data.flags.enable_mipi_converter_optimization = true; 601 602 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 603 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 604 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; 605 606 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) 607 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; 608 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS_DYNAMIC) 609 init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC; 610 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS2_DYNAMIC) 611 init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; 612 else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE) 613 init_data.flags.disable_ips = DMUB_IPS_ENABLE; 614 else 615 init_data.flags.disable_ips = dm_get_default_ips_mode(adev); 616 617 init_data.flags.disable_ips_in_vpb = 0; 618 619 /* DCN35 and above supports dynamic DTBCLK switch */ 620 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0)) 621 init_data.flags.allow_0_dtb_clk = true; 622 623 /* Enable DWB for tested platforms only */ 624 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) 625 init_data.num_virtual_links = 1; 626 627 /* DCN42 and above dpia switch to unified link training path */ 628 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 2, 0)) { 629 init_data.flags.consolidated_dpia_dp_lt = true; 630 init_data.flags.enable_dpia_pre_training = true; 631 init_data.flags.unify_link_enc_assignment = true; 632 init_data.flags.usb4_bw_alloc_support = true; 633 } 634 635 /* DCN201 audio desyncs using DP SS */ 636 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 637 init_data.flags.ignore_dpref_ss = true; 638 639 retrieve_dmi_info(&adev->dm); 640 if (adev->dm.edp0_on_dp1_quirk) 641 init_data.flags.support_edp0_on_dp1 = true; 642 643 if (adev->dm.bb_from_dmub) 644 init_data.bb_from_dmub = adev->dm.bb_from_dmub; 645 else 646 init_data.bb_from_dmub = NULL; 647 648 /* Display Core create. */ 649 adev->dm.dc = dc_create(&init_data); 650 651 if (adev->dm.dc) { 652 drm_info(adev_to_drm(adev), "Display Core v%s initialized on %s\n", DC_VER, 653 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 654 } else { 655 drm_info(adev_to_drm(adev), "Display Core failed to initialize with v%s!\n", DC_VER); 656 goto error; 657 } 658 659 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 660 adev->dm.dc->debug.force_single_disp_pipe_split = false; 661 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 662 } 663 664 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 665 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 666 if (dm_should_disable_stutter(adev->pdev)) 667 adev->dm.dc->debug.disable_stutter = true; 668 669 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 670 adev->dm.dc->debug.disable_stutter = true; 671 672 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 673 adev->dm.dc->debug.disable_dsc = true; 674 675 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 676 adev->dm.dc->debug.disable_clock_gate = true; 677 678 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 679 adev->dm.dc->debug.force_subvp_mclk_switch = true; 680 681 if (amdgpu_dc_debug_mask & DC_DISABLE_SUBVP_FAMS) { 682 adev->dm.dc->debug.force_disable_subvp = true; 683 adev->dm.dc->debug.fams2_config.bits.enable = false; 684 } 685 686 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) { 687 adev->dm.dc->debug.using_dml2 = true; 688 adev->dm.dc->debug.using_dml21 = true; 689 } 690 691 if (amdgpu_dc_debug_mask & DC_HDCP_LC_FORCE_FW_ENABLE) 692 adev->dm.dc->debug.hdcp_lc_force_fw_enable = true; 693 694 if (amdgpu_dc_debug_mask & DC_HDCP_LC_ENABLE_SW_FALLBACK) 695 adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true; 696 697 if (amdgpu_dc_debug_mask & DC_SKIP_DETECTION_LT) 698 adev->dm.dc->debug.skip_detection_link_training = true; 699 700 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 701 702 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 703 adev->dm.dc->debug.ignore_cable_id = true; 704 705 /* temporary enable immediate restore for FAMS2 */ 706 adev->dm.dc->debug.fams2_imm_restore_drr = true; 707 708 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 709 drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n"); 710 711 r = dm_dmub_hw_init(adev); 712 if (r) { 713 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 714 goto error; 715 } 716 717 dc_hardware_init(adev->dm.dc); 718 719 /* Enable cursor offload if the ASIC supports it. */ 720 dc_dmub_srv_cursor_offload_init(adev->dm.dc); 721 722 /* GOP/vBIOS may leave an OPTC enabled for a display present at power-on 723 * but no longer driven (e.g. an external DP unplugged at boot). Such a 724 * dangling pipe keeps DCN out of idle and blocks s0i3. Power it down 725 * here when nothing needs to be preserved. 726 */ 727 if (adev->flags & AMD_IS_APU) 728 dc_disable_dangling_timing_generators(adev->dm.dc); 729 730 adev->dm.hpd_rx_offload_wq = amdgpu_dm_hpd_rx_irq_create_workqueue(adev); 731 if (!adev->dm.hpd_rx_offload_wq) { 732 drm_err(adev_to_drm(adev), "failed to create hpd rx offload workqueue.\n"); 733 goto error; 734 } 735 736 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 737 struct dc_phy_addr_space_config pa_config; 738 739 mmhub_read_system_context(adev, &pa_config); 740 741 // Call the DC init_memory func 742 dc_setup_system_context(adev->dm.dc, &pa_config); 743 } 744 745 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 746 if (!adev->dm.freesync_module) { 747 drm_err(adev_to_drm(adev), 748 "failed to initialize freesync_module.\n"); 749 } else 750 drm_dbg_driver(adev_to_drm(adev), "freesync_module init done %p.\n", 751 adev->dm.freesync_module); 752 753 amdgpu_dm_init_color_mod(); 754 755 if (adev->dm.dc->caps.max_links > 0) { 756 adev->dm.vblank_control_workqueue = 757 create_singlethread_workqueue("dm_vblank_control_workqueue"); 758 if (!adev->dm.vblank_control_workqueue) 759 drm_err(adev_to_drm(adev), "failed to initialize vblank_workqueue.\n"); 760 } 761 762 if (adev->dm.dc->caps.ips_support && 763 adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) 764 adev->dm.idle_workqueue = idle_create_workqueue(adev); 765 766 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 767 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 768 769 if (!adev->dm.hdcp_workqueue) 770 drm_err(adev_to_drm(adev), "failed to initialize hdcp_workqueue.\n"); 771 else 772 drm_dbg_driver(adev_to_drm(adev), 773 "hdcp_workqueue init done %p.\n", 774 adev->dm.hdcp_workqueue); 775 776 dc_init_callbacks(adev->dm.dc, &init_params); 777 } 778 if (adev->dm.dc->caps.max_links > 0) { 779 adev->dm.hdmi_frl_status_polling_wq = 780 create_singlethread_workqueue("hdmi_frl_status_polling_wq"); 781 if (!adev->dm.hdmi_frl_status_polling_wq) 782 drm_err(adev_to_drm(adev), "failed to initialize hdmi_frl_status_polling_wq\n"); 783 } 784 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 785 init_completion(&adev->dm.dmub_aux_transfer_done); 786 adev->dm.dmub_notify = kzalloc_obj(struct dmub_notification); 787 if (!adev->dm.dmub_notify) { 788 drm_info(adev_to_drm(adev), "fail to allocate adev->dm.dmub_notify"); 789 goto error; 790 } 791 792 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 793 if (!adev->dm.delayed_hpd_wq) { 794 drm_err(adev_to_drm(adev), "failed to create hpd offload workqueue.\n"); 795 goto error; 796 } 797 798 amdgpu_dm_outbox_init(adev); 799 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 800 dm_dmub_aux_setconfig_callback, false)) { 801 drm_err(adev_to_drm(adev), "fail to register dmub aux callback"); 802 goto error; 803 } 804 805 for (size_t i = 0; i < ARRAY_SIZE(adev->dm.fused_io); i++) 806 init_completion(&adev->dm.fused_io[i].replied); 807 808 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_FUSED_IO, 809 dm_dmub_aux_fused_io_callback, false)) { 810 drm_err(adev_to_drm(adev), "fail to register dmub fused io callback"); 811 goto error; 812 } 813 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 814 * It is expected that DMUB will resend any pending notifications at this point. Note 815 * that hpd and hpd_irq handler registration are deferred to 816 * amdgpu_dm_register_hpd_handlers() to align legacy interface initialization 817 * sequence. Connection status will be proactivly detected once in the 818 * amdgpu_dm_initialize_drm_device. 819 */ 820 dc_enable_dmub_outbox(adev->dm.dc); 821 822 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 823 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 824 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 825 } 826 827 if (amdgpu_dm_initialize_drm_device(adev)) { 828 drm_err(adev_to_drm(adev), 829 "failed to initialize sw for display support.\n"); 830 goto error; 831 } 832 833 if (amdgpu_dm_init_power_module(&adev->dm)) 834 goto error; 835 836 /* create fake encoders for MST */ 837 dm_dp_create_fake_mst_encoders(adev); 838 839 /* TODO: Add_display_info? */ 840 841 /* TODO use dynamic cursor width */ 842 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 843 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 844 845 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 846 drm_err(adev_to_drm(adev), 847 "failed to initialize vblank for display support.\n"); 848 goto error; 849 } 850 851 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 852 amdgpu_dm_crtc_secure_display_create_contexts(adev); 853 if (!adev->dm.secure_display_ctx.crtc_ctx) 854 drm_err(adev_to_drm(adev), "failed to initialize secure display contexts.\n"); 855 856 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1)) 857 adev->dm.secure_display_ctx.support_mul_roi = true; 858 859 #endif 860 861 drm_dbg_driver(adev_to_drm(adev), "KMS initialized.\n"); 862 863 return 0; 864 error: 865 amdgpu_dm_fini(adev); 866 867 return -EINVAL; 868 } 869 870 STATIC_IFN_KUNIT int amdgpu_dm_early_fini(struct amdgpu_ip_block *ip_block) 871 { 872 struct amdgpu_device *adev = ip_block->adev; 873 874 amdgpu_dm_audio_fini(adev); 875 876 return 0; 877 } 878 EXPORT_IF_KUNIT(amdgpu_dm_early_fini); 879 880 static void amdgpu_dm_fini(struct amdgpu_device *adev) 881 { 882 int i; 883 884 if (adev->dm.vblank_control_workqueue) { 885 destroy_workqueue(adev->dm.vblank_control_workqueue); 886 adev->dm.vblank_control_workqueue = NULL; 887 } 888 889 if (adev->dm.idle_workqueue) { 890 if (adev->dm.idle_workqueue->running) { 891 adev->dm.idle_workqueue->enable = false; 892 flush_work(&adev->dm.idle_workqueue->work); 893 } 894 895 kfree(adev->dm.idle_workqueue); 896 adev->dm.idle_workqueue = NULL; 897 } 898 899 /* 900 * Disable ISM before dc_destroy() invalidates dm->dc. 901 * 902 * Quiesce workers first without dc_lock (they take dc_lock 903 * themselves, so syncing under it would deadlock), then drive the 904 * FSM back to FULL_POWER_RUNNING under dc_lock. 905 */ 906 amdgpu_dm_ism_disable(&adev->dm); 907 scoped_guard(mutex, &adev->dm.dc_lock) 908 amdgpu_dm_ism_force_full_power(&adev->dm); 909 910 amdgpu_dm_destroy_drm_device(&adev->dm); 911 912 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 913 if (adev->dm.secure_display_ctx.crtc_ctx) { 914 for (i = 0; i < adev->mode_info.num_crtc; i++) { 915 if (adev->dm.secure_display_ctx.crtc_ctx[i].crtc) { 916 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].notify_ta_work); 917 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].forward_roi_work); 918 } 919 } 920 kfree(adev->dm.secure_display_ctx.crtc_ctx); 921 adev->dm.secure_display_ctx.crtc_ctx = NULL; 922 } 923 #endif 924 if (adev->dm.hdcp_workqueue) { 925 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 926 adev->dm.hdcp_workqueue = NULL; 927 } 928 929 if (adev->dm.dc) { 930 dc_deinit_callbacks(adev->dm.dc); 931 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 932 if (dc_enable_dmub_notifications(adev->dm.dc)) { 933 kfree(adev->dm.dmub_notify); 934 adev->dm.dmub_notify = NULL; 935 destroy_workqueue(adev->dm.delayed_hpd_wq); 936 adev->dm.delayed_hpd_wq = NULL; 937 } 938 } 939 940 if (adev->dm.dmub_bo) 941 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 942 &adev->dm.dmub_bo_gpu_addr, 943 &adev->dm.dmub_bo_cpu_addr); 944 945 if (adev->dm.boot_time_crc_info.bo_ptr) 946 amdgpu_bo_free_kernel(&adev->dm.boot_time_crc_info.bo_ptr, 947 &adev->dm.boot_time_crc_info.gpu_addr, 948 &adev->dm.boot_time_crc_info.cpu_addr); 949 950 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { 951 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 952 if (adev->dm.hpd_rx_offload_wq[i].wq) { 953 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 954 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 955 } 956 } 957 958 kfree(adev->dm.hpd_rx_offload_wq); 959 adev->dm.hpd_rx_offload_wq = NULL; 960 } 961 962 amdgpu_dm_irq_fini(adev); 963 964 /* DC Destroy TODO: Replace destroy DAL */ 965 if (adev->dm.dc) 966 dc_destroy(&adev->dm.dc); 967 968 if (adev->dm.cgs_device) { 969 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 970 adev->dm.cgs_device = NULL; 971 } 972 if (adev->dm.freesync_module) { 973 mod_freesync_destroy(adev->dm.freesync_module); 974 adev->dm.freesync_module = NULL; 975 } 976 977 if (adev->dm.power_module) { 978 mod_power_destroy(adev->dm.power_module); 979 adev->dm.power_module = NULL; 980 } 981 mutex_destroy(&adev->dm.audio_lock); 982 mutex_destroy(&adev->dm.dc_lock); 983 mutex_destroy(&adev->dm.dpia_aux_lock); 984 } 985 986 STATIC_IFN_KUNIT int load_dmcu_fw(struct amdgpu_device *adev) 987 { 988 const char *fw_name_dmcu = NULL; 989 int r; 990 const struct dmcu_firmware_header_v1_0 *hdr; 991 992 switch (adev->asic_type) { 993 #if defined(CONFIG_DRM_AMD_DC_SI) 994 case CHIP_TAHITI: 995 case CHIP_PITCAIRN: 996 case CHIP_VERDE: 997 case CHIP_OLAND: 998 #endif 999 case CHIP_BONAIRE: 1000 case CHIP_HAWAII: 1001 case CHIP_KAVERI: 1002 case CHIP_KABINI: 1003 case CHIP_MULLINS: 1004 case CHIP_TONGA: 1005 case CHIP_FIJI: 1006 case CHIP_CARRIZO: 1007 case CHIP_STONEY: 1008 case CHIP_POLARIS11: 1009 case CHIP_POLARIS10: 1010 case CHIP_POLARIS12: 1011 case CHIP_VEGAM: 1012 case CHIP_VEGA10: 1013 case CHIP_VEGA12: 1014 case CHIP_VEGA20: 1015 return 0; 1016 case CHIP_NAVI12: 1017 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 1018 break; 1019 case CHIP_RAVEN: 1020 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1021 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1022 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1023 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1024 else 1025 return 0; 1026 break; 1027 default: 1028 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1029 case IP_VERSION(2, 0, 2): 1030 case IP_VERSION(2, 0, 3): 1031 case IP_VERSION(2, 0, 0): 1032 case IP_VERSION(2, 1, 0): 1033 case IP_VERSION(3, 0, 0): 1034 case IP_VERSION(3, 0, 2): 1035 case IP_VERSION(3, 0, 3): 1036 case IP_VERSION(3, 0, 1): 1037 case IP_VERSION(3, 1, 2): 1038 case IP_VERSION(3, 1, 3): 1039 case IP_VERSION(3, 1, 4): 1040 case IP_VERSION(3, 1, 5): 1041 case IP_VERSION(3, 1, 6): 1042 case IP_VERSION(3, 2, 0): 1043 case IP_VERSION(3, 2, 1): 1044 case IP_VERSION(3, 5, 0): 1045 case IP_VERSION(3, 5, 1): 1046 case IP_VERSION(3, 6, 0): 1047 case IP_VERSION(4, 0, 1): 1048 case IP_VERSION(4, 2, 0): 1049 case IP_VERSION(4, 2, 1): 1050 case IP_VERSION(6, 0, 0): 1051 return 0; 1052 default: 1053 break; 1054 } 1055 drm_err(adev_to_drm(adev), "Unsupported ASIC type: 0x%X\n", adev->asic_type); 1056 return -EINVAL; 1057 } 1058 1059 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1060 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not supported on direct or SMU loading\n"); 1061 return 0; 1062 } 1063 1064 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, AMDGPU_UCODE_REQUIRED, 1065 "%s", fw_name_dmcu); 1066 if (r == -ENODEV) { 1067 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 1068 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not found\n"); 1069 adev->dm.fw_dmcu = NULL; 1070 return 0; 1071 } 1072 if (r) { 1073 drm_err(adev_to_drm(adev), "amdgpu_dm: Can't validate firmware \"%s\"\n", 1074 fw_name_dmcu); 1075 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1076 return r; 1077 } 1078 1079 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 1080 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 1081 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 1082 adev->firmware.fw_size += 1083 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1084 1085 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 1086 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 1087 adev->firmware.fw_size += 1088 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1089 1090 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 1091 1092 drm_dbg_kms(adev_to_drm(adev), "PSP loading DMCU firmware\n"); 1093 1094 return 0; 1095 } 1096 EXPORT_IF_KUNIT(load_dmcu_fw); 1097 1098 STATIC_IFN_KUNIT int dm_sw_init(struct amdgpu_ip_block *ip_block) 1099 { 1100 struct amdgpu_device *adev = ip_block->adev; 1101 int r; 1102 1103 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1104 1105 if (!adev->dm.cgs_device) { 1106 drm_err(adev_to_drm(adev), "failed to create cgs device.\n"); 1107 return -EINVAL; 1108 } 1109 1110 /* Moved from dm init since we need to use allocations for storing bounding box data */ 1111 INIT_LIST_HEAD(&adev->dm.da_list); 1112 1113 r = dm_dmub_sw_init(adev); 1114 if (r) 1115 return r; 1116 1117 return load_dmcu_fw(adev); 1118 } 1119 EXPORT_IF_KUNIT(dm_sw_init); 1120 1121 STATIC_IFN_KUNIT int dm_sw_fini(struct amdgpu_ip_block *ip_block) 1122 { 1123 struct amdgpu_device *adev = ip_block->adev; 1124 struct dal_allocation *da; 1125 1126 list_for_each_entry(da, &adev->dm.da_list, list) { 1127 if (adev->dm.bb_from_dmub == (void *) da->cpu_ptr) { 1128 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1129 list_del(&da->list); 1130 kfree(da); 1131 adev->dm.bb_from_dmub = NULL; 1132 break; 1133 } 1134 } 1135 1136 1137 kfree(adev->dm.dmub_fb_info); 1138 adev->dm.dmub_fb_info = NULL; 1139 1140 if (adev->dm.dmub_srv) { 1141 dmub_srv_destroy(adev->dm.dmub_srv); 1142 kfree(adev->dm.dmub_srv); 1143 adev->dm.dmub_srv = NULL; 1144 } 1145 1146 amdgpu_ucode_release(&adev->dm.dmub_fw); 1147 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1148 1149 return 0; 1150 } 1151 EXPORT_IF_KUNIT(dm_sw_fini); 1152 1153 1154 static void amdgpu_dm_boot_time_crc_init(struct amdgpu_device *adev) 1155 { 1156 struct dm_boot_time_crc_info *bootcrc_info = NULL; 1157 struct dmub_srv *dmub = NULL; 1158 union dmub_fw_boot_options option = {0}; 1159 int ret = 0; 1160 const uint32_t fb_size = 3 * 1024 * 1024; /* 3MB for DCC pattern */ 1161 1162 if (!adev || !adev->dm.dc || !adev->dm.dc->ctx || 1163 !adev->dm.dc->ctx->dmub_srv) { 1164 return; 1165 } 1166 1167 dmub = adev->dm.dc->ctx->dmub_srv->dmub; 1168 bootcrc_info = &adev->dm.boot_time_crc_info; 1169 1170 if (!dmub || !dmub->hw_funcs.get_fw_boot_option) { 1171 drm_dbg(adev_to_drm(adev), "failed to init boot time crc buffer\n"); 1172 return; 1173 } 1174 1175 option = dmub->hw_funcs.get_fw_boot_option(dmub); 1176 1177 /* Return if boot time CRC is not enabled */ 1178 if (option.bits.bootcrc_en_at_S0i3 == 0) 1179 return; 1180 1181 /* Create a buffer for boot time CRC */ 1182 ret = amdgpu_bo_create_kernel(adev, fb_size, PAGE_SIZE, 1183 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT, 1184 &bootcrc_info->bo_ptr, 1185 &bootcrc_info->gpu_addr, 1186 &bootcrc_info->cpu_addr); 1187 1188 if (ret) { 1189 drm_dbg(adev_to_drm(adev), "failed to create boot time crc buffer\n"); 1190 } else { 1191 bootcrc_info->size = fb_size; 1192 1193 drm_dbg(adev_to_drm(adev), "boot time crc buffer created addr 0x%llx, size %u\n", 1194 bootcrc_info->gpu_addr, bootcrc_info->size); 1195 1196 /* Send the buffer info to DMUB */ 1197 dc_dmub_srv_boot_time_crc_init(adev->dm.dc, 1198 bootcrc_info->gpu_addr, bootcrc_info->size); 1199 } 1200 } 1201 1202 STATIC_IFN_KUNIT int dm_late_init(struct amdgpu_ip_block *ip_block) 1203 { 1204 struct amdgpu_device *adev = ip_block->adev; 1205 1206 struct dmcu_iram_parameters params; 1207 unsigned int linear_lut[16]; 1208 int i; 1209 struct dmcu *dmcu = NULL; 1210 1211 dmcu = adev->dm.dc->res_pool->dmcu; 1212 1213 /* Init the boot time CRC (skip in resume) */ 1214 if ((adev->in_suspend == 0) && 1215 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 6, 0))) 1216 amdgpu_dm_boot_time_crc_init(adev); 1217 1218 for (i = 0; i < 16; i++) 1219 linear_lut[i] = 0xFFFF * i / 15; 1220 1221 params.set = 0; 1222 params.backlight_ramping_override = false; 1223 params.backlight_ramping_start = 0xCCCC; 1224 params.backlight_ramping_reduction = 0xCCCCCCCC; 1225 params.backlight_lut_array_size = 16; 1226 params.backlight_lut_array = linear_lut; 1227 1228 /* Min backlight level after ABM reduction, Don't allow below 1% 1229 * 0xFFFF x 0.01 = 0x28F 1230 */ 1231 params.min_abm_backlight = 0x28F; 1232 /* In the case where abm is implemented on dmcub, 1233 * dmcu object will be null. 1234 * ABM 2.4 and up are implemented on dmcub. 1235 */ 1236 if (dmcu) { 1237 if (!dmcu_load_iram(dmcu, params)) 1238 return -EINVAL; 1239 } else if (adev->dm.dc->ctx->dmub_srv) { 1240 struct dc_link *edp_links[MAX_NUM_EDP]; 1241 int edp_num; 1242 1243 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 1244 for (i = 0; i < edp_num; i++) { 1245 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 1246 return -EINVAL; 1247 } 1248 } 1249 1250 return amdgpu_dm_detect_mst_link_for_all_connectors(adev_to_drm(adev)); 1251 } 1252 EXPORT_IF_KUNIT(dm_late_init); 1253 1254 STATIC_IFN_KUNIT void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 1255 { 1256 u8 buf[UUID_SIZE]; 1257 guid_t guid; 1258 int ret; 1259 1260 mutex_lock(&mgr->lock); 1261 if (!mgr->mst_primary) 1262 goto out_fail; 1263 1264 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 1265 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1266 goto out_fail; 1267 } 1268 1269 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 1270 DP_MST_EN | 1271 DP_UP_REQ_EN | 1272 DP_UPSTREAM_IS_SRC); 1273 if (ret < 0) { 1274 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 1275 goto out_fail; 1276 } 1277 1278 /* Some hubs forget their guids after they resume */ 1279 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf)); 1280 if (ret != sizeof(buf)) { 1281 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1282 goto out_fail; 1283 } 1284 1285 import_guid(&guid, buf); 1286 1287 if (guid_is_null(&guid)) { 1288 guid_gen(&guid); 1289 export_guid(buf, &guid); 1290 1291 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf)); 1292 1293 if (ret != sizeof(buf)) { 1294 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 1295 goto out_fail; 1296 } 1297 } 1298 1299 guid_copy(&mgr->mst_primary->guid, &guid); 1300 1301 out_fail: 1302 mutex_unlock(&mgr->lock); 1303 } 1304 EXPORT_IF_KUNIT(resume_mst_branch_status); 1305 1306 STATIC_IFN_KUNIT void s3_handle_mst(struct drm_device *dev, bool suspend) 1307 { 1308 struct amdgpu_dm_connector *aconnector; 1309 struct drm_connector *connector; 1310 struct drm_connector_list_iter iter; 1311 struct drm_dp_mst_topology_mgr *mgr; 1312 1313 drm_connector_list_iter_begin(dev, &iter); 1314 drm_for_each_connector_iter(connector, &iter) { 1315 1316 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1317 continue; 1318 1319 aconnector = to_amdgpu_dm_connector(connector); 1320 if (aconnector->dc_link->type != dc_connection_mst_branch || 1321 aconnector->mst_root) 1322 continue; 1323 1324 mgr = &aconnector->mst_mgr; 1325 1326 if (suspend) { 1327 drm_dp_mst_topology_mgr_suspend(mgr); 1328 } else { 1329 /* if extended timeout is supported in hardware, 1330 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 1331 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 1332 */ 1333 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 1334 if (!dp_is_lttpr_present(aconnector->dc_link)) 1335 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 1336 1337 /* TODO: move resume_mst_branch_status() into drm mst resume again 1338 * once topology probing work is pulled out from mst resume into mst 1339 * resume 2nd step. mst resume 2nd step should be called after old 1340 * state getting restored (i.e. drm_atomic_helper_resume()). 1341 */ 1342 resume_mst_branch_status(mgr); 1343 } 1344 } 1345 drm_connector_list_iter_end(&iter); 1346 } 1347 EXPORT_IF_KUNIT(s3_handle_mst); 1348 1349 STATIC_IFN_KUNIT int dm_oem_i2c_hw_init(struct amdgpu_device *adev) 1350 { 1351 struct amdgpu_display_manager *dm = &adev->dm; 1352 struct amdgpu_i2c_adapter *oem_i2c; 1353 struct ddc_service *oem_ddc_service; 1354 int r; 1355 1356 oem_ddc_service = dc_get_oem_i2c_device(adev->dm.dc); 1357 if (oem_ddc_service) { 1358 oem_i2c = amdgpu_dm_create_i2c(oem_ddc_service, true); 1359 if (!oem_i2c) { 1360 drm_info(adev_to_drm(adev), "Failed to create oem i2c adapter data\n"); 1361 return -ENOMEM; 1362 } 1363 1364 r = devm_i2c_add_adapter(adev->dev, &oem_i2c->base); 1365 if (r) { 1366 drm_info(adev_to_drm(adev), "Failed to register oem i2c\n"); 1367 kfree(oem_i2c); 1368 return r; 1369 } 1370 dm->oem_i2c = oem_i2c; 1371 } 1372 1373 return 0; 1374 } 1375 EXPORT_IF_KUNIT(dm_oem_i2c_hw_init); 1376 1377 /** 1378 * dm_hw_init() - Initialize DC device 1379 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1380 * 1381 * Initialize the &struct amdgpu_display_manager device. This involves calling 1382 * the initializers of each DM component, then populating the struct with them. 1383 * 1384 * Although the function implies hardware initialization, both hardware and 1385 * software are initialized here. Splitting them out to their relevant init 1386 * hooks is a future TODO item. 1387 * 1388 * Some notable things that are initialized here: 1389 * 1390 * - Display Core, both software and hardware 1391 * - DC modules that we need (freesync and color management) 1392 * - DRM software states 1393 * - Interrupt sources and handlers 1394 * - Vblank support 1395 * - Debug FS entries, if enabled 1396 */ 1397 static int dm_hw_init(struct amdgpu_ip_block *ip_block) 1398 { 1399 struct amdgpu_device *adev = ip_block->adev; 1400 int r; 1401 1402 adev->dm.i2c_devres_group = devres_open_group(adev->dev, NULL, GFP_KERNEL); 1403 if (!adev->dm.i2c_devres_group) 1404 return -ENOMEM; 1405 1406 /* Create DAL display manager */ 1407 r = amdgpu_dm_init(adev); 1408 if (r) 1409 goto err_release_i2c; 1410 amdgpu_dm_hpd_init(adev); 1411 1412 r = dm_oem_i2c_hw_init(adev); 1413 if (r) 1414 drm_info(adev_to_drm(adev), "Failed to add OEM i2c bus\n"); 1415 1416 devres_close_group(adev->dev, adev->dm.i2c_devres_group); 1417 return 0; 1418 1419 err_release_i2c: 1420 devres_release_group(adev->dev, adev->dm.i2c_devres_group); 1421 return r; 1422 } 1423 1424 /** 1425 * dm_hw_fini() - Teardown DC device 1426 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1427 * 1428 * Teardown components within &struct amdgpu_display_manager that require 1429 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 1430 * were loaded. Also flush IRQ workqueues and disable them. 1431 */ 1432 static int dm_hw_fini(struct amdgpu_ip_block *ip_block) 1433 { 1434 struct amdgpu_device *adev = ip_block->adev; 1435 1436 if (adev->dm.i2c_devres_group) 1437 devres_release_group(adev->dev, adev->dm.i2c_devres_group); 1438 1439 amdgpu_dm_hpd_fini(adev); 1440 1441 amdgpu_dm_fini(adev); 1442 return 0; 1443 } 1444 1445 1446 STATIC_IFN_KUNIT void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 1447 struct dc_state *state, bool enable) 1448 { 1449 enum dc_irq_source irq_source; 1450 struct amdgpu_crtc *acrtc; 1451 int rc = -EBUSY; 1452 int i = 0; 1453 1454 for (i = 0; i < state->stream_count; i++) { 1455 acrtc = amdgpu_dm_get_crtc_by_otg_inst( 1456 adev, state->stream_status[i].primary_otg_inst); 1457 1458 if (acrtc && state->stream_status[i].plane_count != 0 && 1459 amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { 1460 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 1461 rc = amdgpu_dm_irq_set(adev, irq_source, enable) ? 0 : -EBUSY; 1462 if (rc) 1463 drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n", 1464 enable ? "enable" : "disable"); 1465 1466 if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) { 1467 if (enable) { 1468 if (amdgpu_dm_crtc_vrr_active( 1469 to_dm_crtc_state(acrtc->base.state))) 1470 rc = amdgpu_dm_crtc_set_vupdate_irq( 1471 &acrtc->base, true); 1472 } else 1473 rc = amdgpu_dm_crtc_set_vupdate_irq( 1474 &acrtc->base, false); 1475 1476 if (rc) 1477 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", 1478 enable ? "en" : "dis"); 1479 } 1480 1481 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 1482 /* During gpu-reset we disable and then enable vblank irq, so 1483 * don't use amdgpu_irq_get/put() to avoid refcount change. 1484 */ 1485 if (!amdgpu_dm_irq_set(adev, irq_source, enable)) 1486 drm_warn(adev_to_drm(adev), "Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 1487 1488 } else if (acrtc && state->stream_status[i].plane_count != 0) { 1489 /* DCN only needs to toggle VUPDATE_NO_LOCK */ 1490 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, enable); 1491 if (rc) 1492 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", 1493 enable ? "en" : "dis"); 1494 } 1495 } 1496 1497 } 1498 EXPORT_IF_KUNIT(dm_gpureset_toggle_interrupts); 1499 1500 DEFINE_FREE(state_release, struct dc_state *, dc_state_release(_T)) 1501 1502 STATIC_IFN_KUNIT enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 1503 { 1504 struct dc_state *context __free(state_release) = NULL; 1505 int i; 1506 struct dc_stream_state *del_streams[MAX_PIPES]; 1507 int del_streams_count = 0; 1508 struct dc_commit_streams_params params = {}; 1509 1510 memset(del_streams, 0, sizeof(del_streams)); 1511 1512 context = dc_state_create_current_copy(dc); 1513 if (context == NULL) 1514 return DC_ERROR_UNEXPECTED; 1515 1516 /* First remove from context all streams */ 1517 for (i = 0; i < context->stream_count; i++) { 1518 struct dc_stream_state *stream = context->streams[i]; 1519 1520 del_streams[del_streams_count++] = stream; 1521 } 1522 1523 /* Remove all planes for removed streams and then remove the streams */ 1524 for (i = 0; i < del_streams_count; i++) { 1525 enum dc_status res; 1526 1527 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) 1528 return DC_FAIL_DETACH_SURFACES; 1529 1530 res = dc_state_remove_stream(dc, context, del_streams[i]); 1531 if (res != DC_OK) 1532 return res; 1533 } 1534 1535 params.streams = context->streams; 1536 params.stream_count = context->stream_count; 1537 1538 return dc_commit_streams(dc, ¶ms); 1539 } 1540 EXPORT_IF_KUNIT(amdgpu_dm_commit_zero_streams); 1541 1542 STATIC_IFN_KUNIT int dm_cache_state(struct amdgpu_device *adev) 1543 { 1544 int r; 1545 1546 adev->dm.cached_state = dm_atomic_helper_suspend(adev_to_drm(adev)); 1547 if (IS_ERR(adev->dm.cached_state)) { 1548 r = PTR_ERR(adev->dm.cached_state); 1549 adev->dm.cached_state = NULL; 1550 } 1551 1552 return adev->dm.cached_state ? 0 : r; 1553 } 1554 EXPORT_IF_KUNIT(dm_cache_state); 1555 1556 STATIC_IFN_KUNIT void dm_destroy_cached_state(struct amdgpu_device *adev) 1557 { 1558 struct amdgpu_display_manager *dm = &adev->dm; 1559 struct drm_device *ddev = adev_to_drm(adev); 1560 struct dm_plane_state *dm_new_plane_state; 1561 struct drm_plane_state *new_plane_state; 1562 struct dm_crtc_state *dm_new_crtc_state; 1563 struct drm_crtc_state *new_crtc_state; 1564 struct drm_plane *plane; 1565 struct drm_crtc *crtc; 1566 int i; 1567 1568 if (!dm->cached_state) 1569 return; 1570 1571 /* Force mode set in atomic commit */ 1572 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1573 new_crtc_state->active_changed = true; 1574 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1575 amdgpu_dm_reset_freesync_config_for_crtc(dm_new_crtc_state); 1576 } 1577 1578 /* 1579 * atomic_check is expected to create the dc states. We need to release 1580 * them here, since they were duplicated as part of the suspend 1581 * procedure. 1582 */ 1583 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1584 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1585 if (dm_new_crtc_state->stream) { 1586 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 1587 dc_stream_release(dm_new_crtc_state->stream); 1588 dm_new_crtc_state->stream = NULL; 1589 } 1590 dm_new_crtc_state->base.color_mgmt_changed = true; 1591 } 1592 1593 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 1594 dm_new_plane_state = to_dm_plane_state(new_plane_state); 1595 if (dm_new_plane_state->dc_state) { 1596 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 1597 dc_plane_state_release(dm_new_plane_state->dc_state); 1598 dm_new_plane_state->dc_state = NULL; 1599 } 1600 } 1601 1602 drm_atomic_helper_resume(ddev, dm->cached_state); 1603 1604 dm->cached_state = NULL; 1605 } 1606 EXPORT_IF_KUNIT(dm_destroy_cached_state); 1607 1608 static int dm_suspend(struct amdgpu_ip_block *ip_block) 1609 { 1610 struct amdgpu_device *adev = ip_block->adev; 1611 struct amdgpu_display_manager *dm = &adev->dm; 1612 1613 if (amdgpu_in_reset(adev)) { 1614 enum dc_status res; 1615 1616 /* Quiesce ISM workers before taking dc_lock (workers take 1617 * dc_lock themselves; syncing under it would deadlock). 1618 */ 1619 amdgpu_dm_ism_disable(dm); 1620 1621 mutex_lock(&dm->dc_lock); 1622 1623 amdgpu_dm_ism_force_full_power(dm); 1624 dc_allow_idle_optimizations(adev->dm.dc, false); 1625 1626 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); 1627 if (!dm->cached_dc_state) { 1628 drm_err(adev_to_drm(adev), 1629 "Failed to allocate cached DC state during suspend\n"); 1630 mutex_unlock(&dm->dc_lock); 1631 return -ENOMEM; 1632 } 1633 1634 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 1635 1636 res = amdgpu_dm_commit_zero_streams(dm->dc); 1637 if (res != DC_OK) { 1638 drm_err(adev_to_drm(adev), "Failed to commit zero streams: %d\n", res); 1639 dc_state_release(dm->cached_dc_state); 1640 dm->cached_dc_state = NULL; 1641 mutex_unlock(&dm->dc_lock); 1642 return -EINVAL; 1643 } 1644 1645 amdgpu_dm_irq_suspend(adev); 1646 1647 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1648 1649 return 0; 1650 } 1651 1652 if (!adev->dm.cached_state) { 1653 int r = dm_cache_state(adev); 1654 1655 if (r) 1656 return r; 1657 } 1658 1659 amdgpu_dm_s3_handle_hdmi_cec(adev_to_drm(adev), true); 1660 1661 s3_handle_mst(adev_to_drm(adev), true); 1662 1663 amdgpu_dm_irq_suspend(adev); 1664 1665 /* 1666 * Quiesce ISM workers before taking dc_lock (workers take dc_lock 1667 * themselves; syncing under it would deadlock). 1668 */ 1669 amdgpu_dm_ism_disable(dm); 1670 scoped_guard(mutex, &dm->dc_lock) 1671 amdgpu_dm_ism_force_full_power(dm); 1672 1673 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1674 1675 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 1676 1677 if (dm->dc->caps.ips_support && adev->in_s0ix) 1678 dc_allow_idle_optimizations(dm->dc, true); 1679 1680 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); 1681 1682 return 0; 1683 } 1684 1685 void amdgpu_dm_emulated_link_detect(struct dc_link *link) 1686 { 1687 struct dc_sink_init_data sink_init_data = { 0 }; 1688 struct display_sink_capability sink_caps = { 0 }; 1689 enum dc_edid_status edid_status; 1690 struct dc_context *dc_ctx = link->ctx; 1691 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); 1692 struct dc_sink *sink = NULL; 1693 struct dc_sink *prev_sink = NULL; 1694 1695 link->type = dc_connection_none; 1696 prev_sink = link->local_sink; 1697 1698 if (prev_sink) 1699 dc_sink_release(prev_sink); 1700 1701 switch (link->connector_signal) { 1702 case SIGNAL_TYPE_HDMI_TYPE_A: { 1703 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1704 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1705 break; 1706 } 1707 1708 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 1709 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1710 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1711 break; 1712 } 1713 1714 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1715 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1716 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1717 break; 1718 } 1719 1720 case SIGNAL_TYPE_LVDS: { 1721 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1722 sink_caps.signal = SIGNAL_TYPE_LVDS; 1723 break; 1724 } 1725 1726 case SIGNAL_TYPE_EDP: { 1727 sink_caps.transaction_type = 1728 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1729 sink_caps.signal = SIGNAL_TYPE_EDP; 1730 break; 1731 } 1732 1733 case SIGNAL_TYPE_DISPLAY_PORT: { 1734 sink_caps.transaction_type = 1735 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1736 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 1737 break; 1738 } 1739 1740 default: 1741 drm_err(dev, "Invalid connector type! signal:%d\n", 1742 link->connector_signal); 1743 return; 1744 } 1745 1746 sink_init_data.link = link; 1747 sink_init_data.sink_signal = sink_caps.signal; 1748 1749 sink = dc_sink_create(&sink_init_data); 1750 if (!sink) { 1751 drm_err(dev, "Failed to create sink!\n"); 1752 return; 1753 } 1754 1755 /* dc_sink_create returns a new reference */ 1756 link->local_sink = sink; 1757 1758 edid_status = dm_helpers_read_local_edid( 1759 link->ctx, 1760 link, 1761 sink); 1762 1763 if (edid_status != EDID_OK) 1764 drm_err(dev, "Failed to read EDID\n"); 1765 1766 } 1767 EXPORT_IF_KUNIT(amdgpu_dm_emulated_link_detect); 1768 1769 STATIC_IFN_KUNIT void dm_gpureset_commit_state(struct dc_state *dc_state, 1770 struct amdgpu_display_manager *dm) 1771 { 1772 struct { 1773 struct dc_surface_update surface_updates[MAX_SURFACES]; 1774 struct dc_plane_info plane_infos[MAX_SURFACES]; 1775 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 1776 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 1777 struct dc_stream_update stream_update; 1778 } *bundle __free(kfree); 1779 int k, m; 1780 1781 bundle = kzalloc_obj(*bundle); 1782 1783 if (!bundle) { 1784 drm_err(dm->ddev, "Failed to allocate update bundle\n"); 1785 return; 1786 } 1787 1788 for (k = 0; k < dc_state->stream_count; k++) { 1789 bundle->stream_update.stream = dc_state->streams[k]; 1790 1791 for (m = 0; m < dc_state->stream_status[k].plane_count; m++) { 1792 bundle->surface_updates[m].surface = 1793 dc_state->stream_status[k].plane_states[m]; 1794 bundle->surface_updates[m].surface->force_full_update = 1795 true; 1796 } 1797 1798 update_planes_and_stream_adapter(dm->dc, 1799 dc_state->stream_status[k].plane_count, 1800 dc_state->streams[k], 1801 &bundle->stream_update, 1802 bundle->surface_updates); 1803 } 1804 } 1805 EXPORT_IF_KUNIT(dm_gpureset_commit_state); 1806 1807 void amdgpu_dm_apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev, 1808 struct dc_sink *sink) 1809 { 1810 struct dc_panel_patch *ppatch = NULL; 1811 1812 if (!sink) 1813 return; 1814 1815 ppatch = &sink->edid_caps.panel_patch; 1816 if (ppatch->wait_after_dpcd_poweroff_ms) { 1817 msleep(ppatch->wait_after_dpcd_poweroff_ms); 1818 drm_dbg_driver(adev_to_drm(adev), 1819 "%s: adding a %ds delay as w/a for panel\n", 1820 __func__, 1821 ppatch->wait_after_dpcd_poweroff_ms / 1000); 1822 } 1823 } 1824 EXPORT_IF_KUNIT(amdgpu_dm_apply_delay_after_dpcd_poweroff); 1825 1826 /** 1827 * amdgpu_dm_dump_links_and_sinks - Debug dump of all DC links and their sinks 1828 * @adev: amdgpu device pointer 1829 * 1830 * Iterates through all DC links and dumps information about local and remote 1831 * (MST) sinks. Should be called after connector detection is complete to see 1832 * the final state of all links. 1833 */ 1834 STATIC_IFN_KUNIT void amdgpu_dm_dump_links_and_sinks(struct amdgpu_device *adev) 1835 { 1836 struct dc *dc = adev->dm.dc; 1837 struct drm_device *dev = adev_to_drm(adev); 1838 int li; 1839 1840 if (!dc) 1841 return; 1842 1843 for (li = 0; li < dc->link_count; li++) { 1844 struct dc_link *l = dc->links[li]; 1845 const char *name = NULL; 1846 int rs; 1847 1848 if (!l) 1849 continue; 1850 if (l->local_sink && l->local_sink->edid_caps.display_name[0]) 1851 name = l->local_sink->edid_caps.display_name; 1852 else 1853 name = "n/a"; 1854 1855 drm_dbg_kms(dev, 1856 "LINK_DUMP[%d]: local_sink=%p type=%d sink_signal=%d sink_count=%u edid_name=%s mst_capable=%d mst_alloc_streams=%d\n", 1857 li, 1858 l->local_sink, 1859 l->type, 1860 l->local_sink ? l->local_sink->sink_signal : SIGNAL_TYPE_NONE, 1861 l->sink_count, 1862 name, 1863 l->dpcd_caps.is_mst_capable, 1864 l->mst_stream_alloc_table.stream_count); 1865 1866 /* Dump remote (MST) sinks if any */ 1867 for (rs = 0; rs < l->sink_count; rs++) { 1868 struct dc_sink *rsink = l->remote_sinks[rs]; 1869 const char *rname = NULL; 1870 1871 if (!rsink) 1872 continue; 1873 if (rsink->edid_caps.display_name[0]) 1874 rname = rsink->edid_caps.display_name; 1875 else 1876 rname = "n/a"; 1877 drm_dbg_kms(dev, 1878 " REMOTE_SINK[%d:%d]: sink=%p signal=%d edid_name=%s\n", 1879 li, rs, 1880 rsink, 1881 rsink->sink_signal, 1882 rname); 1883 } 1884 } 1885 } 1886 EXPORT_IF_KUNIT(amdgpu_dm_dump_links_and_sinks); 1887 1888 static int dm_resume(struct amdgpu_ip_block *ip_block) 1889 { 1890 struct amdgpu_device *adev = ip_block->adev; 1891 struct drm_device *ddev = adev_to_drm(adev); 1892 struct amdgpu_display_manager *dm = &adev->dm; 1893 struct amdgpu_dm_connector *aconnector; 1894 struct drm_connector *connector; 1895 struct drm_connector_list_iter iter; 1896 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 1897 enum dc_connection_type new_connection_type = dc_connection_none; 1898 struct dc_state *dc_state; 1899 int i, r, j; 1900 struct dc_commit_streams_params commit_params = {}; 1901 1902 if (dm->dc->caps.ips_support) { 1903 if (!amdgpu_in_reset(adev)) 1904 mutex_lock(&dm->dc_lock); 1905 1906 /* Need to set POWER_STATE_D0 first or it will not execute 1907 * idle_power_optimizations command to DMUB. 1908 */ 1909 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 1910 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); 1911 1912 if (!amdgpu_in_reset(adev)) 1913 mutex_unlock(&dm->dc_lock); 1914 } 1915 1916 if (amdgpu_in_reset(adev)) { 1917 dc_state = dm->cached_dc_state; 1918 1919 /* 1920 * The dc->current_state is backed up into dm->cached_dc_state 1921 * before we commit 0 streams. 1922 * 1923 * DC will clear link encoder assignments on the real state 1924 * but the changes won't propagate over to the copy we made 1925 * before the 0 streams commit. 1926 * 1927 * DC expects that link encoder assignments are *not* valid 1928 * when committing a state, so as a workaround we can copy 1929 * off of the current state. 1930 * 1931 * We lose the previous assignments, but we had already 1932 * commit 0 streams anyway. 1933 */ 1934 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 1935 1936 r = dm_dmub_hw_init(adev); 1937 if (r) { 1938 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 1939 dc_state_release(dm->cached_dc_state); 1940 dm->cached_dc_state = NULL; 1941 mutex_unlock(&dm->dc_lock); 1942 return r; 1943 } 1944 1945 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 1946 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 1947 1948 dc_resume(dm->dc); 1949 1950 amdgpu_dm_ism_enable(dm); 1951 amdgpu_dm_irq_resume_early(adev); 1952 1953 for (i = 0; i < dc_state->stream_count; i++) { 1954 dc_state->streams[i]->mode_changed = true; 1955 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 1956 dc_pipe_update_bits_set_full(&dc_state->stream_status[i].plane_states[j]->update_bits); 1957 } 1958 } 1959 1960 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1961 amdgpu_dm_outbox_init(adev); 1962 dc_enable_dmub_outbox(adev->dm.dc); 1963 } 1964 1965 commit_params.streams = dc_state->streams; 1966 commit_params.stream_count = dc_state->stream_count; 1967 dc_exit_ips_for_hw_access(dm->dc); 1968 WARN_ON(!dc_commit_streams(dm->dc, &commit_params)); 1969 1970 dm_gpureset_commit_state(dm->cached_dc_state, dm); 1971 1972 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 1973 1974 dc_state_release(dm->cached_dc_state); 1975 dm->cached_dc_state = NULL; 1976 1977 amdgpu_dm_irq_resume_late(adev); 1978 1979 mutex_unlock(&dm->dc_lock); 1980 1981 /* set the backlight after a reset */ 1982 for (i = 0; i < dm->num_of_edps; i++) { 1983 if (dm->backlight_dev[i]) 1984 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 1985 } 1986 1987 return 0; 1988 } 1989 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 1990 dc_state_release(dm_state->context); 1991 dm_state->context = dc_state_create(dm->dc, NULL); 1992 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 1993 1994 /* Before powering on DC we need to re-initialize DMUB. */ 1995 dm_dmub_hw_resume(adev); 1996 1997 /* Re-enable outbox interrupts for DPIA. */ 1998 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1999 amdgpu_dm_outbox_init(adev); 2000 dc_enable_dmub_outbox(adev->dm.dc); 2001 } 2002 2003 /* power on hardware */ 2004 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 2005 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2006 2007 /* program HPD filter */ 2008 dc_resume(dm->dc); 2009 2010 scoped_guard(mutex, &dm->dc_lock) 2011 amdgpu_dm_ism_enable(dm); 2012 2013 /* 2014 * early enable HPD Rx IRQ, should be done before set mode as short 2015 * pulse interrupts are used for MST 2016 */ 2017 amdgpu_dm_irq_resume_early(adev); 2018 2019 amdgpu_dm_s3_handle_hdmi_cec(ddev, false); 2020 2021 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 2022 s3_handle_mst(ddev, false); 2023 2024 /* Exit IPS before the detection loop's first AUX/DDC access. */ 2025 scoped_guard(mutex, &dm->dc_lock) 2026 dc_exit_ips_for_hw_access(dm->dc); 2027 2028 /* Do detection*/ 2029 drm_connector_list_iter_begin(ddev, &iter); 2030 drm_for_each_connector_iter(connector, &iter) { 2031 bool ret; 2032 2033 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2034 continue; 2035 2036 aconnector = to_amdgpu_dm_connector(connector); 2037 2038 if (!aconnector->dc_link) 2039 continue; 2040 2041 /* 2042 * this is the case when traversing through already created end sink 2043 * MST connectors, should be skipped 2044 */ 2045 if (aconnector->mst_root) 2046 continue; 2047 2048 /* Skip eDP detection, when there is no sink present */ 2049 if (aconnector->dc_link->connector_signal == SIGNAL_TYPE_EDP && 2050 !aconnector->dc_link->edp_sink_present) 2051 continue; 2052 2053 guard(mutex)(&aconnector->hpd_lock); 2054 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 2055 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 2056 2057 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2058 amdgpu_dm_emulated_link_detect(aconnector->dc_link); 2059 } else { 2060 guard(mutex)(&dm->dc_lock); 2061 dc_exit_ips_for_hw_access(dm->dc); 2062 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4); 2063 if (ret) { 2064 /* w/a delay for certain panels */ 2065 amdgpu_dm_apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink); 2066 } 2067 } 2068 2069 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2070 aconnector->fake_enable = false; 2071 2072 if (aconnector->dc_sink) 2073 dc_sink_release(aconnector->dc_sink); 2074 aconnector->dc_sink = NULL; 2075 amdgpu_dm_update_connector_after_detect(aconnector); 2076 } 2077 drm_connector_list_iter_end(&iter); 2078 2079 dm_destroy_cached_state(adev); 2080 2081 /* Do mst topology probing after resuming cached state*/ 2082 drm_connector_list_iter_begin(ddev, &iter); 2083 drm_for_each_connector_iter(connector, &iter) { 2084 bool init = false; 2085 2086 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2087 continue; 2088 2089 aconnector = to_amdgpu_dm_connector(connector); 2090 if (aconnector->dc_link->type != dc_connection_mst_branch || 2091 aconnector->mst_root) 2092 continue; 2093 2094 scoped_guard(mutex, &aconnector->mst_mgr.lock) { 2095 init = !aconnector->mst_mgr.mst_primary; 2096 } 2097 if (init) 2098 dm_helpers_dp_mst_start_top_mgr(aconnector->dc_link->ctx, 2099 aconnector->dc_link, false); 2100 else 2101 drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); 2102 } 2103 drm_connector_list_iter_end(&iter); 2104 2105 /* Debug dump: list all DC links and their associated sinks after detection 2106 * is complete for all connectors. This provides a comprehensive view of the 2107 * final state without repeating the dump for each connector. 2108 */ 2109 amdgpu_dm_dump_links_and_sinks(adev); 2110 2111 amdgpu_dm_irq_resume_late(adev); 2112 2113 amdgpu_dm_smu_write_watermarks_table(adev); 2114 2115 drm_kms_helper_hotplug_event(ddev); 2116 2117 return 0; 2118 } 2119 2120 /** 2121 * DOC: DM Lifecycle 2122 * 2123 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 2124 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 2125 * the base driver's device list to be initialized and torn down accordingly. 2126 * 2127 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 2128 */ 2129 2130 static const struct amd_ip_funcs amdgpu_dm_funcs = { 2131 .name = "dm", 2132 .early_init = dm_early_init, 2133 .late_init = dm_late_init, 2134 .sw_init = dm_sw_init, 2135 .sw_fini = dm_sw_fini, 2136 .early_fini = amdgpu_dm_early_fini, 2137 .hw_init = dm_hw_init, 2138 .hw_fini = dm_hw_fini, 2139 .suspend = dm_suspend, 2140 .resume = dm_resume, 2141 .wait_for_idle = dm_wait_for_idle, 2142 .set_clockgating_state = dm_set_clockgating_state, 2143 .set_powergating_state = dm_set_powergating_state, 2144 }; 2145 2146 const struct amdgpu_ip_block_version dm_ip_block = { 2147 .type = AMD_IP_BLOCK_TYPE_DCE, 2148 .major = 1, 2149 .minor = 0, 2150 .rev = 0, 2151 .funcs = &amdgpu_dm_funcs, 2152 }; 2153 2154 2155 /** 2156 * DOC: atomic 2157 * 2158 * *WIP* 2159 */ 2160 2161 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 2162 .fb_create = amdgpu_display_user_framebuffer_create, 2163 .get_format_info = amdgpu_dm_plane_get_format_info, 2164 .atomic_check = amdgpu_dm_atomic_check, 2165 .atomic_commit = drm_atomic_helper_commit, 2166 }; 2167 2168 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 2169 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 2170 .atomic_commit_setup = amdgpu_dm_atomic_setup_commit, 2171 }; 2172 2173 /* 2174 * Acquires the lock for the atomic state object and returns 2175 * the new atomic state. 2176 * 2177 * This should only be called during atomic check. 2178 */ 2179 int dm_atomic_get_state(struct drm_atomic_commit *state, 2180 struct dm_atomic_state **dm_state) 2181 { 2182 struct drm_device *dev = state->dev; 2183 struct amdgpu_device *adev = drm_to_adev(dev); 2184 struct amdgpu_display_manager *dm = &adev->dm; 2185 struct drm_private_state *priv_state; 2186 2187 if (*dm_state) 2188 return 0; 2189 2190 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 2191 if (IS_ERR(priv_state)) 2192 return PTR_ERR(priv_state); 2193 2194 *dm_state = to_dm_atomic_state(priv_state); 2195 2196 return 0; 2197 } 2198 EXPORT_IF_KUNIT(dm_atomic_get_state); 2199 2200 STATIC_IFN_KUNIT struct dm_atomic_state * 2201 dm_atomic_get_new_state(struct drm_atomic_commit *state) 2202 { 2203 struct drm_device *dev = state->dev; 2204 struct amdgpu_device *adev = drm_to_adev(dev); 2205 struct amdgpu_display_manager *dm = &adev->dm; 2206 struct drm_private_obj *obj; 2207 struct drm_private_state *new_obj_state; 2208 int i; 2209 2210 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 2211 if (obj->funcs == dm->atomic_obj.funcs) 2212 return to_dm_atomic_state(new_obj_state); 2213 } 2214 2215 return NULL; 2216 } 2217 EXPORT_IF_KUNIT(dm_atomic_get_new_state); 2218 2219 STATIC_IFN_KUNIT struct drm_private_state * 2220 dm_atomic_duplicate_state(struct drm_private_obj *obj) 2221 { 2222 struct dm_atomic_state *old_state, *new_state; 2223 2224 new_state = kzalloc_obj(*new_state); 2225 if (!new_state) 2226 return NULL; 2227 2228 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 2229 2230 old_state = to_dm_atomic_state(obj->state); 2231 2232 if (old_state && old_state->context) 2233 new_state->context = dc_state_create_copy(old_state->context); 2234 2235 if (!new_state->context) { 2236 kfree(new_state); 2237 return NULL; 2238 } 2239 2240 return &new_state->base; 2241 } 2242 EXPORT_IF_KUNIT(dm_atomic_duplicate_state); 2243 2244 STATIC_IFN_KUNIT void dm_atomic_destroy_state(struct drm_private_obj *obj, 2245 struct drm_private_state *state) 2246 { 2247 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 2248 2249 if (dm_state && dm_state->context) 2250 dc_state_release(dm_state->context); 2251 2252 kfree(dm_state); 2253 } 2254 EXPORT_IF_KUNIT(dm_atomic_destroy_state); 2255 2256 static struct drm_private_state * 2257 dm_atomic_create_state(struct drm_private_obj *obj) 2258 { 2259 struct amdgpu_device *adev = drm_to_adev(obj->dev); 2260 struct dm_atomic_state *dm_state; 2261 struct dc_state *context; 2262 2263 dm_state = kzalloc_obj(*dm_state); 2264 if (!dm_state) 2265 return ERR_PTR(-ENOMEM); 2266 2267 context = dc_state_create_current_copy(adev->dm.dc); 2268 if (!context) { 2269 kfree(dm_state); 2270 return ERR_PTR(-ENOMEM); 2271 } 2272 2273 __drm_atomic_helper_private_obj_create_state(obj, &dm_state->base); 2274 dm_state->context = context; 2275 2276 return &dm_state->base; 2277 } 2278 2279 static struct drm_private_state_funcs dm_atomic_state_funcs = { 2280 .atomic_create_state = dm_atomic_create_state, 2281 .atomic_duplicate_state = dm_atomic_duplicate_state, 2282 .atomic_destroy_state = dm_atomic_destroy_state, 2283 }; 2284 2285 STATIC_IFN_KUNIT int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 2286 { 2287 int r; 2288 2289 adev->mode_info.mode_config_initialized = true; 2290 2291 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 2292 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 2293 2294 adev_to_drm(adev)->mode_config.max_width = 16384; 2295 adev_to_drm(adev)->mode_config.max_height = 16384; 2296 2297 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2298 if (adev->asic_type == CHIP_HAWAII) 2299 /* disable prefer shadow for now due to hibernation issues */ 2300 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 2301 else 2302 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2303 /* indicates support for immediate flip */ 2304 adev_to_drm(adev)->mode_config.async_page_flip = true; 2305 2306 drm_atomic_private_obj_init(adev_to_drm(adev), 2307 &adev->dm.atomic_obj, 2308 &dm_atomic_state_funcs); 2309 2310 r = amdgpu_display_modeset_create_props(adev); 2311 if (r) 2312 return r; 2313 2314 #ifdef AMD_PRIVATE_COLOR 2315 if (amdgpu_dm_create_color_properties(adev)) 2316 return -ENOMEM; 2317 #endif 2318 2319 r = amdgpu_dm_audio_init(adev); 2320 if (r) 2321 return r; 2322 2323 return 0; 2324 } 2325 EXPORT_IF_KUNIT(amdgpu_dm_mode_config_init); 2326 2327 STATIC_IFN_KUNIT int initialize_plane(struct amdgpu_display_manager *dm, 2328 struct amdgpu_mode_info *mode_info, int plane_id, 2329 enum drm_plane_type plane_type, 2330 const struct dc_plane_cap *plane_cap) 2331 { 2332 struct drm_plane *plane; 2333 unsigned long possible_crtcs; 2334 int ret = 0; 2335 2336 plane = kzalloc_obj(struct drm_plane); 2337 if (!plane) { 2338 drm_err(adev_to_drm(dm->adev), "KMS: Failed to allocate plane\n"); 2339 return -ENOMEM; 2340 } 2341 plane->type = plane_type; 2342 2343 /* 2344 * HACK: IGT tests expect that the primary plane for a CRTC 2345 * can only have one possible CRTC. Only expose support for 2346 * any CRTC if they're not going to be used as a primary plane 2347 * for a CRTC - like overlay or underlay planes. 2348 */ 2349 possible_crtcs = 1 << plane_id; 2350 if (plane_id >= dm->dc->caps.max_streams) 2351 possible_crtcs = 0xff; 2352 2353 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 2354 2355 if (ret) { 2356 drm_err(adev_to_drm(dm->adev), "KMS: Failed to initialize plane\n"); 2357 kfree(plane); 2358 return ret; 2359 } 2360 2361 if (mode_info) 2362 mode_info->planes[plane_id] = plane; 2363 2364 return ret; 2365 } 2366 EXPORT_IF_KUNIT(initialize_plane); 2367 2368 2369 /* 2370 * In this architecture, the association 2371 * connector -> encoder -> crtc 2372 * id not really requried. The crtc and connector will hold the 2373 * display_index as an abstraction to use with DAL component 2374 * 2375 * Returns 0 on success 2376 */ 2377 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 2378 { 2379 struct amdgpu_display_manager *dm = &adev->dm; 2380 s32 i; 2381 struct amdgpu_dm_connector *aconnector = NULL; 2382 struct amdgpu_encoder *aencoder = NULL; 2383 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2384 u32 link_cnt; 2385 s32 primary_planes; 2386 enum dc_connection_type new_connection_type = dc_connection_none; 2387 const struct dc_plane_cap *plane; 2388 bool psr_feature_enabled = false; 2389 bool replay_feature_enabled = false; 2390 int max_overlay = dm->dc->caps.max_slave_planes; 2391 2392 dm->display_indexes_num = dm->dc->caps.max_streams; 2393 /* Update the actual used number of crtc */ 2394 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 2395 2396 amdgpu_dm_set_irq_funcs(adev); 2397 2398 link_cnt = dm->dc->caps.max_links; 2399 if (amdgpu_dm_mode_config_init(dm->adev)) { 2400 drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n"); 2401 return -EINVAL; 2402 } 2403 2404 /* There is one primary plane per CRTC */ 2405 primary_planes = dm->dc->caps.max_streams; 2406 if (primary_planes > AMDGPU_MAX_PLANES) { 2407 drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n"); 2408 return -EINVAL; 2409 } 2410 2411 /* 2412 * Initialize primary planes, implicit planes for legacy IOCTLS. 2413 * Order is reversed to match iteration order in atomic check. 2414 */ 2415 for (i = (primary_planes - 1); i >= 0; i--) { 2416 plane = &dm->dc->caps.planes[i]; 2417 2418 if (initialize_plane(dm, mode_info, i, 2419 DRM_PLANE_TYPE_PRIMARY, plane)) { 2420 drm_err(adev_to_drm(adev), "KMS: Failed to initialize primary plane\n"); 2421 goto fail; 2422 } 2423 } 2424 2425 /* 2426 * Initialize overlay planes, index starting after primary planes. 2427 * These planes have a higher DRM index than the primary planes since 2428 * they should be considered as having a higher z-order. 2429 * Order is reversed to match iteration order in atomic check. 2430 * 2431 * Only support DCN for now, and only expose one so we don't encourage 2432 * userspace to use up all the pipes. 2433 */ 2434 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 2435 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 2436 2437 /* Do not create overlay if MPO disabled */ 2438 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 2439 break; 2440 2441 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 2442 continue; 2443 2444 if (!plane->pixel_format_support.argb8888) 2445 continue; 2446 2447 if (max_overlay-- == 0) 2448 break; 2449 2450 if (initialize_plane(dm, NULL, primary_planes + i, 2451 DRM_PLANE_TYPE_OVERLAY, plane)) { 2452 drm_err(adev_to_drm(adev), "KMS: Failed to initialize overlay plane\n"); 2453 goto fail; 2454 } 2455 } 2456 2457 for (i = 0; i < dm->dc->caps.max_streams; i++) 2458 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 2459 drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n"); 2460 goto fail; 2461 } 2462 2463 /* Use Outbox interrupt */ 2464 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2465 case IP_VERSION(3, 0, 0): 2466 case IP_VERSION(3, 1, 2): 2467 case IP_VERSION(3, 1, 3): 2468 case IP_VERSION(3, 1, 4): 2469 case IP_VERSION(3, 1, 5): 2470 case IP_VERSION(3, 1, 6): 2471 case IP_VERSION(3, 2, 0): 2472 case IP_VERSION(3, 2, 1): 2473 case IP_VERSION(2, 1, 0): 2474 case IP_VERSION(3, 5, 0): 2475 case IP_VERSION(3, 5, 1): 2476 case IP_VERSION(3, 6, 0): 2477 case IP_VERSION(4, 0, 1): 2478 case IP_VERSION(4, 2, 0): 2479 case IP_VERSION(4, 2, 1): 2480 case IP_VERSION(6, 0, 0): 2481 if (amdgpu_dm_register_outbox_irq_handlers(dm->adev)) { 2482 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2483 goto fail; 2484 } 2485 break; 2486 default: 2487 drm_dbg_kms(adev_to_drm(adev), "Unsupported DCN IP version for outbox: 0x%X\n", 2488 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2489 } 2490 2491 /* Determine whether to enable PSR support by default. */ 2492 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 2493 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2494 case IP_VERSION(3, 1, 2): 2495 case IP_VERSION(3, 1, 3): 2496 case IP_VERSION(3, 1, 4): 2497 case IP_VERSION(3, 1, 5): 2498 case IP_VERSION(3, 1, 6): 2499 case IP_VERSION(3, 2, 0): 2500 case IP_VERSION(3, 2, 1): 2501 case IP_VERSION(3, 5, 0): 2502 case IP_VERSION(3, 5, 1): 2503 case IP_VERSION(3, 6, 0): 2504 case IP_VERSION(4, 0, 1): 2505 case IP_VERSION(4, 2, 0): 2506 case IP_VERSION(4, 2, 1): 2507 case IP_VERSION(6, 0, 0): 2508 psr_feature_enabled = true; 2509 break; 2510 default: 2511 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 2512 break; 2513 } 2514 } 2515 2516 /* Determine whether to enable Replay support by default. */ 2517 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 2518 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2519 case IP_VERSION(3, 1, 4): 2520 case IP_VERSION(3, 2, 0): 2521 case IP_VERSION(3, 2, 1): 2522 case IP_VERSION(3, 5, 0): 2523 case IP_VERSION(3, 5, 1): 2524 case IP_VERSION(3, 6, 0): 2525 case IP_VERSION(4, 2, 0): 2526 case IP_VERSION(4, 2, 1): 2527 case IP_VERSION(6, 0, 0): 2528 replay_feature_enabled = true; 2529 break; 2530 2531 default: 2532 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; 2533 break; 2534 } 2535 } 2536 2537 if (link_cnt > MAX_LINKS) { 2538 drm_err(adev_to_drm(adev), 2539 "KMS: Cannot support more than %d display indexes\n", 2540 MAX_LINKS); 2541 goto fail; 2542 } 2543 2544 /* loops over all connectors on the board */ 2545 for (i = 0; i < link_cnt; i++) { 2546 struct dc_link *link = NULL; 2547 2548 link = dc_get_link_at_index(dm->dc, i); 2549 2550 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { 2551 struct amdgpu_dm_wb_connector *wbcon = kzalloc_obj(*wbcon); 2552 2553 if (!wbcon) { 2554 drm_err(adev_to_drm(adev), "KMS: Failed to allocate writeback connector\n"); 2555 continue; 2556 } 2557 2558 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { 2559 drm_err(adev_to_drm(adev), "KMS: Failed to initialize writeback connector\n"); 2560 kfree(wbcon); 2561 continue; 2562 } 2563 2564 link->psr_settings.psr_feature_enabled = false; 2565 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 2566 2567 continue; 2568 } 2569 2570 aconnector = kzalloc_obj(*aconnector); 2571 if (!aconnector) 2572 goto fail; 2573 2574 aencoder = kzalloc_obj(*aencoder); 2575 if (!aencoder) 2576 goto fail; 2577 2578 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 2579 drm_err(adev_to_drm(adev), "KMS: Failed to initialize encoder\n"); 2580 goto fail; 2581 } 2582 2583 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 2584 drm_err(adev_to_drm(adev), "KMS: Failed to initialize connector\n"); 2585 goto fail; 2586 } 2587 2588 if (dm->hpd_rx_offload_wq) 2589 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 2590 aconnector; 2591 2592 if (!dc_link_detect_connection_type(link, &new_connection_type)) 2593 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 2594 2595 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2596 amdgpu_dm_emulated_link_detect(link); 2597 amdgpu_dm_update_connector_after_detect(aconnector); 2598 } else { 2599 bool ret = false; 2600 2601 mutex_lock(&dm->dc_lock); 2602 dc_exit_ips_for_hw_access(dm->dc); 2603 ret = dc_link_detect(link, DETECT_REASON_BOOT); 2604 mutex_unlock(&dm->dc_lock); 2605 2606 if (ret) { 2607 amdgpu_dm_update_connector_after_detect(aconnector); 2608 amdgpu_dm_setup_backlight_device(dm, aconnector); 2609 2610 /* Disable PSR if Replay can be enabled */ 2611 if (replay_feature_enabled) 2612 if (amdgpu_dm_set_replay_caps(link, aconnector)) 2613 psr_feature_enabled = false; 2614 2615 if (psr_feature_enabled) { 2616 amdgpu_dm_set_psr_caps(link, aconnector); 2617 drm_info(adev_to_drm(adev), "%s: PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n", 2618 aconnector->base.name, 2619 link->psr_settings.psr_feature_enabled, 2620 link->psr_settings.psr_version, 2621 link->dpcd_caps.psr_info.psr_version, 2622 link->dpcd_caps.psr_info.psr_dpcd_caps.raw, 2623 link->dpcd_caps.psr_info.psr2_su_y_granularity_cap); 2624 } 2625 } 2626 } 2627 amdgpu_set_panel_orientation(&aconnector->base); 2628 } 2629 2630 /* Debug dump: list all DC links and their associated sinks after detection 2631 * is complete for all connectors. This provides a comprehensive view of the 2632 * final state without repeating the dump for each connector. 2633 */ 2634 amdgpu_dm_dump_links_and_sinks(adev); 2635 2636 /* Software is initialized. Now we can register interrupt handlers. */ 2637 switch (adev->asic_type) { 2638 #if defined(CONFIG_DRM_AMD_DC_SI) 2639 case CHIP_TAHITI: 2640 case CHIP_PITCAIRN: 2641 case CHIP_VERDE: 2642 case CHIP_OLAND: 2643 #endif 2644 case CHIP_BONAIRE: 2645 case CHIP_HAWAII: 2646 case CHIP_KAVERI: 2647 case CHIP_KABINI: 2648 case CHIP_MULLINS: 2649 case CHIP_TONGA: 2650 case CHIP_FIJI: 2651 case CHIP_CARRIZO: 2652 case CHIP_STONEY: 2653 case CHIP_POLARIS11: 2654 case CHIP_POLARIS10: 2655 case CHIP_POLARIS12: 2656 case CHIP_VEGAM: 2657 case CHIP_VEGA10: 2658 case CHIP_VEGA12: 2659 case CHIP_VEGA20: 2660 if (amdgpu_dm_dce110_register_irq_handlers(dm->adev)) { 2661 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2662 goto fail; 2663 } 2664 break; 2665 default: 2666 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2667 case IP_VERSION(1, 0, 0): 2668 case IP_VERSION(1, 0, 1): 2669 case IP_VERSION(2, 0, 2): 2670 case IP_VERSION(2, 0, 3): 2671 case IP_VERSION(2, 0, 0): 2672 case IP_VERSION(2, 1, 0): 2673 case IP_VERSION(3, 0, 0): 2674 case IP_VERSION(3, 0, 2): 2675 case IP_VERSION(3, 0, 3): 2676 case IP_VERSION(3, 0, 1): 2677 case IP_VERSION(3, 1, 2): 2678 case IP_VERSION(3, 1, 3): 2679 case IP_VERSION(3, 1, 4): 2680 case IP_VERSION(3, 1, 5): 2681 case IP_VERSION(3, 1, 6): 2682 case IP_VERSION(3, 2, 0): 2683 case IP_VERSION(3, 2, 1): 2684 case IP_VERSION(3, 5, 0): 2685 case IP_VERSION(3, 5, 1): 2686 case IP_VERSION(3, 6, 0): 2687 case IP_VERSION(4, 0, 1): 2688 case IP_VERSION(4, 2, 0): 2689 case IP_VERSION(4, 2, 1): 2690 case IP_VERSION(6, 0, 0): 2691 if (amdgpu_dm_dcn10_register_irq_handlers(dm->adev)) { 2692 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2693 goto fail; 2694 } 2695 break; 2696 default: 2697 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%X\n", 2698 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2699 goto fail; 2700 } 2701 break; 2702 } 2703 2704 return 0; 2705 fail: 2706 kfree(aencoder); 2707 kfree(aconnector); 2708 2709 return -EINVAL; 2710 } 2711 2712 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2713 { 2714 if (dm->atomic_obj.state) 2715 drm_atomic_private_obj_fini(&dm->atomic_obj); 2716 } 2717 2718 /****************************************************************************** 2719 * amdgpu_display_funcs functions 2720 *****************************************************************************/ 2721 2722 /* 2723 * dm_bandwidth_update - program display watermarks 2724 * 2725 * @adev: amdgpu_device pointer 2726 * 2727 * Calculate and program the display watermarks and line buffer allocation. 2728 */ 2729 STATIC_IFN_KUNIT void dm_bandwidth_update(struct amdgpu_device *adev) 2730 { 2731 /* TODO: implement later */ 2732 } 2733 EXPORT_IF_KUNIT(dm_bandwidth_update); 2734 2735 static const struct amdgpu_display_funcs dm_display_funcs = { 2736 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2737 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2738 .backlight_set_level = NULL, /* never called for DC */ 2739 .backlight_get_level = NULL, /* never called for DC */ 2740 .hpd_sense = NULL,/* called unconditionally */ 2741 .hpd_set_polarity = NULL, /* called unconditionally */ 2742 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2743 .page_flip_get_scanoutpos = 2744 dm_crtc_get_scanoutpos,/* called unconditionally */ 2745 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2746 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2747 }; 2748 2749 #if defined(CONFIG_DEBUG_KERNEL_DC) 2750 2751 static ssize_t s3_debug_store(struct device *device, 2752 struct device_attribute *attr, 2753 const char *buf, 2754 size_t count) 2755 { 2756 int ret; 2757 int s3_state; 2758 struct drm_device *drm_dev = dev_get_drvdata(device); 2759 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2760 struct amdgpu_ip_block *ip_block; 2761 2762 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE); 2763 if (!ip_block) 2764 return -EINVAL; 2765 2766 ret = kstrtoint(buf, 0, &s3_state); 2767 2768 if (ret == 0) { 2769 if (s3_state) { 2770 dm_resume(ip_block); 2771 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 2772 } else 2773 dm_suspend(ip_block); 2774 } 2775 2776 return ret == 0 ? count : 0; 2777 } 2778 2779 DEVICE_ATTR_WO(s3_debug); 2780 2781 #endif 2782 2783 STATIC_IFN_KUNIT int dm_early_init(struct amdgpu_ip_block *ip_block) 2784 { 2785 struct amdgpu_device *adev = ip_block->adev; 2786 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2787 struct atom_context *ctx = mode_info->atom_context; 2788 int index = GetIndexIntoMasterTable(DATA, Object_Header); 2789 u16 data_offset; 2790 2791 /* if there is no object header, skip DM */ 2792 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 2793 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 2794 drm_info(adev_to_drm(adev), "No object header, skipping DM\n"); 2795 return -ENOENT; 2796 } 2797 2798 switch (adev->asic_type) { 2799 #if defined(CONFIG_DRM_AMD_DC_SI) 2800 case CHIP_TAHITI: 2801 case CHIP_PITCAIRN: 2802 case CHIP_VERDE: 2803 adev->mode_info.num_crtc = 6; 2804 adev->mode_info.num_hpd = 6; 2805 adev->mode_info.num_dig = 6; 2806 break; 2807 case CHIP_OLAND: 2808 adev->mode_info.num_crtc = 2; 2809 adev->mode_info.num_hpd = 2; 2810 adev->mode_info.num_dig = 2; 2811 break; 2812 #endif 2813 case CHIP_BONAIRE: 2814 case CHIP_HAWAII: 2815 adev->mode_info.num_crtc = 6; 2816 adev->mode_info.num_hpd = 6; 2817 adev->mode_info.num_dig = 6; 2818 break; 2819 case CHIP_KAVERI: 2820 adev->mode_info.num_crtc = 4; 2821 adev->mode_info.num_hpd = 6; 2822 adev->mode_info.num_dig = 7; 2823 break; 2824 case CHIP_KABINI: 2825 case CHIP_MULLINS: 2826 adev->mode_info.num_crtc = 2; 2827 adev->mode_info.num_hpd = 6; 2828 adev->mode_info.num_dig = 6; 2829 break; 2830 case CHIP_FIJI: 2831 case CHIP_TONGA: 2832 adev->mode_info.num_crtc = 6; 2833 adev->mode_info.num_hpd = 6; 2834 adev->mode_info.num_dig = 7; 2835 break; 2836 case CHIP_CARRIZO: 2837 adev->mode_info.num_crtc = 3; 2838 adev->mode_info.num_hpd = 6; 2839 adev->mode_info.num_dig = 9; 2840 break; 2841 case CHIP_STONEY: 2842 adev->mode_info.num_crtc = 2; 2843 adev->mode_info.num_hpd = 6; 2844 adev->mode_info.num_dig = 9; 2845 break; 2846 case CHIP_POLARIS11: 2847 case CHIP_POLARIS12: 2848 adev->mode_info.num_crtc = 5; 2849 adev->mode_info.num_hpd = 5; 2850 adev->mode_info.num_dig = 5; 2851 break; 2852 case CHIP_POLARIS10: 2853 case CHIP_VEGAM: 2854 adev->mode_info.num_crtc = 6; 2855 adev->mode_info.num_hpd = 6; 2856 adev->mode_info.num_dig = 6; 2857 break; 2858 case CHIP_VEGA10: 2859 case CHIP_VEGA12: 2860 case CHIP_VEGA20: 2861 adev->mode_info.num_crtc = 6; 2862 adev->mode_info.num_hpd = 6; 2863 adev->mode_info.num_dig = 6; 2864 break; 2865 default: 2866 2867 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2868 case IP_VERSION(2, 0, 2): 2869 case IP_VERSION(3, 0, 0): 2870 adev->mode_info.num_crtc = 6; 2871 adev->mode_info.num_hpd = 6; 2872 adev->mode_info.num_dig = 6; 2873 break; 2874 case IP_VERSION(2, 0, 0): 2875 case IP_VERSION(3, 0, 2): 2876 adev->mode_info.num_crtc = 5; 2877 adev->mode_info.num_hpd = 5; 2878 adev->mode_info.num_dig = 5; 2879 break; 2880 case IP_VERSION(2, 0, 3): 2881 case IP_VERSION(3, 0, 3): 2882 adev->mode_info.num_crtc = 2; 2883 adev->mode_info.num_hpd = 2; 2884 adev->mode_info.num_dig = 2; 2885 break; 2886 case IP_VERSION(1, 0, 0): 2887 case IP_VERSION(1, 0, 1): 2888 case IP_VERSION(3, 0, 1): 2889 case IP_VERSION(2, 1, 0): 2890 case IP_VERSION(3, 1, 2): 2891 case IP_VERSION(3, 1, 3): 2892 case IP_VERSION(3, 1, 4): 2893 case IP_VERSION(3, 1, 5): 2894 case IP_VERSION(3, 1, 6): 2895 case IP_VERSION(3, 2, 0): 2896 case IP_VERSION(3, 2, 1): 2897 case IP_VERSION(3, 5, 0): 2898 case IP_VERSION(3, 5, 1): 2899 case IP_VERSION(3, 6, 0): 2900 case IP_VERSION(4, 0, 1): 2901 case IP_VERSION(4, 2, 0): 2902 case IP_VERSION(4, 2, 1): 2903 case IP_VERSION(6, 0, 0): 2904 adev->mode_info.num_crtc = 4; 2905 adev->mode_info.num_hpd = 4; 2906 adev->mode_info.num_dig = 4; 2907 break; 2908 default: 2909 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%x\n", 2910 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2911 return -EINVAL; 2912 } 2913 break; 2914 } 2915 2916 if (adev->mode_info.funcs == NULL) 2917 adev->mode_info.funcs = &dm_display_funcs; 2918 2919 /* 2920 * Note: Do NOT change adev->reg.audio_endpt.rreg and 2921 * adev->reg.audio_endpt.wreg because they are initialised in 2922 * amdgpu_device_init() 2923 */ 2924 #if defined(CONFIG_DEBUG_KERNEL_DC) 2925 device_create_file( 2926 adev_to_drm(adev)->dev, 2927 &dev_attr_s3_debug); 2928 #endif 2929 adev->dc_enabled = true; 2930 2931 return dm_init_microcode(adev); 2932 } 2933 EXPORT_IF_KUNIT(dm_early_init); 2934 2935 STATIC_IFN_KUNIT bool modereset_required(struct drm_crtc_state *crtc_state) 2936 { 2937 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 2938 } 2939 EXPORT_IF_KUNIT(modereset_required); 2940 2941 STATIC_IFN_KUNIT int 2942 fill_plane_color_attributes(struct drm_atomic_commit *state, 2943 const struct drm_plane_state *plane_state, 2944 const enum surface_pixel_format format, 2945 enum dc_color_space *color_space) 2946 { 2947 bool full_range; 2948 2949 *color_space = COLOR_SPACE_SRGB; 2950 2951 /* Ignore properties when DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE is set */ 2952 if (state && state->plane_color_pipeline) 2953 return 0; 2954 2955 /* DRM color properties only affect non-RGB formats. */ 2956 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 2957 return 0; 2958 2959 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 2960 2961 switch (plane_state->color_encoding) { 2962 case DRM_COLOR_YCBCR_BT601: 2963 if (full_range) 2964 *color_space = COLOR_SPACE_YCBCR601; 2965 else 2966 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 2967 break; 2968 2969 case DRM_COLOR_YCBCR_BT709: 2970 if (full_range) 2971 *color_space = COLOR_SPACE_YCBCR709; 2972 else 2973 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 2974 break; 2975 2976 case DRM_COLOR_YCBCR_BT2020: 2977 if (full_range) 2978 *color_space = COLOR_SPACE_2020_YCBCR_FULL; 2979 else 2980 *color_space = COLOR_SPACE_2020_YCBCR_LIMITED; 2981 break; 2982 2983 default: 2984 return -EINVAL; 2985 } 2986 2987 return 0; 2988 } 2989 EXPORT_IF_KUNIT(fill_plane_color_attributes); 2990 2991 STATIC_IFN_KUNIT int 2992 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 2993 struct drm_atomic_commit *state, 2994 const struct drm_plane_state *plane_state, 2995 struct dc_plane_info *plane_info, 2996 struct dc_plane_address *address, 2997 bool tmz_surface) 2998 { 2999 const struct drm_framebuffer *fb = plane_state->fb; 3000 const struct amdgpu_framebuffer *afb = 3001 to_amdgpu_framebuffer(plane_state->fb); 3002 int ret; 3003 3004 memset(plane_info, 0, sizeof(*plane_info)); 3005 3006 switch (fb->format->format) { 3007 case DRM_FORMAT_C8: 3008 plane_info->format = 3009 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 3010 break; 3011 case DRM_FORMAT_RGB565: 3012 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 3013 break; 3014 case DRM_FORMAT_XRGB8888: 3015 case DRM_FORMAT_ARGB8888: 3016 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 3017 break; 3018 case DRM_FORMAT_XRGB2101010: 3019 case DRM_FORMAT_ARGB2101010: 3020 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 3021 break; 3022 case DRM_FORMAT_XBGR2101010: 3023 case DRM_FORMAT_ABGR2101010: 3024 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 3025 break; 3026 case DRM_FORMAT_XBGR8888: 3027 case DRM_FORMAT_ABGR8888: 3028 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 3029 break; 3030 case DRM_FORMAT_NV21: 3031 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 3032 break; 3033 case DRM_FORMAT_NV12: 3034 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 3035 break; 3036 case DRM_FORMAT_P010: 3037 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 3038 break; 3039 case DRM_FORMAT_XRGB16161616F: 3040 case DRM_FORMAT_ARGB16161616F: 3041 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 3042 break; 3043 case DRM_FORMAT_XBGR16161616F: 3044 case DRM_FORMAT_ABGR16161616F: 3045 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 3046 break; 3047 case DRM_FORMAT_XRGB16161616: 3048 case DRM_FORMAT_ARGB16161616: 3049 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 3050 break; 3051 case DRM_FORMAT_XBGR16161616: 3052 case DRM_FORMAT_ABGR16161616: 3053 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 3054 break; 3055 default: 3056 drm_err(adev_to_drm(adev), 3057 "Unsupported screen format %p4cc\n", 3058 &fb->format->format); 3059 return -EINVAL; 3060 } 3061 3062 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 3063 case DRM_MODE_ROTATE_0: 3064 plane_info->rotation = ROTATION_ANGLE_0; 3065 break; 3066 case DRM_MODE_ROTATE_90: 3067 plane_info->rotation = ROTATION_ANGLE_90; 3068 break; 3069 case DRM_MODE_ROTATE_180: 3070 plane_info->rotation = ROTATION_ANGLE_180; 3071 break; 3072 case DRM_MODE_ROTATE_270: 3073 plane_info->rotation = ROTATION_ANGLE_270; 3074 break; 3075 default: 3076 plane_info->rotation = ROTATION_ANGLE_0; 3077 break; 3078 } 3079 3080 3081 plane_info->visible = true; 3082 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 3083 3084 plane_info->layer_index = plane_state->normalized_zpos; 3085 3086 ret = fill_plane_color_attributes(state, plane_state, plane_info->format, 3087 &plane_info->color_space); 3088 if (ret) 3089 return ret; 3090 3091 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 3092 plane_info->rotation, 3093 &plane_info->tiling_info, 3094 &plane_info->plane_size, 3095 &plane_info->dcc, address, 3096 tmz_surface); 3097 if (ret) 3098 return ret; 3099 3100 amdgpu_dm_plane_fill_blending_from_plane_state( 3101 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 3102 &plane_info->global_alpha, &plane_info->global_alpha_value); 3103 3104 return 0; 3105 } 3106 EXPORT_IF_KUNIT(fill_dc_plane_info_and_addr); 3107 3108 STATIC_IFN_KUNIT int fill_dc_plane_attributes(struct amdgpu_device *adev, 3109 struct dc_plane_state *dc_plane_state, 3110 struct drm_plane_state *plane_state, 3111 struct drm_crtc_state *crtc_state) 3112 { 3113 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3114 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 3115 struct dc_scaling_info scaling_info; 3116 struct dc_plane_info plane_info; 3117 int ret; 3118 3119 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 3120 if (ret) 3121 return ret; 3122 3123 dc_plane_state->src_rect = scaling_info.src_rect; 3124 dc_plane_state->dst_rect = scaling_info.dst_rect; 3125 dc_plane_state->clip_rect = scaling_info.clip_rect; 3126 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 3127 3128 ret = fill_dc_plane_info_and_addr(adev, plane_state->state, plane_state, 3129 &plane_info, 3130 &dc_plane_state->address, 3131 afb->tmz_surface); 3132 if (ret) 3133 return ret; 3134 3135 dc_plane_state->format = plane_info.format; 3136 dc_plane_state->color_space = plane_info.color_space; 3137 dc_plane_state->format = plane_info.format; 3138 dc_plane_state->plane_size = plane_info.plane_size; 3139 dc_plane_state->rotation = plane_info.rotation; 3140 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 3141 dc_plane_state->stereo_format = plane_info.stereo_format; 3142 dc_plane_state->tiling_info = plane_info.tiling_info; 3143 dc_plane_state->visible = plane_info.visible; 3144 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 3145 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 3146 dc_plane_state->global_alpha = plane_info.global_alpha; 3147 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 3148 dc_plane_state->dcc = plane_info.dcc; 3149 dc_plane_state->layer_index = plane_info.layer_index; 3150 dc_plane_state->flip_int_enabled = true; 3151 3152 /* 3153 * Always set input transfer function, since plane state is refreshed 3154 * every time. 3155 */ 3156 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, 3157 plane_state, 3158 dc_plane_state); 3159 if (ret) 3160 return ret; 3161 3162 return 0; 3163 } 3164 EXPORT_IF_KUNIT(fill_dc_plane_attributes); 3165 3166 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 3167 struct rect *dirty_rect, int32_t x, 3168 s32 y, s32 width, s32 height, 3169 int *i, bool ffu) 3170 { 3171 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 3172 3173 dirty_rect->x = x; 3174 dirty_rect->y = y; 3175 dirty_rect->width = width; 3176 dirty_rect->height = height; 3177 3178 if (ffu) 3179 drm_dbg(plane->dev, 3180 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 3181 plane->base.id, width, height); 3182 else 3183 drm_dbg(plane->dev, 3184 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 3185 plane->base.id, x, y, width, height); 3186 3187 (*i)++; 3188 } 3189 3190 /** 3191 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 3192 * 3193 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 3194 * remote fb 3195 * @old_plane_state: Old state of @plane 3196 * @new_plane_state: New state of @plane 3197 * @crtc_state: New state of CRTC connected to the @plane 3198 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 3199 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. 3200 * If PSR SU is enabled and damage clips are available, only the regions of the screen 3201 * that have changed will be updated. If PSR SU is not enabled, 3202 * or if damage clips are not available, the entire screen will be updated. 3203 * @dirty_regions_changed: dirty regions changed 3204 * 3205 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 3206 * (referred to as "damage clips" in DRM nomenclature) that require updating on 3207 * the eDP remote buffer. The responsibility of specifying the dirty regions is 3208 * amdgpu_dm's. 3209 * 3210 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 3211 * plane with regions that require flushing to the eDP remote buffer. In 3212 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 3213 * implicitly provide damage clips without any client support via the plane 3214 * bounds. 3215 */ 3216 STATIC_IFN_KUNIT void fill_dc_dirty_rects(struct drm_plane *plane, 3217 struct drm_plane_state *old_plane_state, 3218 struct drm_plane_state *new_plane_state, 3219 struct drm_crtc_state *crtc_state, 3220 struct dc_flip_addrs *flip_addrs, 3221 bool is_psr_su, 3222 bool *dirty_regions_changed) 3223 { 3224 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3225 struct rect *dirty_rects = flip_addrs->dirty_rects; 3226 u32 num_clips = 0; 3227 struct drm_mode_rect *clips = NULL; 3228 bool bb_changed; 3229 bool fb_changed; 3230 u32 i = 0; 3231 *dirty_regions_changed = false; 3232 3233 /* 3234 * Cursor plane has it's own dirty rect update interface. See 3235 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 3236 */ 3237 if (plane->type == DRM_PLANE_TYPE_CURSOR) 3238 return; 3239 3240 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 3241 goto ffu; 3242 3243 if (!new_plane_state->ignore_damage_clips) { 3244 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 3245 clips = drm_plane_get_damage_clips(new_plane_state); 3246 } 3247 3248 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && 3249 is_psr_su))) 3250 goto ffu; 3251 3252 if (!dm_crtc_state->mpo_requested) { 3253 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 3254 goto ffu; 3255 3256 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 3257 fill_dc_dirty_rect(new_plane_state->plane, 3258 &dirty_rects[flip_addrs->dirty_rect_count], 3259 clips->x1, clips->y1, 3260 clips->x2 - clips->x1, clips->y2 - clips->y1, 3261 &flip_addrs->dirty_rect_count, 3262 false); 3263 return; 3264 } 3265 3266 /* 3267 * MPO is requested. Add entire plane bounding box to dirty rects if 3268 * flipped to or damaged. 3269 * 3270 * If plane is moved or resized, also add old bounding box to dirty 3271 * rects. 3272 */ 3273 fb_changed = old_plane_state->fb->base.id != 3274 new_plane_state->fb->base.id; 3275 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 3276 old_plane_state->crtc_y != new_plane_state->crtc_y || 3277 old_plane_state->crtc_w != new_plane_state->crtc_w || 3278 old_plane_state->crtc_h != new_plane_state->crtc_h); 3279 3280 drm_dbg(plane->dev, 3281 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 3282 new_plane_state->plane->base.id, 3283 bb_changed, fb_changed, num_clips); 3284 3285 *dirty_regions_changed = bb_changed; 3286 3287 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 3288 goto ffu; 3289 3290 if (bb_changed) { 3291 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3292 new_plane_state->crtc_x, 3293 new_plane_state->crtc_y, 3294 new_plane_state->crtc_w, 3295 new_plane_state->crtc_h, &i, false); 3296 3297 /* Add old plane bounding-box if plane is moved or resized */ 3298 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3299 old_plane_state->crtc_x, 3300 old_plane_state->crtc_y, 3301 old_plane_state->crtc_w, 3302 old_plane_state->crtc_h, &i, false); 3303 } 3304 3305 if (num_clips) { 3306 for (; i < num_clips; clips++) 3307 fill_dc_dirty_rect(new_plane_state->plane, 3308 &dirty_rects[i], clips->x1, 3309 clips->y1, clips->x2 - clips->x1, 3310 clips->y2 - clips->y1, &i, false); 3311 } else if (fb_changed && !bb_changed) { 3312 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3313 new_plane_state->crtc_x, 3314 new_plane_state->crtc_y, 3315 new_plane_state->crtc_w, 3316 new_plane_state->crtc_h, &i, false); 3317 } 3318 3319 flip_addrs->dirty_rect_count = i; 3320 return; 3321 3322 ffu: 3323 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 3324 dm_crtc_state->base.mode.crtc_hdisplay, 3325 dm_crtc_state->base.mode.crtc_vdisplay, 3326 &flip_addrs->dirty_rect_count, true); 3327 } 3328 EXPORT_IF_KUNIT(fill_dc_dirty_rects); 3329 3330 STATIC_IFN_KUNIT int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_commit *state, 3331 struct dc_state *dc_state, 3332 struct dsc_mst_fairness_vars *vars) 3333 { 3334 struct dc_stream_state *stream = NULL; 3335 struct drm_connector *connector; 3336 struct drm_connector_state *new_con_state; 3337 struct amdgpu_dm_connector *aconnector; 3338 struct dm_connector_state *dm_conn_state; 3339 int i, j, ret; 3340 int vcpi, pbn_div, pbn = 0, slot_num = 0; 3341 3342 for_each_new_connector_in_state(state, connector, new_con_state, i) { 3343 3344 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3345 continue; 3346 3347 aconnector = to_amdgpu_dm_connector(connector); 3348 3349 if (!aconnector->mst_output_port) 3350 continue; 3351 3352 if (!new_con_state || !new_con_state->crtc) 3353 continue; 3354 3355 dm_conn_state = to_dm_connector_state(new_con_state); 3356 3357 for (j = 0; j < dc_state->stream_count; j++) { 3358 stream = dc_state->streams[j]; 3359 if (!stream) 3360 continue; 3361 3362 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 3363 break; 3364 3365 stream = NULL; 3366 } 3367 3368 if (!stream) 3369 continue; 3370 3371 pbn_div = dm_mst_get_pbn_divider(stream->link); 3372 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 3373 for (j = 0; j < dc_state->stream_count; j++) { 3374 if (vars[j].aconnector == aconnector) { 3375 pbn = vars[j].pbn; 3376 break; 3377 } 3378 } 3379 3380 if (j == dc_state->stream_count || pbn_div == 0) 3381 continue; 3382 3383 slot_num = DIV_ROUND_UP(pbn, pbn_div); 3384 3385 if (stream->timing.flags.DSC != 1) { 3386 dm_conn_state->pbn = pbn; 3387 dm_conn_state->vcpi_slots = slot_num; 3388 3389 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 3390 dm_conn_state->pbn, false); 3391 if (ret < 0) 3392 return ret; 3393 3394 continue; 3395 } 3396 3397 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 3398 if (vcpi < 0) 3399 return vcpi; 3400 3401 dm_conn_state->pbn = pbn; 3402 dm_conn_state->vcpi_slots = vcpi; 3403 } 3404 return 0; 3405 } 3406 EXPORT_IF_KUNIT(dm_update_mst_vcpi_slots_for_dsc); 3407 3408 STATIC_IFN_KUNIT void manage_dm_interrupts(struct amdgpu_device *adev, 3409 struct amdgpu_crtc *acrtc, 3410 struct dm_crtc_state *acrtc_state) 3411 { /* 3412 * We cannot be sure that the frontend index maps to the same 3413 * backend index - some even map to more than one. 3414 * So we have to go through the CRTC to find the right IRQ. 3415 */ 3416 int irq_type = amdgpu_display_crtc_idx_to_irq_type( 3417 adev, 3418 acrtc->crtc_id); 3419 struct drm_device *dev = adev_to_drm(adev); 3420 3421 struct drm_vblank_crtc_config config = {0}; 3422 struct dc_crtc_timing *timing; 3423 int offdelay; 3424 3425 if (acrtc_state) { 3426 timing = &acrtc_state->stream->timing; 3427 3428 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < 3429 IP_VERSION(3, 5, 0) || 3430 !(adev->flags & AMD_IS_APU)) { 3431 /* 3432 * Older HW and DGPU have issues with instant off; 3433 * use a 2 frame offdelay. 3434 */ 3435 offdelay = DIV64_U64_ROUND_UP((u64)20 * 3436 timing->v_total * 3437 timing->h_total, 3438 timing->pix_clk_100hz); 3439 3440 config.offdelay_ms = offdelay ?: 30; 3441 } else { 3442 /* offdelay_ms = 0 will never disable vblank */ 3443 config.offdelay_ms = 1; 3444 config.disable_immediate = true; 3445 } 3446 3447 drm_crtc_vblank_on_config(&acrtc->base, 3448 &config); 3449 /* 3450 * Since pflip_high_irq is no longer registered for DCN, grab an 3451 * extra reference to vupdate irq instead to workaround this 3452 * issue: 3453 * https://gitlab.freedesktop.org/drm/amd/-/work_items/3936 3454 * 3455 * The callbacks to drm_vblank_on/off should really take care of 3456 * this though. 3457 */ 3458 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3459 case IP_VERSION(3, 0, 0): 3460 case IP_VERSION(3, 0, 2): 3461 case IP_VERSION(3, 0, 3): 3462 case IP_VERSION(3, 2, 0): 3463 if (amdgpu_irq_get(adev, &adev->vupdate_irq, irq_type)) 3464 drm_err(dev, "DM_IRQ: Cannot get vupdate irq!\n"); 3465 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3466 if (amdgpu_irq_get(adev, &adev->vline0_irq, irq_type)) 3467 drm_err(dev, "DM_IRQ: Cannot get vline0 irq!\n"); 3468 #endif 3469 } 3470 3471 } else { 3472 /* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_put.*/ 3473 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3474 case IP_VERSION(3, 0, 0): 3475 case IP_VERSION(3, 0, 2): 3476 case IP_VERSION(3, 0, 3): 3477 case IP_VERSION(3, 2, 0): 3478 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3479 if (amdgpu_irq_put(adev, &adev->vline0_irq, irq_type)) 3480 drm_err(dev, "DM_IRQ: Cannot put vline0 irq!\n"); 3481 #endif 3482 if (amdgpu_irq_put(adev, &adev->vupdate_irq, irq_type)) 3483 drm_err(dev, "DM_IRQ: Cannot put vupdate irq!\n"); 3484 } 3485 3486 drm_crtc_vblank_off(&acrtc->base); 3487 } 3488 } 3489 EXPORT_IF_KUNIT(manage_dm_interrupts); 3490 3491 STATIC_IFN_KUNIT void dm_update_pflip_irq_state(struct amdgpu_device *adev, 3492 struct amdgpu_crtc *acrtc) 3493 { 3494 int irq_type = 3495 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 3496 3497 /* GRPH_PFLIP is not used on DCN; nothing to reapply. */ 3498 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) 3499 return; 3500 3501 /** 3502 * This reads the current state for the IRQ and force reapplies 3503 * the setting to hardware. 3504 */ 3505 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 3506 } 3507 EXPORT_IF_KUNIT(dm_update_pflip_irq_state); 3508 3509 STATIC_IFN_KUNIT bool 3510 is_scaling_state_different(const struct dm_connector_state *dm_state, 3511 const struct dm_connector_state *old_dm_state) 3512 { 3513 if (dm_state->scaling != old_dm_state->scaling) 3514 return true; 3515 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 3516 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 3517 return true; 3518 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 3519 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 3520 return true; 3521 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 3522 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 3523 return true; 3524 return false; 3525 } 3526 EXPORT_IF_KUNIT(is_scaling_state_different); 3527 3528 STATIC_IFN_KUNIT bool 3529 is_content_protection_different(struct drm_crtc_state *new_crtc_state, 3530 struct drm_crtc_state *old_crtc_state, 3531 struct drm_connector_state *new_conn_state, 3532 struct drm_connector_state *old_conn_state, 3533 const struct drm_connector *connector, 3534 struct hdcp_workqueue *hdcp_w) 3535 { 3536 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3537 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3538 3539 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 3540 connector->index, connector->status, connector->dpms); 3541 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 3542 old_conn_state->content_protection, new_conn_state->content_protection); 3543 3544 if (old_crtc_state) 3545 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3546 old_crtc_state->enable, 3547 old_crtc_state->active, 3548 old_crtc_state->mode_changed, 3549 old_crtc_state->active_changed, 3550 old_crtc_state->connectors_changed); 3551 3552 if (new_crtc_state) 3553 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3554 new_crtc_state->enable, 3555 new_crtc_state->active, 3556 new_crtc_state->mode_changed, 3557 new_crtc_state->active_changed, 3558 new_crtc_state->connectors_changed); 3559 3560 /* hdcp content type change */ 3561 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 3562 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 3563 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3564 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 3565 return true; 3566 } 3567 3568 /* CP is being re enabled, ignore this */ 3569 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 3570 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3571 if (new_crtc_state && new_crtc_state->mode_changed) { 3572 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3573 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 3574 return true; 3575 } 3576 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 3577 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 3578 return false; 3579 } 3580 3581 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 3582 * 3583 * Handles: UNDESIRED -> ENABLED 3584 */ 3585 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 3586 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3587 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3588 3589 /* Stream removed and re-enabled 3590 * 3591 * Can sometimes overlap with the HPD case, 3592 * thus set update_hdcp to false to avoid 3593 * setting HDCP multiple times. 3594 * 3595 * Handles: DESIRED -> DESIRED (Special case) 3596 */ 3597 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 3598 new_conn_state->crtc && new_conn_state->crtc->enabled && 3599 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3600 dm_con_state->update_hdcp = false; 3601 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 3602 __func__); 3603 return true; 3604 } 3605 3606 /* Hot-plug, headless s3, dpms 3607 * 3608 * Only start HDCP if the display is connected/enabled. 3609 * update_hdcp flag will be set to false until the next 3610 * HPD comes in. 3611 * 3612 * Handles: DESIRED -> DESIRED (Special case) 3613 */ 3614 if (dm_con_state->update_hdcp && 3615 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 3616 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 3617 dm_con_state->update_hdcp = false; 3618 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 3619 __func__); 3620 return true; 3621 } 3622 3623 if (old_conn_state->content_protection == new_conn_state->content_protection) { 3624 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3625 if (new_crtc_state && new_crtc_state->mode_changed) { 3626 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 3627 __func__); 3628 return true; 3629 } 3630 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 3631 __func__); 3632 return false; 3633 } 3634 3635 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 3636 return false; 3637 } 3638 3639 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 3640 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 3641 __func__); 3642 return true; 3643 } 3644 3645 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 3646 return false; 3647 } 3648 EXPORT_IF_KUNIT(is_content_protection_different); 3649 3650 static void remove_stream(struct amdgpu_device *adev, 3651 struct amdgpu_crtc *acrtc, 3652 struct dc_stream_state *stream) 3653 { 3654 /* this is the update mode case */ 3655 3656 acrtc->otg_inst = -1; 3657 acrtc->enabled = false; 3658 } 3659 3660 STATIC_IFN_KUNIT void amdgpu_dm_commit_cursors(struct drm_atomic_commit *state) 3661 { 3662 struct drm_plane *plane; 3663 struct drm_plane_state *old_plane_state; 3664 int i; 3665 3666 /* 3667 * TODO: Make this per-stream so we don't issue redundant updates for 3668 * commits with multiple streams. 3669 */ 3670 for_each_old_plane_in_state(state, plane, old_plane_state, i) 3671 if (plane->type == DRM_PLANE_TYPE_CURSOR) 3672 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 3673 } 3674 EXPORT_IF_KUNIT(amdgpu_dm_commit_cursors); 3675 3676 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 3677 { 3678 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 3679 3680 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 3681 } 3682 3683 STATIC_IFN_KUNIT void amdgpu_dm_update_cursor(struct drm_plane *plane, 3684 struct drm_plane_state *old_plane_state, 3685 struct dc_stream_update *update) 3686 { 3687 struct amdgpu_device *adev = drm_to_adev(plane->dev); 3688 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 3689 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 3690 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 3691 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 3692 uint64_t address = afb ? afb->address : 0; 3693 struct dc_cursor_position position = {0}; 3694 struct dc_cursor_attributes attributes; 3695 int ret; 3696 3697 if (!plane->state->fb && !old_plane_state->fb) 3698 return; 3699 3700 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 3701 amdgpu_crtc->crtc_id, plane->state->crtc_w, 3702 plane->state->crtc_h); 3703 3704 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 3705 if (ret) 3706 return; 3707 3708 if (!position.enable) { 3709 /* turn off cursor */ 3710 if (crtc_state && crtc_state->stream) { 3711 dc_stream_set_cursor_position(crtc_state->stream, 3712 &position); 3713 update->cursor_position = &crtc_state->stream->cursor_position; 3714 } 3715 return; 3716 } 3717 3718 amdgpu_crtc->cursor_width = plane->state->crtc_w; 3719 amdgpu_crtc->cursor_height = plane->state->crtc_h; 3720 3721 memset(&attributes, 0, sizeof(attributes)); 3722 attributes.address.high_part = upper_32_bits(address); 3723 attributes.address.low_part = lower_32_bits(address); 3724 attributes.width = plane->state->crtc_w; 3725 attributes.height = plane->state->crtc_h; 3726 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 3727 attributes.rotation_angle = 0; 3728 attributes.attribute_flags.value = 0; 3729 3730 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 3731 * legacy gamma setup. 3732 */ 3733 if (crtc_state->cm_is_degamma_srgb && 3734 adev->dm.dc->caps.color.dpp.gamma_corr) 3735 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 3736 3737 if (afb) 3738 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 3739 3740 if (crtc_state->stream) { 3741 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 3742 &attributes)) 3743 drm_err(adev_to_drm(adev), "DC failed to set cursor attributes\n"); 3744 3745 update->cursor_attributes = &crtc_state->stream->cursor_attributes; 3746 3747 if (!dc_stream_set_cursor_position(crtc_state->stream, 3748 &position)) 3749 drm_err(adev_to_drm(adev), "DC failed to set cursor position\n"); 3750 3751 update->cursor_position = &crtc_state->stream->cursor_position; 3752 } 3753 } 3754 EXPORT_IF_KUNIT(amdgpu_dm_update_cursor); 3755 3756 STATIC_IFN_KUNIT void amdgpu_dm_enable_self_refresh(struct amdgpu_display_manager *dm, 3757 struct amdgpu_crtc *acrtc_attach, 3758 const struct dm_crtc_state *acrtc_state, 3759 const u64 current_ts) 3760 { 3761 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; 3762 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; 3763 struct amdgpu_dm_connector *aconn = 3764 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 3765 3766 if (!acrtc_state->base.async_flip) { 3767 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false, 3768 psr_event_immediate_flip, false); 3769 amdgpu_dm_replay_set_event(dm, acrtc_state->stream, false, 3770 replay_event_immediate_flip, false); 3771 } 3772 3773 /* Decrement skip count when SR is enabled and we're doing fast updates. */ 3774 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 3775 (psr->psr_feature_enabled || pr->replay_feature_enabled)) { 3776 if (aconn->sr_skip_count > 0) 3777 aconn->sr_skip_count--; 3778 3779 /* Allow SR when skip count is 0. */ 3780 acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count; 3781 3782 /* 3783 * If sink supports PSR SU/Panel Replay, there is no need to rely on 3784 * a vblank event disable request to enable PSR/RP. PSR SU/RP 3785 * can be enabled immediately once OS demonstrates an 3786 * adequate number of fast atomic commits to notify KMD 3787 * of update events. 3788 * See `amdgpu_dm_crtc_vblank_control_worker()`. 3789 */ 3790 if (acrtc_attach->dm_irq_params.allow_sr_entry && 3791 (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) { 3792 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false, 3793 psr_event_hw_programming, false); 3794 3795 amdgpu_dm_replay_set_event(dm, acrtc_state->stream, false, 3796 replay_event_hw_programming, false); 3797 } 3798 } else { 3799 acrtc_attach->dm_irq_params.allow_sr_entry = false; 3800 } 3801 } 3802 EXPORT_IF_KUNIT(amdgpu_dm_enable_self_refresh); 3803 3804 STATIC_IFN_KUNIT void dm_arm_vblank_event(struct amdgpu_crtc *acrtc, 3805 struct dm_crtc_state *acrtc_state, 3806 bool pflip_update, 3807 bool cursor_update) 3808 { 3809 assert_spin_locked(&acrtc->base.dev->event_lock); 3810 3811 if (!acrtc->base.state->event || acrtc_state->active_planes == 0) 3812 return; 3813 3814 if (pflip_update) { 3815 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE); 3816 WARN_ON(acrtc->event); 3817 3818 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 3819 acrtc->event = acrtc->base.state->event; 3820 acrtc->base.state->event = NULL; 3821 3822 drm_dbg_state(acrtc->base.dev, 3823 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 3824 acrtc->crtc_id); 3825 } else if (cursor_update) { 3826 acrtc->event = acrtc->base.state->event; 3827 acrtc->base.state->event = NULL; 3828 } 3829 } 3830 EXPORT_IF_KUNIT(dm_arm_vblank_event); 3831 3832 /** 3833 * dm_arm_vblank_event_pre_programming - Prepare for programming 3834 * @acrtc: The amdgpu CRTC to prepare 3835 * @acrtc_state: The new CRTC state 3836 * @pflip_update: Whether a page flip is being programmed 3837 * @cursor_update: Whether a cursor update is being programmed 3838 * 3839 * Grab a reference on the vblank counter if a page flip or cursor update is to 3840 * be programmed. Do this before programming so the HW is not in any 3841 * idle-optimized state (such as PSR). 3842 */ 3843 STATIC_IFN_KUNIT void dm_arm_vblank_event_pre_programming(struct amdgpu_crtc *acrtc, 3844 struct dm_crtc_state *acrtc_state, 3845 bool pflip_update, 3846 bool cursor_update) 3847 { 3848 assert_spin_locked(&acrtc->base.dev->event_lock); 3849 3850 if (!acrtc->base.state->event || acrtc_state->active_planes == 0) 3851 return; 3852 3853 if (pflip_update || cursor_update) 3854 drm_crtc_vblank_get(&acrtc->base); 3855 } 3856 EXPORT_IF_KUNIT(dm_arm_vblank_event_pre_programming); 3857 3858 static void amdgpu_dm_commit_planes(struct drm_atomic_commit *state, 3859 struct drm_device *dev, 3860 struct amdgpu_display_manager *dm, 3861 struct drm_crtc *pcrtc, 3862 bool wait_for_vblank) 3863 { 3864 u32 i; 3865 u64 timestamp_ns = ktime_get_ns(); 3866 struct drm_plane *plane; 3867 struct drm_plane_state *old_plane_state, *new_plane_state; 3868 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 3869 struct drm_crtc_state *new_pcrtc_state = 3870 drm_atomic_get_new_crtc_state(state, pcrtc); 3871 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 3872 struct dm_crtc_state *dm_old_crtc_state = 3873 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 3874 int planes_count = 0, vpos, hpos; 3875 unsigned long flags; 3876 u32 target_vblank, last_flip_vblank; 3877 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 3878 bool cursor_update = false; 3879 bool pflip_present = false; 3880 bool immediate_flip = false; 3881 bool flip_latched_during_prog = false; 3882 bool dirty_rects_changed = false; 3883 bool updated_planes_and_streams = false; 3884 bool stream_update_needed = false; 3885 struct { 3886 struct dc_surface_update surface_updates[MAX_SURFACES]; 3887 struct dc_plane_info plane_infos[MAX_SURFACES]; 3888 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 3889 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 3890 struct dc_stream_update stream_update; 3891 } *bundle; 3892 3893 bundle = kzalloc_obj(*bundle); 3894 3895 if (!bundle) { 3896 drm_err(dev, "Failed to allocate update bundle\n"); 3897 goto cleanup; 3898 } 3899 3900 /* 3901 * Disable the cursor first if we're disabling all the planes. 3902 * It'll remain on the screen after the planes are re-enabled 3903 * if we don't. 3904 * 3905 * If the cursor is transitioning from native to overlay mode, the 3906 * native cursor needs to be disabled first. 3907 */ 3908 if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE && 3909 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 3910 struct dc_cursor_position cursor_position = {0}; 3911 3912 if (!dc_stream_set_cursor_position(acrtc_state->stream, 3913 &cursor_position)) 3914 drm_err(dev, "DC failed to disable native cursor\n"); 3915 3916 bundle->stream_update.cursor_position = 3917 &acrtc_state->stream->cursor_position; 3918 stream_update_needed = true; 3919 } 3920 3921 if (acrtc_state->active_planes == 0 && 3922 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 3923 amdgpu_dm_commit_cursors(state); 3924 3925 /* update planes when needed */ 3926 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 3927 struct drm_crtc *crtc = new_plane_state->crtc; 3928 struct drm_crtc_state *new_crtc_state; 3929 struct drm_framebuffer *fb = new_plane_state->fb; 3930 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 3931 bool plane_needs_flip; 3932 struct dc_plane_state *dc_plane; 3933 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 3934 struct dm_plane_state *dm_old_plane_state = to_dm_plane_state(old_plane_state); 3935 3936 /* Cursor plane is handled after stream updates */ 3937 if (plane->type == DRM_PLANE_TYPE_CURSOR && 3938 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 3939 if ((fb && crtc == pcrtc) || 3940 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) { 3941 cursor_update = true; 3942 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) { 3943 amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update); 3944 stream_update_needed = true; 3945 } 3946 } 3947 3948 continue; 3949 } 3950 3951 if (!fb || !crtc || pcrtc != crtc) 3952 continue; 3953 3954 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 3955 if (!new_crtc_state->active) 3956 continue; 3957 3958 dc_plane = dm_new_plane_state->dc_state; 3959 if (!dc_plane) 3960 continue; 3961 3962 bundle->surface_updates[planes_count].surface = dc_plane; 3963 if (new_pcrtc_state->color_mgmt_changed || new_plane_state->color_mgmt_changed) { 3964 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; 3965 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func; 3966 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 3967 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; 3968 bundle->surface_updates[planes_count].cm = &dc_plane->cm; 3969 } 3970 3971 if (amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 3972 &bundle->scaling_infos[planes_count])) { 3973 planes_count += 1; 3974 continue; 3975 } 3976 3977 /* Cache the newly computed scaling_info in the plane state */ 3978 *dm_new_plane_state->scaling_info = 3979 bundle->scaling_infos[planes_count]; 3980 3981 /* Only send a scaling_info update if it changed vs the old state */ 3982 if (memcmp(dm_old_plane_state->scaling_info, 3983 dm_new_plane_state->scaling_info, 3984 sizeof(struct dc_scaling_info))) 3985 bundle->surface_updates[planes_count].scaling_info = 3986 &bundle->scaling_infos[planes_count]; 3987 3988 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 3989 3990 pflip_present = pflip_present || plane_needs_flip; 3991 3992 if (!plane_needs_flip) { 3993 planes_count += 1; 3994 continue; 3995 } 3996 3997 fill_dc_plane_info_and_addr( 3998 dm->adev, state, new_plane_state, 3999 &bundle->plane_infos[planes_count], 4000 &bundle->flip_addrs[planes_count].address, 4001 afb->tmz_surface); 4002 4003 bundle->plane_infos[planes_count].color_space = dc_plane->color_space; 4004 4005 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 4006 new_plane_state->plane->index, 4007 bundle->plane_infos[planes_count].dcc.enable); 4008 4009 /* Cache the newly computed plane_info in the plane state */ 4010 *dm_new_plane_state->plane_info = 4011 bundle->plane_infos[planes_count]; 4012 4013 /* Only send a plane_info update if it changed vs the old state */ 4014 if (memcmp(dm_old_plane_state->plane_info, 4015 dm_new_plane_state->plane_info, 4016 sizeof(struct dc_plane_info))) 4017 bundle->surface_updates[planes_count].plane_info = 4018 &bundle->plane_infos[planes_count]; 4019 4020 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 4021 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 4022 fill_dc_dirty_rects(plane, old_plane_state, 4023 new_plane_state, new_crtc_state, 4024 &bundle->flip_addrs[planes_count], 4025 acrtc_state->stream->link->psr_settings.psr_version == 4026 DC_PSR_VERSION_SU_1, 4027 &dirty_rects_changed); 4028 4029 /* 4030 * If the dirty regions changed, PSR-SU need to be disabled temporarily 4031 * and enabled it again after dirty regions are stable to avoid video glitch. 4032 * PSR-SU will be enabled in 4033 * amdgpu_dm_crtc_vblank_control_worker() if user 4034 * pause the video during the PSR-SU was disabled. 4035 */ 4036 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 4037 acrtc_attach->dm_irq_params.allow_sr_entry && 4038 dirty_rects_changed) { 4039 mutex_lock(&dm->dc_lock); 4040 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 4041 timestamp_ns; 4042 dc_exit_ips_for_hw_access(dm->dc); 4043 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, true, 4044 psr_event_hw_programming, true); 4045 mutex_unlock(&dm->dc_lock); 4046 } 4047 } 4048 4049 /* 4050 * Only allow immediate flips for fast updates that don't 4051 * change memory domain, FB pitch, DCC state, rotation or 4052 * mirroring. 4053 * 4054 * dm_crtc_helper_atomic_check() only accepts async flips with 4055 * fast updates. 4056 */ 4057 if (crtc->state->async_flip && 4058 (acrtc_state->update_type != UPDATE_TYPE_FAST || 4059 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 4060 drm_warn_once(state->dev, 4061 "[PLANE:%d:%s] async flip with non-fast update\n", 4062 plane->base.id, plane->name); 4063 4064 bundle->flip_addrs[planes_count].flip_immediate = 4065 crtc->state->async_flip && 4066 acrtc_state->update_type == UPDATE_TYPE_FAST && 4067 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 4068 4069 immediate_flip |= bundle->flip_addrs[planes_count].flip_immediate; 4070 4071 timestamp_ns = ktime_get_ns(); 4072 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 4073 /* Cache the newly computed flip_addr in the plane state */ 4074 *dm_new_plane_state->flip_addr = 4075 bundle->flip_addrs[planes_count]; 4076 4077 /* Only send a flip_addr update if it changed vs the old state */ 4078 if (memcmp(dm_old_plane_state->flip_addr, 4079 dm_new_plane_state->flip_addr, 4080 sizeof(struct dc_flip_addrs))) 4081 bundle->surface_updates[planes_count].flip_addr = 4082 &bundle->flip_addrs[planes_count]; 4083 bundle->surface_updates[planes_count].surface = dc_plane; 4084 4085 if (!bundle->surface_updates[planes_count].surface) { 4086 drm_err(dev, "No surface for CRTC: id=%d\n", 4087 acrtc_attach->crtc_id); 4088 continue; 4089 } 4090 4091 if (plane == pcrtc->primary) 4092 amdgpu_dm_update_freesync_state_on_stream( 4093 dm, 4094 acrtc_state, 4095 acrtc_state->stream, 4096 dc_plane, 4097 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 4098 4099 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 4100 __func__, 4101 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 4102 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 4103 4104 planes_count += 1; 4105 4106 } 4107 4108 if (pflip_present) { 4109 if (!vrr_active) { 4110 /* Use old throttling in non-vrr fixed refresh rate mode 4111 * to keep flip scheduling based on target vblank counts 4112 * working in a backwards compatible way, e.g., for 4113 * clients using the GLX_OML_sync_control extension or 4114 * DRI3/Present extension with defined target_msc. 4115 */ 4116 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 4117 } else { 4118 /* For variable refresh rate mode only: 4119 * Get vblank of last completed flip to avoid > 1 vrr 4120 * flips per video frame by use of throttling, but allow 4121 * flip programming anywhere in the possibly large 4122 * variable vrr vblank interval for fine-grained flip 4123 * timing control and more opportunity to avoid stutter 4124 * on late submission of flips. 4125 */ 4126 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4127 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 4128 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4129 } 4130 4131 target_vblank = last_flip_vblank + wait_for_vblank; 4132 4133 /* 4134 * Wait until we're out of the vertical blank period before the one 4135 * targeted by the flip 4136 */ 4137 while ((acrtc_attach->enabled && 4138 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 4139 0, &vpos, &hpos, NULL, 4140 NULL, &pcrtc->hwmode) 4141 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 4142 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 4143 (int)(target_vblank - 4144 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 4145 usleep_range(1000, 1100); 4146 } 4147 4148 if (acrtc_state->stream) { 4149 if (acrtc_state->freesync_vrr_info_changed) { 4150 bundle->stream_update.vrr_infopacket = 4151 &acrtc_state->stream->vrr_infopacket; 4152 bundle->stream_update.vtem_infopacket = 4153 &acrtc_state->stream->vtem_infopacket; 4154 bundle->stream_update.vsp_infopacket = 4155 &acrtc_state->stream->vsp_infopacket; 4156 stream_update_needed = true; 4157 } 4158 } 4159 } 4160 4161 scoped_guard(spinlock_irqsave, &pcrtc->dev->event_lock) { 4162 dm_arm_vblank_event_pre_programming(acrtc_attach, acrtc_state, 4163 pflip_present, 4164 cursor_update); 4165 /* 4166 * DCE depends on a combination of GRPH_FLIP, VLINE0, and 4167 * VUPDATE for event delivery. Only GRPH_FLIP handler can send 4168 * pflip events, and it only fires if HW latched to the flip. 4169 * Maintain legacy behavior by arming event before programming. 4170 */ 4171 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) { 4172 dm_arm_vblank_event(acrtc_attach, acrtc_state, 4173 pflip_present, cursor_update); 4174 } 4175 } 4176 4177 /* Update the planes if changed or disable if we don't have any. */ 4178 if ((planes_count || acrtc_state->active_planes == 0) && 4179 acrtc_state->stream) { 4180 /* 4181 * If PSR or idle optimizations are enabled then flush out 4182 * any pending work before hardware programming. 4183 */ 4184 if (dm->vblank_control_workqueue) 4185 flush_workqueue(dm->vblank_control_workqueue); 4186 4187 bundle->stream_update.stream = acrtc_state->stream; 4188 if (new_pcrtc_state->mode_changed) { 4189 bundle->stream_update.src = acrtc_state->stream->src; 4190 bundle->stream_update.dst = acrtc_state->stream->dst; 4191 stream_update_needed = true; 4192 } 4193 4194 if (new_pcrtc_state->color_mgmt_changed) { 4195 /* 4196 * TODO: This isn't fully correct since we've actually 4197 * already modified the stream in place. 4198 */ 4199 bundle->stream_update.gamut_remap = 4200 &acrtc_state->stream->gamut_remap_matrix; 4201 bundle->stream_update.output_csc_transform = 4202 &acrtc_state->stream->csc_color_matrix; 4203 bundle->stream_update.out_transfer_func = 4204 &acrtc_state->stream->out_transfer_func; 4205 bundle->stream_update.lut3d_func = 4206 (struct dc_3dlut *) acrtc_state->stream->lut3d_func; 4207 bundle->stream_update.func_shaper = 4208 (struct dc_transfer_func *) acrtc_state->stream->func_shaper; 4209 stream_update_needed = true; 4210 } 4211 4212 acrtc_state->stream->abm_level = acrtc_state->abm_level; 4213 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) { 4214 bundle->stream_update.abm_level = &acrtc_state->abm_level; 4215 stream_update_needed = true; 4216 } 4217 4218 /* 4219 * If FreeSync state on the stream has changed then we need to 4220 * re-adjust the min/max bounds now that DC doesn't handle this 4221 * as part of commit. 4222 */ 4223 if (amdgpu_dm_is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 4224 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4225 dc_stream_adjust_vmin_vmax( 4226 dm->dc, acrtc_state->stream, 4227 &acrtc_attach->dm_irq_params.vrr_params.adjust); 4228 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4229 } 4230 mutex_lock(&dm->dc_lock); 4231 /* 4232 * Tearing (immediate) flips cannot work with panel self-refresh 4233 * features. The event is cleared by 4234 * amdgpu_dm_enable_self_refresh() once async flips stop. 4235 */ 4236 if (immediate_flip) { 4237 dc_exit_ips_for_hw_access(dm->dc); 4238 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, true, 4239 psr_event_immediate_flip, true); 4240 amdgpu_dm_replay_set_event(dm, acrtc_state->stream, true, 4241 replay_event_immediate_flip, true); 4242 } 4243 update_planes_and_stream_adapter(dm->dc, 4244 planes_count, 4245 acrtc_state->stream, 4246 stream_update_needed ? &bundle->stream_update : NULL, 4247 bundle->surface_updates); 4248 updated_planes_and_streams = true; 4249 4250 /** 4251 * Enable or disable the interrupts on the backend. 4252 * 4253 * Most pipes are put into power gating when unused. 4254 * 4255 * When power gating is enabled on a pipe we lose the 4256 * interrupt enablement state when power gating is disabled. 4257 * 4258 * So we need to update the IRQ control state in hardware 4259 * whenever the pipe turns on (since it could be previously 4260 * power gated) or off (since some pipes can't be power gated 4261 * on some ASICs). 4262 */ 4263 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 4264 dm_update_pflip_irq_state(drm_to_adev(dev), 4265 acrtc_attach); 4266 amdgpu_dm_enable_self_refresh(dm, acrtc_attach, acrtc_state, 4267 timestamp_ns); 4268 mutex_unlock(&dm->dc_lock); 4269 } 4270 4271 /* 4272 * Update cursor state *after* programming all the planes. 4273 * This avoids redundant programming in the case where we're going 4274 * to be disabling a single plane - those pipes are being disabled. 4275 */ 4276 if (acrtc_state->active_planes && 4277 (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) && 4278 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 4279 amdgpu_dm_commit_cursors(state); 4280 4281 /* 4282 * DCN specific vblank handling 4283 * ============================ 4284 * 4285 * With the event_lock held, arm the vblank event, and determine whether 4286 * deliver it immediately, or in VUPDATE_NO_LOCK IRQ (i.e. HW latch 4287 * point) handler. Do this *after* programming so that the IRQ handler 4288 * will not deliver the event before HW laches onto the programmed 4289 * values: 4290 * 4291 * Commit thread IRQ handler HW 4292 * ----------------------------------------------------------------- 4293 * arm_vblank_event() 4294 * vupdate() 4295 * vupdate_handler() 4296 * cook_timestamp() 4297 * # prev flip already latched, 4298 * # so flip_latched == true. 4299 * if event_armed && flip_latched: 4300 * send_vblank_event() 4301 * # sent before latch, **BAD!** 4302 * hw_program() 4303 * vupdate() 4304 * **latch** 4305 * 4306 * There's a consequence of arming after: it's possible for HW to latch 4307 * between start of HW programming and acrtc->event/pflip_status arming. 4308 * When this happens, the IRQ handler will send the event on the next 4309 * immediate latch point, even though HW has already latched. This is 4310 * handled by optimistically checking for HW latch after programming, 4311 * and if latched, send the event immediately: 4312 * 4313 * Commit thread IRQ handler HW 4314 * ----------------------------------------------------------------- 4315 * hw_program() 4316 * vupdate() 4317 * **latch** 4318 * vupdate_handler() 4319 * cook_timestamp() 4320 * # event_armed == false 4321 * # **no event sent!** 4322 * arm_vblank_event() 4323 * if flip_latched: 4324 * **send_vblank_event()** 4325 * disarm_vblank_event() 4326 * 4327 * The IRQ handler is expected to cook the timestamp, but we need to 4328 * cook the timestamp before optimistic sending as well. That's because 4329 * the following sequence is possible: 4330 * 4331 * Commit thread IRQ handler HW 4332 * ----------------------------------------------------------------- 4333 * hw_program() 4334 * arm_vblank_event() 4335 * vupdate() 4336 * **latch** 4337 * if flip_latched: 4338 * # Need cook before send! 4339 * **cook_timestamp()** 4340 * send_vblank_event() 4341 * disarm_vblank_event() 4342 * vupdate_handler() 4343 * cook_timestamp() 4344 * # event_armed == false 4345 * # no event sent! 4346 * 4347 * Cooking twice is OK, since DRM scanout accurate timestamps report A) 4348 * the previous vactive start if currently in vactive, or B) the next 4349 * vactive start if currently in vblank (see &get_vblank_counter). 'A)' 4350 * is what we want for the optimistic send, and for 'B)', we'll cook a 4351 * timestamp no later than the next IRQ handler run. 4352 * 4353 * The more correct fix is to wrap programming and arming with the 4354 * event_lock and thus serializing it with the IRQ handler. However, 4355 * there are various sleep-waits within 4356 * update_planes_and_stream_adapter() that makes spin locking illegal. 4357 * And on full updates, it can take 1-2 frame-times to return (see 4358 * commit_planes_for_stream). 4359 * 4360 * On DCE, GRPH_PFLIP IRQ is used and takes care of this. 4361 */ 4362 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) { 4363 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4364 4365 if (updated_planes_and_streams) { 4366 flip_latched_during_prog = 4367 !dc_get_flip_pending_on_otg(dm->dc, acrtc_attach->otg_inst); 4368 } 4369 4370 dm_arm_vblank_event(acrtc_attach, acrtc_state, 4371 pflip_present, cursor_update); 4372 4373 /* 4374 * Deliver the event immediately on immediate flip, or on a 4375 * update that has already latched. 4376 */ 4377 if ((immediate_flip || flip_latched_during_prog) && 4378 acrtc_attach->pflip_status == AMDGPU_FLIP_SUBMITTED && 4379 acrtc_attach->event) { 4380 drm_crtc_accurate_vblank_count(&acrtc_attach->base); 4381 drm_crtc_send_vblank_event(&acrtc_attach->base, 4382 acrtc_attach->event); 4383 acrtc_attach->event = NULL; 4384 drm_crtc_vblank_put(&acrtc_attach->base); 4385 acrtc_attach->pflip_status = AMDGPU_FLIP_NONE; 4386 } 4387 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4388 } 4389 4390 cleanup: 4391 kfree(bundle); 4392 } 4393 4394 /* 4395 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 4396 * @crtc_state: the DRM CRTC state 4397 * @stream_state: the DC stream state. 4398 * 4399 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 4400 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 4401 */ 4402 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 4403 struct dc_stream_state *stream_state) 4404 { 4405 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 4406 } 4407 4408 /** 4409 * amdgpu_dm_crtc_complete_writeback - finish a pending writeback job 4410 * @acrtc: the CRTC whose pending writeback should be completed 4411 * 4412 * Clears the pending state, signals the writeback out fence and releases the 4413 * vblank reference taken in dm_set_writeback() while the writeback was armed. 4414 * The pending flag is tested and cleared under the writeback job lock, so this 4415 * is safe to call concurrently from the completion vblank IRQ 4416 * (dm_crtc_high_irq()) and from the writeback teardown path 4417 * (dm_clear_writeback()); only the caller that observes the pending job 4418 * performs the completion. 4419 * 4420 * Return: true if a pending writeback job was completed by this call. 4421 */ 4422 bool amdgpu_dm_crtc_complete_writeback(struct amdgpu_crtc *acrtc) 4423 { 4424 unsigned long flags; 4425 bool pending; 4426 4427 if (!acrtc->wb_conn) 4428 return false; 4429 4430 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); 4431 pending = acrtc->wb_pending; 4432 acrtc->wb_pending = false; 4433 acrtc->wb_frame_done = false; 4434 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 4435 4436 if (!pending) 4437 return false; 4438 4439 drm_writeback_signal_completion(acrtc->wb_conn, 0); 4440 drm_crtc_vblank_put(&acrtc->base); 4441 4442 return true; 4443 } 4444 EXPORT_IF_KUNIT(amdgpu_dm_crtc_complete_writeback); 4445 4446 STATIC_IFN_KUNIT void dm_clear_writeback(struct amdgpu_display_manager *dm, 4447 struct amdgpu_crtc *acrtc, 4448 struct dm_crtc_state *crtc_state) 4449 { 4450 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); 4451 4452 /* 4453 * If the writeback is still pending when it is torn down (its 4454 * completion vblank IRQ never fired), signal the out fence so a 4455 * waiting client does not stall and release the vblank reference 4456 * taken in dm_set_writeback(). 4457 */ 4458 amdgpu_dm_crtc_complete_writeback(acrtc); 4459 } 4460 EXPORT_IF_KUNIT(dm_clear_writeback); 4461 4462 /** 4463 * amdgpu_dm_mod_power_update_streams - update mod_power stream state on modeset 4464 * @state: the drm atomic state 4465 * @dm: the display manager to update mod_power on 4466 * 4467 * Notify mod_power of stream changes on modeset events, and disable PSR/Replay 4468 * in preparation for hardware programming. See also 4469 * amdgpu_dm_mod_power_setup_streams() for post-modeset mod_power setup. 4470 */ 4471 STATIC_IFN_KUNIT void amdgpu_dm_mod_power_update_streams(struct drm_atomic_commit *state, 4472 struct amdgpu_display_manager *dm) 4473 { 4474 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4475 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4476 struct amdgpu_dm_connector *aconnector; 4477 struct drm_crtc *crtc; 4478 int i = 0; 4479 4480 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4481 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4482 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4483 4484 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4485 continue; 4486 4487 /* 4488 * Update mod_power on modeset event in preparation for hw 4489 * programming. Always use the old stream, since it would have 4490 * been previously added to mod_power. If old stream is null (on 4491 * crtc enable, for example), mod_power will no-op, which is the 4492 * desried behavior. 4493 */ 4494 if (old_crtc_state->active) { 4495 scoped_guard(mutex, &dm->dc_lock) { 4496 dc_exit_ips_for_hw_access(dm->dc); 4497 amdgpu_dm_psr_set_event(dm, dm_old_crtc_state->stream, true, 4498 psr_event_hw_programming, true); 4499 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true, 4500 replay_event_hw_programming, true); 4501 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, false, 4502 replay_event_general_ui, false); 4503 } 4504 } 4505 4506 if (new_crtc_state->active) { 4507 aconnector = (struct amdgpu_dm_connector *) 4508 dm_new_crtc_state->stream->dm_stream_context; 4509 if (old_crtc_state->active) { 4510 mod_power_replace_stream(dm->power_module, 4511 dm_old_crtc_state->stream, 4512 dm_new_crtc_state->stream, 4513 &aconnector->psr_caps); 4514 } else { 4515 mod_power_add_stream(dm->power_module, 4516 dm_new_crtc_state->stream, 4517 &aconnector->psr_caps); 4518 } 4519 } else if (old_crtc_state->active) { 4520 mod_power_remove_stream(dm->power_module, 4521 dm_old_crtc_state->stream); 4522 } 4523 } 4524 } 4525 EXPORT_IF_KUNIT(amdgpu_dm_mod_power_update_streams); 4526 4527 /** 4528 * amdgpu_dm_mod_power_setup_streams - setup mod_power stream state post modeset 4529 * @state: the drm atomic state 4530 * @dm: the display manager to update mod_power on 4531 * 4532 * Notify mod_power of mode_change. This needs to be done after dc_stream 4533 * updates have been committed, and VRR parameters have been updated. 4534 */ 4535 STATIC_IFN_KUNIT void amdgpu_dm_mod_power_setup_streams(struct drm_atomic_commit *state, 4536 struct amdgpu_display_manager *dm) 4537 { 4538 struct dm_crtc_state *dm_new_crtc_state; 4539 struct drm_crtc_state *new_crtc_state; 4540 struct amdgpu_crtc *acrtc; 4541 struct drm_crtc *crtc; 4542 int i = 0; 4543 4544 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4545 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4546 acrtc = to_amdgpu_crtc(crtc); 4547 4548 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4549 continue; 4550 4551 if (new_crtc_state->active) { 4552 amdgpu_dm_link_setup_replay(dm_new_crtc_state->stream, 4553 &acrtc->dm_irq_params.vrr_params); 4554 mod_power_notify_mode_change(dm->power_module, 4555 dm_new_crtc_state->stream, 4556 false); 4557 4558 /* 4559 * Block PSR / Replay on the new stream until display settles post-modeset. 4560 * These events will be cleared by amdgpu_dm_enable_self_refresh() once 4561 * allow_sr_entry becomes true. 4562 */ 4563 amdgpu_dm_psr_set_event(dm, dm_new_crtc_state->stream, true, 4564 psr_event_hw_programming, true); 4565 4566 amdgpu_dm_replay_set_event(dm, dm_new_crtc_state->stream, true, 4567 replay_event_hw_programming | replay_event_general_ui, 4568 true); 4569 } 4570 } 4571 4572 } 4573 EXPORT_IF_KUNIT(amdgpu_dm_mod_power_setup_streams); 4574 4575 static void amdgpu_dm_commit_streams(struct drm_atomic_commit *state, 4576 struct dc_state *dc_state) 4577 { 4578 struct drm_device *dev = state->dev; 4579 struct amdgpu_device *adev = drm_to_adev(dev); 4580 struct amdgpu_display_manager *dm = &adev->dm; 4581 struct drm_crtc *crtc; 4582 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4583 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4584 struct drm_connector_state *old_con_state; 4585 struct drm_connector *connector; 4586 bool mode_set_reset_required = false; 4587 u32 i; 4588 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 4589 bool set_backlight_level = false; 4590 4591 /* Disable writeback */ 4592 for_each_old_connector_in_state(state, connector, old_con_state, i) { 4593 struct dm_connector_state *dm_old_con_state; 4594 struct amdgpu_crtc *acrtc; 4595 4596 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 4597 continue; 4598 4599 old_crtc_state = NULL; 4600 4601 dm_old_con_state = to_dm_connector_state(old_con_state); 4602 if (!dm_old_con_state->base.crtc) 4603 continue; 4604 4605 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); 4606 if (acrtc) 4607 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4608 4609 if (!acrtc || !acrtc->wb_enabled) 4610 continue; 4611 4612 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4613 4614 dm_clear_writeback(dm, acrtc, dm_old_crtc_state); 4615 acrtc->wb_enabled = false; 4616 } 4617 4618 amdgpu_dm_mod_power_update_streams(state, dm); 4619 4620 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 4621 new_crtc_state, i) { 4622 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4623 4624 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4625 4626 if (old_crtc_state->active && 4627 (!new_crtc_state->active || 4628 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 4629 manage_dm_interrupts(adev, acrtc, NULL); 4630 /* 4631 * ISM hysteresis lives on system_dfl_wq, not the 4632 * vblank workqueue. Wait it out so a timer armed while 4633 * the stream existed cannot allow idle after the 4634 * stream is released. 4635 */ 4636 amdgpu_dm_ism_flush(&acrtc->ism); 4637 dc_stream_release(dm_old_crtc_state->stream); 4638 } 4639 } 4640 4641 drm_atomic_helper_calc_timestamping_constants(state); 4642 4643 /* update changed items */ 4644 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4645 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4646 4647 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4648 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4649 4650 drm_dbg_state(state->dev, 4651 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 4652 acrtc->crtc_id, 4653 new_crtc_state->enable, 4654 new_crtc_state->active, 4655 new_crtc_state->planes_changed, 4656 new_crtc_state->mode_changed, 4657 new_crtc_state->active_changed, 4658 new_crtc_state->connectors_changed); 4659 4660 /* Disable cursor if disabling crtc */ 4661 if (old_crtc_state->active && !new_crtc_state->active) { 4662 struct dc_cursor_position position; 4663 4664 memset(&position, 0, sizeof(position)); 4665 mutex_lock(&dm->dc_lock); 4666 dc_exit_ips_for_hw_access(dm->dc); 4667 dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position); 4668 mutex_unlock(&dm->dc_lock); 4669 } 4670 4671 /* Copy all transient state flags into dc state */ 4672 if (dm_new_crtc_state->stream) { 4673 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 4674 dm_new_crtc_state->stream); 4675 } 4676 4677 /* handles headless hotplug case, updating new_state and 4678 * aconnector as needed 4679 */ 4680 4681 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 4682 4683 drm_dbg_atomic(dev, 4684 "Atomic commit: SET crtc id %d: [%p]\n", 4685 acrtc->crtc_id, acrtc); 4686 4687 if (!dm_new_crtc_state->stream) { 4688 /* 4689 * this could happen because of issues with 4690 * userspace notifications delivery. 4691 * In this case userspace tries to set mode on 4692 * display which is disconnected in fact. 4693 * dc_sink is NULL in this case on aconnector. 4694 * We expect reset mode will come soon. 4695 * 4696 * This can also happen when unplug is done 4697 * during resume sequence ended 4698 * 4699 * In this case, we want to pretend we still 4700 * have a sink to keep the pipe running so that 4701 * hw state is consistent with the sw state 4702 */ 4703 drm_dbg_atomic(dev, 4704 "Failed to create new stream for crtc %d\n", 4705 acrtc->base.base.id); 4706 continue; 4707 } 4708 4709 if (dm_old_crtc_state->stream) 4710 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4711 4712 pm_runtime_get_noresume(dev->dev); 4713 4714 acrtc->enabled = true; 4715 acrtc->hw_mode = new_crtc_state->mode; 4716 crtc->hwmode = new_crtc_state->mode; 4717 mode_set_reset_required = true; 4718 set_backlight_level = true; 4719 } else if (modereset_required(new_crtc_state)) { 4720 drm_dbg_atomic(dev, 4721 "Atomic commit: RESET. crtc id %d:[%p]\n", 4722 acrtc->crtc_id, acrtc); 4723 /* i.e. reset mode */ 4724 if (dm_old_crtc_state->stream) 4725 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4726 4727 mode_set_reset_required = true; 4728 } 4729 } /* for_each_crtc_in_state() */ 4730 4731 /* if there mode set or reset, flush vblank work queue */ 4732 if (mode_set_reset_required) { 4733 if (dm->vblank_control_workqueue) 4734 flush_workqueue(dm->vblank_control_workqueue); 4735 } 4736 4737 dm_enable_per_frame_crtc_master_sync(dc_state); 4738 mutex_lock(&dm->dc_lock); 4739 dc_exit_ips_for_hw_access(dm->dc); 4740 WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); 4741 4742 bool frl_stream_found = false; 4743 4744 for (i = 0; i < params.stream_count; i++) { 4745 struct dc_stream_state *stream = params.streams[i]; 4746 4747 if (stream->signal == SIGNAL_TYPE_HDMI_FRL) { 4748 frl_stream_found = true; 4749 break; 4750 } 4751 } 4752 if (frl_stream_found) { 4753 if (queue_delayed_work(dm->hdmi_frl_status_polling_wq, 4754 &dm->hdmi_frl_status_polling_work, 4755 msecs_to_jiffies(dm->hdmi_frl_status_polling_delay_ms))) 4756 drm_dbg_kms(dev, "200ms frl status polling starts ...\n"); 4757 } else { 4758 if (cancel_delayed_work_sync(&dm->hdmi_frl_status_polling_work)) 4759 drm_dbg_kms(dev, "200ms frl status polling stops ...\n"); 4760 } 4761 /* Allow idle optimization when vblank count is 0 for display off */ 4762 if ((dm->active_vblank_irq_count == 0) && amdgpu_dm_is_headless(dm->adev)) 4763 dc_allow_idle_optimizations(dm->dc, true); 4764 mutex_unlock(&dm->dc_lock); 4765 4766 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4767 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4768 4769 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4770 4771 if (dm_new_crtc_state->stream != NULL) { 4772 const struct dc_stream_status *status = 4773 dc_stream_get_status(dm_new_crtc_state->stream); 4774 4775 if (!status) 4776 status = dc_state_get_stream_status(dc_state, 4777 dm_new_crtc_state->stream); 4778 if (!status) 4779 drm_err(dev, 4780 "got no status for stream %p on acrtc%p\n", 4781 dm_new_crtc_state->stream, acrtc); 4782 else 4783 acrtc->otg_inst = status->primary_otg_inst; 4784 } 4785 } 4786 4787 /* During boot up and resume the DC layer will reset the panel brightness 4788 * to fix a flicker issue. 4789 * It will cause the dm->actual_brightness is not the current panel brightness 4790 * level. (the dm->brightness is the correct panel level) 4791 * So we set the backlight level with dm->brightness value after set mode 4792 */ 4793 if (set_backlight_level) { 4794 for (i = 0; i < dm->num_of_edps; i++) { 4795 if (dm->backlight_dev[i]) 4796 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 4797 } 4798 } 4799 } 4800 4801 STATIC_IFN_KUNIT void 4802 dm_set_writeback(struct amdgpu_display_manager *dm, 4803 struct dm_crtc_state *crtc_state, 4804 struct drm_connector *connector, 4805 struct drm_connector_state *new_con_state) 4806 { 4807 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); 4808 struct amdgpu_device *adev = dm->adev; 4809 struct amdgpu_crtc *acrtc; 4810 struct dc_writeback_info *wb_info; 4811 struct pipe_ctx *pipe = NULL; 4812 struct amdgpu_framebuffer *afb; 4813 int i = 0; 4814 4815 wb_info = kzalloc_obj(*wb_info); 4816 if (!wb_info) { 4817 drm_err(adev_to_drm(adev), "Failed to allocate wb_info\n"); 4818 goto cleanup; 4819 } 4820 4821 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); 4822 if (!acrtc) { 4823 drm_err(adev_to_drm(adev), "no amdgpu_crtc found\n"); 4824 goto cleanup; 4825 } 4826 4827 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); 4828 if (!afb) { 4829 drm_err(adev_to_drm(adev), "No amdgpu_framebuffer found\n"); 4830 goto cleanup; 4831 } 4832 4833 for (i = 0; i < MAX_PIPES; i++) { 4834 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { 4835 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; 4836 break; 4837 } 4838 } 4839 4840 if (!pipe) { 4841 drm_err(adev_to_drm(adev), "No pipe found for stream\n"); 4842 goto cleanup; 4843 } 4844 4845 /* fill in wb_info */ 4846 wb_info->wb_enabled = true; 4847 4848 wb_info->dwb_pipe_inst = 0; 4849 wb_info->dwb_params.dwbscl_black_color = 0; 4850 wb_info->dwb_params.hdr_mult = 0x1F000; 4851 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; 4852 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; 4853 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; 4854 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; 4855 4856 /* width & height from crtc */ 4857 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; 4858 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; 4859 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; 4860 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; 4861 4862 wb_info->dwb_params.cnv_params.crop_en = false; 4863 wb_info->dwb_params.stereo_params.stereo_enabled = false; 4864 4865 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits 4866 wb_info->dwb_params.cnv_params.out_min_pix_val = 0; 4867 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; 4868 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; 4869 4870 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; 4871 4872 wb_info->dwb_params.capture_rate = dwb_capture_rate_0; 4873 4874 wb_info->dwb_params.scaler_taps.h_taps = 1; 4875 wb_info->dwb_params.scaler_taps.v_taps = 1; 4876 wb_info->dwb_params.scaler_taps.h_taps_c = 1; 4877 wb_info->dwb_params.scaler_taps.v_taps_c = 1; 4878 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; 4879 4880 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; 4881 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; 4882 4883 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { 4884 wb_info->mcif_buf_params.luma_address[i] = afb->address; 4885 wb_info->mcif_buf_params.chroma_address[i] = 0; 4886 } 4887 4888 wb_info->mcif_buf_params.p_vmid = 1; 4889 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) { 4890 wb_info->mcif_warmup_params.start_address.quad_part = afb->address; 4891 wb_info->mcif_warmup_params.region_size = 4892 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; 4893 } 4894 wb_info->mcif_warmup_params.p_vmid = 1; 4895 wb_info->writeback_source_plane = pipe->plane_state; 4896 4897 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); 4898 4899 acrtc->wb_conn = wb_conn; 4900 drm_writeback_queue_job(wb_conn, new_con_state); 4901 4902 /* 4903 * Writeback completion is detected in the CRTC vblank IRQ 4904 * (dm_crtc_high_irq()). Take a vblank reference so the vblank interrupt 4905 * stays enabled while the writeback is pending; otherwise a 4906 * writeback-only commit right after drm_crtc_vblank_on() (e.g. 4907 * re-enabling a CRTC that was disabled) has no other vblank reference, 4908 * the IRQ never fires and the out fence times out. The matching put 4909 * happens once completion is signalled in dm_crtc_high_irq(), or when 4910 * the writeback is torn down in dm_clear_writeback(). 4911 * 4912 * Arm wb_pending only after the reference is held so the completion IRQ 4913 * cannot run its matching vblank_put before this get. 4914 */ 4915 WARN_ON(drm_crtc_vblank_get(&acrtc->base)); 4916 acrtc->wb_frame_done = false; 4917 acrtc->wb_pending = true; 4918 4919 cleanup: 4920 kfree(wb_info); 4921 } 4922 EXPORT_IF_KUNIT(dm_set_writeback); 4923 4924 STATIC_IFN_KUNIT void amdgpu_dm_update_hdcp(struct drm_atomic_commit *state) 4925 { 4926 struct drm_connector_state *old_con_state, *new_con_state; 4927 struct drm_device *dev = state->dev; 4928 struct drm_connector *connector; 4929 struct amdgpu_device *adev = drm_to_adev(dev); 4930 int i; 4931 4932 if (!adev->dm.hdcp_workqueue) 4933 return; 4934 4935 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 4936 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 4937 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 4938 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4939 struct dm_crtc_state *dm_new_crtc_state; 4940 struct amdgpu_dm_connector *aconnector; 4941 4942 if (!connector || connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 4943 continue; 4944 4945 aconnector = to_amdgpu_dm_connector(connector); 4946 4947 drm_dbg(dev, "[HDCP_DM] -------------- i : %x ----------\n", i); 4948 4949 drm_dbg(dev, "[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 4950 connector->index, connector->status, connector->dpms); 4951 drm_dbg(dev, "[HDCP_DM] state protection old: %x new: %x\n", 4952 old_con_state->content_protection, new_con_state->content_protection); 4953 4954 if (aconnector->dc_sink) { 4955 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 4956 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 4957 drm_dbg(dev, "[HDCP_DM] pipe_ctx dispname=%s\n", 4958 aconnector->dc_sink->edid_caps.display_name); 4959 } 4960 } 4961 4962 new_crtc_state = NULL; 4963 old_crtc_state = NULL; 4964 4965 if (acrtc) { 4966 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 4967 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4968 } 4969 4970 if (old_crtc_state) 4971 drm_dbg(dev, "old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 4972 old_crtc_state->enable, 4973 old_crtc_state->active, 4974 old_crtc_state->mode_changed, 4975 old_crtc_state->active_changed, 4976 old_crtc_state->connectors_changed); 4977 4978 if (new_crtc_state) 4979 drm_dbg(dev, "NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 4980 new_crtc_state->enable, 4981 new_crtc_state->active, 4982 new_crtc_state->mode_changed, 4983 new_crtc_state->active_changed, 4984 new_crtc_state->connectors_changed); 4985 4986 4987 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4988 4989 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 4990 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 4991 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 4992 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 4993 dm_new_con_state->update_hdcp = true; 4994 continue; 4995 } 4996 4997 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 4998 old_con_state, connector, adev->dm.hdcp_workqueue)) { 4999 /* when display is unplugged from mst hub, connctor will 5000 * be destroyed within dm_dp_mst_connector_destroy. connector 5001 * hdcp perperties, like type, undesired, desired, enabled, 5002 * will be lost. So, save hdcp properties into hdcp_work within 5003 * amdgpu_dm_atomic_commit_tail. if the same display is 5004 * plugged back with same display index, its hdcp properties 5005 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 5006 */ 5007 5008 bool enable_encryption = false; 5009 5010 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 5011 enable_encryption = true; 5012 5013 if (aconnector->dc_link && aconnector->dc_sink && 5014 aconnector->dc_link->type == dc_connection_mst_branch) { 5015 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 5016 struct hdcp_workqueue *hdcp_w = 5017 &hdcp_work[aconnector->dc_link->link_index]; 5018 5019 hdcp_w->hdcp_content_type[connector->index] = 5020 new_con_state->hdcp_content_type; 5021 hdcp_w->content_protection[connector->index] = 5022 new_con_state->content_protection; 5023 } 5024 5025 if (new_crtc_state && new_crtc_state->mode_changed && 5026 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 5027 enable_encryption = true; 5028 5029 drm_info(dev, "[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 5030 5031 if (aconnector->dc_link) 5032 hdcp_update_display( 5033 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 5034 new_con_state->hdcp_content_type, enable_encryption); 5035 } 5036 } 5037 } 5038 EXPORT_IF_KUNIT(amdgpu_dm_update_hdcp); 5039 5040 STATIC_IFN_KUNIT int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state) 5041 { 5042 struct drm_crtc *crtc; 5043 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5044 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5045 int i, ret; 5046 5047 ret = drm_dp_mst_atomic_setup_commit(state); 5048 if (ret) 5049 return ret; 5050 5051 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5052 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5053 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5054 /* 5055 * Color management settings. We also update color properties 5056 * when a modeset is needed, to ensure it gets reprogrammed. 5057 */ 5058 if (dm_new_crtc_state->base.active && dm_new_crtc_state->stream && 5059 (dm_new_crtc_state->base.color_mgmt_changed || 5060 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 5061 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5062 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 5063 if (ret) { 5064 drm_dbg_atomic(state->dev, "Failed to update color state\n"); 5065 return ret; 5066 } 5067 } 5068 } 5069 5070 return 0; 5071 } 5072 EXPORT_IF_KUNIT(amdgpu_dm_atomic_setup_commit); 5073 5074 STATIC_IFN_KUNIT void set_multisync_trigger_params( 5075 struct dc_stream_state *stream) 5076 { 5077 struct dc_stream_state *master = NULL; 5078 5079 if (stream->triggered_crtc_reset.enabled) { 5080 master = stream->triggered_crtc_reset.event_source; 5081 stream->triggered_crtc_reset.event = 5082 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 5083 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 5084 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 5085 } 5086 } 5087 EXPORT_IF_KUNIT(set_multisync_trigger_params); 5088 5089 STATIC_IFN_KUNIT void set_master_stream(struct dc_stream_state *stream_set[], 5090 int stream_count) 5091 { 5092 int j, highest_rfr = 0, master_stream = 0; 5093 5094 for (j = 0; j < stream_count; j++) { 5095 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 5096 int refresh_rate = 0; 5097 5098 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 5099 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 5100 if (refresh_rate > highest_rfr) { 5101 highest_rfr = refresh_rate; 5102 master_stream = j; 5103 } 5104 } 5105 } 5106 for (j = 0; j < stream_count; j++) { 5107 if (stream_set[j]) 5108 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 5109 } 5110 } 5111 EXPORT_IF_KUNIT(set_master_stream); 5112 5113 STATIC_IFN_KUNIT void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 5114 { 5115 int i = 0; 5116 struct dc_stream_state *stream; 5117 5118 if (context->stream_count < 2) 5119 return; 5120 for (i = 0; i < context->stream_count ; i++) { 5121 if (!context->streams[i]) 5122 continue; 5123 /* 5124 * TODO: add a function to read AMD VSDB bits and set 5125 * crtc_sync_master.multi_sync_enabled flag 5126 * For now it's set to false 5127 */ 5128 } 5129 5130 set_master_stream(context->streams, context->stream_count); 5131 5132 for (i = 0; i < context->stream_count ; i++) { 5133 stream = context->streams[i]; 5134 5135 if (!stream) 5136 continue; 5137 5138 set_multisync_trigger_params(stream); 5139 } 5140 } 5141 EXPORT_IF_KUNIT(dm_enable_per_frame_crtc_master_sync); 5142 5143 /** 5144 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 5145 * @state: The atomic state to commit 5146 * 5147 * This will tell DC to commit the constructed DC state from atomic_check, 5148 * programming the hardware. Any failures here implies a hardware failure, since 5149 * atomic check should have filtered anything non-kosher. 5150 */ 5151 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state) 5152 { 5153 struct drm_device *dev = state->dev; 5154 struct amdgpu_device *adev = drm_to_adev(dev); 5155 struct amdgpu_display_manager *dm = &adev->dm; 5156 struct dm_atomic_state *dm_state; 5157 struct dc_state *dc_state = NULL; 5158 u32 i, j; 5159 struct drm_crtc *crtc; 5160 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5161 unsigned long flags; 5162 bool wait_for_vblank = true; 5163 struct drm_connector *connector; 5164 struct drm_connector_state *old_con_state = NULL, *new_con_state = NULL; 5165 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5166 int crtc_disable_count = 0; 5167 5168 trace_amdgpu_dm_atomic_commit_tail_begin(state); 5169 5170 drm_atomic_helper_update_legacy_modeset_state(dev, state); 5171 drm_dp_mst_atomic_wait_for_dependencies(state); 5172 5173 dm_state = dm_atomic_get_new_state(state); 5174 if (dm_state && dm_state->context) { 5175 dc_state = dm_state->context; 5176 amdgpu_dm_commit_streams(state, dc_state); 5177 } 5178 5179 amdgpu_dm_update_hdcp(state); 5180 5181 /* Handle connector state changes */ 5182 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5183 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5184 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 5185 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5186 struct dc_surface_update *dummy_updates; 5187 struct dc_stream_update stream_update; 5188 struct dc_info_packet hdr_packet; 5189 struct dc_stream_status *status = NULL; 5190 bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false; 5191 5192 memset(&stream_update, 0, sizeof(stream_update)); 5193 5194 if (acrtc) { 5195 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5196 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 5197 } 5198 5199 /* Skip any modesets/resets */ 5200 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 5201 continue; 5202 5203 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5204 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5205 5206 scaling_changed = is_scaling_state_different(dm_new_con_state, 5207 dm_old_con_state); 5208 5209 if ((new_con_state->hdmi.broadcast_rgb != old_con_state->hdmi.broadcast_rgb) && 5210 (dm_old_crtc_state->stream->output_color_space != 5211 amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state))) 5212 output_color_space_changed = true; 5213 5214 abm_changed = dm_new_crtc_state->abm_level != 5215 dm_old_crtc_state->abm_level; 5216 5217 hdr_changed = 5218 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 5219 5220 if (!scaling_changed && !abm_changed && !hdr_changed && !output_color_space_changed) 5221 continue; 5222 5223 stream_update.stream = dm_new_crtc_state->stream; 5224 if (scaling_changed) { 5225 amdgpu_dm_update_stream_scaling_settings(dev, &dm_new_con_state->base.crtc->mode, 5226 dm_new_con_state, dm_new_crtc_state->stream); 5227 5228 stream_update.src = dm_new_crtc_state->stream->src; 5229 stream_update.dst = dm_new_crtc_state->stream->dst; 5230 } 5231 5232 if (output_color_space_changed) { 5233 dm_new_crtc_state->stream->output_color_space 5234 = amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state); 5235 5236 stream_update.output_color_space = &dm_new_crtc_state->stream->output_color_space; 5237 } 5238 5239 if (abm_changed) { 5240 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 5241 5242 stream_update.abm_level = &dm_new_crtc_state->abm_level; 5243 } 5244 5245 if (hdr_changed) { 5246 amdgpu_dm_fill_hdr_info_packet(new_con_state, &hdr_packet); 5247 stream_update.hdr_static_metadata = &hdr_packet; 5248 } 5249 5250 status = dc_stream_get_status(dm_new_crtc_state->stream); 5251 5252 if (WARN_ON(!status)) 5253 continue; 5254 5255 WARN_ON(!status->plane_count); 5256 5257 /* 5258 * TODO: DC refuses to perform stream updates without a dc_surface_update. 5259 * Here we create an empty update on each plane. 5260 * To fix this, DC should permit updating only stream properties. 5261 */ 5262 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_KERNEL); 5263 if (!dummy_updates) { 5264 drm_err(adev_to_drm(adev), "Failed to allocate memory for dummy_updates.\n"); 5265 continue; 5266 } 5267 for (j = 0; j < status->plane_count; j++) 5268 dummy_updates[j].surface = status->plane_states[j]; 5269 5270 sort(dummy_updates, status->plane_count, 5271 sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL); 5272 5273 mutex_lock(&dm->dc_lock); 5274 dc_exit_ips_for_hw_access(dm->dc); 5275 dc_update_planes_and_stream(dm->dc, 5276 dummy_updates, 5277 status->plane_count, 5278 dm_new_crtc_state->stream, 5279 &stream_update); 5280 mutex_unlock(&dm->dc_lock); 5281 kfree(dummy_updates); 5282 5283 drm_connector_update_privacy_screen(new_con_state); 5284 } 5285 5286 /** 5287 * Enable interrupts for CRTCs that are newly enabled or went through 5288 * a modeset. It was intentionally deferred until after the front end 5289 * state was modified to wait until the OTG was on and so the IRQ 5290 * handlers didn't access stale or invalid state. 5291 */ 5292 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5293 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5294 #ifdef CONFIG_DEBUG_FS 5295 enum amdgpu_dm_pipe_crc_source cur_crc_src; 5296 #endif 5297 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 5298 if (old_crtc_state->active && !new_crtc_state->active) 5299 crtc_disable_count++; 5300 5301 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5302 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5303 5304 /* For freesync config update on crtc state and params for irq */ 5305 amdgpu_dm_update_stream_irq_parameters(dm, dm_new_crtc_state); 5306 5307 #ifdef CONFIG_DEBUG_FS 5308 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5309 cur_crc_src = acrtc->dm_irq_params.crc_src; 5310 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5311 #endif 5312 5313 if (new_crtc_state->active && 5314 (!old_crtc_state->active || 5315 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5316 dc_stream_retain(dm_new_crtc_state->stream); 5317 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 5318 manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); 5319 } 5320 /* Handle vrr on->off / off->on transitions */ 5321 amdgpu_dm_handle_vrr_transition(dm, dm_old_crtc_state, dm_new_crtc_state); 5322 5323 #ifdef CONFIG_DEBUG_FS 5324 if (new_crtc_state->active && 5325 (!old_crtc_state->active || 5326 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5327 /** 5328 * Frontend may have changed so reapply the CRC capture 5329 * settings for the stream. 5330 */ 5331 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 5332 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 5333 if (amdgpu_dm_crc_window_is_activated(crtc)) { 5334 uint8_t cnt; 5335 5336 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5337 for (cnt = 0; cnt < MAX_CRC_WINDOW_NUM; cnt++) { 5338 if (acrtc->dm_irq_params.window_param[cnt].enable) { 5339 acrtc->dm_irq_params.window_param[cnt].update_win = true; 5340 5341 /** 5342 * It takes 2 frames for HW to stably generate CRC when 5343 * resuming from suspend, so we set skip_frame_cnt 2. 5344 */ 5345 acrtc->dm_irq_params.window_param[cnt].skip_frame_cnt = 2; 5346 } 5347 } 5348 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5349 } 5350 #endif 5351 if (amdgpu_dm_crtc_configure_crc_source( 5352 crtc, dm_new_crtc_state, cur_crc_src)) 5353 drm_dbg_atomic(dev, "Failed to configure crc source"); 5354 } 5355 } 5356 #endif 5357 } 5358 5359 amdgpu_dm_mod_power_setup_streams(state, dm); 5360 5361 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 5362 if (new_crtc_state->async_flip) 5363 wait_for_vblank = false; 5364 5365 /* update planes when needed per crtc*/ 5366 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 5367 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5368 5369 if (dm_new_crtc_state->stream) 5370 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 5371 } 5372 5373 /* Enable writeback */ 5374 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5375 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5376 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5377 5378 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5379 continue; 5380 5381 if (!new_con_state->writeback_job) 5382 continue; 5383 5384 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5385 5386 if (!new_crtc_state) 5387 continue; 5388 5389 if (acrtc->wb_enabled) 5390 continue; 5391 5392 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5393 5394 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); 5395 acrtc->wb_enabled = true; 5396 } 5397 5398 /* Update audio instances for each connector. */ 5399 amdgpu_dm_commit_audio(dev, state); 5400 5401 /* restore the backlight level */ 5402 for (i = 0; i < dm->num_of_edps; i++) { 5403 if (dm->backlight_dev[i] && 5404 (dm->actual_brightness[i] != dm->brightness[i])) 5405 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 5406 } 5407 5408 /* 5409 * send vblank event on all events not handled in flip and 5410 * mark consumed event for drm_atomic_helper_commit_hw_done 5411 */ 5412 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5413 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5414 5415 if (new_crtc_state->event) 5416 drm_send_event_locked(dev, &new_crtc_state->event->base); 5417 5418 new_crtc_state->event = NULL; 5419 } 5420 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5421 5422 /* Signal HW programming completion */ 5423 drm_atomic_helper_commit_hw_done(state); 5424 5425 if (wait_for_vblank) 5426 drm_atomic_helper_wait_for_flip_done(dev, state); 5427 5428 drm_atomic_helper_cleanup_planes(dev, state); 5429 5430 /* Don't free the memory if we are hitting this as part of suspend. 5431 * This way we don't free any memory during suspend; see 5432 * amdgpu_bo_free_kernel(). The memory will be freed in the first 5433 * non-suspend modeset or when the driver is torn down. 5434 */ 5435 if (!adev->in_suspend) { 5436 /* return the stolen vga memory back to VRAM */ 5437 if (!adev->mman.keep_stolen_vga_memory) 5438 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_VGA); 5439 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_EXTENDED); 5440 } 5441 5442 /* 5443 * Finally, drop a runtime PM reference for each newly disabled CRTC, 5444 * so we can put the GPU into runtime suspend if we're not driving any 5445 * displays anymore 5446 */ 5447 for (i = 0; i < crtc_disable_count; i++) 5448 pm_runtime_put_autosuspend(dev->dev); 5449 pm_runtime_mark_last_busy(dev->dev); 5450 5451 trace_amdgpu_dm_atomic_commit_tail_finish(state); 5452 } 5453 5454 /* 5455 * Grabs all modesetting locks to serialize against any blocking commits, 5456 * Waits for completion of all non blocking commits. 5457 */ 5458 STATIC_IFN_KUNIT int do_aquire_global_lock(struct drm_device *dev, 5459 struct drm_atomic_commit *state) 5460 { 5461 struct drm_crtc *crtc; 5462 struct drm_crtc_commit *commit; 5463 long ret; 5464 5465 /* 5466 * Adding all modeset locks to aquire_ctx will 5467 * ensure that when the framework release it the 5468 * extra locks we are locking here will get released to 5469 */ 5470 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 5471 if (ret) 5472 return ret; 5473 5474 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5475 spin_lock(&crtc->commit_lock); 5476 commit = list_first_entry_or_null(&crtc->commit_list, 5477 struct drm_crtc_commit, commit_entry); 5478 if (commit) 5479 drm_crtc_commit_get(commit); 5480 spin_unlock(&crtc->commit_lock); 5481 5482 if (!commit) 5483 continue; 5484 5485 /* 5486 * Make sure all pending HW programming completed and 5487 * page flips done 5488 */ 5489 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 5490 5491 if (ret > 0) 5492 ret = wait_for_completion_interruptible_timeout( 5493 &commit->flip_done, 10*HZ); 5494 5495 if (ret == 0) 5496 drm_err(dev, "[CRTC:%d:%s] hw_done or flip_done timed out\n", 5497 crtc->base.id, crtc->name); 5498 5499 drm_crtc_commit_put(commit); 5500 } 5501 5502 return ret < 0 ? ret : 0; 5503 } 5504 EXPORT_IF_KUNIT(do_aquire_global_lock); 5505 5506 STATIC_IFN_KUNIT int dm_update_crtc_state(struct amdgpu_display_manager *dm, 5507 struct drm_atomic_commit *state, 5508 struct drm_crtc *crtc, 5509 struct drm_crtc_state *old_crtc_state, 5510 struct drm_crtc_state *new_crtc_state, 5511 bool enable, 5512 bool *needs_dc_state_realloc) 5513 { 5514 struct dm_atomic_state *dm_state = NULL; 5515 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5516 struct dc_stream_state *new_stream; 5517 struct amdgpu_device *adev = dm->adev; 5518 int ret = 0; 5519 5520 /* 5521 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 5522 * update changed items 5523 */ 5524 struct amdgpu_crtc *acrtc = NULL; 5525 struct drm_connector *connector = NULL; 5526 struct amdgpu_dm_connector *aconnector = NULL; 5527 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 5528 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 5529 5530 new_stream = NULL; 5531 5532 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5533 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5534 acrtc = to_amdgpu_crtc(crtc); 5535 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 5536 if (connector) 5537 aconnector = to_amdgpu_dm_connector(connector); 5538 5539 /* TODO This hack should go away */ 5540 if (connector && enable) { 5541 /* Make sure fake sink is created in plug-in scenario */ 5542 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 5543 connector); 5544 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 5545 connector); 5546 5547 if (WARN_ON(!drm_new_conn_state)) { 5548 ret = -EINVAL; 5549 goto fail; 5550 } 5551 5552 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 5553 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 5554 5555 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5556 goto skip_modeset; 5557 5558 new_stream = amdgpu_dm_create_validate_stream_for_sink(connector, 5559 &new_crtc_state->mode, 5560 dm_new_conn_state, 5561 dm_old_crtc_state->stream); 5562 5563 /* 5564 * we can have no stream on ACTION_SET if a display 5565 * was disconnected during S3, in this case it is not an 5566 * error, the OS will be updated after detection, and 5567 * will do the right thing on next atomic commit 5568 */ 5569 5570 if (!new_stream) { 5571 drm_dbg_driver(adev_to_drm(adev), "%s: Failed to create new stream for crtc %d\n", 5572 __func__, acrtc->base.base.id); 5573 ret = -ENOMEM; 5574 goto fail; 5575 } 5576 5577 /* 5578 * TODO: Check VSDB bits to decide whether this should 5579 * be enabled or not. 5580 */ 5581 new_stream->triggered_crtc_reset.enabled = 5582 dm->force_timing_sync; 5583 5584 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5585 5586 ret = amdgpu_dm_fill_hdr_info_packet(drm_new_conn_state, 5587 &new_stream->hdr_static_metadata); 5588 if (ret) 5589 goto fail; 5590 5591 /* 5592 * If we already removed the old stream from the context 5593 * (and set the new stream to NULL) then we can't reuse 5594 * the old stream even if the stream and scaling are unchanged. 5595 * We'll hit the BUG_ON and black screen. 5596 * 5597 * TODO: Refactor this function to allow this check to work 5598 * in all conditions. 5599 */ 5600 if (amdgpu_freesync_vid_mode && 5601 dm_new_crtc_state->stream && 5602 amdgpu_dm_is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 5603 goto skip_modeset; 5604 5605 if (dm_new_crtc_state->stream && 5606 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5607 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 5608 new_crtc_state->mode_changed = false; 5609 drm_dbg_driver(adev_to_drm(adev), "Mode change not required, setting mode_changed to %d", 5610 new_crtc_state->mode_changed); 5611 } 5612 } 5613 5614 /* mode_changed flag may get updated above, need to check again */ 5615 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5616 goto skip_modeset; 5617 5618 drm_dbg_state(state->dev, 5619 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 5620 acrtc->crtc_id, 5621 new_crtc_state->enable, 5622 new_crtc_state->active, 5623 new_crtc_state->planes_changed, 5624 new_crtc_state->mode_changed, 5625 new_crtc_state->active_changed, 5626 new_crtc_state->connectors_changed); 5627 5628 /* Remove stream for any changed/disabled CRTC */ 5629 if (!enable) { 5630 5631 if (!dm_old_crtc_state->stream) 5632 goto skip_modeset; 5633 5634 /* Unset freesync video if it was active before */ 5635 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 5636 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 5637 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 5638 } 5639 5640 /* Now check if we should set freesync video mode */ 5641 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 5642 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5643 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 5644 amdgpu_dm_is_timing_unchanged_for_freesync(new_crtc_state, 5645 old_crtc_state)) { 5646 new_crtc_state->mode_changed = false; 5647 drm_dbg_driver(adev_to_drm(adev), 5648 "Mode change not required for front porch change, setting mode_changed to %d", 5649 new_crtc_state->mode_changed); 5650 5651 amdgpu_dm_set_freesync_fixed_config(dm_new_crtc_state); 5652 5653 goto skip_modeset; 5654 } else if (amdgpu_freesync_vid_mode && aconnector && 5655 amdgpu_dm_is_freesync_video_mode(&new_crtc_state->mode, 5656 aconnector)) { 5657 struct drm_display_mode *high_mode; 5658 5659 high_mode = amdgpu_dm_get_highest_refresh_rate_mode(aconnector, false); 5660 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 5661 amdgpu_dm_set_freesync_fixed_config(dm_new_crtc_state); 5662 } 5663 5664 ret = dm_atomic_get_state(state, &dm_state); 5665 if (ret) 5666 goto fail; 5667 5668 drm_dbg_driver(adev_to_drm(adev), "Disabling DRM crtc: %d\n", 5669 crtc->base.id); 5670 5671 /* i.e. reset mode */ 5672 if (dc_state_remove_stream( 5673 dm->dc, 5674 dm_state->context, 5675 dm_old_crtc_state->stream) != DC_OK) { 5676 ret = -EINVAL; 5677 goto fail; 5678 } 5679 5680 dc_stream_release(dm_old_crtc_state->stream); 5681 dm_new_crtc_state->stream = NULL; 5682 5683 amdgpu_dm_reset_freesync_config_for_crtc(dm_new_crtc_state); 5684 5685 *needs_dc_state_realloc = true; 5686 5687 } else {/* Add stream for any updated/enabled CRTC */ 5688 /* 5689 * Quick fix to prevent NULL pointer on new_stream when 5690 * added MST connectors not found in existing crtc_state in the chained mode 5691 * TODO: need to dig out the root cause of that 5692 */ 5693 if (!connector) 5694 goto skip_modeset; 5695 5696 if (modereset_required(new_crtc_state)) 5697 goto skip_modeset; 5698 5699 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 5700 dm_old_crtc_state->stream)) { 5701 5702 WARN_ON(dm_new_crtc_state->stream); 5703 5704 ret = dm_atomic_get_state(state, &dm_state); 5705 if (ret) 5706 goto fail; 5707 5708 dm_new_crtc_state->stream = new_stream; 5709 5710 dc_stream_retain(new_stream); 5711 5712 drm_dbg_atomic(adev_to_drm(adev), "Enabling DRM crtc: %d\n", 5713 crtc->base.id); 5714 5715 if (dc_state_add_stream( 5716 dm->dc, 5717 dm_state->context, 5718 dm_new_crtc_state->stream) != DC_OK) { 5719 ret = -EINVAL; 5720 goto fail; 5721 } 5722 5723 *needs_dc_state_realloc = true; 5724 } 5725 } 5726 5727 skip_modeset: 5728 /* Release extra reference */ 5729 if (new_stream) { 5730 dc_stream_release(new_stream); 5731 new_stream = NULL; 5732 } 5733 new_stream = NULL; 5734 5735 /* 5736 * We want to do dc stream updates that do not require a 5737 * full modeset below. 5738 */ 5739 if (!(enable && connector && new_crtc_state->active)) 5740 return 0; 5741 /* 5742 * Given above conditions, the dc state cannot be NULL because: 5743 * 1. We're in the process of enabling CRTCs (just been added 5744 * to the dc context, or already is on the context) 5745 * 2. Has a valid connector attached, and 5746 * 3. Is currently active and enabled. 5747 * => The dc stream state currently exists. 5748 */ 5749 BUG_ON(dm_new_crtc_state->stream == NULL); 5750 5751 /* Scaling or underscan settings */ 5752 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 5753 drm_atomic_crtc_needs_modeset(new_crtc_state)) 5754 amdgpu_dm_update_stream_scaling_settings(adev_to_drm(adev), 5755 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 5756 5757 /* ABM settings */ 5758 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5759 5760 /* 5761 * Color management settings. We also update color properties 5762 * when a modeset is needed, to ensure it gets reprogrammed. 5763 */ 5764 if (dm_new_crtc_state->base.color_mgmt_changed || 5765 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 5766 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 5767 ret = amdgpu_dm_check_crtc_color_mgmt(dm_new_crtc_state, true); 5768 if (ret) 5769 goto fail; 5770 } 5771 5772 /* Update Freesync settings. */ 5773 amdgpu_dm_get_freesync_config_for_crtc(dm_new_crtc_state, 5774 dm_new_conn_state); 5775 5776 return ret; 5777 5778 fail: 5779 if (new_stream) 5780 dc_stream_release(new_stream); 5781 return ret; 5782 } 5783 EXPORT_IF_KUNIT(dm_update_crtc_state); 5784 5785 STATIC_IFN_KUNIT bool should_reset_plane(struct drm_atomic_commit *state, 5786 struct drm_plane *plane, 5787 struct drm_plane_state *old_plane_state, 5788 struct drm_plane_state *new_plane_state) 5789 { 5790 struct drm_plane *other; 5791 struct drm_plane_state *old_other_state, *new_other_state; 5792 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5793 struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; 5794 struct amdgpu_device *adev = drm_to_adev(plane->dev); 5795 struct drm_connector_state *new_con_state; 5796 struct drm_connector *connector; 5797 int i; 5798 5799 /* 5800 * TODO: Remove this hack for all asics once it proves that the 5801 * fast updates works fine on DCN3.2+. 5802 */ 5803 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && 5804 state->allow_modeset) 5805 return true; 5806 5807 /* Check for writeback commit */ 5808 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5809 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5810 continue; 5811 5812 if (new_con_state->writeback_job) 5813 return true; 5814 } 5815 5816 if (amdgpu_in_reset(adev) && state->allow_modeset) 5817 return true; 5818 5819 /* Exit early if we know that we're adding or removing the plane. */ 5820 if (old_plane_state->crtc != new_plane_state->crtc) 5821 return true; 5822 5823 /* old crtc == new_crtc == NULL, plane not in context. */ 5824 if (!new_plane_state->crtc) 5825 return false; 5826 5827 new_crtc_state = 5828 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 5829 old_crtc_state = 5830 drm_atomic_get_old_crtc_state(state, old_plane_state->crtc); 5831 5832 if (!new_crtc_state) 5833 return true; 5834 5835 /* 5836 * A change in cursor mode means a new dc pipe needs to be acquired or 5837 * released from the state 5838 */ 5839 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 5840 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 5841 if (plane->type == DRM_PLANE_TYPE_CURSOR && 5842 old_dm_crtc_state != NULL && 5843 old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) { 5844 return true; 5845 } 5846 5847 /* CRTC Degamma changes currently require us to recreate planes. */ 5848 if (new_crtc_state->color_mgmt_changed) 5849 return true; 5850 5851 /* Plane color pipeline or its colorop changes. */ 5852 if (new_plane_state->color_mgmt_changed) 5853 return true; 5854 5855 /* 5856 * On zpos change, planes need to be reordered by removing and re-adding 5857 * them one by one to the dc state, in order of descending zpos. 5858 * 5859 * TODO: We can likely skip bandwidth validation if the only thing that 5860 * changed about the plane was it'z z-ordering. 5861 */ 5862 if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos) 5863 return true; 5864 5865 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 5866 return true; 5867 5868 /* 5869 * If there are any new primary or overlay planes being added or 5870 * removed then the z-order can potentially change. To ensure 5871 * correct z-order and pipe acquisition the current DC architecture 5872 * requires us to remove and recreate all existing planes. 5873 * 5874 * TODO: Come up with a more elegant solution for this. 5875 */ 5876 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 5877 struct amdgpu_framebuffer *old_afb, *new_afb; 5878 struct dm_plane_state *dm_new_other_state, *dm_old_other_state; 5879 5880 dm_new_other_state = to_dm_plane_state(new_other_state); 5881 dm_old_other_state = to_dm_plane_state(old_other_state); 5882 5883 if (other->type == DRM_PLANE_TYPE_CURSOR) 5884 continue; 5885 5886 if (old_other_state->crtc != new_plane_state->crtc && 5887 new_other_state->crtc != new_plane_state->crtc) 5888 continue; 5889 5890 if (old_other_state->crtc != new_other_state->crtc) 5891 return true; 5892 5893 /* Src/dst size and scaling updates. */ 5894 if (old_other_state->src_w != new_other_state->src_w || 5895 old_other_state->src_h != new_other_state->src_h || 5896 old_other_state->crtc_w != new_other_state->crtc_w || 5897 old_other_state->crtc_h != new_other_state->crtc_h) 5898 return true; 5899 5900 /* Rotation / mirroring updates. */ 5901 if (old_other_state->rotation != new_other_state->rotation) 5902 return true; 5903 5904 /* Blending updates. */ 5905 if (old_other_state->pixel_blend_mode != 5906 new_other_state->pixel_blend_mode) 5907 return true; 5908 5909 /* Alpha updates. */ 5910 if (old_other_state->alpha != new_other_state->alpha) 5911 return true; 5912 5913 /* Colorspace changes. */ 5914 if (old_other_state->color_range != new_other_state->color_range || 5915 old_other_state->color_encoding != new_other_state->color_encoding) 5916 return true; 5917 5918 /* HDR/Transfer Function changes. */ 5919 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf || 5920 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut || 5921 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || 5922 dm_old_other_state->ctm != dm_new_other_state->ctm || 5923 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut || 5924 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf || 5925 dm_old_other_state->lut3d != dm_new_other_state->lut3d || 5926 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut || 5927 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf) 5928 return true; 5929 5930 /* Framebuffer checks fall at the end. */ 5931 if (!old_other_state->fb || !new_other_state->fb) 5932 continue; 5933 5934 /* Pixel format changes can require bandwidth updates. */ 5935 if (old_other_state->fb->format != new_other_state->fb->format) 5936 return true; 5937 5938 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 5939 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 5940 5941 /* Tiling and DCC changes also require bandwidth updates. */ 5942 if (old_afb->base.modifier != new_afb->base.modifier) 5943 return true; 5944 } 5945 5946 return false; 5947 } 5948 EXPORT_IF_KUNIT(should_reset_plane); 5949 5950 STATIC_IFN_KUNIT int 5951 dm_update_plane_state(struct dc *dc, 5952 struct drm_atomic_commit *state, 5953 struct drm_plane *plane, 5954 struct drm_plane_state *old_plane_state, 5955 struct drm_plane_state *new_plane_state, 5956 bool enable, 5957 bool *needs_dc_state_realloc, 5958 bool *is_top_most_overlay) 5959 { 5960 5961 struct dm_atomic_state *dm_state = NULL; 5962 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 5963 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5964 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 5965 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 5966 bool needs_reset, update_native_cursor; 5967 int ret = 0; 5968 5969 5970 new_plane_crtc = new_plane_state->crtc; 5971 old_plane_crtc = old_plane_state->crtc; 5972 dm_new_plane_state = to_dm_plane_state(new_plane_state); 5973 dm_old_plane_state = to_dm_plane_state(old_plane_state); 5974 5975 update_native_cursor = amdgpu_dm_should_update_native_cursor(state, 5976 old_plane_crtc, 5977 new_plane_crtc, 5978 enable); 5979 5980 if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) { 5981 ret = amdgpu_dm_check_native_cursor_state(new_plane_crtc, plane, 5982 new_plane_state, enable); 5983 if (ret) 5984 return ret; 5985 5986 return 0; 5987 } 5988 5989 needs_reset = should_reset_plane(state, plane, old_plane_state, 5990 new_plane_state); 5991 5992 /* Remove any changed/removed planes */ 5993 if (!enable) { 5994 if (!needs_reset) 5995 return 0; 5996 5997 if (!old_plane_crtc) 5998 return 0; 5999 6000 old_crtc_state = drm_atomic_get_old_crtc_state( 6001 state, old_plane_crtc); 6002 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6003 6004 if (!dm_old_crtc_state->stream) 6005 return 0; 6006 6007 drm_dbg_atomic(old_plane_crtc->dev, "Disabling DRM plane: %d on DRM crtc %d\n", 6008 plane->base.id, old_plane_crtc->base.id); 6009 6010 ret = dm_atomic_get_state(state, &dm_state); 6011 if (ret) 6012 return ret; 6013 6014 if (!dc_state_remove_plane( 6015 dc, 6016 dm_old_crtc_state->stream, 6017 dm_old_plane_state->dc_state, 6018 dm_state->context)) { 6019 6020 return -EINVAL; 6021 } 6022 6023 if (dm_old_plane_state->dc_state) 6024 dc_plane_state_release(dm_old_plane_state->dc_state); 6025 6026 dm_new_plane_state->dc_state = NULL; 6027 6028 *needs_dc_state_realloc = true; 6029 6030 } else { /* Add new planes */ 6031 struct dc_plane_state *dc_new_plane_state; 6032 6033 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 6034 return 0; 6035 6036 if (!new_plane_crtc) 6037 return 0; 6038 6039 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 6040 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6041 6042 if (!dm_new_crtc_state->stream) 6043 return 0; 6044 6045 if (!needs_reset) 6046 return 0; 6047 6048 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 6049 if (ret) 6050 goto out; 6051 6052 /* 6053 * Recreating the plane re-derives its DC color pipeline from the 6054 * colorop states in this commit. Pull the plane's colorops in so 6055 * the derivation sees the current pipeline; otherwise every stage 6056 * silently defaults to bypass (dropping YUV->RGB, shaper, 3D LUT 6057 * and regamma) when userspace didn't touch color in this commit. 6058 */ 6059 if (new_plane_state->color_pipeline) { 6060 ret = drm_atomic_add_affected_colorops(state, plane); 6061 if (ret) 6062 goto out; 6063 } 6064 6065 WARN_ON(dm_new_plane_state->dc_state); 6066 6067 dc_new_plane_state = dc_create_plane_state(dc); 6068 if (!dc_new_plane_state) { 6069 ret = -ENOMEM; 6070 goto out; 6071 } 6072 6073 drm_dbg_atomic(new_plane_crtc->dev, "Enabling DRM plane: %d on DRM crtc %d\n", 6074 plane->base.id, new_plane_crtc->base.id); 6075 6076 ret = fill_dc_plane_attributes( 6077 drm_to_adev(new_plane_crtc->dev), 6078 dc_new_plane_state, 6079 new_plane_state, 6080 new_crtc_state); 6081 if (ret) { 6082 dc_plane_state_release(dc_new_plane_state); 6083 goto out; 6084 } 6085 6086 ret = dm_atomic_get_state(state, &dm_state); 6087 if (ret) { 6088 dc_plane_state_release(dc_new_plane_state); 6089 goto out; 6090 } 6091 6092 /* 6093 * Any atomic check errors that occur after this will 6094 * not need a release. The plane state will be attached 6095 * to the stream, and therefore part of the atomic 6096 * state. It'll be released when the atomic state is 6097 * cleaned. 6098 */ 6099 if (!dc_state_add_plane( 6100 dc, 6101 dm_new_crtc_state->stream, 6102 dc_new_plane_state, 6103 dm_state->context)) { 6104 6105 dc_plane_state_release(dc_new_plane_state); 6106 ret = -EINVAL; 6107 goto out; 6108 } 6109 6110 dm_new_plane_state->dc_state = dc_new_plane_state; 6111 6112 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 6113 6114 /* Tell DC to do a full surface update every time there 6115 * is a plane change. Inefficient, but works for now. 6116 */ 6117 dm_new_plane_state->dc_state->update_bits.full_update = 1; 6118 6119 *needs_dc_state_realloc = true; 6120 } 6121 6122 out: 6123 /* If enabling cursor overlay failed, attempt fallback to native mode */ 6124 if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) { 6125 ret = amdgpu_dm_check_native_cursor_state(new_plane_crtc, plane, 6126 new_plane_state, enable); 6127 if (ret) 6128 return ret; 6129 6130 dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE; 6131 } 6132 6133 return ret; 6134 } 6135 EXPORT_IF_KUNIT(dm_update_plane_state); 6136 6137 /* 6138 * The normalized_zpos value cannot be used by this iterator directly. It's only 6139 * calculated for enabled planes, potentially causing normalized_zpos collisions 6140 * between enabled/disabled planes in the atomic state. We need a unique value 6141 * so that the iterator will not generate the same object twice, or loop 6142 * indefinitely. 6143 */ 6144 struct __drm_planes_state *amdgpu_dm_get_next_zpos( 6145 struct drm_atomic_commit *state, 6146 struct __drm_planes_state *prev) 6147 { 6148 unsigned int highest_zpos = 0, prev_zpos = 256; 6149 uint32_t highest_id = 0, prev_id = UINT_MAX; 6150 struct drm_plane_state *new_plane_state; 6151 struct drm_plane *plane; 6152 int i, highest_i = -1; 6153 6154 if (prev != NULL) { 6155 prev_zpos = prev->new_state->zpos; 6156 prev_id = prev->ptr->base.id; 6157 } 6158 6159 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 6160 /* Skip planes with higher zpos than the previously returned */ 6161 if (new_plane_state->zpos > prev_zpos || 6162 (new_plane_state->zpos == prev_zpos && 6163 plane->base.id >= prev_id)) 6164 continue; 6165 6166 /* Save the index of the plane with highest zpos */ 6167 if (new_plane_state->zpos > highest_zpos || 6168 (new_plane_state->zpos == highest_zpos && 6169 plane->base.id > highest_id)) { 6170 highest_zpos = new_plane_state->zpos; 6171 highest_id = plane->base.id; 6172 highest_i = i; 6173 } 6174 } 6175 6176 if (highest_i < 0) 6177 return NULL; 6178 6179 return &state->planes[highest_i]; 6180 } 6181 6182 STATIC_IFN_KUNIT int add_affected_mst_dsc_crtcs(struct drm_atomic_commit *state, 6183 struct drm_crtc *crtc) 6184 { 6185 struct drm_connector *connector; 6186 struct drm_connector_state *conn_state, *old_conn_state; 6187 struct amdgpu_dm_connector *aconnector = NULL; 6188 int i; 6189 6190 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 6191 if (!conn_state->crtc) 6192 conn_state = old_conn_state; 6193 6194 if (conn_state->crtc != crtc) 6195 continue; 6196 6197 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 6198 continue; 6199 6200 aconnector = to_amdgpu_dm_connector(connector); 6201 if (!aconnector->mst_output_port || !aconnector->mst_root) 6202 aconnector = NULL; 6203 else 6204 break; 6205 } 6206 6207 if (!aconnector) 6208 return 0; 6209 6210 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 6211 } 6212 EXPORT_IF_KUNIT(add_affected_mst_dsc_crtcs); 6213 6214 STATIC_IFN_KUNIT bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev, 6215 struct drm_atomic_commit *state, 6216 struct drm_crtc_state *crtc_state) 6217 { 6218 struct drm_plane *plane; 6219 struct drm_plane_state *new_plane_state, *old_plane_state; 6220 6221 drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) { 6222 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 6223 old_plane_state = drm_atomic_get_old_plane_state(state, plane); 6224 6225 if (!old_plane_state || !new_plane_state) 6226 continue; 6227 6228 if (old_plane_state->fb && new_plane_state->fb && 6229 get_mem_type(old_plane_state->fb) != get_mem_type(new_plane_state->fb)) 6230 return true; 6231 } 6232 6233 return false; 6234 } 6235 EXPORT_IF_KUNIT(amdgpu_dm_crtc_mem_type_changed); 6236 6237 /** 6238 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 6239 * 6240 * @dev: The DRM device 6241 * @state: The atomic state to commit 6242 * 6243 * Validate that the given atomic state is programmable by DC into hardware. 6244 * This involves constructing a &struct dc_state reflecting the new hardware 6245 * state we wish to commit, then querying DC to see if it is programmable. It's 6246 * important not to modify the existing DC state. Otherwise, atomic_check 6247 * may unexpectedly commit hardware changes. 6248 * 6249 * When validating the DC state, it's important that the right locks are 6250 * acquired. For full updates case which removes/adds/updates streams on one 6251 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 6252 * that any such full update commit will wait for completion of any outstanding 6253 * flip using DRMs synchronization events. 6254 * 6255 * Note that DM adds the affected connectors for all CRTCs in state, when that 6256 * might not seem necessary. This is because DC stream creation requires the 6257 * DC sink, which is tied to the DRM connector state. Cleaning this up should 6258 * be possible but non-trivial - a possible TODO item. 6259 * 6260 * Return: -Error code if validation failed. 6261 */ 6262 STATIC_IFN_KUNIT int amdgpu_dm_atomic_check(struct drm_device *dev, 6263 struct drm_atomic_commit *state) 6264 { 6265 struct amdgpu_device *adev = drm_to_adev(dev); 6266 struct dm_atomic_state *dm_state = NULL; 6267 struct dc *dc = adev->dm.dc; 6268 struct drm_connector *connector; 6269 struct drm_connector_state *old_con_state, *new_con_state; 6270 struct drm_crtc *crtc; 6271 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6272 struct drm_plane *plane; 6273 struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state; 6274 enum dc_status status; 6275 int ret, i; 6276 bool needs_dc_state_realloc = false; 6277 bool is_top_most_overlay = true; 6278 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6279 struct drm_dp_mst_topology_mgr *mgr; 6280 struct drm_dp_mst_topology_state *mst_state; 6281 struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; 6282 6283 trace_amdgpu_dm_atomic_check_begin(state); 6284 6285 ret = drm_atomic_helper_check_modeset(dev, state); 6286 if (ret) { 6287 drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed: %pe\n", ERR_PTR(ret)); 6288 goto fail; 6289 } 6290 6291 /* Check connector changes */ 6292 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6293 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6294 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6295 6296 /* Skip connectors that are disabled or part of modeset already. */ 6297 if (!new_con_state->crtc) 6298 continue; 6299 6300 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 6301 if (IS_ERR(new_crtc_state)) { 6302 drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed: %pe\n", new_crtc_state); 6303 ret = PTR_ERR(new_crtc_state); 6304 goto fail; 6305 } 6306 6307 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 6308 dm_old_con_state->scaling != dm_new_con_state->scaling) 6309 new_crtc_state->connectors_changed = true; 6310 } 6311 6312 if (dc_resource_is_dsc_encoding_supported(dc)) { 6313 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6314 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6315 dm_new_crtc_state->mode_changed_independent_from_dsc = new_crtc_state->mode_changed; 6316 } 6317 6318 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6319 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 6320 ret = add_affected_mst_dsc_crtcs(state, crtc); 6321 if (ret) { 6322 drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed: %pe\n", ERR_PTR(ret)); 6323 goto fail; 6324 } 6325 } 6326 } 6327 } 6328 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6329 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6330 6331 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 6332 !new_crtc_state->color_mgmt_changed && 6333 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 6334 dm_old_crtc_state->dsc_force_changed == false) 6335 continue; 6336 6337 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 6338 if (ret) { 6339 drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed: %pe\n", ERR_PTR(ret)); 6340 goto fail; 6341 } 6342 6343 if (!new_crtc_state->enable) 6344 continue; 6345 6346 ret = drm_atomic_add_affected_connectors(state, crtc); 6347 if (ret) { 6348 drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed: %pe\n", ERR_PTR(ret)); 6349 goto fail; 6350 } 6351 6352 ret = drm_atomic_add_affected_planes(state, crtc); 6353 if (ret) { 6354 drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed: %pe\n", ERR_PTR(ret)); 6355 goto fail; 6356 } 6357 6358 if (dm_old_crtc_state->dsc_force_changed) 6359 new_crtc_state->mode_changed = true; 6360 } 6361 6362 /* 6363 * Add all primary and overlay planes on the CRTC to the state 6364 * whenever a plane is enabled to maintain correct z-ordering 6365 * and to enable fast surface updates. 6366 */ 6367 drm_for_each_crtc(crtc, dev) { 6368 bool modified = false; 6369 6370 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 6371 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6372 continue; 6373 6374 if (new_plane_state->crtc == crtc || 6375 old_plane_state->crtc == crtc) { 6376 modified = true; 6377 break; 6378 } 6379 } 6380 6381 if (!modified) 6382 continue; 6383 6384 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 6385 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6386 continue; 6387 6388 new_plane_state = 6389 drm_atomic_get_plane_state(state, plane); 6390 6391 if (IS_ERR(new_plane_state)) { 6392 ret = PTR_ERR(new_plane_state); 6393 drm_dbg_atomic(dev, "new_plane_state is BAD: %pe\n", new_plane_state); 6394 goto fail; 6395 } 6396 } 6397 } 6398 6399 /* 6400 * DC consults the zpos (layer_index in DC terminology) to determine the 6401 * hw plane on which to enable the hw cursor (see 6402 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 6403 * atomic state, so call drm helper to normalize zpos. 6404 */ 6405 ret = drm_atomic_normalize_zpos(dev, state); 6406 if (ret) { 6407 drm_dbg(dev, "drm_atomic_normalize_zpos() failed: %pe\n", ERR_PTR(ret)); 6408 goto fail; 6409 } 6410 6411 /* 6412 * Determine whether cursors on each CRTC should be enabled in native or 6413 * overlay mode. 6414 */ 6415 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6416 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6417 6418 ret = amdgpu_dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 6419 &dm_new_crtc_state->cursor_mode); 6420 if (ret) { 6421 drm_dbg(dev, "Failed to determine cursor mode: %pe\n", ERR_PTR(ret)); 6422 goto fail; 6423 } 6424 6425 /* 6426 * If overlay cursor is needed, DC cannot go through the 6427 * native cursor update path. All enabled planes on the CRTC 6428 * need to be added for DC to not disable a plane by mistake 6429 */ 6430 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) { 6431 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { 6432 drm_dbg(dev, "Overlay cursor not supported on DCE\n"); 6433 ret = -EINVAL; 6434 goto fail; 6435 } 6436 6437 ret = drm_atomic_add_affected_planes(state, crtc); 6438 if (ret) 6439 goto fail; 6440 } 6441 } 6442 6443 /* Remove exiting planes if they are modified */ 6444 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 6445 6446 ret = dm_update_plane_state(dc, state, plane, 6447 old_plane_state, 6448 new_plane_state, 6449 false, 6450 &needs_dc_state_realloc, 6451 &is_top_most_overlay); 6452 if (ret) { 6453 drm_dbg_atomic(dev, "dm_update_plane_state() failed: %pe\n", ERR_PTR(ret)); 6454 goto fail; 6455 } 6456 } 6457 6458 /* Disable all crtcs which require disable */ 6459 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6460 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6461 old_crtc_state, 6462 new_crtc_state, 6463 false, 6464 &needs_dc_state_realloc); 6465 if (ret) { 6466 drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed: %pe\n", ERR_PTR(ret)); 6467 goto fail; 6468 } 6469 } 6470 6471 /* Enable all crtcs which require enable */ 6472 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6473 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6474 old_crtc_state, 6475 new_crtc_state, 6476 true, 6477 &needs_dc_state_realloc); 6478 if (ret) { 6479 drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed: %pe\n", ERR_PTR(ret)); 6480 goto fail; 6481 } 6482 } 6483 6484 /* Add new/modified planes */ 6485 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 6486 ret = dm_update_plane_state(dc, state, plane, 6487 old_plane_state, 6488 new_plane_state, 6489 true, 6490 &needs_dc_state_realloc, 6491 &is_top_most_overlay); 6492 if (ret) { 6493 drm_dbg_atomic(dev, "dm_update_plane_state() failed: %pe\n", ERR_PTR(ret)); 6494 goto fail; 6495 } 6496 } 6497 6498 #if defined(CONFIG_DRM_AMD_DC_FP) 6499 if (dc_resource_is_dsc_encoding_supported(dc)) { 6500 ret = pre_validate_dsc(state, &dm_state, vars); 6501 if (ret != 0) 6502 goto fail; 6503 } 6504 #endif 6505 6506 /* Run this here since we want to validate the streams we created */ 6507 ret = drm_atomic_helper_check_planes(dev, state); 6508 if (ret) { 6509 drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed: %pe\n", ERR_PTR(ret)); 6510 goto fail; 6511 } 6512 6513 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6514 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6515 if (dm_new_crtc_state->mpo_requested) 6516 drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); 6517 } 6518 6519 /* Check cursor restrictions */ 6520 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6521 enum amdgpu_dm_cursor_mode required_cursor_mode; 6522 int is_rotated, is_scaled; 6523 6524 /* Overlay cusor not subject to native cursor restrictions */ 6525 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6526 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) 6527 continue; 6528 6529 /* Check if rotation or scaling is enabled on DCN 4x and above */ 6530 if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) && 6531 (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1))) { 6532 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); 6533 6534 is_rotated = new_cursor_state && 6535 ((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0); 6536 is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) || 6537 (new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h)); 6538 6539 if (is_rotated || is_scaled) { 6540 drm_dbg_driver( 6541 crtc->dev, 6542 "[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n", 6543 crtc->base.id, crtc->name); 6544 ret = -EINVAL; 6545 goto fail; 6546 } 6547 } 6548 6549 /* If HW can only do native cursor, check restrictions again */ 6550 ret = amdgpu_dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 6551 &required_cursor_mode); 6552 if (ret) { 6553 drm_dbg_driver(crtc->dev, 6554 "[CRTC:%d:%s] Checking cursor mode failed\n", 6555 crtc->base.id, crtc->name); 6556 goto fail; 6557 } else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) { 6558 drm_dbg_driver(crtc->dev, 6559 "[CRTC:%d:%s] Cannot enable native cursor due to scaling, YUV, or color pipeline restrictions\n", 6560 crtc->base.id, crtc->name); 6561 ret = -EINVAL; 6562 goto fail; 6563 } 6564 } 6565 6566 if (state->legacy_cursor_update) { 6567 /* 6568 * This is a fast cursor update coming from the plane update 6569 * helper, check if it can be done asynchronously for better 6570 * performance. 6571 */ 6572 state->async_update = 6573 !drm_atomic_helper_async_check(dev, state); 6574 6575 /* 6576 * Skip the remaining global validation if this is an async 6577 * update. Cursor updates can be done without affecting 6578 * state or bandwidth calcs and this avoids the performance 6579 * penalty of locking the private state object and 6580 * allocating a new dc_state. 6581 */ 6582 if (state->async_update) 6583 return 0; 6584 } 6585 6586 /* Check scaling and underscan changes*/ 6587 /* TODO Removed scaling changes validation due to inability to commit 6588 * new stream into context w\o causing full reset. Need to 6589 * decide how to handle. 6590 */ 6591 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6592 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6593 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6594 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 6595 6596 /* Skip any modesets/resets */ 6597 if (!acrtc || drm_atomic_crtc_needs_modeset( 6598 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 6599 continue; 6600 6601 /* Skip any thing not scale or underscan changes */ 6602 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 6603 continue; 6604 6605 needs_dc_state_realloc = true; 6606 } 6607 6608 /* set the slot info for each mst_state based on the link encoding format */ 6609 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 6610 struct amdgpu_dm_connector *aconnector; 6611 struct drm_connector *connector; 6612 struct drm_connector_list_iter iter; 6613 u8 link_coding_cap; 6614 6615 drm_connector_list_iter_begin(dev, &iter); 6616 drm_for_each_connector_iter(connector, &iter) { 6617 if (connector->index == mst_state->mgr->conn_base_id) { 6618 aconnector = to_amdgpu_dm_connector(connector); 6619 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 6620 drm_dp_mst_update_slots(mst_state, link_coding_cap); 6621 6622 break; 6623 } 6624 } 6625 drm_connector_list_iter_end(&iter); 6626 } 6627 6628 /** 6629 * Streams and planes are reset when there are changes that affect 6630 * bandwidth. Anything that affects bandwidth needs to go through 6631 * DC global validation to ensure that the configuration can be applied 6632 * to hardware. 6633 * 6634 * We have to currently stall out here in atomic_check for outstanding 6635 * commits to finish in this case because our IRQ handlers reference 6636 * DRM state directly - we can end up disabling interrupts too early 6637 * if we don't. 6638 * 6639 * TODO: Remove this stall and drop DM state private objects. 6640 */ 6641 if (needs_dc_state_realloc) { 6642 ret = dm_atomic_get_state(state, &dm_state); 6643 if (ret) { 6644 drm_dbg_atomic(dev, "dm_atomic_get_state() failed: %pe\n", ERR_PTR(ret)); 6645 goto fail; 6646 } 6647 6648 ret = do_aquire_global_lock(dev, state); 6649 if (ret) { 6650 drm_dbg_atomic(dev, "do_aquire_global_lock() failed: %pe\n", ERR_PTR(ret)); 6651 goto fail; 6652 } 6653 6654 #if defined(CONFIG_DRM_AMD_DC_FP) 6655 if (dc_resource_is_dsc_encoding_supported(dc)) { 6656 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 6657 if (ret) { 6658 drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed: %pe\n", ERR_PTR(ret)); 6659 ret = -EINVAL; 6660 goto fail; 6661 } 6662 } 6663 #endif 6664 6665 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 6666 if (ret) { 6667 drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed: %pe\n", ERR_PTR(ret)); 6668 goto fail; 6669 } 6670 6671 /* 6672 * Perform validation of MST topology in the state: 6673 * We need to perform MST atomic check before calling 6674 * dc_validate_global_state(), or there is a chance 6675 * to get stuck in an infinite loop and hang eventually. 6676 */ 6677 ret = drm_dp_mst_atomic_check(state); 6678 if (ret) { 6679 drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed: %pe\n", ERR_PTR(ret)); 6680 goto fail; 6681 } 6682 status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY); 6683 if (status != DC_OK) { 6684 drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", 6685 dc_status_to_str(status), status); 6686 ret = -EINVAL; 6687 goto fail; 6688 } 6689 } else { 6690 /* 6691 * The commit is a fast update. Fast updates shouldn't change 6692 * the DC context, affect global validation, and can have their 6693 * commit work done in parallel with other commits not touching 6694 * the same resource. If we have a new DC context as part of 6695 * the DM atomic state from validation we need to free it and 6696 * retain the existing one instead. 6697 * 6698 * Furthermore, since the DM atomic state only contains the DC 6699 * context and can safely be annulled, we can free the state 6700 * and clear the associated private object now to free 6701 * some memory and avoid a possible use-after-free later. 6702 */ 6703 6704 for (i = 0; i < state->num_private_objs; i++) { 6705 struct drm_private_obj *obj = state->private_objs[i].ptr; 6706 6707 if (obj->funcs == adev->dm.atomic_obj.funcs) { 6708 int j = state->num_private_objs-1; 6709 6710 dm_atomic_destroy_state(obj, 6711 state->private_objs[i].state_to_destroy); 6712 6713 /* If i is not at the end of the array then the 6714 * last element needs to be moved to where i was 6715 * before the array can safely be truncated. 6716 */ 6717 if (i != j) 6718 state->private_objs[i] = 6719 state->private_objs[j]; 6720 6721 state->private_objs[j].ptr = NULL; 6722 state->private_objs[j].state_to_destroy = NULL; 6723 state->private_objs[j].old_state = NULL; 6724 state->private_objs[j].new_state = NULL; 6725 6726 state->num_private_objs = j; 6727 break; 6728 } 6729 } 6730 } 6731 6732 /* Store the overall update type for use later in atomic check. */ 6733 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6734 struct dm_crtc_state *dm_new_crtc_state = 6735 to_dm_crtc_state(new_crtc_state); 6736 6737 /* 6738 * Only allow async flips for fast updates that don't change 6739 * the FB pitch, the DCC state, rotation, mem_type, etc. 6740 */ 6741 if (new_crtc_state->async_flip && 6742 (needs_dc_state_realloc || 6743 amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) { 6744 drm_dbg_atomic(crtc->dev, 6745 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 6746 crtc->base.id, crtc->name); 6747 ret = -EINVAL; 6748 goto fail; 6749 } 6750 6751 dm_new_crtc_state->update_type = needs_dc_state_realloc ? 6752 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 6753 } 6754 6755 /* Must be success */ 6756 WARN_ON(ret); 6757 6758 trace_amdgpu_dm_atomic_check_finish(state, ret); 6759 6760 return ret; 6761 6762 fail: 6763 if (ret == -EDEADLK) 6764 drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n"); 6765 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 6766 drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n"); 6767 else 6768 drm_dbg_atomic(dev, "Atomic check failed: %pe\n", ERR_PTR(ret)); 6769 6770 trace_amdgpu_dm_atomic_check_finish(state, ret); 6771 6772 return ret; 6773 } 6774 EXPORT_IF_KUNIT(amdgpu_dm_atomic_check); 6775 6776 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 6777 { 6778 struct amdgpu_device *adev = drm_to_adev(dev); 6779 struct dc *dc = adev->dm.dc; 6780 int i; 6781 6782 mutex_lock(&adev->dm.dc_lock); 6783 if (dc->current_state) { 6784 for (i = 0; i < dc->current_state->stream_count; ++i) 6785 dc->current_state->streams[i] 6786 ->triggered_crtc_reset.enabled = 6787 adev->dm.force_timing_sync; 6788 6789 dm_enable_per_frame_crtc_master_sync(dc->current_state); 6790 dc_trigger_sync(dc, dc->current_state); 6791 } 6792 mutex_unlock(&adev->dm.dc_lock); 6793 } 6794 EXPORT_IF_KUNIT(amdgpu_dm_trigger_timing_sync); 6795 6796 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 6797 u32 value, const char *func_name) 6798 { 6799 #ifdef DM_CHECK_ADDR_0 6800 if (address == 0) { 6801 drm_err(adev_to_drm(ctx->driver_context), 6802 "invalid register write. address = 0"); 6803 return; 6804 } 6805 #endif 6806 6807 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 6808 cgs_write_register(ctx->cgs_device, address, value); 6809 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 6810 } 6811 6812 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 6813 const char *func_name) 6814 { 6815 u32 value; 6816 #ifdef DM_CHECK_ADDR_0 6817 if (address == 0) { 6818 drm_err(adev_to_drm(ctx->driver_context), 6819 "invalid register read; address = 0\n"); 6820 return 0; 6821 } 6822 #endif 6823 6824 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 6825 6826 value = cgs_read_register(ctx->cgs_device, address); 6827 6828 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 6829 6830 return value; 6831 } 6832 6833 void dm_acpi_process_phy_transition_interlock( 6834 const struct dc_context *ctx, 6835 struct dm_process_phy_transition_init_params process_phy_transition_init_params) 6836 { 6837 // Not yet implemented 6838 } 6839 EXPORT_IF_KUNIT(dm_acpi_process_phy_transition_interlock); 6840