1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/pci.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_dpm.h"
30 #include "amdgpu_atombios.h"
31 #include "amdgpu_dpm_internal.h"
32 #include "amd_pcie.h"
33 #include "atom.h"
34 #include "gfx_v6_0.h"
35 #include "r600_dpm.h"
36 #include "sid.h"
37 #include "si_dpm.h"
38 #include "../include/pptable.h"
39 #include <linux/math64.h>
40 #include <linux/seq_file.h>
41 #include <linux/firmware.h>
42 #include <legacy_dpm.h>
43
44 #include "bif/bif_3_0_d.h"
45 #include "bif/bif_3_0_sh_mask.h"
46
47 #include "dce/dce_6_0_d.h"
48 #include "dce/dce_6_0_sh_mask.h"
49
50 #include "gca/gfx_6_0_d.h"
51 #include "gca/gfx_6_0_sh_mask.h"
52
53 #include"gmc/gmc_6_0_d.h"
54 #include"gmc/gmc_6_0_sh_mask.h"
55
56 #include "smu/smu_6_0_d.h"
57 #include "smu/smu_6_0_sh_mask.h"
58
59 #define MC_CG_ARB_FREQ_F0 0x0a
60 #define MC_CG_ARB_FREQ_F1 0x0b
61 #define MC_CG_ARB_FREQ_F2 0x0c
62 #define MC_CG_ARB_FREQ_F3 0x0d
63
64 #define SMC_RAM_END 0x20000
65
66 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
67
68
69 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
70 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
71 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
72 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
73 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
74 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
75 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
76
77 #define BIOS_SCRATCH_4 0x5cd
78
79 MODULE_FIRMWARE("amdgpu/tahiti_smc.bin");
80 MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin");
81 MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin");
82 MODULE_FIRMWARE("amdgpu/verde_smc.bin");
83 MODULE_FIRMWARE("amdgpu/verde_k_smc.bin");
84 MODULE_FIRMWARE("amdgpu/oland_smc.bin");
85 MODULE_FIRMWARE("amdgpu/oland_k_smc.bin");
86 MODULE_FIRMWARE("amdgpu/hainan_smc.bin");
87 MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin");
88 MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin");
89
90 static const struct amd_pm_funcs si_dpm_funcs;
91
92 union power_info {
93 struct _ATOM_POWERPLAY_INFO info;
94 struct _ATOM_POWERPLAY_INFO_V2 info_2;
95 struct _ATOM_POWERPLAY_INFO_V3 info_3;
96 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
97 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
98 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
99 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
100 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
101 };
102
103 union fan_info {
104 struct _ATOM_PPLIB_FANTABLE fan;
105 struct _ATOM_PPLIB_FANTABLE2 fan2;
106 struct _ATOM_PPLIB_FANTABLE3 fan3;
107 };
108
109 union pplib_clock_info {
110 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
111 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
112 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
113 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
114 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
115 };
116
117 enum si_dpm_auto_throttle_src {
118 SI_DPM_AUTO_THROTTLE_SRC_THERMAL,
119 SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL
120 };
121
122 enum si_dpm_event_src {
123 SI_DPM_EVENT_SRC_ANALOG = 0,
124 SI_DPM_EVENT_SRC_EXTERNAL = 1,
125 SI_DPM_EVENT_SRC_DIGITAL = 2,
126 SI_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
127 SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
128 };
129
130 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
131 {
132 R600_UTC_DFLT_00,
133 R600_UTC_DFLT_01,
134 R600_UTC_DFLT_02,
135 R600_UTC_DFLT_03,
136 R600_UTC_DFLT_04,
137 R600_UTC_DFLT_05,
138 R600_UTC_DFLT_06,
139 R600_UTC_DFLT_07,
140 R600_UTC_DFLT_08,
141 R600_UTC_DFLT_09,
142 R600_UTC_DFLT_10,
143 R600_UTC_DFLT_11,
144 R600_UTC_DFLT_12,
145 R600_UTC_DFLT_13,
146 R600_UTC_DFLT_14,
147 };
148
149 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
150 {
151 R600_DTC_DFLT_00,
152 R600_DTC_DFLT_01,
153 R600_DTC_DFLT_02,
154 R600_DTC_DFLT_03,
155 R600_DTC_DFLT_04,
156 R600_DTC_DFLT_05,
157 R600_DTC_DFLT_06,
158 R600_DTC_DFLT_07,
159 R600_DTC_DFLT_08,
160 R600_DTC_DFLT_09,
161 R600_DTC_DFLT_10,
162 R600_DTC_DFLT_11,
163 R600_DTC_DFLT_12,
164 R600_DTC_DFLT_13,
165 R600_DTC_DFLT_14,
166 };
167
168 static const struct si_cac_config_reg cac_weights_tahiti[] =
169 {
170 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
171 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
172 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
173 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
174 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
175 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
177 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
180 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
182 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
183 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
184 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
185 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
186 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
187 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
188 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
189 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
190 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
191 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
192 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
193 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
194 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
195 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
196 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
197 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
198 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
199 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
200 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
201 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
202 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
203 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
204 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
205 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
206 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
207 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
208 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
209 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
210 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
211 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
212 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
213 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
214 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
215 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
216 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
217 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
218 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
219 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
220 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
221 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
222 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
223 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
224 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
225 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
226 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
227 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
228 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
229 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
230 { 0xFFFFFFFF }
231 };
232
233 static const struct si_cac_config_reg lcac_tahiti[] =
234 {
235 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
236 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
237 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
238 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
239 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
240 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
241 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
242 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
243 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
244 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
245 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
246 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
247 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
248 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
249 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
250 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
251 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
252 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
253 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
254 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
255 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
256 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
257 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
258 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
259 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
260 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
261 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
262 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
263 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
264 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
265 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
266 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
267 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
268 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
269 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
270 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
271 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
272 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
273 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
274 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
275 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
276 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
277 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
278 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
279 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
280 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
281 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
282 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
283 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
284 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
285 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
286 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
287 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
288 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
289 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
290 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
291 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
292 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
293 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
294 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
295 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
296 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
297 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
298 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
299 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
300 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
301 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
302 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
303 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
304 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
305 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
306 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
307 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
308 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
309 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
310 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
311 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
312 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
313 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
314 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
315 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
316 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
317 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
318 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
319 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
320 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
321 { 0xFFFFFFFF }
322
323 };
324
325 static const struct si_cac_config_reg cac_override_tahiti[] =
326 {
327 { 0xFFFFFFFF }
328 };
329
330 static const struct si_powertune_data powertune_data_tahiti =
331 {
332 ((1 << 16) | 27027),
333 6,
334 0,
335 4,
336 95,
337 {
338 0UL,
339 0UL,
340 4521550UL,
341 309631529UL,
342 -1270850L,
343 4513710L,
344 40
345 },
346 595000000UL,
347 12,
348 {
349 0,
350 0,
351 0,
352 0,
353 0,
354 0,
355 0,
356 0
357 },
358 true
359 };
360
361 static const struct si_dte_data dte_data_tahiti =
362 {
363 { 1159409, 0, 0, 0, 0 },
364 { 777, 0, 0, 0, 0 },
365 2,
366 54000,
367 127000,
368 25,
369 2,
370 10,
371 13,
372 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
373 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
374 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
375 85,
376 false
377 };
378
379 static const struct si_dte_data dte_data_tahiti_pro =
380 {
381 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
382 { 0x0, 0x0, 0x0, 0x0, 0x0 },
383 5,
384 45000,
385 100,
386 0xA,
387 1,
388 0,
389 0x10,
390 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
391 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
392 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
393 90,
394 true
395 };
396
397 static const struct si_dte_data dte_data_new_zealand =
398 {
399 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
400 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
401 0x5,
402 0xAFC8,
403 0x69,
404 0x32,
405 1,
406 0,
407 0x10,
408 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
409 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
410 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
411 85,
412 true
413 };
414
415 static const struct si_dte_data dte_data_aruba_pro =
416 {
417 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
418 { 0x0, 0x0, 0x0, 0x0, 0x0 },
419 5,
420 45000,
421 100,
422 0xA,
423 1,
424 0,
425 0x10,
426 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
427 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
428 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
429 90,
430 true
431 };
432
433 static const struct si_dte_data dte_data_malta =
434 {
435 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
436 { 0x0, 0x0, 0x0, 0x0, 0x0 },
437 5,
438 45000,
439 100,
440 0xA,
441 1,
442 0,
443 0x10,
444 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
445 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
446 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
447 90,
448 true
449 };
450
451 static const struct si_cac_config_reg cac_weights_pitcairn[] =
452 {
453 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
454 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
455 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
456 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
457 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
458 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
459 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
460 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
461 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
462 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
463 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
464 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
465 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
466 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
467 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
468 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
469 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
470 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
471 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
472 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
473 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
474 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
475 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
476 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
477 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
479 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
480 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
484 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
486 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
488 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
489 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
490 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
491 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
492 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
493 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
499 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
500 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
503 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
504 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
507 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
508 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
509 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
510 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
511 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
512 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
513 { 0xFFFFFFFF }
514 };
515
516 static const struct si_cac_config_reg lcac_pitcairn[] =
517 {
518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
522 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
524 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
526 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
528 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
530 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
531 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
532 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
533 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
534 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
535 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
536 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
537 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
538 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
539 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
540 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
541 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
542 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
543 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
544 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
545 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
546 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
547 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
548 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
549 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
550 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
551 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
552 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
553 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
554 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
555 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
556 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
557 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
558 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
559 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
560 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
561 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
562 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
563 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
564 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
565 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
566 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
567 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
568 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
569 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
570 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
571 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
572 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
573 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
574 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
575 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
576 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
577 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
578 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
579 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
580 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
581 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
582 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
583 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
584 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
585 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
586 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
587 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
588 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
589 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
590 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
591 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
592 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
593 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
594 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
595 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
596 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
597 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
598 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
599 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
600 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
601 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
602 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
603 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
604 { 0xFFFFFFFF }
605 };
606
607 static const struct si_cac_config_reg cac_override_pitcairn[] =
608 {
609 { 0xFFFFFFFF }
610 };
611
612 static const struct si_powertune_data powertune_data_pitcairn =
613 {
614 ((1 << 16) | 27027),
615 5,
616 0,
617 6,
618 100,
619 {
620 51600000UL,
621 1800000UL,
622 7194395UL,
623 309631529UL,
624 -1270850L,
625 4513710L,
626 100
627 },
628 117830498UL,
629 12,
630 {
631 0,
632 0,
633 0,
634 0,
635 0,
636 0,
637 0,
638 0
639 },
640 true
641 };
642
643 static const struct si_dte_data dte_data_pitcairn =
644 {
645 { 0, 0, 0, 0, 0 },
646 { 0, 0, 0, 0, 0 },
647 0,
648 0,
649 0,
650 0,
651 0,
652 0,
653 0,
654 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
655 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
656 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
657 0,
658 false
659 };
660
661 static const struct si_dte_data dte_data_curacao_xt =
662 {
663 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
664 { 0x0, 0x0, 0x0, 0x0, 0x0 },
665 5,
666 45000,
667 100,
668 0xA,
669 1,
670 0,
671 0x10,
672 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
673 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
674 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
675 90,
676 true
677 };
678
679 static const struct si_dte_data dte_data_curacao_pro =
680 {
681 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
682 { 0x0, 0x0, 0x0, 0x0, 0x0 },
683 5,
684 45000,
685 100,
686 0xA,
687 1,
688 0,
689 0x10,
690 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
691 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
692 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
693 90,
694 true
695 };
696
697 static const struct si_dte_data dte_data_neptune_xt =
698 {
699 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
700 { 0x0, 0x0, 0x0, 0x0, 0x0 },
701 5,
702 45000,
703 100,
704 0xA,
705 1,
706 0,
707 0x10,
708 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
709 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
710 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
711 90,
712 true
713 };
714
715 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
716 {
717 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
718 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
719 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
720 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
721 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
722 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
723 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
724 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
725 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
726 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
727 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
728 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
729 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
730 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
731 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
732 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
733 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
734 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
735 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
736 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
737 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
738 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
739 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
740 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
741 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
742 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
743 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
744 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
746 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
747 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
748 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
749 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
750 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
751 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
752 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
753 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
754 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
755 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
756 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
757 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
758 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
759 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
760 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
761 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
762 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
763 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
764 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
765 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
766 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
767 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
768 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
769 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
770 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
771 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
772 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
773 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
774 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
775 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
776 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
777 { 0xFFFFFFFF }
778 };
779
780 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
781 {
782 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
783 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
784 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
785 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
786 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
787 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
788 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
789 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
790 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
791 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
792 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
793 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
794 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
795 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
796 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
797 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
798 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
799 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
800 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
801 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
802 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
803 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
804 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
805 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
806 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
807 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
808 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
809 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
811 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
812 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
813 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
814 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
815 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
816 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
817 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
818 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
819 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
820 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
821 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
822 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
823 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
824 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
825 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
826 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
827 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
828 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
829 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
830 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
831 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
832 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
833 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
834 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
835 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
836 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
837 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
838 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
839 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
840 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
841 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
842 { 0xFFFFFFFF }
843 };
844
845 static const struct si_cac_config_reg cac_weights_heathrow[] =
846 {
847 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
848 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
849 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
850 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
851 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
852 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
853 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
854 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
855 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
856 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
857 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
858 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
859 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
860 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
861 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
862 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
863 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
864 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
865 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
866 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
867 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
868 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
869 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
870 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
871 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
872 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
873 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
874 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
876 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
877 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
878 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
879 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
880 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
881 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
882 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
883 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
884 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
885 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
886 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
887 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
888 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
889 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
890 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
891 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
892 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
893 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
894 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
895 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
896 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
897 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
898 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
899 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
900 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
901 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
902 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
903 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
904 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
905 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
906 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
907 { 0xFFFFFFFF }
908 };
909
910 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
911 {
912 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
913 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
914 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
915 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
916 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
917 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
918 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
919 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
920 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
921 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
922 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
923 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
924 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
925 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
926 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
927 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
928 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
929 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
930 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
931 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
932 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
933 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
934 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
935 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
936 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
937 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
938 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
939 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
940 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
942 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
943 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
944 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
945 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
946 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
947 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
948 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
949 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
950 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
951 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
952 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
953 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
954 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
955 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
956 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
957 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
958 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
959 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
960 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
961 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
962 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
963 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
964 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
965 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
966 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
967 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
968 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
969 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
970 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
971 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
972 { 0xFFFFFFFF }
973 };
974
975 static const struct si_cac_config_reg cac_weights_cape_verde[] =
976 {
977 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
978 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
979 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
980 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
981 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
982 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
983 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
984 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
985 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
986 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
987 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
988 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
989 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
990 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
991 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
992 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
993 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
994 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
995 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
996 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
997 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
998 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
999 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1000 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1001 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1002 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1003 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1004 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1006 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1007 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1008 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1009 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1010 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1011 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1012 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1013 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1014 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1015 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1016 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1017 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1018 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1019 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1020 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1021 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1022 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1023 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1024 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1025 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1026 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1027 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1028 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1029 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1030 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1031 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1032 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1033 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1034 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1035 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1036 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1037 { 0xFFFFFFFF }
1038 };
1039
1040 static const struct si_cac_config_reg lcac_cape_verde[] =
1041 {
1042 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1043 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1045 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1047 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1049 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1051 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1053 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1059 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1061 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1063 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1065 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1069 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1073 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1075 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1077 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1079 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1081 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1082 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1083 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1084 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1085 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1086 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1087 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1088 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1089 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1090 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1091 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1092 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1093 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1094 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1095 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1096 { 0xFFFFFFFF }
1097 };
1098
1099 static const struct si_cac_config_reg cac_override_cape_verde[] =
1100 {
1101 { 0xFFFFFFFF }
1102 };
1103
1104 static const struct si_powertune_data powertune_data_cape_verde =
1105 {
1106 ((1 << 16) | 0x6993),
1107 5,
1108 0,
1109 7,
1110 105,
1111 {
1112 0UL,
1113 0UL,
1114 7194395UL,
1115 309631529UL,
1116 -1270850L,
1117 4513710L,
1118 100
1119 },
1120 117830498UL,
1121 12,
1122 {
1123 0,
1124 0,
1125 0,
1126 0,
1127 0,
1128 0,
1129 0,
1130 0
1131 },
1132 true
1133 };
1134
1135 static const struct si_dte_data dte_data_cape_verde =
1136 {
1137 { 0, 0, 0, 0, 0 },
1138 { 0, 0, 0, 0, 0 },
1139 0,
1140 0,
1141 0,
1142 0,
1143 0,
1144 0,
1145 0,
1146 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1147 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1148 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1149 0,
1150 false
1151 };
1152
1153 static const struct si_dte_data dte_data_venus_xtx =
1154 {
1155 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1156 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1157 5,
1158 55000,
1159 0x69,
1160 0xA,
1161 1,
1162 0,
1163 0x3,
1164 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1165 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1166 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167 90,
1168 true
1169 };
1170
1171 static const struct si_dte_data dte_data_venus_xt =
1172 {
1173 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1174 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1175 5,
1176 55000,
1177 0x69,
1178 0xA,
1179 1,
1180 0,
1181 0x3,
1182 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1183 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1184 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185 90,
1186 true
1187 };
1188
1189 static const struct si_dte_data dte_data_venus_pro =
1190 {
1191 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1192 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1193 5,
1194 55000,
1195 0x69,
1196 0xA,
1197 1,
1198 0,
1199 0x3,
1200 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1201 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1202 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1203 90,
1204 true
1205 };
1206
1207 static const struct si_cac_config_reg cac_weights_oland[] =
1208 {
1209 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1210 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1211 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1212 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1213 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1214 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1215 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1216 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1217 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1218 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1219 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1220 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1221 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1222 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1223 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1224 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1225 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1226 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1227 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1228 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1229 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1230 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1231 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1232 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1233 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1234 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1235 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1236 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1238 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1239 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1240 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1241 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1242 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1243 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1244 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1245 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1246 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1247 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1248 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1249 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1250 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1251 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1252 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1253 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1254 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1255 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1256 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1257 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1258 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1259 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1260 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1261 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1262 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1263 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1264 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1265 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1266 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1267 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1268 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1269 { 0xFFFFFFFF }
1270 };
1271
1272 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1273 {
1274 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1275 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1276 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1277 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1278 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1279 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1280 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1281 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1282 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1283 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1284 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1285 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1286 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1287 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1288 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1289 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1290 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1291 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1292 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1293 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1294 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1295 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1296 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1297 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1298 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1299 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1300 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1301 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1302 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1303 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1304 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1305 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1307 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1308 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1309 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1310 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1312 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1313 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1314 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1315 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1316 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1317 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1318 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1319 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1320 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1321 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1322 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1323 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1324 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1325 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1326 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1327 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1328 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1329 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1330 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1331 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1332 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1333 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1334 { 0xFFFFFFFF }
1335 };
1336
1337 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1338 {
1339 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1340 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1341 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1342 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1343 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1344 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1345 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1346 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1347 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1348 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1349 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1350 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1351 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1352 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1353 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1354 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1355 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1356 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1357 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1358 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1359 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1360 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1361 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1362 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1363 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1364 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1365 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1366 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1367 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1368 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1369 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1370 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1372 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1373 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1374 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1375 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1377 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1378 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1379 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1380 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1381 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1382 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1383 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1384 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1385 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1386 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1387 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1388 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1389 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1390 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1391 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1392 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1393 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1394 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1395 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1396 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1397 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1398 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1399 { 0xFFFFFFFF }
1400 };
1401
1402 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1403 {
1404 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1405 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1406 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1407 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1408 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1409 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1410 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1411 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1412 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1413 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1414 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1415 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1416 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1417 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1418 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1419 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1420 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1421 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1422 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1423 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1424 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1425 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1426 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1427 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1428 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1429 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1430 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1431 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1432 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1434 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1435 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1437 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1438 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1439 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1440 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1442 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1443 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1444 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1445 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1446 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1447 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1448 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1449 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1450 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1451 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1452 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1453 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1454 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1455 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1456 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1457 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1458 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1459 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1460 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1461 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1462 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1463 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1464 { 0xFFFFFFFF }
1465 };
1466
1467 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1468 {
1469 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1470 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1471 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1472 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1473 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1474 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1475 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1476 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1477 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1478 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1479 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1480 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1481 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1482 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1483 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1484 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1485 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1486 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1487 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1488 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1489 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1490 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1491 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1492 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1493 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1494 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1495 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1496 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1497 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1499 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1500 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1502 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1503 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1504 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1505 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1507 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1508 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1509 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1510 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1511 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1512 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1513 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1514 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1515 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1516 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1517 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1518 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1519 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1520 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1521 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1522 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1523 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1524 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1525 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1526 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1527 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1528 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1529 { 0xFFFFFFFF }
1530 };
1531
1532 static const struct si_cac_config_reg lcac_oland[] =
1533 {
1534 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1535 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1537 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1539 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1541 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1543 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1545 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1549 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1561 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1562 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1563 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1564 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1565 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1566 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1567 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1568 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1569 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1570 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1571 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1572 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1573 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1574 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1575 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1576 { 0xFFFFFFFF }
1577 };
1578
1579 static const struct si_cac_config_reg lcac_mars_pro[] =
1580 {
1581 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1582 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1584 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1586 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1588 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1590 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1592 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1596 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1608 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1609 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1610 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1611 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1612 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1613 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1614 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1615 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1616 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1617 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1618 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1619 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1620 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1621 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1622 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1623 { 0xFFFFFFFF }
1624 };
1625
1626 static const struct si_cac_config_reg cac_override_oland[] =
1627 {
1628 { 0xFFFFFFFF }
1629 };
1630
1631 static const struct si_powertune_data powertune_data_oland =
1632 {
1633 ((1 << 16) | 0x6993),
1634 5,
1635 0,
1636 7,
1637 105,
1638 {
1639 0UL,
1640 0UL,
1641 7194395UL,
1642 309631529UL,
1643 -1270850L,
1644 4513710L,
1645 100
1646 },
1647 117830498UL,
1648 12,
1649 {
1650 0,
1651 0,
1652 0,
1653 0,
1654 0,
1655 0,
1656 0,
1657 0
1658 },
1659 true
1660 };
1661
1662 static const struct si_powertune_data powertune_data_mars_pro =
1663 {
1664 ((1 << 16) | 0x6993),
1665 5,
1666 0,
1667 7,
1668 105,
1669 {
1670 0UL,
1671 0UL,
1672 7194395UL,
1673 309631529UL,
1674 -1270850L,
1675 4513710L,
1676 100
1677 },
1678 117830498UL,
1679 12,
1680 {
1681 0,
1682 0,
1683 0,
1684 0,
1685 0,
1686 0,
1687 0,
1688 0
1689 },
1690 true
1691 };
1692
1693 static const struct si_dte_data dte_data_oland =
1694 {
1695 { 0, 0, 0, 0, 0 },
1696 { 0, 0, 0, 0, 0 },
1697 0,
1698 0,
1699 0,
1700 0,
1701 0,
1702 0,
1703 0,
1704 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1705 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1706 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1707 0,
1708 false
1709 };
1710
1711 static const struct si_dte_data dte_data_mars_pro =
1712 {
1713 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1714 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1715 5,
1716 55000,
1717 105,
1718 0xA,
1719 1,
1720 0,
1721 0x10,
1722 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1723 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1724 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1725 90,
1726 true
1727 };
1728
1729 static const struct si_dte_data dte_data_sun_xt =
1730 {
1731 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1732 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1733 5,
1734 55000,
1735 105,
1736 0xA,
1737 1,
1738 0,
1739 0x10,
1740 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1741 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1742 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1743 90,
1744 true
1745 };
1746
1747
1748 static const struct si_cac_config_reg cac_weights_hainan[] =
1749 {
1750 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1751 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1752 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1753 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1754 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1755 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1756 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1757 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1758 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1760 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1761 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1762 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1763 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1764 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1765 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1768 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1769 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1770 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1771 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1772 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1773 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1774 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1776 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1777 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1781 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1785 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1786 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1787 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1788 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1789 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1790 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1791 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1792 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1793 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1794 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1795 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1796 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1797 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1798 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1799 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1800 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1801 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1802 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1803 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1804 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1805 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1806 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1807 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1808 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1809 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1810 { 0xFFFFFFFF }
1811 };
1812
1813 static const struct si_powertune_data powertune_data_hainan =
1814 {
1815 ((1 << 16) | 0x6993),
1816 5,
1817 0,
1818 9,
1819 105,
1820 {
1821 0UL,
1822 0UL,
1823 7194395UL,
1824 309631529UL,
1825 -1270850L,
1826 4513710L,
1827 100
1828 },
1829 117830498UL,
1830 12,
1831 {
1832 0,
1833 0,
1834 0,
1835 0,
1836 0,
1837 0,
1838 0,
1839 0
1840 },
1841 true
1842 };
1843
1844 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1845 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1846 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1847 static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
1848
1849 static int si_populate_voltage_value(struct amdgpu_device *adev,
1850 const struct atom_voltage_table *table,
1851 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1852 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1853 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1854 u16 *std_voltage);
1855 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1856 u16 reg_offset, u32 value);
1857 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1858 struct rv7xx_pl *pl,
1859 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1860 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1861 u32 engine_clock,
1862 SISLANDS_SMC_SCLK_VALUE *sclk);
1863
1864 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1865 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1866 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1867
si_get_pi(struct amdgpu_device * adev)1868 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1869 {
1870 struct si_power_info *pi = adev->pm.dpm.priv;
1871 return pi;
1872 }
1873
si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients * coeff,u16 v,s32 t,u32 ileakage,u32 * leakage)1874 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1875 u16 v, s32 t, u32 ileakage, u32 *leakage)
1876 {
1877 s64 kt, kv, leakage_w, i_leakage, vddc;
1878 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1879 s64 tmp;
1880
1881 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1882 vddc = div64_s64(drm_int2fixp(v), 1000);
1883 temperature = div64_s64(drm_int2fixp(t), 1000);
1884
1885 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1886 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1887 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1888 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1889 t_ref = drm_int2fixp(coeff->t_ref);
1890
1891 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1892 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1893 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1894 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1895
1896 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1897
1898 *leakage = drm_fixp2int(leakage_w * 1000);
1899 }
1900
si_calculate_leakage_for_v_and_t(struct amdgpu_device * adev,const struct ni_leakage_coeffients * coeff,u16 v,s32 t,u32 i_leakage,u32 * leakage)1901 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1902 const struct ni_leakage_coeffients *coeff,
1903 u16 v,
1904 s32 t,
1905 u32 i_leakage,
1906 u32 *leakage)
1907 {
1908 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1909 }
1910
si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients * coeff,const u32 fixed_kt,u16 v,u32 ileakage,u32 * leakage)1911 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1912 const u32 fixed_kt, u16 v,
1913 u32 ileakage, u32 *leakage)
1914 {
1915 s64 kt, kv, leakage_w, i_leakage, vddc;
1916
1917 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1918 vddc = div64_s64(drm_int2fixp(v), 1000);
1919
1920 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1921 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1922 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1923
1924 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1925
1926 *leakage = drm_fixp2int(leakage_w * 1000);
1927 }
1928
si_calculate_leakage_for_v(struct amdgpu_device * adev,const struct ni_leakage_coeffients * coeff,const u32 fixed_kt,u16 v,u32 i_leakage,u32 * leakage)1929 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1930 const struct ni_leakage_coeffients *coeff,
1931 const u32 fixed_kt,
1932 u16 v,
1933 u32 i_leakage,
1934 u32 *leakage)
1935 {
1936 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1937 }
1938
1939
si_update_dte_from_pl2(struct amdgpu_device * adev,struct si_dte_data * dte_data)1940 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1941 struct si_dte_data *dte_data)
1942 {
1943 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1944 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1945 u32 k = dte_data->k;
1946 u32 t_max = dte_data->max_t;
1947 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1948 u32 t_0 = dte_data->t0;
1949 u32 i;
1950
1951 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1952 dte_data->tdep_count = 3;
1953
1954 for (i = 0; i < k; i++) {
1955 dte_data->r[i] =
1956 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1957 (p_limit2 * (u32)100);
1958 }
1959
1960 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1961
1962 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1963 dte_data->tdep_r[i] = dte_data->r[4];
1964 }
1965 } else {
1966 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1967 }
1968 }
1969
rv770_get_pi(struct amdgpu_device * adev)1970 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1971 {
1972 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1973
1974 return pi;
1975 }
1976
ni_get_pi(struct amdgpu_device * adev)1977 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1978 {
1979 struct ni_power_info *pi = adev->pm.dpm.priv;
1980
1981 return pi;
1982 }
1983
si_get_ps(struct amdgpu_ps * aps)1984 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1985 {
1986 struct si_ps *ps = aps->ps_priv;
1987
1988 return ps;
1989 }
1990
si_initialize_powertune_defaults(struct amdgpu_device * adev)1991 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1992 {
1993 struct ni_power_info *ni_pi = ni_get_pi(adev);
1994 struct si_power_info *si_pi = si_get_pi(adev);
1995 bool update_dte_from_pl2 = false;
1996
1997 if (adev->asic_type == CHIP_TAHITI) {
1998 si_pi->cac_weights = cac_weights_tahiti;
1999 si_pi->lcac_config = lcac_tahiti;
2000 si_pi->cac_override = cac_override_tahiti;
2001 si_pi->powertune_data = &powertune_data_tahiti;
2002 si_pi->dte_data = dte_data_tahiti;
2003
2004 switch (adev->pdev->device) {
2005 case 0x6798:
2006 si_pi->dte_data.enable_dte_by_default = true;
2007 break;
2008 case 0x6799:
2009 si_pi->dte_data = dte_data_new_zealand;
2010 break;
2011 case 0x6790:
2012 case 0x6791:
2013 case 0x6792:
2014 case 0x679E:
2015 si_pi->dte_data = dte_data_aruba_pro;
2016 update_dte_from_pl2 = true;
2017 break;
2018 case 0x679B:
2019 si_pi->dte_data = dte_data_malta;
2020 update_dte_from_pl2 = true;
2021 break;
2022 case 0x679A:
2023 si_pi->dte_data = dte_data_tahiti_pro;
2024 update_dte_from_pl2 = true;
2025 break;
2026 default:
2027 if (si_pi->dte_data.enable_dte_by_default == true)
2028 DRM_ERROR("DTE is not enabled!\n");
2029 break;
2030 }
2031 } else if (adev->asic_type == CHIP_PITCAIRN) {
2032 si_pi->cac_weights = cac_weights_pitcairn;
2033 si_pi->lcac_config = lcac_pitcairn;
2034 si_pi->cac_override = cac_override_pitcairn;
2035 si_pi->powertune_data = &powertune_data_pitcairn;
2036
2037 switch (adev->pdev->device) {
2038 case 0x6810:
2039 case 0x6818:
2040 si_pi->dte_data = dte_data_curacao_xt;
2041 update_dte_from_pl2 = true;
2042 break;
2043 case 0x6819:
2044 case 0x6811:
2045 si_pi->dte_data = dte_data_curacao_pro;
2046 update_dte_from_pl2 = true;
2047 break;
2048 case 0x6800:
2049 case 0x6806:
2050 si_pi->dte_data = dte_data_neptune_xt;
2051 update_dte_from_pl2 = true;
2052 break;
2053 default:
2054 si_pi->dte_data = dte_data_pitcairn;
2055 break;
2056 }
2057 } else if (adev->asic_type == CHIP_VERDE) {
2058 si_pi->lcac_config = lcac_cape_verde;
2059 si_pi->cac_override = cac_override_cape_verde;
2060 si_pi->powertune_data = &powertune_data_cape_verde;
2061
2062 switch (adev->pdev->device) {
2063 case 0x683B:
2064 case 0x683F:
2065 case 0x6829:
2066 case 0x6835:
2067 si_pi->cac_weights = cac_weights_cape_verde_pro;
2068 si_pi->dte_data = dte_data_cape_verde;
2069 break;
2070 case 0x682C:
2071 si_pi->cac_weights = cac_weights_cape_verde_pro;
2072 si_pi->dte_data = dte_data_sun_xt;
2073 update_dte_from_pl2 = true;
2074 break;
2075 case 0x6825:
2076 case 0x6827:
2077 si_pi->cac_weights = cac_weights_heathrow;
2078 si_pi->dte_data = dte_data_cape_verde;
2079 break;
2080 case 0x6824:
2081 case 0x682D:
2082 si_pi->cac_weights = cac_weights_chelsea_xt;
2083 si_pi->dte_data = dte_data_cape_verde;
2084 break;
2085 case 0x682F:
2086 si_pi->cac_weights = cac_weights_chelsea_pro;
2087 si_pi->dte_data = dte_data_cape_verde;
2088 break;
2089 case 0x6820:
2090 si_pi->cac_weights = cac_weights_heathrow;
2091 si_pi->dte_data = dte_data_venus_xtx;
2092 break;
2093 case 0x6821:
2094 si_pi->cac_weights = cac_weights_heathrow;
2095 si_pi->dte_data = dte_data_venus_xt;
2096 break;
2097 case 0x6823:
2098 case 0x682B:
2099 case 0x6822:
2100 case 0x682A:
2101 si_pi->cac_weights = cac_weights_chelsea_pro;
2102 si_pi->dte_data = dte_data_venus_pro;
2103 break;
2104 default:
2105 si_pi->cac_weights = cac_weights_cape_verde;
2106 si_pi->dte_data = dte_data_cape_verde;
2107 break;
2108 }
2109 } else if (adev->asic_type == CHIP_OLAND) {
2110 si_pi->lcac_config = lcac_mars_pro;
2111 si_pi->cac_override = cac_override_oland;
2112 si_pi->powertune_data = &powertune_data_mars_pro;
2113 si_pi->dte_data = dte_data_mars_pro;
2114
2115 switch (adev->pdev->device) {
2116 case 0x6601:
2117 case 0x6621:
2118 case 0x6603:
2119 case 0x6605:
2120 si_pi->cac_weights = cac_weights_mars_pro;
2121 update_dte_from_pl2 = true;
2122 break;
2123 case 0x6600:
2124 case 0x6606:
2125 case 0x6620:
2126 case 0x6604:
2127 si_pi->cac_weights = cac_weights_mars_xt;
2128 update_dte_from_pl2 = true;
2129 break;
2130 case 0x6611:
2131 case 0x6613:
2132 case 0x6608:
2133 si_pi->cac_weights = cac_weights_oland_pro;
2134 update_dte_from_pl2 = true;
2135 break;
2136 case 0x6610:
2137 si_pi->cac_weights = cac_weights_oland_xt;
2138 update_dte_from_pl2 = true;
2139 break;
2140 default:
2141 si_pi->cac_weights = cac_weights_oland;
2142 si_pi->lcac_config = lcac_oland;
2143 si_pi->cac_override = cac_override_oland;
2144 si_pi->powertune_data = &powertune_data_oland;
2145 si_pi->dte_data = dte_data_oland;
2146 break;
2147 }
2148 } else if (adev->asic_type == CHIP_HAINAN) {
2149 si_pi->cac_weights = cac_weights_hainan;
2150 si_pi->lcac_config = lcac_oland;
2151 si_pi->cac_override = cac_override_oland;
2152 si_pi->powertune_data = &powertune_data_hainan;
2153 si_pi->dte_data = dte_data_sun_xt;
2154 update_dte_from_pl2 = true;
2155 } else {
2156 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2157 return;
2158 }
2159
2160 ni_pi->enable_power_containment = false;
2161 ni_pi->enable_cac = false;
2162 ni_pi->enable_sq_ramping = false;
2163 si_pi->enable_dte = false;
2164
2165 if (si_pi->powertune_data->enable_powertune_by_default) {
2166 ni_pi->enable_power_containment = true;
2167 ni_pi->enable_cac = true;
2168 if (si_pi->dte_data.enable_dte_by_default) {
2169 si_pi->enable_dte = true;
2170 if (update_dte_from_pl2)
2171 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2172
2173 }
2174 ni_pi->enable_sq_ramping = true;
2175 }
2176
2177 ni_pi->driver_calculate_cac_leakage = true;
2178 ni_pi->cac_configuration_required = true;
2179
2180 if (ni_pi->cac_configuration_required) {
2181 ni_pi->support_cac_long_term_average = true;
2182 si_pi->dyn_powertune_data.l2_lta_window_size =
2183 si_pi->powertune_data->l2_lta_window_size_default;
2184 si_pi->dyn_powertune_data.lts_truncate =
2185 si_pi->powertune_data->lts_truncate_default;
2186 } else {
2187 ni_pi->support_cac_long_term_average = false;
2188 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2189 si_pi->dyn_powertune_data.lts_truncate = 0;
2190 }
2191
2192 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2193 }
2194
si_get_smc_power_scaling_factor(struct amdgpu_device * adev)2195 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2196 {
2197 return 1;
2198 }
2199
si_calculate_cac_wintime(struct amdgpu_device * adev)2200 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2201 {
2202 u32 xclk;
2203 u32 wintime;
2204 u32 cac_window;
2205 u32 cac_window_size;
2206
2207 xclk = amdgpu_asic_get_xclk(adev);
2208
2209 if (xclk == 0)
2210 return 0;
2211
2212 cac_window = RREG32(mmCG_CAC_CTRL) & CG_CAC_CTRL__CAC_WINDOW_MASK;
2213 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2214
2215 wintime = (cac_window_size * 100) / xclk;
2216
2217 return wintime;
2218 }
2219
si_scale_power_for_smc(u32 power_in_watts,u32 scaling_factor)2220 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2221 {
2222 return power_in_watts;
2223 }
2224
si_calculate_adjusted_tdp_limits(struct amdgpu_device * adev,bool adjust_polarity,u32 tdp_adjustment,u32 * tdp_limit,u32 * near_tdp_limit)2225 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2226 bool adjust_polarity,
2227 u32 tdp_adjustment,
2228 u32 *tdp_limit,
2229 u32 *near_tdp_limit)
2230 {
2231 u32 adjustment_delta, max_tdp_limit;
2232
2233 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2234 return -EINVAL;
2235
2236 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2237
2238 if (adjust_polarity) {
2239 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2240 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2241 } else {
2242 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2243 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2244 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2245 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2246 else
2247 *near_tdp_limit = 0;
2248 }
2249
2250 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2251 return -EINVAL;
2252 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2253 return -EINVAL;
2254
2255 return 0;
2256 }
2257
si_populate_smc_tdp_limits(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)2258 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2259 struct amdgpu_ps *amdgpu_state)
2260 {
2261 struct ni_power_info *ni_pi = ni_get_pi(adev);
2262 struct si_power_info *si_pi = si_get_pi(adev);
2263
2264 if (ni_pi->enable_power_containment) {
2265 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2266 PP_SIslands_PAPMParameters *papm_parm;
2267 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2268 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2269 u32 tdp_limit;
2270 u32 near_tdp_limit;
2271 int ret;
2272
2273 if (scaling_factor == 0)
2274 return -EINVAL;
2275
2276 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2277
2278 ret = si_calculate_adjusted_tdp_limits(adev,
2279 false, /* ??? */
2280 adev->pm.dpm.tdp_adjustment,
2281 &tdp_limit,
2282 &near_tdp_limit);
2283 if (ret)
2284 return ret;
2285
2286 smc_table->dpm2Params.TDPLimit =
2287 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2288 smc_table->dpm2Params.NearTDPLimit =
2289 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2290 smc_table->dpm2Params.SafePowerLimit =
2291 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2292
2293 ret = amdgpu_si_copy_bytes_to_smc(adev,
2294 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2295 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2296 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2297 sizeof(u32) * 3,
2298 si_pi->sram_end);
2299 if (ret)
2300 return ret;
2301
2302 if (si_pi->enable_ppm) {
2303 papm_parm = &si_pi->papm_parm;
2304 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2305 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2306 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2307 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2308 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2309 papm_parm->PlatformPowerLimit = 0xffffffff;
2310 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2311
2312 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2313 (u8 *)papm_parm,
2314 sizeof(PP_SIslands_PAPMParameters),
2315 si_pi->sram_end);
2316 if (ret)
2317 return ret;
2318 }
2319 }
2320 return 0;
2321 }
2322
si_populate_smc_tdp_limits_2(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)2323 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2324 struct amdgpu_ps *amdgpu_state)
2325 {
2326 struct ni_power_info *ni_pi = ni_get_pi(adev);
2327 struct si_power_info *si_pi = si_get_pi(adev);
2328
2329 if (ni_pi->enable_power_containment) {
2330 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2331 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2332 int ret;
2333
2334 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2335
2336 smc_table->dpm2Params.NearTDPLimit =
2337 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2338 smc_table->dpm2Params.SafePowerLimit =
2339 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2340
2341 ret = amdgpu_si_copy_bytes_to_smc(adev,
2342 (si_pi->state_table_start +
2343 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2344 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2345 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2346 sizeof(u32) * 2,
2347 si_pi->sram_end);
2348 if (ret)
2349 return ret;
2350 }
2351
2352 return 0;
2353 }
2354
si_calculate_power_efficiency_ratio(struct amdgpu_device * adev,const u16 prev_std_vddc,const u16 curr_std_vddc)2355 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2356 const u16 prev_std_vddc,
2357 const u16 curr_std_vddc)
2358 {
2359 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2360 u64 prev_vddc = (u64)prev_std_vddc;
2361 u64 curr_vddc = (u64)curr_std_vddc;
2362 u64 pwr_efficiency_ratio, n, d;
2363
2364 if ((prev_vddc == 0) || (curr_vddc == 0))
2365 return 0;
2366
2367 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2368 d = prev_vddc * prev_vddc;
2369 pwr_efficiency_ratio = div64_u64(n, d);
2370
2371 if (pwr_efficiency_ratio > (u64)0xFFFF)
2372 return 0;
2373
2374 return (u16)pwr_efficiency_ratio;
2375 }
2376
si_should_disable_uvd_powertune(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)2377 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2378 struct amdgpu_ps *amdgpu_state)
2379 {
2380 struct si_power_info *si_pi = si_get_pi(adev);
2381
2382 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2383 amdgpu_state->vclk && amdgpu_state->dclk)
2384 return true;
2385
2386 return false;
2387 }
2388
evergreen_get_pi(struct amdgpu_device * adev)2389 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2390 {
2391 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2392
2393 return pi;
2394 }
2395
si_populate_power_containment_values(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)2396 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2397 struct amdgpu_ps *amdgpu_state,
2398 SISLANDS_SMC_SWSTATE *smc_state)
2399 {
2400 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2401 struct ni_power_info *ni_pi = ni_get_pi(adev);
2402 struct si_ps *state = si_get_ps(amdgpu_state);
2403 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2404 u32 prev_sclk;
2405 u32 max_sclk;
2406 u32 min_sclk;
2407 u16 prev_std_vddc;
2408 u16 curr_std_vddc;
2409 int i;
2410 u16 pwr_efficiency_ratio;
2411 u8 max_ps_percent;
2412 bool disable_uvd_power_tune;
2413 int ret;
2414
2415 if (ni_pi->enable_power_containment == false)
2416 return 0;
2417
2418 if (state->performance_level_count == 0)
2419 return -EINVAL;
2420
2421 if (smc_state->levelCount != state->performance_level_count)
2422 return -EINVAL;
2423
2424 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2425
2426 smc_state->levels[0].dpm2.MaxPS = 0;
2427 smc_state->levels[0].dpm2.NearTDPDec = 0;
2428 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2429 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2430 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2431
2432 for (i = 1; i < state->performance_level_count; i++) {
2433 prev_sclk = state->performance_levels[i-1].sclk;
2434 max_sclk = state->performance_levels[i].sclk;
2435 if (i == 1)
2436 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2437 else
2438 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2439
2440 if (prev_sclk > max_sclk)
2441 return -EINVAL;
2442
2443 if ((max_ps_percent == 0) ||
2444 (prev_sclk == max_sclk) ||
2445 disable_uvd_power_tune)
2446 min_sclk = max_sclk;
2447 else if (i == 1)
2448 min_sclk = prev_sclk;
2449 else
2450 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2451
2452 if (min_sclk < state->performance_levels[0].sclk)
2453 min_sclk = state->performance_levels[0].sclk;
2454
2455 if (min_sclk == 0)
2456 return -EINVAL;
2457
2458 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2459 state->performance_levels[i-1].vddc, &vddc);
2460 if (ret)
2461 return ret;
2462
2463 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2464 if (ret)
2465 return ret;
2466
2467 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2468 state->performance_levels[i].vddc, &vddc);
2469 if (ret)
2470 return ret;
2471
2472 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2473 if (ret)
2474 return ret;
2475
2476 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2477 prev_std_vddc, curr_std_vddc);
2478
2479 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2480 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2481 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2482 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2483 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2484 }
2485
2486 return 0;
2487 }
2488
si_populate_sq_ramping_values(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)2489 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2490 struct amdgpu_ps *amdgpu_state,
2491 SISLANDS_SMC_SWSTATE *smc_state)
2492 {
2493 struct ni_power_info *ni_pi = ni_get_pi(adev);
2494 struct si_ps *state = si_get_ps(amdgpu_state);
2495 u32 sq_power_throttle, sq_power_throttle2;
2496 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2497 int i;
2498
2499 if (state->performance_level_count == 0)
2500 return -EINVAL;
2501
2502 if (smc_state->levelCount != state->performance_level_count)
2503 return -EINVAL;
2504
2505 if (adev->pm.dpm.sq_ramping_threshold == 0)
2506 return -EINVAL;
2507
2508 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (SQ_POWER_THROTTLE__MAX_POWER_MASK >> SQ_POWER_THROTTLE__MAX_POWER__SHIFT))
2509 enable_sq_ramping = false;
2510
2511 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (SQ_POWER_THROTTLE__MIN_POWER_MASK >> SQ_POWER_THROTTLE__MIN_POWER__SHIFT))
2512 enable_sq_ramping = false;
2513
2514 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK >> SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT))
2515 enable_sq_ramping = false;
2516
2517 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK >> SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT))
2518 enable_sq_ramping = false;
2519
2520 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK >> SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT))
2521 enable_sq_ramping = false;
2522
2523 for (i = 0; i < state->performance_level_count; i++) {
2524 sq_power_throttle = 0;
2525 sq_power_throttle2 = 0;
2526
2527 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2528 enable_sq_ramping) {
2529 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER << SQ_POWER_THROTTLE__MAX_POWER__SHIFT;
2530 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MIN_POWER << SQ_POWER_THROTTLE__MIN_POWER__SHIFT;
2531 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA << SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT;
2532 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_STI_SIZE << SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT;
2533 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_LTI_RATIO << SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT;
2534 } else {
2535 sq_power_throttle |= SQ_POWER_THROTTLE__MAX_POWER_MASK |
2536 SQ_POWER_THROTTLE__MIN_POWER_MASK;
2537 sq_power_throttle2 |= SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK |
2538 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK |
2539 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK;
2540 }
2541
2542 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2543 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2544 }
2545
2546 return 0;
2547 }
2548
si_enable_power_containment(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,bool enable)2549 static int si_enable_power_containment(struct amdgpu_device *adev,
2550 struct amdgpu_ps *amdgpu_new_state,
2551 bool enable)
2552 {
2553 struct ni_power_info *ni_pi = ni_get_pi(adev);
2554 PPSMC_Result smc_result;
2555 int ret = 0;
2556
2557 if (ni_pi->enable_power_containment) {
2558 if (enable) {
2559 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2560 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2561 if (smc_result != PPSMC_Result_OK) {
2562 ret = -EINVAL;
2563 ni_pi->pc_enabled = false;
2564 } else {
2565 ni_pi->pc_enabled = true;
2566 }
2567 }
2568 } else {
2569 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2570 if (smc_result != PPSMC_Result_OK)
2571 ret = -EINVAL;
2572 ni_pi->pc_enabled = false;
2573 }
2574 }
2575
2576 return ret;
2577 }
2578
si_initialize_smc_dte_tables(struct amdgpu_device * adev)2579 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2580 {
2581 struct si_power_info *si_pi = si_get_pi(adev);
2582 int ret = 0;
2583 struct si_dte_data *dte_data = &si_pi->dte_data;
2584 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2585 u32 table_size;
2586 u8 tdep_count;
2587 u32 i;
2588
2589 if (dte_data == NULL)
2590 si_pi->enable_dte = false;
2591
2592 if (si_pi->enable_dte == false)
2593 return 0;
2594
2595 if (dte_data->k <= 0)
2596 return -EINVAL;
2597
2598 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2599 if (dte_tables == NULL) {
2600 si_pi->enable_dte = false;
2601 return -ENOMEM;
2602 }
2603
2604 table_size = dte_data->k;
2605
2606 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2607 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2608
2609 tdep_count = dte_data->tdep_count;
2610 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2611 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2612
2613 dte_tables->K = cpu_to_be32(table_size);
2614 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2615 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2616 dte_tables->WindowSize = dte_data->window_size;
2617 dte_tables->temp_select = dte_data->temp_select;
2618 dte_tables->DTE_mode = dte_data->dte_mode;
2619 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2620
2621 if (tdep_count > 0)
2622 table_size--;
2623
2624 for (i = 0; i < table_size; i++) {
2625 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2626 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2627 }
2628
2629 dte_tables->Tdep_count = tdep_count;
2630
2631 for (i = 0; i < (u32)tdep_count; i++) {
2632 dte_tables->T_limits[i] = dte_data->t_limits[i];
2633 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2634 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2635 }
2636
2637 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2638 (u8 *)dte_tables,
2639 sizeof(Smc_SIslands_DTE_Configuration),
2640 si_pi->sram_end);
2641 kfree(dte_tables);
2642
2643 return ret;
2644 }
2645
si_get_cac_std_voltage_max_min(struct amdgpu_device * adev,u16 * max,u16 * min)2646 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2647 u16 *max, u16 *min)
2648 {
2649 struct si_power_info *si_pi = si_get_pi(adev);
2650 struct amdgpu_cac_leakage_table *table =
2651 &adev->pm.dpm.dyn_state.cac_leakage_table;
2652 u32 i;
2653 u32 v0_loadline;
2654
2655 if (table == NULL)
2656 return -EINVAL;
2657
2658 *max = 0;
2659 *min = 0xFFFF;
2660
2661 for (i = 0; i < table->count; i++) {
2662 if (table->entries[i].vddc > *max)
2663 *max = table->entries[i].vddc;
2664 if (table->entries[i].vddc < *min)
2665 *min = table->entries[i].vddc;
2666 }
2667
2668 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2669 return -EINVAL;
2670
2671 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2672
2673 if (v0_loadline > 0xFFFFUL)
2674 return -EINVAL;
2675
2676 *min = (u16)v0_loadline;
2677
2678 if ((*min > *max) || (*max == 0) || (*min == 0))
2679 return -EINVAL;
2680
2681 return 0;
2682 }
2683
si_get_cac_std_voltage_step(u16 max,u16 min)2684 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2685 {
2686 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2687 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2688 }
2689
si_init_dte_leakage_table(struct amdgpu_device * adev,PP_SIslands_CacConfig * cac_tables,u16 vddc_max,u16 vddc_min,u16 vddc_step,u16 t0,u16 t_step)2690 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2691 PP_SIslands_CacConfig *cac_tables,
2692 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2693 u16 t0, u16 t_step)
2694 {
2695 struct si_power_info *si_pi = si_get_pi(adev);
2696 u32 leakage;
2697 unsigned int i, j;
2698 s32 t;
2699 u32 smc_leakage;
2700 u32 scaling_factor;
2701 u16 voltage;
2702
2703 scaling_factor = si_get_smc_power_scaling_factor(adev);
2704
2705 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2706 t = (1000 * (i * t_step + t0));
2707
2708 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2709 voltage = vddc_max - (vddc_step * j);
2710
2711 si_calculate_leakage_for_v_and_t(adev,
2712 &si_pi->powertune_data->leakage_coefficients,
2713 voltage,
2714 t,
2715 si_pi->dyn_powertune_data.cac_leakage,
2716 &leakage);
2717
2718 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2719
2720 if (smc_leakage > 0xFFFF)
2721 smc_leakage = 0xFFFF;
2722
2723 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2724 cpu_to_be16((u16)smc_leakage);
2725 }
2726 }
2727 return 0;
2728 }
2729
si_init_simplified_leakage_table(struct amdgpu_device * adev,PP_SIslands_CacConfig * cac_tables,u16 vddc_max,u16 vddc_min,u16 vddc_step)2730 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2731 PP_SIslands_CacConfig *cac_tables,
2732 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2733 {
2734 struct si_power_info *si_pi = si_get_pi(adev);
2735 u32 leakage;
2736 unsigned int i, j;
2737 u32 smc_leakage;
2738 u32 scaling_factor;
2739 u16 voltage;
2740
2741 scaling_factor = si_get_smc_power_scaling_factor(adev);
2742
2743 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2744 voltage = vddc_max - (vddc_step * j);
2745
2746 si_calculate_leakage_for_v(adev,
2747 &si_pi->powertune_data->leakage_coefficients,
2748 si_pi->powertune_data->fixed_kt,
2749 voltage,
2750 si_pi->dyn_powertune_data.cac_leakage,
2751 &leakage);
2752
2753 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2754
2755 if (smc_leakage > 0xFFFF)
2756 smc_leakage = 0xFFFF;
2757
2758 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2759 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2760 cpu_to_be16((u16)smc_leakage);
2761 }
2762 return 0;
2763 }
2764
si_initialize_smc_cac_tables(struct amdgpu_device * adev)2765 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2766 {
2767 struct ni_power_info *ni_pi = ni_get_pi(adev);
2768 struct si_power_info *si_pi = si_get_pi(adev);
2769 PP_SIslands_CacConfig *cac_tables = NULL;
2770 u16 vddc_max, vddc_min, vddc_step;
2771 u16 t0, t_step;
2772 u32 load_line_slope, reg;
2773 int ret = 0;
2774 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2775
2776 if (ni_pi->enable_cac == false)
2777 return 0;
2778
2779 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2780 if (!cac_tables)
2781 return -ENOMEM;
2782
2783 reg = RREG32(mmCG_CAC_CTRL) & ~CG_CAC_CTRL__CAC_WINDOW_MASK;
2784 reg |= (si_pi->powertune_data->cac_window << CG_CAC_CTRL__CAC_WINDOW__SHIFT);
2785 WREG32(mmCG_CAC_CTRL, reg);
2786
2787 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2788 si_pi->dyn_powertune_data.dc_pwr_value =
2789 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2790 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2791 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2792
2793 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2794
2795 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2796 if (ret)
2797 goto done_free;
2798
2799 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2800 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2801 t_step = 4;
2802 t0 = 60;
2803
2804 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2805 ret = si_init_dte_leakage_table(adev, cac_tables,
2806 vddc_max, vddc_min, vddc_step,
2807 t0, t_step);
2808 else
2809 ret = si_init_simplified_leakage_table(adev, cac_tables,
2810 vddc_max, vddc_min, vddc_step);
2811 if (ret)
2812 goto done_free;
2813
2814 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2815
2816 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2817 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2818 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2819 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2820 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2821 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2822 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2823 cac_tables->calculation_repeats = cpu_to_be32(2);
2824 cac_tables->dc_cac = cpu_to_be32(0);
2825 cac_tables->log2_PG_LKG_SCALE = 12;
2826 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2827 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2828 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2829
2830 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2831 (u8 *)cac_tables,
2832 sizeof(PP_SIslands_CacConfig),
2833 si_pi->sram_end);
2834
2835 if (ret)
2836 goto done_free;
2837
2838 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2839
2840 done_free:
2841 if (ret) {
2842 ni_pi->enable_cac = false;
2843 ni_pi->enable_power_containment = false;
2844 }
2845
2846 kfree(cac_tables);
2847
2848 return ret;
2849 }
2850
si_program_cac_config_registers(struct amdgpu_device * adev,const struct si_cac_config_reg * cac_config_regs)2851 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2852 const struct si_cac_config_reg *cac_config_regs)
2853 {
2854 const struct si_cac_config_reg *config_regs = cac_config_regs;
2855 u32 data = 0, offset;
2856
2857 if (!config_regs)
2858 return -EINVAL;
2859
2860 while (config_regs->offset != 0xFFFFFFFF) {
2861 switch (config_regs->type) {
2862 case SISLANDS_CACCONFIG_CGIND:
2863 offset = SMC_CG_IND_START + config_regs->offset;
2864 if (offset < SMC_CG_IND_END)
2865 data = RREG32_SMC(offset);
2866 break;
2867 default:
2868 data = RREG32(config_regs->offset);
2869 break;
2870 }
2871
2872 data &= ~config_regs->mask;
2873 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2874
2875 switch (config_regs->type) {
2876 case SISLANDS_CACCONFIG_CGIND:
2877 offset = SMC_CG_IND_START + config_regs->offset;
2878 if (offset < SMC_CG_IND_END)
2879 WREG32_SMC(offset, data);
2880 break;
2881 default:
2882 WREG32(config_regs->offset, data);
2883 break;
2884 }
2885 config_regs++;
2886 }
2887 return 0;
2888 }
2889
si_initialize_hardware_cac_manager(struct amdgpu_device * adev)2890 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2891 {
2892 struct ni_power_info *ni_pi = ni_get_pi(adev);
2893 struct si_power_info *si_pi = si_get_pi(adev);
2894 int ret;
2895
2896 if ((ni_pi->enable_cac == false) ||
2897 (ni_pi->cac_configuration_required == false))
2898 return 0;
2899
2900 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2901 if (ret)
2902 return ret;
2903 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2904 if (ret)
2905 return ret;
2906 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2907 if (ret)
2908 return ret;
2909
2910 return 0;
2911 }
2912
si_enable_smc_cac(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,bool enable)2913 static int si_enable_smc_cac(struct amdgpu_device *adev,
2914 struct amdgpu_ps *amdgpu_new_state,
2915 bool enable)
2916 {
2917 struct ni_power_info *ni_pi = ni_get_pi(adev);
2918 struct si_power_info *si_pi = si_get_pi(adev);
2919 PPSMC_Result smc_result;
2920 int ret = 0;
2921
2922 if (ni_pi->enable_cac) {
2923 if (enable) {
2924 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2925 if (ni_pi->support_cac_long_term_average) {
2926 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2927 if (smc_result != PPSMC_Result_OK)
2928 ni_pi->support_cac_long_term_average = false;
2929 }
2930
2931 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2932 if (smc_result != PPSMC_Result_OK) {
2933 ret = -EINVAL;
2934 ni_pi->cac_enabled = false;
2935 } else {
2936 ni_pi->cac_enabled = true;
2937 }
2938
2939 if (si_pi->enable_dte) {
2940 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2941 if (smc_result != PPSMC_Result_OK)
2942 ret = -EINVAL;
2943 }
2944 }
2945 } else if (ni_pi->cac_enabled) {
2946 if (si_pi->enable_dte)
2947 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2948
2949 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2950
2951 ni_pi->cac_enabled = false;
2952
2953 if (ni_pi->support_cac_long_term_average)
2954 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2955 }
2956 }
2957 return ret;
2958 }
2959
si_init_smc_spll_table(struct amdgpu_device * adev)2960 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2961 {
2962 struct ni_power_info *ni_pi = ni_get_pi(adev);
2963 struct si_power_info *si_pi = si_get_pi(adev);
2964 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2965 SISLANDS_SMC_SCLK_VALUE sclk_params;
2966 u32 fb_div, p_div;
2967 u32 clk_s, clk_v;
2968 u32 sclk = 0;
2969 int ret = 0;
2970 u32 tmp;
2971 int i;
2972
2973 if (si_pi->spll_table_start == 0)
2974 return -EINVAL;
2975
2976 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2977 if (spll_table == NULL)
2978 return -ENOMEM;
2979
2980 for (i = 0; i < 256; i++) {
2981 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2982 if (ret)
2983 break;
2984 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK) >> CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT;
2985 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK) >> CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT;
2986 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK) >> CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT;
2987 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK) >> CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT;
2988
2989 fb_div &= ~0x00001FFF;
2990 fb_div >>= 1;
2991 clk_v >>= 6;
2992
2993 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2994 ret = -EINVAL;
2995 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2996 ret = -EINVAL;
2997 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2998 ret = -EINVAL;
2999 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
3000 ret = -EINVAL;
3001
3002 if (ret)
3003 break;
3004
3005 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
3006 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
3007 spll_table->freq[i] = cpu_to_be32(tmp);
3008
3009 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
3010 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
3011 spll_table->ss[i] = cpu_to_be32(tmp);
3012
3013 sclk += 512;
3014 }
3015
3016
3017 if (!ret)
3018 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
3019 (u8 *)spll_table,
3020 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3021 si_pi->sram_end);
3022
3023 if (ret)
3024 ni_pi->enable_power_containment = false;
3025
3026 kfree(spll_table);
3027
3028 return ret;
3029 }
3030
si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device * adev,u16 vce_voltage)3031 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3032 u16 vce_voltage)
3033 {
3034 u16 highest_leakage = 0;
3035 struct si_power_info *si_pi = si_get_pi(adev);
3036 int i;
3037
3038 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3039 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3040 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3041 }
3042
3043 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3044 return highest_leakage;
3045
3046 return vce_voltage;
3047 }
3048
si_get_vce_clock_voltage(struct amdgpu_device * adev,u32 evclk,u32 ecclk,u16 * voltage)3049 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3050 u32 evclk, u32 ecclk, u16 *voltage)
3051 {
3052 u32 i;
3053 int ret = -EINVAL;
3054 struct amdgpu_vce_clock_voltage_dependency_table *table =
3055 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3056
3057 if (((evclk == 0) && (ecclk == 0)) ||
3058 (table && (table->count == 0))) {
3059 *voltage = 0;
3060 return 0;
3061 }
3062
3063 for (i = 0; i < table->count; i++) {
3064 if ((evclk <= table->entries[i].evclk) &&
3065 (ecclk <= table->entries[i].ecclk)) {
3066 *voltage = table->entries[i].v;
3067 ret = 0;
3068 break;
3069 }
3070 }
3071
3072 /* if no match return the highest voltage */
3073 if (ret)
3074 *voltage = table->entries[table->count - 1].v;
3075
3076 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3077
3078 return ret;
3079 }
3080
si_dpm_vblank_too_short(void * handle)3081 static bool si_dpm_vblank_too_short(void *handle)
3082 {
3083 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3084 u32 vblank_time = adev->pm.pm_display_cfg.min_vblank_time;
3085 /* we never hit the non-gddr5 limit so disable it */
3086 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3087
3088 /* Consider zero vblank time too short and disable MCLK switching.
3089 * Note that the vblank time is set to maximum when no displays are attached,
3090 * so we'll still enable MCLK switching in that case.
3091 */
3092 if (vblank_time == 0)
3093 return true;
3094 else if (vblank_time < switch_limit)
3095 return true;
3096 else
3097 return false;
3098
3099 }
3100
ni_copy_and_switch_arb_sets(struct amdgpu_device * adev,u32 arb_freq_src,u32 arb_freq_dest)3101 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3102 u32 arb_freq_src, u32 arb_freq_dest)
3103 {
3104 u32 mc_arb_dram_timing;
3105 u32 mc_arb_dram_timing2;
3106 u32 burst_time;
3107 u32 mc_cg_config;
3108
3109 switch (arb_freq_src) {
3110 case MC_CG_ARB_FREQ_F0:
3111 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3112 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3113 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3114 break;
3115 case MC_CG_ARB_FREQ_F1:
3116 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3117 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3118 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3119 break;
3120 case MC_CG_ARB_FREQ_F2:
3121 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3122 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3123 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3124 break;
3125 case MC_CG_ARB_FREQ_F3:
3126 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3127 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3128 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3129 break;
3130 default:
3131 return -EINVAL;
3132 }
3133
3134 switch (arb_freq_dest) {
3135 case MC_CG_ARB_FREQ_F0:
3136 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3137 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3138 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3139 break;
3140 case MC_CG_ARB_FREQ_F1:
3141 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3142 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3143 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3144 break;
3145 case MC_CG_ARB_FREQ_F2:
3146 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3147 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3148 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3149 break;
3150 case MC_CG_ARB_FREQ_F3:
3151 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3152 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3153 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3154 break;
3155 default:
3156 return -EINVAL;
3157 }
3158
3159 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3160 WREG32(MC_CG_CONFIG, mc_cg_config);
3161 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3162
3163 return 0;
3164 }
3165
ni_update_current_ps(struct amdgpu_device * adev,struct amdgpu_ps * rps)3166 static void ni_update_current_ps(struct amdgpu_device *adev,
3167 struct amdgpu_ps *rps)
3168 {
3169 struct si_ps *new_ps = si_get_ps(rps);
3170 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3171 struct ni_power_info *ni_pi = ni_get_pi(adev);
3172
3173 eg_pi->current_rps = *rps;
3174 ni_pi->current_ps = *new_ps;
3175 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3176 adev->pm.dpm.current_ps = &eg_pi->current_rps;
3177 }
3178
ni_update_requested_ps(struct amdgpu_device * adev,struct amdgpu_ps * rps)3179 static void ni_update_requested_ps(struct amdgpu_device *adev,
3180 struct amdgpu_ps *rps)
3181 {
3182 struct si_ps *new_ps = si_get_ps(rps);
3183 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3184 struct ni_power_info *ni_pi = ni_get_pi(adev);
3185
3186 eg_pi->requested_rps = *rps;
3187 ni_pi->requested_ps = *new_ps;
3188 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3189 adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3190 }
3191
ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device * adev,struct amdgpu_ps * new_ps,struct amdgpu_ps * old_ps)3192 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3193 struct amdgpu_ps *new_ps,
3194 struct amdgpu_ps *old_ps)
3195 {
3196 struct si_ps *new_state = si_get_ps(new_ps);
3197 struct si_ps *current_state = si_get_ps(old_ps);
3198
3199 if ((new_ps->vclk == old_ps->vclk) &&
3200 (new_ps->dclk == old_ps->dclk))
3201 return;
3202
3203 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3204 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3205 return;
3206
3207 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3208 }
3209
ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device * adev,struct amdgpu_ps * new_ps,struct amdgpu_ps * old_ps)3210 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3211 struct amdgpu_ps *new_ps,
3212 struct amdgpu_ps *old_ps)
3213 {
3214 struct si_ps *new_state = si_get_ps(new_ps);
3215 struct si_ps *current_state = si_get_ps(old_ps);
3216
3217 if ((new_ps->vclk == old_ps->vclk) &&
3218 (new_ps->dclk == old_ps->dclk))
3219 return;
3220
3221 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3222 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3223 return;
3224
3225 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3226 }
3227
btc_find_voltage(struct atom_voltage_table * table,u16 voltage)3228 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3229 {
3230 unsigned int i;
3231
3232 for (i = 0; i < table->count; i++)
3233 if (voltage <= table->entries[i].value)
3234 return table->entries[i].value;
3235
3236 return table->entries[table->count - 1].value;
3237 }
3238
btc_find_valid_clock(struct amdgpu_clock_array * clocks,u32 max_clock,u32 requested_clock)3239 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3240 u32 max_clock, u32 requested_clock)
3241 {
3242 unsigned int i;
3243
3244 if ((clocks == NULL) || (clocks->count == 0))
3245 return (requested_clock < max_clock) ? requested_clock : max_clock;
3246
3247 for (i = 0; i < clocks->count; i++) {
3248 if (clocks->values[i] >= requested_clock)
3249 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3250 }
3251
3252 return (clocks->values[clocks->count - 1] < max_clock) ?
3253 clocks->values[clocks->count - 1] : max_clock;
3254 }
3255
btc_get_valid_mclk(struct amdgpu_device * adev,u32 max_mclk,u32 requested_mclk)3256 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3257 u32 max_mclk, u32 requested_mclk)
3258 {
3259 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3260 max_mclk, requested_mclk);
3261 }
3262
btc_get_valid_sclk(struct amdgpu_device * adev,u32 max_sclk,u32 requested_sclk)3263 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3264 u32 max_sclk, u32 requested_sclk)
3265 {
3266 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3267 max_sclk, requested_sclk);
3268 }
3269
btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table * table,u32 * max_clock)3270 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3271 u32 *max_clock)
3272 {
3273 u32 i, clock = 0;
3274
3275 if ((table == NULL) || (table->count == 0)) {
3276 *max_clock = clock;
3277 return;
3278 }
3279
3280 for (i = 0; i < table->count; i++) {
3281 if (clock < table->entries[i].clk)
3282 clock = table->entries[i].clk;
3283 }
3284 *max_clock = clock;
3285 }
3286
btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table * table,u32 clock,u16 max_voltage,u16 * voltage)3287 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3288 u32 clock, u16 max_voltage, u16 *voltage)
3289 {
3290 u32 i;
3291
3292 if ((table == NULL) || (table->count == 0))
3293 return;
3294
3295 for (i= 0; i < table->count; i++) {
3296 if (clock <= table->entries[i].clk) {
3297 if (*voltage < table->entries[i].v)
3298 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3299 table->entries[i].v : max_voltage);
3300 return;
3301 }
3302 }
3303
3304 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3305 }
3306
btc_adjust_clock_combinations(struct amdgpu_device * adev,const struct amdgpu_clock_and_voltage_limits * max_limits,struct rv7xx_pl * pl)3307 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3308 const struct amdgpu_clock_and_voltage_limits *max_limits,
3309 struct rv7xx_pl *pl)
3310 {
3311
3312 if ((pl->mclk == 0) || (pl->sclk == 0))
3313 return;
3314
3315 if (pl->mclk == pl->sclk)
3316 return;
3317
3318 if (pl->mclk > pl->sclk) {
3319 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3320 pl->sclk = btc_get_valid_sclk(adev,
3321 max_limits->sclk,
3322 (pl->mclk +
3323 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3324 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3325 } else {
3326 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3327 pl->mclk = btc_get_valid_mclk(adev,
3328 max_limits->mclk,
3329 pl->sclk -
3330 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3331 }
3332 }
3333
btc_apply_voltage_delta_rules(struct amdgpu_device * adev,u16 max_vddc,u16 max_vddci,u16 * vddc,u16 * vddci)3334 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3335 u16 max_vddc, u16 max_vddci,
3336 u16 *vddc, u16 *vddci)
3337 {
3338 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3339 u16 new_voltage;
3340
3341 if ((0 == *vddc) || (0 == *vddci))
3342 return;
3343
3344 if (*vddc > *vddci) {
3345 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3346 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3347 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3348 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3349 }
3350 } else {
3351 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3352 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3353 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3354 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3355 }
3356 }
3357 }
3358
r600_calculate_u_and_p(u32 i,u32 r_c,u32 p_b,u32 * p,u32 * u)3359 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3360 u32 *p, u32 *u)
3361 {
3362 u32 b_c = 0;
3363 u32 i_c;
3364 u32 tmp;
3365
3366 i_c = (i * r_c) / 100;
3367 tmp = i_c >> p_b;
3368
3369 while (tmp) {
3370 b_c++;
3371 tmp >>= 1;
3372 }
3373
3374 *u = (b_c + 1) / 2;
3375 *p = i_c / (1 << (2 * (*u)));
3376 }
3377
r600_calculate_at(u32 t,u32 h,u32 fh,u32 fl,u32 * tl,u32 * th)3378 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3379 {
3380 u32 k, a, ah, al;
3381 u32 t1;
3382
3383 if ((fl == 0) || (fh == 0) || (fl > fh))
3384 return -EINVAL;
3385
3386 k = (100 * fh) / fl;
3387 t1 = (t * (k - 100));
3388 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3389 a = (a + 5) / 10;
3390 ah = ((a * t) + 5000) / 10000;
3391 al = a - ah;
3392
3393 *th = t - ah;
3394 *tl = t + al;
3395
3396 return 0;
3397 }
3398
r600_is_uvd_state(u32 class,u32 class2)3399 static bool r600_is_uvd_state(u32 class, u32 class2)
3400 {
3401 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3402 return true;
3403 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3404 return true;
3405 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3406 return true;
3407 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3408 return true;
3409 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3410 return true;
3411 return false;
3412 }
3413
rv770_get_memory_module_index(struct amdgpu_device * adev)3414 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3415 {
3416 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3417 }
3418
rv770_get_max_vddc(struct amdgpu_device * adev)3419 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3420 {
3421 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3422 u16 vddc;
3423
3424 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3425 pi->max_vddc = 0;
3426 else
3427 pi->max_vddc = vddc;
3428 }
3429
rv770_get_engine_memory_ss(struct amdgpu_device * adev)3430 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3431 {
3432 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3433 struct amdgpu_atom_ss ss;
3434
3435 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3436 ASIC_INTERNAL_ENGINE_SS, 0);
3437 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3438 ASIC_INTERNAL_MEMORY_SS, 0);
3439
3440 if (pi->sclk_ss || pi->mclk_ss)
3441 pi->dynamic_ss = true;
3442 else
3443 pi->dynamic_ss = false;
3444 }
3445
3446
si_apply_state_adjust_rules(struct amdgpu_device * adev,struct amdgpu_ps * rps)3447 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3448 struct amdgpu_ps *rps)
3449 {
3450 const struct amd_pp_display_configuration *display_cfg =
3451 &adev->pm.pm_display_cfg;
3452 struct si_ps *ps = si_get_ps(rps);
3453 struct amdgpu_clock_and_voltage_limits *max_limits;
3454 bool disable_mclk_switching = false;
3455 bool disable_sclk_switching = false;
3456 u32 mclk, sclk;
3457 u16 vddc, vddci, min_vce_voltage = 0;
3458 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3459 u32 max_sclk = 0, max_mclk = 0;
3460 u32 high_pixelclock_count = 0;
3461 int i;
3462
3463 if (adev->asic_type == CHIP_HAINAN) {
3464 if ((adev->pdev->revision == 0x81) ||
3465 (adev->pdev->revision == 0xC3) ||
3466 (adev->pdev->device == 0x6664) ||
3467 (adev->pdev->device == 0x6665) ||
3468 (adev->pdev->device == 0x6667)) {
3469 max_sclk = 75000;
3470 }
3471 if ((adev->pdev->revision == 0xC3) ||
3472 (adev->pdev->device == 0x6665)) {
3473 max_sclk = 60000;
3474 max_mclk = 80000;
3475 }
3476 } else if (adev->asic_type == CHIP_OLAND) {
3477 if ((adev->pdev->revision == 0xC7) ||
3478 (adev->pdev->revision == 0x80) ||
3479 (adev->pdev->revision == 0x81) ||
3480 (adev->pdev->revision == 0x83) ||
3481 (adev->pdev->revision == 0x87) ||
3482 (adev->pdev->device == 0x6604) ||
3483 (adev->pdev->device == 0x6605)) {
3484 max_sclk = 75000;
3485 }
3486 }
3487
3488 /* We define "high pixelclock" for SI as higher than necessary for 4K 30Hz.
3489 * For example, 4K 60Hz and 1080p 144Hz fall into this category.
3490 * Find number of such displays connected.
3491 */
3492 for (i = 0; i < display_cfg->num_display; i++) {
3493 /* The array only contains active displays. */
3494 if (display_cfg->displays[i].pixel_clock > 297000)
3495 high_pixelclock_count++;
3496 }
3497
3498 /* These are some ad-hoc fixes to some issues observed with SI GPUs.
3499 * They are necessary because we don't have something like dce_calcs
3500 * for these GPUs to calculate bandwidth requirements.
3501 */
3502 if (high_pixelclock_count) {
3503 /* Work around flickering lines at the bottom edge
3504 * of the screen when using a single 4K 60Hz monitor.
3505 */
3506 disable_mclk_switching = true;
3507
3508 /* On Oland, we observe some flickering when two 4K 60Hz
3509 * displays are connected, possibly because voltage is too low.
3510 * Raise the voltage by requiring a higher SCLK.
3511 * (Voltage cannot be adjusted independently without also SCLK.)
3512 */
3513 if (high_pixelclock_count > 1 && adev->asic_type == CHIP_OLAND)
3514 disable_sclk_switching = true;
3515 }
3516
3517 if (rps->vce_active) {
3518 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3519 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3520 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3521 &min_vce_voltage);
3522 } else {
3523 rps->evclk = 0;
3524 rps->ecclk = 0;
3525 }
3526
3527 if ((adev->pm.pm_display_cfg.num_display > 1) ||
3528 si_dpm_vblank_too_short(adev))
3529 disable_mclk_switching = true;
3530
3531 if (rps->vclk || rps->dclk) {
3532 disable_mclk_switching = true;
3533 disable_sclk_switching = true;
3534 }
3535
3536 if (adev->pm.ac_power)
3537 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3538 else
3539 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3540
3541 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3542 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3543 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3544 }
3545 if (adev->pm.ac_power == false) {
3546 for (i = 0; i < ps->performance_level_count; i++) {
3547 if (ps->performance_levels[i].mclk > max_limits->mclk)
3548 ps->performance_levels[i].mclk = max_limits->mclk;
3549 if (ps->performance_levels[i].sclk > max_limits->sclk)
3550 ps->performance_levels[i].sclk = max_limits->sclk;
3551 if (ps->performance_levels[i].vddc > max_limits->vddc)
3552 ps->performance_levels[i].vddc = max_limits->vddc;
3553 if (ps->performance_levels[i].vddci > max_limits->vddci)
3554 ps->performance_levels[i].vddci = max_limits->vddci;
3555 }
3556 }
3557
3558 /* limit clocks to max supported clocks based on voltage dependency tables */
3559 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3560 &max_sclk_vddc);
3561 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3562 &max_mclk_vddci);
3563 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3564 &max_mclk_vddc);
3565
3566 for (i = 0; i < ps->performance_level_count; i++) {
3567 if (max_sclk_vddc) {
3568 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3569 ps->performance_levels[i].sclk = max_sclk_vddc;
3570 }
3571 if (max_mclk_vddci) {
3572 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3573 ps->performance_levels[i].mclk = max_mclk_vddci;
3574 }
3575 if (max_mclk_vddc) {
3576 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3577 ps->performance_levels[i].mclk = max_mclk_vddc;
3578 }
3579 if (max_mclk) {
3580 if (ps->performance_levels[i].mclk > max_mclk)
3581 ps->performance_levels[i].mclk = max_mclk;
3582 }
3583 if (max_sclk) {
3584 if (ps->performance_levels[i].sclk > max_sclk)
3585 ps->performance_levels[i].sclk = max_sclk;
3586 }
3587 }
3588
3589 /* XXX validate the min clocks required for display */
3590
3591 if (disable_mclk_switching) {
3592 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3593 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3594 } else {
3595 mclk = ps->performance_levels[0].mclk;
3596 vddci = ps->performance_levels[0].vddci;
3597 }
3598
3599 if (disable_sclk_switching) {
3600 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3601 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3602 } else {
3603 sclk = ps->performance_levels[0].sclk;
3604 vddc = ps->performance_levels[0].vddc;
3605 }
3606
3607 if (rps->vce_active) {
3608 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3609 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3610 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3611 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3612 }
3613
3614 /* adjusted low state */
3615 ps->performance_levels[0].sclk = sclk;
3616 ps->performance_levels[0].mclk = mclk;
3617 ps->performance_levels[0].vddc = vddc;
3618 ps->performance_levels[0].vddci = vddci;
3619
3620 if (disable_sclk_switching) {
3621 sclk = ps->performance_levels[0].sclk;
3622 for (i = 1; i < ps->performance_level_count; i++) {
3623 if (sclk < ps->performance_levels[i].sclk)
3624 sclk = ps->performance_levels[i].sclk;
3625 }
3626 for (i = 0; i < ps->performance_level_count; i++) {
3627 ps->performance_levels[i].sclk = sclk;
3628 ps->performance_levels[i].vddc = vddc;
3629 }
3630 } else {
3631 for (i = 1; i < ps->performance_level_count; i++) {
3632 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3633 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3634 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3635 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3636 }
3637 }
3638
3639 if (disable_mclk_switching) {
3640 mclk = ps->performance_levels[0].mclk;
3641 for (i = 1; i < ps->performance_level_count; i++) {
3642 if (mclk < ps->performance_levels[i].mclk)
3643 mclk = ps->performance_levels[i].mclk;
3644 }
3645 for (i = 0; i < ps->performance_level_count; i++) {
3646 ps->performance_levels[i].mclk = mclk;
3647 ps->performance_levels[i].vddci = vddci;
3648 }
3649 } else {
3650 for (i = 1; i < ps->performance_level_count; i++) {
3651 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3652 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3653 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3654 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3655 }
3656 }
3657
3658 for (i = 0; i < ps->performance_level_count; i++)
3659 btc_adjust_clock_combinations(adev, max_limits,
3660 &ps->performance_levels[i]);
3661
3662 for (i = 0; i < ps->performance_level_count; i++) {
3663 if (ps->performance_levels[i].vddc < min_vce_voltage)
3664 ps->performance_levels[i].vddc = min_vce_voltage;
3665 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3666 ps->performance_levels[i].sclk,
3667 max_limits->vddc, &ps->performance_levels[i].vddc);
3668 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3669 ps->performance_levels[i].mclk,
3670 max_limits->vddci, &ps->performance_levels[i].vddci);
3671 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3672 ps->performance_levels[i].mclk,
3673 max_limits->vddc, &ps->performance_levels[i].vddc);
3674 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3675 display_cfg->display_clk,
3676 max_limits->vddc, &ps->performance_levels[i].vddc);
3677 }
3678
3679 for (i = 0; i < ps->performance_level_count; i++) {
3680 btc_apply_voltage_delta_rules(adev,
3681 max_limits->vddc, max_limits->vddci,
3682 &ps->performance_levels[i].vddc,
3683 &ps->performance_levels[i].vddci);
3684 }
3685
3686 ps->dc_compatible = true;
3687 for (i = 0; i < ps->performance_level_count; i++) {
3688 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3689 ps->dc_compatible = false;
3690 }
3691 }
3692
3693 #if 0
3694 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3695 u16 reg_offset, u32 *value)
3696 {
3697 struct si_power_info *si_pi = si_get_pi(adev);
3698
3699 return amdgpu_si_read_smc_sram_dword(adev,
3700 si_pi->soft_regs_start + reg_offset, value,
3701 si_pi->sram_end);
3702 }
3703 #endif
3704
si_write_smc_soft_register(struct amdgpu_device * adev,u16 reg_offset,u32 value)3705 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3706 u16 reg_offset, u32 value)
3707 {
3708 struct si_power_info *si_pi = si_get_pi(adev);
3709
3710 return amdgpu_si_write_smc_sram_dword(adev,
3711 si_pi->soft_regs_start + reg_offset,
3712 value, si_pi->sram_end);
3713 }
3714
si_is_special_1gb_platform(struct amdgpu_device * adev)3715 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3716 {
3717 bool ret = false;
3718 u32 tmp, width, row, column, bank, density;
3719 bool is_memory_gddr5, is_special;
3720
3721 tmp = RREG32(MC_SEQ_MISC0);
3722 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3723 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3724 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3725
3726 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3727 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3728
3729 tmp = RREG32(mmMC_ARB_RAMCFG);
3730 row = ((tmp & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT) + 10;
3731 column = ((tmp & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT) + 8;
3732 bank = ((tmp & MC_ARB_RAMCFG__NOOFBANK_MASK) >> MC_ARB_RAMCFG__NOOFBANK__SHIFT) + 2;
3733
3734 density = (1 << (row + column - 20 + bank)) * width;
3735
3736 if ((adev->pdev->device == 0x6819) &&
3737 is_memory_gddr5 && is_special && (density == 0x400))
3738 ret = true;
3739
3740 return ret;
3741 }
3742
si_get_leakage_vddc(struct amdgpu_device * adev)3743 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3744 {
3745 struct si_power_info *si_pi = si_get_pi(adev);
3746 u16 vddc, count = 0;
3747 int i, ret;
3748
3749 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3750 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3751
3752 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3753 si_pi->leakage_voltage.entries[count].voltage = vddc;
3754 si_pi->leakage_voltage.entries[count].leakage_index =
3755 SISLANDS_LEAKAGE_INDEX0 + i;
3756 count++;
3757 }
3758 }
3759 si_pi->leakage_voltage.count = count;
3760 }
3761
si_get_leakage_voltage_from_leakage_index(struct amdgpu_device * adev,u32 index,u16 * leakage_voltage)3762 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3763 u32 index, u16 *leakage_voltage)
3764 {
3765 struct si_power_info *si_pi = si_get_pi(adev);
3766 int i;
3767
3768 if (leakage_voltage == NULL)
3769 return -EINVAL;
3770
3771 if ((index & 0xff00) != 0xff00)
3772 return -EINVAL;
3773
3774 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3775 return -EINVAL;
3776
3777 if (index < SISLANDS_LEAKAGE_INDEX0)
3778 return -EINVAL;
3779
3780 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3781 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3782 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3783 return 0;
3784 }
3785 }
3786 return -EAGAIN;
3787 }
3788
si_set_dpm_event_sources(struct amdgpu_device * adev,u32 sources)3789 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3790 {
3791 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3792 bool want_thermal_protection;
3793 enum si_dpm_event_src dpm_event_src;
3794
3795 switch (sources) {
3796 case 0:
3797 default:
3798 want_thermal_protection = false;
3799 break;
3800 case (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL):
3801 want_thermal_protection = true;
3802 dpm_event_src = SI_DPM_EVENT_SRC_DIGITAL;
3803 break;
3804 case (1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3805 want_thermal_protection = true;
3806 dpm_event_src = SI_DPM_EVENT_SRC_EXTERNAL;
3807 break;
3808 case ((1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3809 (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3810 want_thermal_protection = true;
3811 dpm_event_src = SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3812 break;
3813 }
3814
3815 if (want_thermal_protection) {
3816 WREG32_P(mmCG_THERMAL_CTRL, dpm_event_src << CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT, ~CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK);
3817 if (pi->thermal_protection)
3818 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
3819 } else {
3820 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
3821 }
3822 }
3823
si_enable_auto_throttle_source(struct amdgpu_device * adev,enum si_dpm_auto_throttle_src source,bool enable)3824 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3825 enum si_dpm_auto_throttle_src source,
3826 bool enable)
3827 {
3828 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3829
3830 if (enable) {
3831 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3832 pi->active_auto_throttle_sources |= 1 << source;
3833 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3834 }
3835 } else {
3836 if (pi->active_auto_throttle_sources & (1 << source)) {
3837 pi->active_auto_throttle_sources &= ~(1 << source);
3838 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3839 }
3840 }
3841 }
3842
si_start_dpm(struct amdgpu_device * adev)3843 static void si_start_dpm(struct amdgpu_device *adev)
3844 {
3845 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK);
3846 }
3847
si_stop_dpm(struct amdgpu_device * adev)3848 static void si_stop_dpm(struct amdgpu_device *adev)
3849 {
3850 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK);
3851 }
3852
si_enable_sclk_control(struct amdgpu_device * adev,bool enable)3853 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3854 {
3855 if (enable)
3856 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK);
3857 else
3858 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK);
3859
3860 }
3861
3862 #if 0
3863 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3864 u32 thermal_level)
3865 {
3866 PPSMC_Result ret;
3867
3868 if (thermal_level == 0) {
3869 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3870 if (ret == PPSMC_Result_OK)
3871 return 0;
3872 else
3873 return -EINVAL;
3874 }
3875 return 0;
3876 }
3877
3878 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3879 {
3880 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3881 }
3882 #endif
3883
3884 #if 0
3885 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3886 {
3887 if (ac_power)
3888 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3889 0 : -EINVAL;
3890
3891 return 0;
3892 }
3893 #endif
3894
si_send_msg_to_smc_with_parameter(struct amdgpu_device * adev,PPSMC_Msg msg,u32 parameter)3895 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3896 PPSMC_Msg msg, u32 parameter)
3897 {
3898 WREG32(mmSMC_SCRATCH0, parameter);
3899 return amdgpu_si_send_msg_to_smc(adev, msg);
3900 }
3901
si_restrict_performance_levels_before_switch(struct amdgpu_device * adev)3902 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3903 {
3904 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3905 return -EINVAL;
3906
3907 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3908 0 : -EINVAL;
3909 }
3910
si_dpm_force_performance_level(void * handle,enum amd_dpm_forced_level level)3911 static int si_dpm_force_performance_level(void *handle,
3912 enum amd_dpm_forced_level level)
3913 {
3914 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3915 struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3916 struct si_ps *ps = si_get_ps(rps);
3917 u32 levels = ps->performance_level_count;
3918
3919 if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
3920 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3921 return -EINVAL;
3922
3923 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3924 return -EINVAL;
3925 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
3926 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3927 return -EINVAL;
3928
3929 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3930 return -EINVAL;
3931 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
3932 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3933 return -EINVAL;
3934
3935 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3936 return -EINVAL;
3937 }
3938
3939 adev->pm.dpm.forced_level = level;
3940
3941 return 0;
3942 }
3943
3944 #if 0
3945 static int si_set_boot_state(struct amdgpu_device *adev)
3946 {
3947 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3948 0 : -EINVAL;
3949 }
3950 #endif
3951
si_set_sw_state(struct amdgpu_device * adev)3952 static int si_set_sw_state(struct amdgpu_device *adev)
3953 {
3954 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3955 0 : -EINVAL;
3956 }
3957
si_halt_smc(struct amdgpu_device * adev)3958 static int si_halt_smc(struct amdgpu_device *adev)
3959 {
3960 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3961 return -EINVAL;
3962
3963 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3964 0 : -EINVAL;
3965 }
3966
si_resume_smc(struct amdgpu_device * adev)3967 static int si_resume_smc(struct amdgpu_device *adev)
3968 {
3969 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3970 return -EINVAL;
3971
3972 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3973 0 : -EINVAL;
3974 }
3975
si_dpm_start_smc(struct amdgpu_device * adev)3976 static void si_dpm_start_smc(struct amdgpu_device *adev)
3977 {
3978 amdgpu_si_program_jump_on_start(adev);
3979 amdgpu_si_start_smc(adev);
3980 amdgpu_si_smc_clock(adev, true);
3981 }
3982
si_dpm_stop_smc(struct amdgpu_device * adev)3983 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3984 {
3985 amdgpu_si_reset_smc(adev);
3986 amdgpu_si_smc_clock(adev, false);
3987 }
3988
si_process_firmware_header(struct amdgpu_device * adev)3989 static int si_process_firmware_header(struct amdgpu_device *adev)
3990 {
3991 struct si_power_info *si_pi = si_get_pi(adev);
3992 u32 tmp;
3993 int ret;
3994
3995 ret = amdgpu_si_read_smc_sram_dword(adev,
3996 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3997 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3998 &tmp, si_pi->sram_end);
3999 if (ret)
4000 return ret;
4001
4002 si_pi->state_table_start = tmp;
4003
4004 ret = amdgpu_si_read_smc_sram_dword(adev,
4005 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4006 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
4007 &tmp, si_pi->sram_end);
4008 if (ret)
4009 return ret;
4010
4011 si_pi->soft_regs_start = tmp;
4012
4013 ret = amdgpu_si_read_smc_sram_dword(adev,
4014 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4015 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
4016 &tmp, si_pi->sram_end);
4017 if (ret)
4018 return ret;
4019
4020 si_pi->mc_reg_table_start = tmp;
4021
4022 ret = amdgpu_si_read_smc_sram_dword(adev,
4023 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4024 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
4025 &tmp, si_pi->sram_end);
4026 if (ret)
4027 return ret;
4028
4029 si_pi->fan_table_start = tmp;
4030
4031 ret = amdgpu_si_read_smc_sram_dword(adev,
4032 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4033 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4034 &tmp, si_pi->sram_end);
4035 if (ret)
4036 return ret;
4037
4038 si_pi->arb_table_start = tmp;
4039
4040 ret = amdgpu_si_read_smc_sram_dword(adev,
4041 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4042 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4043 &tmp, si_pi->sram_end);
4044 if (ret)
4045 return ret;
4046
4047 si_pi->cac_table_start = tmp;
4048
4049 ret = amdgpu_si_read_smc_sram_dword(adev,
4050 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4051 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4052 &tmp, si_pi->sram_end);
4053 if (ret)
4054 return ret;
4055
4056 si_pi->dte_table_start = tmp;
4057
4058 ret = amdgpu_si_read_smc_sram_dword(adev,
4059 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4060 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4061 &tmp, si_pi->sram_end);
4062 if (ret)
4063 return ret;
4064
4065 si_pi->spll_table_start = tmp;
4066
4067 ret = amdgpu_si_read_smc_sram_dword(adev,
4068 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4069 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4070 &tmp, si_pi->sram_end);
4071 if (ret)
4072 return ret;
4073
4074 si_pi->papm_cfg_table_start = tmp;
4075
4076 return ret;
4077 }
4078
si_read_clock_registers(struct amdgpu_device * adev)4079 static void si_read_clock_registers(struct amdgpu_device *adev)
4080 {
4081 struct si_power_info *si_pi = si_get_pi(adev);
4082
4083 si_pi->clock_registers.cg_spll_func_cntl = RREG32(mmCG_SPLL_FUNC_CNTL);
4084 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(mmCG_SPLL_FUNC_CNTL_2);
4085 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(mmCG_SPLL_FUNC_CNTL_3);
4086 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(mmCG_SPLL_FUNC_CNTL_4);
4087 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(mmCG_SPLL_SPREAD_SPECTRUM);
4088 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(mmCG_SPLL_SPREAD_SPECTRUM_2);
4089 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4090 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4091 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4092 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4093 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4094 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4095 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4096 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4097 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4098 }
4099
si_enable_thermal_protection(struct amdgpu_device * adev,bool enable)4100 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4101 bool enable)
4102 {
4103 if (enable)
4104 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
4105 else
4106 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
4107 }
4108
si_enable_acpi_power_management(struct amdgpu_device * adev)4109 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4110 {
4111 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__STATIC_PM_EN_MASK, ~GENERAL_PWRMGT__STATIC_PM_EN_MASK);
4112 }
4113
4114 #if 0
4115 static int si_enter_ulp_state(struct amdgpu_device *adev)
4116 {
4117 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4118
4119 udelay(25000);
4120
4121 return 0;
4122 }
4123
4124 static int si_exit_ulp_state(struct amdgpu_device *adev)
4125 {
4126 int i;
4127
4128 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4129
4130 udelay(7000);
4131
4132 for (i = 0; i < adev->usec_timeout; i++) {
4133 if (RREG32(SMC_RESP_0) == 1)
4134 break;
4135 udelay(1000);
4136 }
4137
4138 return 0;
4139 }
4140 #endif
4141
si_notify_smc_display_change(struct amdgpu_device * adev,bool has_display)4142 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4143 bool has_display)
4144 {
4145 PPSMC_Msg msg = has_display ?
4146 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4147
4148 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4149 0 : -EINVAL;
4150 }
4151
si_program_response_times(struct amdgpu_device * adev)4152 static void si_program_response_times(struct amdgpu_device *adev)
4153 {
4154 u32 voltage_response_time, acpi_delay_time, vbi_time_out;
4155 u32 vddc_dly, acpi_dly, vbi_dly;
4156 u32 reference_clock;
4157
4158 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4159
4160 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4161
4162 if (voltage_response_time == 0)
4163 voltage_response_time = 1000;
4164
4165 acpi_delay_time = 15000;
4166 vbi_time_out = 100000;
4167
4168 reference_clock = amdgpu_asic_get_xclk(adev);
4169
4170 vddc_dly = (voltage_response_time * reference_clock) / 100;
4171 acpi_dly = (acpi_delay_time * reference_clock) / 100;
4172 vbi_dly = (vbi_time_out * reference_clock) / 100;
4173
4174 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
4175 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
4176 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4177 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4178 }
4179
si_program_ds_registers(struct amdgpu_device * adev)4180 static void si_program_ds_registers(struct amdgpu_device *adev)
4181 {
4182 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4183 u32 tmp;
4184
4185 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4186 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4187 tmp = 0x10;
4188 else
4189 tmp = 0x1;
4190
4191 if (eg_pi->sclk_deep_sleep) {
4192 WREG32_P(mmMISC_CLK_CNTL, (tmp << MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT), ~MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK);
4193 WREG32_P(mmCG_SPLL_AUTOSCALE_CNTL, CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK,
4194 ~CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK);
4195 }
4196 }
4197
si_program_display_gap(struct amdgpu_device * adev)4198 static void si_program_display_gap(struct amdgpu_device *adev)
4199 {
4200 const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg;
4201 u32 tmp, pipe;
4202
4203 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL) & ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK);
4204 if (cfg->num_display > 0)
4205 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT;
4206 else
4207 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT;
4208
4209 if (cfg->num_display > 1)
4210 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT;
4211 else
4212 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT;
4213
4214 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp);
4215
4216 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4217 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4218
4219 if (cfg->num_display > 0 && pipe != cfg->crtc_index) {
4220 pipe = cfg->crtc_index;
4221
4222 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4223 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4224 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4225 }
4226
4227 /* Setting this to false forces the performance state to low if the crtcs are disabled.
4228 * This can be a problem on PowerXpress systems or if you want to use the card
4229 * for offscreen rendering or compute if there are no crtcs enabled.
4230 */
4231 si_notify_smc_display_change(adev, cfg->num_display > 0);
4232 }
4233
si_enable_spread_spectrum(struct amdgpu_device * adev,bool enable)4234 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4235 {
4236 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4237
4238 if (enable) {
4239 if (pi->sclk_ss)
4240 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK);
4241 } else {
4242 WREG32_P(mmCG_SPLL_SPREAD_SPECTRUM, 0, ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
4243 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK);
4244 }
4245 }
4246
si_setup_bsp(struct amdgpu_device * adev)4247 static void si_setup_bsp(struct amdgpu_device *adev)
4248 {
4249 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4250 u32 xclk = amdgpu_asic_get_xclk(adev);
4251
4252 r600_calculate_u_and_p(pi->asi,
4253 xclk,
4254 16,
4255 &pi->bsp,
4256 &pi->bsu);
4257
4258 r600_calculate_u_and_p(pi->pasi,
4259 xclk,
4260 16,
4261 &pi->pbsp,
4262 &pi->pbsu);
4263
4264
4265 pi->dsp = (pi->bsp << CG_BSP__BSP__SHIFT) | (pi->bsu << CG_BSP__BSU__SHIFT);
4266 pi->psp = (pi->pbsp << CG_BSP__BSP__SHIFT) | (pi->pbsu << CG_BSP__BSU__SHIFT);
4267
4268 WREG32(mmCG_BSP, pi->dsp);
4269 }
4270
si_program_git(struct amdgpu_device * adev)4271 static void si_program_git(struct amdgpu_device *adev)
4272 {
4273 WREG32_P(mmCG_GIT, R600_GICST_DFLT << CG_GIT__CG_GICST__SHIFT, ~CG_GIT__CG_GICST_MASK);
4274 }
4275
si_program_tp(struct amdgpu_device * adev)4276 static void si_program_tp(struct amdgpu_device *adev)
4277 {
4278 int i;
4279 enum r600_td td = R600_TD_DFLT;
4280
4281 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4282 WREG32(mmCG_FFCT_0 + i, (r600_utc[i] << CG_FFCT_0__UTC_0__SHIFT | r600_dtc[i] << CG_FFCT_0__DTC_0__SHIFT));
4283
4284 if (td == R600_TD_AUTO)
4285 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK);
4286 else
4287 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK);
4288
4289 if (td == R600_TD_UP)
4290 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK);
4291
4292 if (td == R600_TD_DOWN)
4293 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK);
4294 }
4295
si_program_tpp(struct amdgpu_device * adev)4296 static void si_program_tpp(struct amdgpu_device *adev)
4297 {
4298 WREG32(mmCG_TPC, R600_TPC_DFLT);
4299 }
4300
si_program_sstp(struct amdgpu_device * adev)4301 static void si_program_sstp(struct amdgpu_device *adev)
4302 {
4303 WREG32(mmCG_SSP, (R600_SSTU_DFLT << CG_SSP__SSTU__SHIFT| R600_SST_DFLT << CG_SSP__SST__SHIFT));
4304 }
4305
si_enable_display_gap(struct amdgpu_device * adev)4306 static void si_enable_display_gap(struct amdgpu_device *adev)
4307 {
4308 u32 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL);
4309
4310 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK);
4311 tmp |= (R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT |
4312 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT);
4313
4314 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG_MASK);
4315 tmp |= (R600_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG__SHIFT |
4316 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG__SHIFT);
4317 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp);
4318 }
4319
si_program_vc(struct amdgpu_device * adev)4320 static void si_program_vc(struct amdgpu_device *adev)
4321 {
4322 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4323
4324 WREG32(mmCG_FTV, pi->vrc);
4325 }
4326
si_clear_vc(struct amdgpu_device * adev)4327 static void si_clear_vc(struct amdgpu_device *adev)
4328 {
4329 WREG32(mmCG_FTV, 0);
4330 }
4331
si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)4332 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4333 {
4334 u8 mc_para_index;
4335
4336 if (memory_clock < 10000)
4337 mc_para_index = 0;
4338 else if (memory_clock >= 80000)
4339 mc_para_index = 0x0f;
4340 else
4341 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4342 return mc_para_index;
4343 }
4344
si_get_mclk_frequency_ratio(u32 memory_clock,bool strobe_mode)4345 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4346 {
4347 u8 mc_para_index;
4348
4349 if (strobe_mode) {
4350 if (memory_clock < 12500)
4351 mc_para_index = 0x00;
4352 else if (memory_clock > 47500)
4353 mc_para_index = 0x0f;
4354 else
4355 mc_para_index = (u8)((memory_clock - 10000) / 2500);
4356 } else {
4357 if (memory_clock < 65000)
4358 mc_para_index = 0x00;
4359 else if (memory_clock > 135000)
4360 mc_para_index = 0x0f;
4361 else
4362 mc_para_index = (u8)((memory_clock - 60000) / 5000);
4363 }
4364 return mc_para_index;
4365 }
4366
si_get_strobe_mode_settings(struct amdgpu_device * adev,u32 mclk)4367 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4368 {
4369 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4370 bool strobe_mode = false;
4371 u8 result = 0;
4372
4373 if (mclk <= pi->mclk_strobe_mode_threshold)
4374 strobe_mode = true;
4375
4376 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4377 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4378 else
4379 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4380
4381 if (strobe_mode)
4382 result |= SISLANDS_SMC_STROBE_ENABLE;
4383
4384 return result;
4385 }
4386
si_upload_firmware(struct amdgpu_device * adev)4387 static int si_upload_firmware(struct amdgpu_device *adev)
4388 {
4389 struct si_power_info *si_pi = si_get_pi(adev);
4390
4391 amdgpu_si_reset_smc(adev);
4392 amdgpu_si_smc_clock(adev, false);
4393
4394 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4395 }
4396
si_validate_phase_shedding_tables(struct amdgpu_device * adev,const struct atom_voltage_table * table,const struct amdgpu_phase_shedding_limits_table * limits)4397 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4398 const struct atom_voltage_table *table,
4399 const struct amdgpu_phase_shedding_limits_table *limits)
4400 {
4401 u32 data, num_bits, num_levels;
4402
4403 if ((table == NULL) || (limits == NULL))
4404 return false;
4405
4406 data = table->mask_low;
4407
4408 num_bits = hweight32(data);
4409
4410 if (num_bits == 0)
4411 return false;
4412
4413 num_levels = (1 << num_bits);
4414
4415 if (table->count != num_levels)
4416 return false;
4417
4418 if (limits->count != (num_levels - 1))
4419 return false;
4420
4421 return true;
4422 }
4423
si_trim_voltage_table_to_fit_state_table(struct amdgpu_device * adev,u32 max_voltage_steps,struct atom_voltage_table * voltage_table)4424 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4425 u32 max_voltage_steps,
4426 struct atom_voltage_table *voltage_table)
4427 {
4428 unsigned int i, diff;
4429
4430 if (voltage_table->count <= max_voltage_steps)
4431 return;
4432
4433 diff = voltage_table->count - max_voltage_steps;
4434
4435 for (i= 0; i < max_voltage_steps; i++)
4436 voltage_table->entries[i] = voltage_table->entries[i + diff];
4437
4438 voltage_table->count = max_voltage_steps;
4439 }
4440
si_get_svi2_voltage_table(struct amdgpu_device * adev,struct amdgpu_clock_voltage_dependency_table * voltage_dependency_table,struct atom_voltage_table * voltage_table)4441 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4442 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4443 struct atom_voltage_table *voltage_table)
4444 {
4445 u32 i;
4446
4447 if (voltage_dependency_table == NULL)
4448 return -EINVAL;
4449
4450 voltage_table->mask_low = 0;
4451 voltage_table->phase_delay = 0;
4452
4453 voltage_table->count = voltage_dependency_table->count;
4454 for (i = 0; i < voltage_table->count; i++) {
4455 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4456 voltage_table->entries[i].smio_low = 0;
4457 }
4458
4459 return 0;
4460 }
4461
si_construct_voltage_tables(struct amdgpu_device * adev)4462 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4463 {
4464 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4465 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4466 struct si_power_info *si_pi = si_get_pi(adev);
4467 int ret;
4468
4469 if (pi->voltage_control) {
4470 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4471 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4472 if (ret)
4473 return ret;
4474
4475 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4476 si_trim_voltage_table_to_fit_state_table(adev,
4477 SISLANDS_MAX_NO_VREG_STEPS,
4478 &eg_pi->vddc_voltage_table);
4479 } else if (si_pi->voltage_control_svi2) {
4480 ret = si_get_svi2_voltage_table(adev,
4481 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4482 &eg_pi->vddc_voltage_table);
4483 if (ret)
4484 return ret;
4485 } else {
4486 return -EINVAL;
4487 }
4488
4489 if (eg_pi->vddci_control) {
4490 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4491 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4492 if (ret)
4493 return ret;
4494
4495 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4496 si_trim_voltage_table_to_fit_state_table(adev,
4497 SISLANDS_MAX_NO_VREG_STEPS,
4498 &eg_pi->vddci_voltage_table);
4499 }
4500 if (si_pi->vddci_control_svi2) {
4501 ret = si_get_svi2_voltage_table(adev,
4502 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4503 &eg_pi->vddci_voltage_table);
4504 if (ret)
4505 return ret;
4506 }
4507
4508 if (pi->mvdd_control) {
4509 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4510 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4511
4512 if (ret) {
4513 pi->mvdd_control = false;
4514 return ret;
4515 }
4516
4517 if (si_pi->mvdd_voltage_table.count == 0) {
4518 pi->mvdd_control = false;
4519 return -EINVAL;
4520 }
4521
4522 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4523 si_trim_voltage_table_to_fit_state_table(adev,
4524 SISLANDS_MAX_NO_VREG_STEPS,
4525 &si_pi->mvdd_voltage_table);
4526 }
4527
4528 if (si_pi->vddc_phase_shed_control) {
4529 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4530 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4531 if (ret)
4532 si_pi->vddc_phase_shed_control = false;
4533
4534 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4535 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4536 si_pi->vddc_phase_shed_control = false;
4537 }
4538
4539 return 0;
4540 }
4541
si_populate_smc_voltage_table(struct amdgpu_device * adev,const struct atom_voltage_table * voltage_table,SISLANDS_SMC_STATETABLE * table)4542 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4543 const struct atom_voltage_table *voltage_table,
4544 SISLANDS_SMC_STATETABLE *table)
4545 {
4546 unsigned int i;
4547
4548 for (i = 0; i < voltage_table->count; i++)
4549 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4550 }
4551
si_populate_smc_voltage_tables(struct amdgpu_device * adev,SISLANDS_SMC_STATETABLE * table)4552 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4553 SISLANDS_SMC_STATETABLE *table)
4554 {
4555 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4556 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4557 struct si_power_info *si_pi = si_get_pi(adev);
4558 u8 i;
4559
4560 if (si_pi->voltage_control_svi2) {
4561 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4562 si_pi->svc_gpio_id);
4563 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4564 si_pi->svd_gpio_id);
4565 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4566 2);
4567 } else {
4568 if (eg_pi->vddc_voltage_table.count) {
4569 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4570 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4571 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4572
4573 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4574 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4575 table->maxVDDCIndexInPPTable = i;
4576 break;
4577 }
4578 }
4579 }
4580
4581 if (eg_pi->vddci_voltage_table.count) {
4582 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4583
4584 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4585 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4586 }
4587
4588
4589 if (si_pi->mvdd_voltage_table.count) {
4590 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4591
4592 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4593 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4594 }
4595
4596 if (si_pi->vddc_phase_shed_control) {
4597 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4598 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4599 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4600
4601 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4602 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4603
4604 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4605 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4606 } else {
4607 si_pi->vddc_phase_shed_control = false;
4608 }
4609 }
4610 }
4611
4612 return 0;
4613 }
4614
si_populate_voltage_value(struct amdgpu_device * adev,const struct atom_voltage_table * table,u16 value,SISLANDS_SMC_VOLTAGE_VALUE * voltage)4615 static int si_populate_voltage_value(struct amdgpu_device *adev,
4616 const struct atom_voltage_table *table,
4617 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4618 {
4619 unsigned int i;
4620
4621 for (i = 0; i < table->count; i++) {
4622 if (value <= table->entries[i].value) {
4623 voltage->index = (u8)i;
4624 voltage->value = cpu_to_be16(table->entries[i].value);
4625 break;
4626 }
4627 }
4628
4629 if (i >= table->count)
4630 return -EINVAL;
4631
4632 return 0;
4633 }
4634
si_populate_mvdd_value(struct amdgpu_device * adev,u32 mclk,SISLANDS_SMC_VOLTAGE_VALUE * voltage)4635 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4636 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4637 {
4638 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4639 struct si_power_info *si_pi = si_get_pi(adev);
4640
4641 if (pi->mvdd_control) {
4642 if (mclk <= pi->mvdd_split_frequency)
4643 voltage->index = 0;
4644 else
4645 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4646
4647 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4648 }
4649 return 0;
4650 }
4651
si_get_std_voltage_value(struct amdgpu_device * adev,SISLANDS_SMC_VOLTAGE_VALUE * voltage,u16 * std_voltage)4652 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4653 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4654 u16 *std_voltage)
4655 {
4656 u16 v_index;
4657 bool voltage_found = false;
4658 *std_voltage = be16_to_cpu(voltage->value);
4659
4660 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4661 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4662 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4663 return -EINVAL;
4664
4665 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4666 if (be16_to_cpu(voltage->value) ==
4667 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4668 voltage_found = true;
4669 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4670 *std_voltage =
4671 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4672 else
4673 *std_voltage =
4674 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4675 break;
4676 }
4677 }
4678
4679 if (!voltage_found) {
4680 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4681 if (be16_to_cpu(voltage->value) <=
4682 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4683 voltage_found = true;
4684 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4685 *std_voltage =
4686 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4687 else
4688 *std_voltage =
4689 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4690 break;
4691 }
4692 }
4693 }
4694 } else {
4695 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4696 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4697 }
4698 }
4699
4700 return 0;
4701 }
4702
si_populate_std_voltage_value(struct amdgpu_device * adev,u16 value,u8 index,SISLANDS_SMC_VOLTAGE_VALUE * voltage)4703 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4704 u16 value, u8 index,
4705 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4706 {
4707 voltage->index = index;
4708 voltage->value = cpu_to_be16(value);
4709
4710 return 0;
4711 }
4712
si_populate_phase_shedding_value(struct amdgpu_device * adev,const struct amdgpu_phase_shedding_limits_table * limits,u16 voltage,u32 sclk,u32 mclk,SISLANDS_SMC_VOLTAGE_VALUE * smc_voltage)4713 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4714 const struct amdgpu_phase_shedding_limits_table *limits,
4715 u16 voltage, u32 sclk, u32 mclk,
4716 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4717 {
4718 unsigned int i;
4719
4720 for (i = 0; i < limits->count; i++) {
4721 if ((voltage <= limits->entries[i].voltage) &&
4722 (sclk <= limits->entries[i].sclk) &&
4723 (mclk <= limits->entries[i].mclk))
4724 break;
4725 }
4726
4727 smc_voltage->phase_settings = (u8)i;
4728
4729 return 0;
4730 }
4731
si_init_arb_table_index(struct amdgpu_device * adev)4732 static int si_init_arb_table_index(struct amdgpu_device *adev)
4733 {
4734 struct si_power_info *si_pi = si_get_pi(adev);
4735 u32 tmp;
4736 int ret;
4737
4738 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4739 &tmp, si_pi->sram_end);
4740 if (ret)
4741 return ret;
4742
4743 tmp &= 0x00FFFFFF;
4744 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4745
4746 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4747 tmp, si_pi->sram_end);
4748 }
4749
si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device * adev)4750 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4751 {
4752 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4753 }
4754
si_reset_to_default(struct amdgpu_device * adev)4755 static int si_reset_to_default(struct amdgpu_device *adev)
4756 {
4757 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4758 0 : -EINVAL;
4759 }
4760
si_force_switch_to_arb_f0(struct amdgpu_device * adev)4761 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4762 {
4763 struct si_power_info *si_pi = si_get_pi(adev);
4764 u32 tmp;
4765 int ret;
4766
4767 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4768 &tmp, si_pi->sram_end);
4769 if (ret)
4770 return ret;
4771
4772 tmp = (tmp >> 24) & 0xff;
4773
4774 if (tmp == MC_CG_ARB_FREQ_F0)
4775 return 0;
4776
4777 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4778 }
4779
si_calculate_memory_refresh_rate(struct amdgpu_device * adev,u32 engine_clock)4780 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4781 u32 engine_clock)
4782 {
4783 u32 dram_rows;
4784 u32 dram_refresh_rate;
4785 u32 mc_arb_rfsh_rate;
4786 u32 tmp = (RREG32(mmMC_ARB_RAMCFG) & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT;
4787
4788 if (tmp >= 4)
4789 dram_rows = 16384;
4790 else
4791 dram_rows = 1 << (tmp + 10);
4792
4793 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4794 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4795
4796 return mc_arb_rfsh_rate;
4797 }
4798
si_populate_memory_timing_parameters(struct amdgpu_device * adev,struct rv7xx_pl * pl,SMC_SIslands_MCArbDramTimingRegisterSet * arb_regs)4799 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4800 struct rv7xx_pl *pl,
4801 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4802 {
4803 u32 dram_timing;
4804 u32 dram_timing2;
4805 u32 burst_time;
4806 int ret;
4807
4808 arb_regs->mc_arb_rfsh_rate =
4809 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4810
4811 ret = amdgpu_atombios_set_engine_dram_timings(adev, pl->sclk,
4812 pl->mclk);
4813 if (ret)
4814 return ret;
4815
4816 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4817 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4818 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4819
4820 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4821 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4822 arb_regs->mc_arb_burst_time = (u8)burst_time;
4823
4824 return 0;
4825 }
4826
si_do_program_memory_timing_parameters(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,unsigned int first_arb_set)4827 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4828 struct amdgpu_ps *amdgpu_state,
4829 unsigned int first_arb_set)
4830 {
4831 struct si_power_info *si_pi = si_get_pi(adev);
4832 struct si_ps *state = si_get_ps(amdgpu_state);
4833 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4834 int i, ret = 0;
4835
4836 for (i = 0; i < state->performance_level_count; i++) {
4837 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4838 if (ret)
4839 break;
4840 ret = amdgpu_si_copy_bytes_to_smc(adev,
4841 si_pi->arb_table_start +
4842 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4843 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4844 (u8 *)&arb_regs,
4845 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4846 si_pi->sram_end);
4847 if (ret)
4848 break;
4849 }
4850
4851 return ret;
4852 }
4853
si_program_memory_timing_parameters(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)4854 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4855 struct amdgpu_ps *amdgpu_new_state)
4856 {
4857 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4858 SISLANDS_DRIVER_STATE_ARB_INDEX);
4859 }
4860
si_populate_initial_mvdd_value(struct amdgpu_device * adev,struct SISLANDS_SMC_VOLTAGE_VALUE * voltage)4861 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4862 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4863 {
4864 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4865 struct si_power_info *si_pi = si_get_pi(adev);
4866
4867 if (pi->mvdd_control)
4868 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4869 si_pi->mvdd_bootup_value, voltage);
4870
4871 return 0;
4872 }
4873
si_populate_smc_initial_state(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_initial_state,SISLANDS_SMC_STATETABLE * table)4874 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4875 struct amdgpu_ps *amdgpu_initial_state,
4876 SISLANDS_SMC_STATETABLE *table)
4877 {
4878 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4879 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4880 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4881 struct si_power_info *si_pi = si_get_pi(adev);
4882 u32 reg;
4883 int ret;
4884
4885 table->initialState.level.mclk.vDLL_CNTL =
4886 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4887 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL =
4888 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4889 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL =
4890 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4891 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL =
4892 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4893 table->initialState.level.mclk.vMPLL_FUNC_CNTL =
4894 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4895 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 =
4896 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4897 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 =
4898 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4899 table->initialState.level.mclk.vMPLL_SS =
4900 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4901 table->initialState.level.mclk.vMPLL_SS2 =
4902 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4903
4904 table->initialState.level.mclk.mclk_value =
4905 cpu_to_be32(initial_state->performance_levels[0].mclk);
4906
4907 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL =
4908 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4909 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
4910 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4911 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
4912 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4913 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
4914 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4915 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM =
4916 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4917 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4918 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4919
4920 table->initialState.level.sclk.sclk_value =
4921 cpu_to_be32(initial_state->performance_levels[0].sclk);
4922
4923 table->initialState.level.arbRefreshState =
4924 SISLANDS_INITIAL_STATE_ARB_INDEX;
4925
4926 table->initialState.level.ACIndex = 0;
4927
4928 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4929 initial_state->performance_levels[0].vddc,
4930 &table->initialState.level.vddc);
4931
4932 if (!ret) {
4933 u16 std_vddc;
4934
4935 ret = si_get_std_voltage_value(adev,
4936 &table->initialState.level.vddc,
4937 &std_vddc);
4938 if (!ret)
4939 si_populate_std_voltage_value(adev, std_vddc,
4940 table->initialState.level.vddc.index,
4941 &table->initialState.level.std_vddc);
4942 }
4943
4944 if (eg_pi->vddci_control)
4945 si_populate_voltage_value(adev,
4946 &eg_pi->vddci_voltage_table,
4947 initial_state->performance_levels[0].vddci,
4948 &table->initialState.level.vddci);
4949
4950 if (si_pi->vddc_phase_shed_control)
4951 si_populate_phase_shedding_value(adev,
4952 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4953 initial_state->performance_levels[0].vddc,
4954 initial_state->performance_levels[0].sclk,
4955 initial_state->performance_levels[0].mclk,
4956 &table->initialState.level.vddc);
4957
4958 si_populate_initial_mvdd_value(adev, &table->initialState.level.mvdd);
4959
4960 reg = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT;
4961 table->initialState.level.aT = cpu_to_be32(reg);
4962 table->initialState.level.bSP = cpu_to_be32(pi->dsp);
4963 table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen;
4964
4965 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4966 table->initialState.level.strobeMode =
4967 si_get_strobe_mode_settings(adev,
4968 initial_state->performance_levels[0].mclk);
4969
4970 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4971 table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4972 else
4973 table->initialState.level.mcFlags = 0;
4974 }
4975
4976 table->initialState.levelCount = 1;
4977
4978 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4979
4980 table->initialState.level.dpm2.MaxPS = 0;
4981 table->initialState.level.dpm2.NearTDPDec = 0;
4982 table->initialState.level.dpm2.AboveSafeInc = 0;
4983 table->initialState.level.dpm2.BelowSafeInc = 0;
4984 table->initialState.level.dpm2.PwrEfficiencyRatio = 0;
4985
4986 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK |
4987 SQ_POWER_THROTTLE__MAX_POWER_MASK;
4988 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);
4989
4990 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK |
4991 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK |
4992 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK;
4993 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
4994
4995 return 0;
4996 }
4997
si_gen_pcie_gen_support(struct amdgpu_device * adev,u32 sys_mask,enum si_pcie_gen asic_gen,enum si_pcie_gen default_gen)4998 static enum si_pcie_gen si_gen_pcie_gen_support(struct amdgpu_device *adev,
4999 u32 sys_mask,
5000 enum si_pcie_gen asic_gen,
5001 enum si_pcie_gen default_gen)
5002 {
5003 switch (asic_gen) {
5004 case SI_PCIE_GEN1:
5005 return SI_PCIE_GEN1;
5006 case SI_PCIE_GEN2:
5007 return SI_PCIE_GEN2;
5008 case SI_PCIE_GEN3:
5009 return SI_PCIE_GEN3;
5010 default:
5011 if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) &&
5012 (default_gen == SI_PCIE_GEN3))
5013 return SI_PCIE_GEN3;
5014 else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) &&
5015 (default_gen == SI_PCIE_GEN2))
5016 return SI_PCIE_GEN2;
5017 else
5018 return SI_PCIE_GEN1;
5019 }
5020 return SI_PCIE_GEN1;
5021 }
5022
si_populate_smc_acpi_state(struct amdgpu_device * adev,SISLANDS_SMC_STATETABLE * table)5023 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
5024 SISLANDS_SMC_STATETABLE *table)
5025 {
5026 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5027 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5028 struct si_power_info *si_pi = si_get_pi(adev);
5029 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5030 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5031 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5032 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5033 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5034 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5035 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5036 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5037 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5038 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5039 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5040 u32 reg;
5041 int ret;
5042
5043 table->ACPIState = table->initialState;
5044
5045 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
5046
5047 if (pi->acpi_vddc) {
5048 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5049 pi->acpi_vddc, &table->ACPIState.level.vddc);
5050 if (!ret) {
5051 u16 std_vddc;
5052
5053 ret = si_get_std_voltage_value(adev,
5054 &table->ACPIState.level.vddc, &std_vddc);
5055 if (!ret)
5056 si_populate_std_voltage_value(adev, std_vddc,
5057 table->ACPIState.level.vddc.index,
5058 &table->ACPIState.level.std_vddc);
5059 }
5060 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen;
5061
5062 if (si_pi->vddc_phase_shed_control) {
5063 si_populate_phase_shedding_value(adev,
5064 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5065 pi->acpi_vddc,
5066 0,
5067 0,
5068 &table->ACPIState.level.vddc);
5069 }
5070 } else {
5071 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5072 pi->min_vddc_in_table, &table->ACPIState.level.vddc);
5073 if (!ret) {
5074 u16 std_vddc;
5075
5076 ret = si_get_std_voltage_value(adev,
5077 &table->ACPIState.level.vddc, &std_vddc);
5078
5079 if (!ret)
5080 si_populate_std_voltage_value(adev, std_vddc,
5081 table->ACPIState.level.vddc.index,
5082 &table->ACPIState.level.std_vddc);
5083 }
5084 table->ACPIState.level.gen2PCIE =
5085 (u8)si_gen_pcie_gen_support(adev,
5086 si_pi->sys_pcie_mask,
5087 si_pi->boot_pcie_gen,
5088 SI_PCIE_GEN1);
5089
5090 if (si_pi->vddc_phase_shed_control)
5091 si_populate_phase_shedding_value(adev,
5092 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5093 pi->min_vddc_in_table,
5094 0,
5095 0,
5096 &table->ACPIState.level.vddc);
5097 }
5098
5099 if (pi->acpi_vddc) {
5100 if (eg_pi->acpi_vddci)
5101 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5102 eg_pi->acpi_vddci,
5103 &table->ACPIState.level.vddci);
5104 }
5105
5106 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5107 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5108
5109 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5110
5111 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
5112 spll_func_cntl_2 |= 4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT;
5113
5114 table->ACPIState.level.mclk.vDLL_CNTL =
5115 cpu_to_be32(dll_cntl);
5116 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL =
5117 cpu_to_be32(mclk_pwrmgt_cntl);
5118 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL =
5119 cpu_to_be32(mpll_ad_func_cntl);
5120 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL =
5121 cpu_to_be32(mpll_dq_func_cntl);
5122 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL =
5123 cpu_to_be32(mpll_func_cntl);
5124 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 =
5125 cpu_to_be32(mpll_func_cntl_1);
5126 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 =
5127 cpu_to_be32(mpll_func_cntl_2);
5128 table->ACPIState.level.mclk.vMPLL_SS =
5129 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5130 table->ACPIState.level.mclk.vMPLL_SS2 =
5131 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5132
5133 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL =
5134 cpu_to_be32(spll_func_cntl);
5135 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
5136 cpu_to_be32(spll_func_cntl_2);
5137 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
5138 cpu_to_be32(spll_func_cntl_3);
5139 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
5140 cpu_to_be32(spll_func_cntl_4);
5141
5142 table->ACPIState.level.mclk.mclk_value = 0;
5143 table->ACPIState.level.sclk.sclk_value = 0;
5144
5145 si_populate_mvdd_value(adev, 0, &table->ACPIState.level.mvdd);
5146
5147 if (eg_pi->dynamic_ac_timing)
5148 table->ACPIState.level.ACIndex = 0;
5149
5150 table->ACPIState.level.dpm2.MaxPS = 0;
5151 table->ACPIState.level.dpm2.NearTDPDec = 0;
5152 table->ACPIState.level.dpm2.AboveSafeInc = 0;
5153 table->ACPIState.level.dpm2.BelowSafeInc = 0;
5154 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0;
5155
5156 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK | SQ_POWER_THROTTLE__MAX_POWER_MASK;
5157 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);
5158
5159 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK;
5160 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
5161
5162 return 0;
5163 }
5164
si_populate_ulv_state(struct amdgpu_device * adev,struct SISLANDS_SMC_SWSTATE_SINGLE * state)5165 static int si_populate_ulv_state(struct amdgpu_device *adev,
5166 struct SISLANDS_SMC_SWSTATE_SINGLE *state)
5167 {
5168 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5169 struct si_power_info *si_pi = si_get_pi(adev);
5170 struct si_ulv_param *ulv = &si_pi->ulv;
5171 u32 sclk_in_sr = 1350; /* ??? */
5172 int ret;
5173
5174 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5175 &state->level);
5176 if (!ret) {
5177 if (eg_pi->sclk_deep_sleep) {
5178 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5179 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5180 else
5181 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5182 }
5183 if (ulv->one_pcie_lane_in_ulv)
5184 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5185 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5186 state->level.ACIndex = 1;
5187 state->level.std_vddc = state->level.vddc;
5188 state->levelCount = 1;
5189
5190 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5191 }
5192
5193 return ret;
5194 }
5195
si_program_ulv_memory_timing_parameters(struct amdgpu_device * adev)5196 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5197 {
5198 struct si_power_info *si_pi = si_get_pi(adev);
5199 struct si_ulv_param *ulv = &si_pi->ulv;
5200 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5201 int ret;
5202
5203 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5204 &arb_regs);
5205 if (ret)
5206 return ret;
5207
5208 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5209 ulv->volt_change_delay);
5210
5211 ret = amdgpu_si_copy_bytes_to_smc(adev,
5212 si_pi->arb_table_start +
5213 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5214 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5215 (u8 *)&arb_regs,
5216 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5217 si_pi->sram_end);
5218
5219 return ret;
5220 }
5221
si_get_mvdd_configuration(struct amdgpu_device * adev)5222 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5223 {
5224 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5225
5226 pi->mvdd_split_frequency = 30000;
5227 }
5228
si_init_smc_table(struct amdgpu_device * adev)5229 static int si_init_smc_table(struct amdgpu_device *adev)
5230 {
5231 struct si_power_info *si_pi = si_get_pi(adev);
5232 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5233 const struct si_ulv_param *ulv = &si_pi->ulv;
5234 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
5235 int ret;
5236 u32 lane_width;
5237 u32 vr_hot_gpio;
5238
5239 si_populate_smc_voltage_tables(adev, table);
5240
5241 switch (adev->pm.int_thermal_type) {
5242 case THERMAL_TYPE_SI:
5243 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5244 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5245 break;
5246 case THERMAL_TYPE_NONE:
5247 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5248 break;
5249 default:
5250 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5251 break;
5252 }
5253
5254 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5255 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5256
5257 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5258 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5259 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5260 }
5261
5262 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5263 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5264
5265 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5266 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5267
5268 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5269 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5270
5271 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5272 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5273 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5274 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5275 vr_hot_gpio);
5276 }
5277
5278 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5279 if (ret)
5280 return ret;
5281
5282 ret = si_populate_smc_acpi_state(adev, table);
5283 if (ret)
5284 return ret;
5285
5286 table->driverState.flags = table->initialState.flags;
5287 table->driverState.levelCount = table->initialState.levelCount;
5288 table->driverState.levels[0] = table->initialState.level;
5289
5290 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5291 SISLANDS_INITIAL_STATE_ARB_INDEX);
5292 if (ret)
5293 return ret;
5294
5295 if (ulv->supported && ulv->pl.vddc) {
5296 ret = si_populate_ulv_state(adev, &table->ULVState);
5297 if (ret)
5298 return ret;
5299
5300 ret = si_program_ulv_memory_timing_parameters(adev);
5301 if (ret)
5302 return ret;
5303
5304 WREG32(mmCG_ULV_CONTROL, ulv->cg_ulv_control);
5305 WREG32(mmCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5306
5307 lane_width = amdgpu_get_pcie_lanes(adev);
5308 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5309 } else {
5310 table->ULVState = table->initialState;
5311 }
5312
5313 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5314 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5315 si_pi->sram_end);
5316 }
5317
si_calculate_sclk_params(struct amdgpu_device * adev,u32 engine_clock,SISLANDS_SMC_SCLK_VALUE * sclk)5318 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5319 u32 engine_clock,
5320 SISLANDS_SMC_SCLK_VALUE *sclk)
5321 {
5322 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5323 struct si_power_info *si_pi = si_get_pi(adev);
5324 struct atom_clock_dividers dividers;
5325 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5326 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5327 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5328 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5329 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5330 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5331 u64 tmp;
5332 u32 reference_clock = adev->clock.spll.reference_freq;
5333 u32 reference_divider;
5334 u32 fbdiv;
5335 int ret;
5336
5337 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5338 engine_clock, false, ÷rs);
5339 if (ret)
5340 return ret;
5341
5342 reference_divider = 1 + dividers.ref_div;
5343
5344 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5345 do_div(tmp, reference_clock);
5346 fbdiv = (u32) tmp;
5347
5348 spll_func_cntl &= ~(CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK | CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK);
5349 spll_func_cntl |= dividers.ref_div << CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT;
5350 spll_func_cntl |= dividers.post_div << CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT;
5351
5352 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
5353 spll_func_cntl_2 |= 2 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT;
5354
5355 spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
5356 spll_func_cntl_3 |= fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT;
5357 spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
5358
5359 if (pi->sclk_ss) {
5360 struct amdgpu_atom_ss ss;
5361 u32 vco_freq = engine_clock * dividers.post_div;
5362
5363 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5364 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5365 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5366 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5367
5368 cg_spll_spread_spectrum &= ~CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK;
5369 cg_spll_spread_spectrum |= clk_s << CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT;
5370 cg_spll_spread_spectrum |= CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
5371
5372 cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK;
5373 cg_spll_spread_spectrum_2 |= clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT;
5374 }
5375 }
5376
5377 sclk->sclk_value = engine_clock;
5378 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5379 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5380 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5381 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5382 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5383 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5384
5385 return 0;
5386 }
5387
si_populate_sclk_value(struct amdgpu_device * adev,u32 engine_clock,SISLANDS_SMC_SCLK_VALUE * sclk)5388 static int si_populate_sclk_value(struct amdgpu_device *adev,
5389 u32 engine_clock,
5390 SISLANDS_SMC_SCLK_VALUE *sclk)
5391 {
5392 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5393 int ret;
5394
5395 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5396 if (!ret) {
5397 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5398 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5399 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5400 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5401 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5402 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5403 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5404 }
5405
5406 return ret;
5407 }
5408
si_populate_mclk_value(struct amdgpu_device * adev,u32 engine_clock,u32 memory_clock,SISLANDS_SMC_MCLK_VALUE * mclk,bool strobe_mode,bool dll_state_on)5409 static int si_populate_mclk_value(struct amdgpu_device *adev,
5410 u32 engine_clock,
5411 u32 memory_clock,
5412 SISLANDS_SMC_MCLK_VALUE *mclk,
5413 bool strobe_mode,
5414 bool dll_state_on)
5415 {
5416 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5417 struct si_power_info *si_pi = si_get_pi(adev);
5418 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5419 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5420 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5421 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5422 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5423 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5424 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5425 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5426 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5427 struct atom_mpll_param mpll_param;
5428 int ret;
5429
5430 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5431 if (ret)
5432 return ret;
5433
5434 mpll_func_cntl &= ~BWCTRL_MASK;
5435 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5436
5437 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5438 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5439 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5440
5441 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5442 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5443
5444 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5445 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5446 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5447 YCLK_POST_DIV(mpll_param.post_div);
5448 }
5449
5450 if (pi->mclk_ss) {
5451 struct amdgpu_atom_ss ss;
5452 u32 freq_nom;
5453 u32 tmp;
5454 u32 reference_clock = adev->clock.mpll.reference_freq;
5455
5456 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5457 freq_nom = memory_clock * 4;
5458 else
5459 freq_nom = memory_clock * 2;
5460
5461 tmp = freq_nom / reference_clock;
5462 tmp = tmp * tmp;
5463 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5464 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5465 u32 clks = reference_clock * 5 / ss.rate;
5466 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5467
5468 mpll_ss1 &= ~CLKV_MASK;
5469 mpll_ss1 |= CLKV(clkv);
5470
5471 mpll_ss2 &= ~CLKS_MASK;
5472 mpll_ss2 |= CLKS(clks);
5473 }
5474 }
5475
5476 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5477 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5478
5479 if (dll_state_on)
5480 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5481 else
5482 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5483
5484 mclk->mclk_value = cpu_to_be32(memory_clock);
5485 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5486 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5487 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5488 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5489 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5490 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5491 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5492 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5493 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5494
5495 return 0;
5496 }
5497
si_populate_smc_sp(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)5498 static void si_populate_smc_sp(struct amdgpu_device *adev,
5499 struct amdgpu_ps *amdgpu_state,
5500 SISLANDS_SMC_SWSTATE *smc_state)
5501 {
5502 struct si_ps *ps = si_get_ps(amdgpu_state);
5503 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5504 int i;
5505
5506 for (i = 0; i < ps->performance_level_count - 1; i++)
5507 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5508
5509 smc_state->levels[ps->performance_level_count - 1].bSP =
5510 cpu_to_be32(pi->psp);
5511 }
5512
si_convert_power_level_to_smc(struct amdgpu_device * adev,struct rv7xx_pl * pl,SISLANDS_SMC_HW_PERFORMANCE_LEVEL * level)5513 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5514 struct rv7xx_pl *pl,
5515 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5516 {
5517 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5518 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5519 struct si_power_info *si_pi = si_get_pi(adev);
5520 int ret;
5521 bool dll_state_on;
5522 u16 std_vddc;
5523
5524 if (eg_pi->pcie_performance_request &&
5525 (si_pi->force_pcie_gen != SI_PCIE_GEN_INVALID))
5526 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5527 else
5528 level->gen2PCIE = (u8)pl->pcie_gen;
5529
5530 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5531 if (ret)
5532 return ret;
5533
5534 level->mcFlags = 0;
5535
5536 if (pi->mclk_stutter_mode_threshold &&
5537 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5538 !eg_pi->uvd_enabled &&
5539 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
5540 (adev->pm.pm_display_cfg.num_display <= 2)) {
5541 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5542 }
5543
5544 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5545 if (pl->mclk > pi->mclk_edc_enable_threshold)
5546 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5547
5548 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5549 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5550
5551 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5552
5553 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5554 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5555 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5556 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5557 else
5558 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5559 } else {
5560 dll_state_on = false;
5561 }
5562 } else {
5563 level->strobeMode = si_get_strobe_mode_settings(adev,
5564 pl->mclk);
5565
5566 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5567 }
5568
5569 ret = si_populate_mclk_value(adev,
5570 pl->sclk,
5571 pl->mclk,
5572 &level->mclk,
5573 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5574 if (ret)
5575 return ret;
5576
5577 ret = si_populate_voltage_value(adev,
5578 &eg_pi->vddc_voltage_table,
5579 pl->vddc, &level->vddc);
5580 if (ret)
5581 return ret;
5582
5583
5584 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5585 if (ret)
5586 return ret;
5587
5588 ret = si_populate_std_voltage_value(adev, std_vddc,
5589 level->vddc.index, &level->std_vddc);
5590 if (ret)
5591 return ret;
5592
5593 if (eg_pi->vddci_control) {
5594 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5595 pl->vddci, &level->vddci);
5596 if (ret)
5597 return ret;
5598 }
5599
5600 if (si_pi->vddc_phase_shed_control) {
5601 ret = si_populate_phase_shedding_value(adev,
5602 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5603 pl->vddc,
5604 pl->sclk,
5605 pl->mclk,
5606 &level->vddc);
5607 if (ret)
5608 return ret;
5609 }
5610
5611 level->MaxPoweredUpCU = si_pi->max_cu;
5612
5613 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5614
5615 return ret;
5616 }
5617
si_populate_smc_t(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)5618 static int si_populate_smc_t(struct amdgpu_device *adev,
5619 struct amdgpu_ps *amdgpu_state,
5620 SISLANDS_SMC_SWSTATE *smc_state)
5621 {
5622 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5623 struct si_ps *state = si_get_ps(amdgpu_state);
5624 u32 a_t;
5625 u32 t_l, t_h;
5626 u32 high_bsp;
5627 int i, ret;
5628
5629 if (state->performance_level_count >= 9)
5630 return -EINVAL;
5631
5632 if (state->performance_level_count < 2) {
5633 a_t = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT;
5634 smc_state->levels[0].aT = cpu_to_be32(a_t);
5635 return 0;
5636 }
5637
5638 smc_state->levels[0].aT = cpu_to_be32(0);
5639
5640 for (i = 0; i <= state->performance_level_count - 2; i++) {
5641 ret = r600_calculate_at(
5642 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5643 100 * R600_AH_DFLT,
5644 state->performance_levels[i + 1].sclk,
5645 state->performance_levels[i].sclk,
5646 &t_l,
5647 &t_h);
5648
5649 if (ret) {
5650 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5651 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5652 }
5653
5654 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_AT__CG_R_MASK;
5655 a_t |= (t_l * pi->bsp / 20000) << CG_AT__CG_R__SHIFT;
5656 smc_state->levels[i].aT = cpu_to_be32(a_t);
5657
5658 high_bsp = (i == state->performance_level_count - 2) ?
5659 pi->pbsp : pi->bsp;
5660 a_t = (0xffff) << CG_AT__CG_R__SHIFT | (t_h * high_bsp / 20000) << CG_AT__CG_L__SHIFT;
5661 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5662 }
5663
5664 return 0;
5665 }
5666
si_disable_ulv(struct amdgpu_device * adev)5667 static int si_disable_ulv(struct amdgpu_device *adev)
5668 {
5669 PPSMC_Result r;
5670
5671 r = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV);
5672 return (r == PPSMC_Result_OK) ? 0 : -EINVAL;
5673 }
5674
si_is_state_ulv_compatible(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)5675 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5676 struct amdgpu_ps *amdgpu_state)
5677 {
5678 const struct si_power_info *si_pi = si_get_pi(adev);
5679 const struct si_ulv_param *ulv = &si_pi->ulv;
5680 const struct si_ps *state = si_get_ps(amdgpu_state);
5681 int i;
5682
5683 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5684 return false;
5685
5686 /* XXX validate against display requirements! */
5687
5688 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5689 if (adev->pm.pm_display_cfg.display_clk <=
5690 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5691 if (ulv->pl.vddc <
5692 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5693 return false;
5694 }
5695 }
5696
5697 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5698 return false;
5699
5700 return true;
5701 }
5702
si_set_power_state_conditionally_enable_ulv(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)5703 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5704 struct amdgpu_ps *amdgpu_new_state)
5705 {
5706 const struct si_power_info *si_pi = si_get_pi(adev);
5707 const struct si_ulv_param *ulv = &si_pi->ulv;
5708
5709 if (ulv->supported) {
5710 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5711 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5712 0 : -EINVAL;
5713 }
5714 return 0;
5715 }
5716
si_convert_power_state_to_smc(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)5717 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5718 struct amdgpu_ps *amdgpu_state,
5719 SISLANDS_SMC_SWSTATE *smc_state)
5720 {
5721 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5722 struct ni_power_info *ni_pi = ni_get_pi(adev);
5723 struct si_power_info *si_pi = si_get_pi(adev);
5724 struct si_ps *state = si_get_ps(amdgpu_state);
5725 int i, ret;
5726 u32 threshold;
5727 u32 sclk_in_sr = 1350; /* ??? */
5728
5729 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5730 return -EINVAL;
5731
5732 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5733
5734 if (amdgpu_state->vclk && amdgpu_state->dclk) {
5735 eg_pi->uvd_enabled = true;
5736 if (eg_pi->smu_uvd_hs)
5737 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5738 } else {
5739 eg_pi->uvd_enabled = false;
5740 }
5741
5742 if (state->dc_compatible)
5743 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5744
5745 smc_state->levelCount = 0;
5746 for (i = 0; i < state->performance_level_count; i++) {
5747 if (eg_pi->sclk_deep_sleep) {
5748 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5749 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5750 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5751 else
5752 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5753 }
5754 }
5755
5756 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5757 &smc_state->levels[i]);
5758 smc_state->levels[i].arbRefreshState =
5759 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5760
5761 if (ret)
5762 return ret;
5763
5764 if (ni_pi->enable_power_containment)
5765 smc_state->levels[i].displayWatermark =
5766 (state->performance_levels[i].sclk < threshold) ?
5767 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5768 else
5769 smc_state->levels[i].displayWatermark = (i < 2) ?
5770 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5771
5772 if (eg_pi->dynamic_ac_timing)
5773 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5774 else
5775 smc_state->levels[i].ACIndex = 0;
5776
5777 smc_state->levelCount++;
5778 }
5779
5780 si_write_smc_soft_register(adev,
5781 SI_SMC_SOFT_REGISTER_watermark_threshold,
5782 threshold / 512);
5783
5784 si_populate_smc_sp(adev, amdgpu_state, smc_state);
5785
5786 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5787 if (ret)
5788 ni_pi->enable_power_containment = false;
5789
5790 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5791 if (ret)
5792 ni_pi->enable_sq_ramping = false;
5793
5794 return si_populate_smc_t(adev, amdgpu_state, smc_state);
5795 }
5796
si_upload_sw_state(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)5797 static int si_upload_sw_state(struct amdgpu_device *adev,
5798 struct amdgpu_ps *amdgpu_new_state)
5799 {
5800 struct si_power_info *si_pi = si_get_pi(adev);
5801 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
5802 int ret;
5803 u32 address = si_pi->state_table_start +
5804 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5805 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5806 size_t state_size = struct_size(smc_state, levels,
5807 new_state->performance_level_count);
5808 memset(smc_state, 0, state_size);
5809
5810 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5811 if (ret)
5812 return ret;
5813
5814 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5815 state_size, si_pi->sram_end);
5816 }
5817
si_upload_ulv_state(struct amdgpu_device * adev)5818 static int si_upload_ulv_state(struct amdgpu_device *adev)
5819 {
5820 struct si_power_info *si_pi = si_get_pi(adev);
5821 struct si_ulv_param *ulv = &si_pi->ulv;
5822 int ret = 0;
5823
5824 if (ulv->supported && ulv->pl.vddc) {
5825 u32 address = si_pi->state_table_start +
5826 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5827 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState;
5828 u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE);
5829
5830 memset(smc_state, 0, state_size);
5831
5832 ret = si_populate_ulv_state(adev, smc_state);
5833 if (!ret)
5834 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5835 state_size, si_pi->sram_end);
5836 }
5837
5838 return ret;
5839 }
5840
si_upload_smc_data(struct amdgpu_device * adev)5841 static int si_upload_smc_data(struct amdgpu_device *adev)
5842 {
5843 const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg;
5844 u32 crtc_index = 0;
5845 u32 mclk_change_block_cp_min = 0;
5846 u32 mclk_change_block_cp_max = 0;
5847
5848 /* When a display is plugged in, program these so that the SMC
5849 * performs MCLK switching when it doesn't cause flickering.
5850 * When no display is plugged in, there is no need to restrict
5851 * MCLK switching, so program them to zero.
5852 */
5853 if (cfg->num_display) {
5854 crtc_index = cfg->crtc_index;
5855
5856 if (cfg->line_time_in_us) {
5857 mclk_change_block_cp_min = 200 / cfg->line_time_in_us;
5858 mclk_change_block_cp_max = 100 / cfg->line_time_in_us;
5859 }
5860 }
5861
5862 si_write_smc_soft_register(adev,
5863 SI_SMC_SOFT_REGISTER_crtc_index,
5864 crtc_index);
5865
5866 si_write_smc_soft_register(adev,
5867 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5868 mclk_change_block_cp_min);
5869
5870 si_write_smc_soft_register(adev,
5871 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5872 mclk_change_block_cp_max);
5873
5874 return 0;
5875 }
5876
si_set_mc_special_registers(struct amdgpu_device * adev,struct si_mc_reg_table * table)5877 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5878 struct si_mc_reg_table *table)
5879 {
5880 u8 i, j, k;
5881 u32 temp_reg;
5882
5883 for (i = 0, j = table->last; i < table->last; i++) {
5884 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5885 return -EINVAL;
5886 switch (table->mc_reg_address[i].s1) {
5887 case MC_SEQ_MISC1:
5888 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5889 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5890 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5891 for (k = 0; k < table->num_entries; k++)
5892 table->mc_reg_table_entry[k].mc_data[j] =
5893 ((temp_reg & 0xffff0000)) |
5894 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5895 j++;
5896
5897 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5898 return -EINVAL;
5899 temp_reg = RREG32(MC_PMG_CMD_MRS);
5900 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5901 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5902 for (k = 0; k < table->num_entries; k++) {
5903 table->mc_reg_table_entry[k].mc_data[j] =
5904 (temp_reg & 0xffff0000) |
5905 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5906 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5907 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5908 }
5909 j++;
5910
5911 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5912 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5913 return -EINVAL;
5914 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5915 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5916 for (k = 0; k < table->num_entries; k++)
5917 table->mc_reg_table_entry[k].mc_data[j] =
5918 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5919 j++;
5920 }
5921 break;
5922 case MC_SEQ_RESERVE_M:
5923 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5924 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5925 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5926 for(k = 0; k < table->num_entries; k++)
5927 table->mc_reg_table_entry[k].mc_data[j] =
5928 (temp_reg & 0xffff0000) |
5929 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5930 j++;
5931 break;
5932 default:
5933 break;
5934 }
5935 }
5936
5937 table->last = j;
5938
5939 return 0;
5940 }
5941
si_check_s0_mc_reg_index(u16 in_reg,u16 * out_reg)5942 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5943 {
5944 bool result = true;
5945 switch (in_reg) {
5946 case MC_SEQ_RAS_TIMING:
5947 *out_reg = MC_SEQ_RAS_TIMING_LP;
5948 break;
5949 case MC_SEQ_CAS_TIMING:
5950 *out_reg = MC_SEQ_CAS_TIMING_LP;
5951 break;
5952 case MC_SEQ_MISC_TIMING:
5953 *out_reg = MC_SEQ_MISC_TIMING_LP;
5954 break;
5955 case MC_SEQ_MISC_TIMING2:
5956 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5957 break;
5958 case MC_SEQ_RD_CTL_D0:
5959 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5960 break;
5961 case MC_SEQ_RD_CTL_D1:
5962 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5963 break;
5964 case MC_SEQ_WR_CTL_D0:
5965 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5966 break;
5967 case MC_SEQ_WR_CTL_D1:
5968 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5969 break;
5970 case MC_PMG_CMD_EMRS:
5971 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5972 break;
5973 case MC_PMG_CMD_MRS:
5974 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5975 break;
5976 case MC_PMG_CMD_MRS1:
5977 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5978 break;
5979 case MC_SEQ_PMG_TIMING:
5980 *out_reg = MC_SEQ_PMG_TIMING_LP;
5981 break;
5982 case MC_PMG_CMD_MRS2:
5983 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5984 break;
5985 case MC_SEQ_WR_CTL_2:
5986 *out_reg = MC_SEQ_WR_CTL_2_LP;
5987 break;
5988 default:
5989 result = false;
5990 break;
5991 }
5992
5993 return result;
5994 }
5995
si_set_valid_flag(struct si_mc_reg_table * table)5996 static void si_set_valid_flag(struct si_mc_reg_table *table)
5997 {
5998 u8 i, j;
5999
6000 for (i = 0; i < table->last; i++) {
6001 for (j = 1; j < table->num_entries; j++) {
6002 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
6003 table->valid_flag |= 1 << i;
6004 break;
6005 }
6006 }
6007 }
6008 }
6009
si_set_s0_mc_reg_index(struct si_mc_reg_table * table)6010 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
6011 {
6012 u32 i;
6013 u16 address;
6014
6015 for (i = 0; i < table->last; i++)
6016 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
6017 address : table->mc_reg_address[i].s1;
6018
6019 }
6020
si_copy_vbios_mc_reg_table(struct atom_mc_reg_table * table,struct si_mc_reg_table * si_table)6021 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
6022 struct si_mc_reg_table *si_table)
6023 {
6024 u8 i, j;
6025
6026 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6027 return -EINVAL;
6028 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
6029 return -EINVAL;
6030
6031 for (i = 0; i < table->last; i++)
6032 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
6033 si_table->last = table->last;
6034
6035 for (i = 0; i < table->num_entries; i++) {
6036 si_table->mc_reg_table_entry[i].mclk_max =
6037 table->mc_reg_table_entry[i].mclk_max;
6038 for (j = 0; j < table->last; j++) {
6039 si_table->mc_reg_table_entry[i].mc_data[j] =
6040 table->mc_reg_table_entry[i].mc_data[j];
6041 }
6042 }
6043 si_table->num_entries = table->num_entries;
6044
6045 return 0;
6046 }
6047
si_initialize_mc_reg_table(struct amdgpu_device * adev)6048 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6049 {
6050 struct si_power_info *si_pi = si_get_pi(adev);
6051 struct atom_mc_reg_table *table;
6052 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6053 u8 module_index = rv770_get_memory_module_index(adev);
6054 int ret;
6055
6056 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6057 if (!table)
6058 return -ENOMEM;
6059
6060 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6061 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6062 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6063 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6064 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6065 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6066 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6067 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6068 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6069 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6070 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6071 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6072 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6073 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6074
6075 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6076 if (ret)
6077 goto init_mc_done;
6078
6079 ret = si_copy_vbios_mc_reg_table(table, si_table);
6080 if (ret)
6081 goto init_mc_done;
6082
6083 si_set_s0_mc_reg_index(si_table);
6084
6085 ret = si_set_mc_special_registers(adev, si_table);
6086 if (ret)
6087 goto init_mc_done;
6088
6089 si_set_valid_flag(si_table);
6090
6091 init_mc_done:
6092 kfree(table);
6093
6094 return ret;
6095
6096 }
6097
si_populate_mc_reg_addresses(struct amdgpu_device * adev,SMC_SIslands_MCRegisters * mc_reg_table)6098 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6099 SMC_SIslands_MCRegisters *mc_reg_table)
6100 {
6101 struct si_power_info *si_pi = si_get_pi(adev);
6102 u32 i, j;
6103
6104 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6105 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6106 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6107 break;
6108 mc_reg_table->address[i].s0 =
6109 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6110 mc_reg_table->address[i].s1 =
6111 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6112 i++;
6113 }
6114 }
6115 mc_reg_table->last = (u8)i;
6116 }
6117
si_convert_mc_registers(const struct si_mc_reg_entry * entry,SMC_SIslands_MCRegisterSet * data,u32 num_entries,u32 valid_flag)6118 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6119 SMC_SIslands_MCRegisterSet *data,
6120 u32 num_entries, u32 valid_flag)
6121 {
6122 u32 i, j;
6123
6124 for(i = 0, j = 0; j < num_entries; j++) {
6125 if (valid_flag & (1 << j)) {
6126 data->value[i] = cpu_to_be32(entry->mc_data[j]);
6127 i++;
6128 }
6129 }
6130 }
6131
si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device * adev,struct rv7xx_pl * pl,SMC_SIslands_MCRegisterSet * mc_reg_table_data)6132 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6133 struct rv7xx_pl *pl,
6134 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6135 {
6136 struct si_power_info *si_pi = si_get_pi(adev);
6137 u32 i = 0;
6138
6139 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6140 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6141 break;
6142 }
6143
6144 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6145 --i;
6146
6147 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6148 mc_reg_table_data, si_pi->mc_reg_table.last,
6149 si_pi->mc_reg_table.valid_flag);
6150 }
6151
si_convert_mc_reg_table_to_smc(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SMC_SIslands_MCRegisters * mc_reg_table)6152 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6153 struct amdgpu_ps *amdgpu_state,
6154 SMC_SIslands_MCRegisters *mc_reg_table)
6155 {
6156 struct si_ps *state = si_get_ps(amdgpu_state);
6157 int i;
6158
6159 for (i = 0; i < state->performance_level_count; i++) {
6160 si_convert_mc_reg_table_entry_to_smc(adev,
6161 &state->performance_levels[i],
6162 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6163 }
6164 }
6165
si_populate_mc_reg_table(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_boot_state)6166 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6167 struct amdgpu_ps *amdgpu_boot_state)
6168 {
6169 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6170 struct si_power_info *si_pi = si_get_pi(adev);
6171 struct si_ulv_param *ulv = &si_pi->ulv;
6172 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6173
6174 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6175
6176 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6177
6178 si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6179
6180 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6181 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6182
6183 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6184 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6185 si_pi->mc_reg_table.last,
6186 si_pi->mc_reg_table.valid_flag);
6187
6188 if (ulv->supported && ulv->pl.vddc != 0)
6189 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6190 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6191 else
6192 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6193 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6194 si_pi->mc_reg_table.last,
6195 si_pi->mc_reg_table.valid_flag);
6196
6197 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6198
6199 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6200 (u8 *)smc_mc_reg_table,
6201 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6202 }
6203
si_upload_mc_reg_table(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)6204 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6205 struct amdgpu_ps *amdgpu_new_state)
6206 {
6207 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6208 struct si_power_info *si_pi = si_get_pi(adev);
6209 u32 address = si_pi->mc_reg_table_start +
6210 offsetof(SMC_SIslands_MCRegisters,
6211 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6212 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6213
6214 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6215
6216 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6217
6218 return amdgpu_si_copy_bytes_to_smc(adev, address,
6219 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6220 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6221 si_pi->sram_end);
6222 }
6223
si_enable_voltage_control(struct amdgpu_device * adev,bool enable)6224 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6225 {
6226 if (enable)
6227 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK);
6228 else
6229 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK);
6230 }
6231
si_get_maximum_link_speed(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)6232 static enum si_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6233 struct amdgpu_ps *amdgpu_state)
6234 {
6235 struct si_ps *state = si_get_ps(amdgpu_state);
6236 int i;
6237 u16 pcie_speed, max_speed = 0;
6238
6239 for (i = 0; i < state->performance_level_count; i++) {
6240 pcie_speed = state->performance_levels[i].pcie_gen;
6241 if (max_speed < pcie_speed)
6242 max_speed = pcie_speed;
6243 }
6244 return max_speed;
6245 }
6246
si_get_current_pcie_speed(struct amdgpu_device * adev)6247 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6248 {
6249 u32 speed_cntl;
6250
6251 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL) & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
6252 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
6253
6254 return (u16)speed_cntl;
6255 }
6256
si_request_link_speed_change_before_state_change(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,struct amdgpu_ps * amdgpu_current_state)6257 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6258 struct amdgpu_ps *amdgpu_new_state,
6259 struct amdgpu_ps *amdgpu_current_state)
6260 {
6261 struct si_power_info *si_pi = si_get_pi(adev);
6262 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6263 enum si_pcie_gen current_link_speed;
6264
6265 if (si_pi->force_pcie_gen == SI_PCIE_GEN_INVALID)
6266 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6267 else
6268 current_link_speed = si_pi->force_pcie_gen;
6269
6270 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID;
6271 si_pi->pspp_notify_required = false;
6272 if (target_link_speed > current_link_speed) {
6273 switch (target_link_speed) {
6274 #if defined(CONFIG_ACPI)
6275 case SI_PCIE_GEN3:
6276 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6277 break;
6278 si_pi->force_pcie_gen = SI_PCIE_GEN2;
6279 if (current_link_speed == SI_PCIE_GEN2)
6280 break;
6281 fallthrough;
6282 case SI_PCIE_GEN2:
6283 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6284 break;
6285 fallthrough;
6286 #endif
6287 default:
6288 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6289 break;
6290 }
6291 } else {
6292 if (target_link_speed < current_link_speed)
6293 si_pi->pspp_notify_required = true;
6294 }
6295 }
6296
si_notify_link_speed_change_after_state_change(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,struct amdgpu_ps * amdgpu_current_state)6297 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6298 struct amdgpu_ps *amdgpu_new_state,
6299 struct amdgpu_ps *amdgpu_current_state)
6300 {
6301 struct si_power_info *si_pi = si_get_pi(adev);
6302 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6303 u8 request;
6304
6305 if (si_pi->pspp_notify_required) {
6306 if (target_link_speed == SI_PCIE_GEN3)
6307 request = PCIE_PERF_REQ_PECI_GEN3;
6308 else if (target_link_speed == SI_PCIE_GEN2)
6309 request = PCIE_PERF_REQ_PECI_GEN2;
6310 else
6311 request = PCIE_PERF_REQ_PECI_GEN1;
6312
6313 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6314 (si_get_current_pcie_speed(adev) > 0))
6315 return;
6316
6317 #if defined(CONFIG_ACPI)
6318 amdgpu_acpi_pcie_performance_request(adev, request, false);
6319 #endif
6320 }
6321 }
6322
6323 #if 0
6324 static int si_ds_request(struct amdgpu_device *adev,
6325 bool ds_status_on, u32 count_write)
6326 {
6327 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6328
6329 if (eg_pi->sclk_deep_sleep) {
6330 if (ds_status_on)
6331 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6332 PPSMC_Result_OK) ?
6333 0 : -EINVAL;
6334 else
6335 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6336 PPSMC_Result_OK) ? 0 : -EINVAL;
6337 }
6338 return 0;
6339 }
6340 #endif
6341
si_set_max_cu_value(struct amdgpu_device * adev)6342 static void si_set_max_cu_value(struct amdgpu_device *adev)
6343 {
6344 struct si_power_info *si_pi = si_get_pi(adev);
6345
6346 if (adev->asic_type == CHIP_VERDE) {
6347 switch (adev->pdev->device) {
6348 case 0x6820:
6349 case 0x6825:
6350 case 0x6821:
6351 case 0x6823:
6352 case 0x6827:
6353 si_pi->max_cu = 10;
6354 break;
6355 case 0x682D:
6356 case 0x6824:
6357 case 0x682F:
6358 case 0x6826:
6359 si_pi->max_cu = 8;
6360 break;
6361 case 0x6828:
6362 case 0x6830:
6363 case 0x6831:
6364 case 0x6838:
6365 case 0x6839:
6366 case 0x683D:
6367 si_pi->max_cu = 10;
6368 break;
6369 case 0x683B:
6370 case 0x683F:
6371 case 0x6829:
6372 si_pi->max_cu = 8;
6373 break;
6374 default:
6375 si_pi->max_cu = 0;
6376 break;
6377 }
6378 } else {
6379 si_pi->max_cu = 0;
6380 }
6381 }
6382
si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device * adev,struct amdgpu_clock_voltage_dependency_table * table)6383 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6384 struct amdgpu_clock_voltage_dependency_table *table)
6385 {
6386 u32 i;
6387 int j;
6388 u16 leakage_voltage;
6389
6390 if (table) {
6391 for (i = 0; i < table->count; i++) {
6392 switch (si_get_leakage_voltage_from_leakage_index(adev,
6393 table->entries[i].v,
6394 &leakage_voltage)) {
6395 case 0:
6396 table->entries[i].v = leakage_voltage;
6397 break;
6398 case -EAGAIN:
6399 return -EINVAL;
6400 case -EINVAL:
6401 default:
6402 break;
6403 }
6404 }
6405
6406 for (j = (table->count - 2); j >= 0; j--) {
6407 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6408 table->entries[j].v : table->entries[j + 1].v;
6409 }
6410 }
6411 return 0;
6412 }
6413
si_patch_dependency_tables_based_on_leakage(struct amdgpu_device * adev)6414 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6415 {
6416 int ret = 0;
6417
6418 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6419 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6420 if (ret)
6421 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6422 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6423 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6424 if (ret)
6425 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6426 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6427 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6428 if (ret)
6429 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6430 return ret;
6431 }
6432
si_set_pcie_lane_width_in_smc(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,struct amdgpu_ps * amdgpu_current_state)6433 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6434 struct amdgpu_ps *amdgpu_new_state,
6435 struct amdgpu_ps *amdgpu_current_state)
6436 {
6437 u32 lane_width;
6438 u32 new_lane_width =
6439 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6440 u32 current_lane_width =
6441 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6442
6443 if (new_lane_width != current_lane_width) {
6444 amdgpu_set_pcie_lanes(adev, new_lane_width);
6445 lane_width = amdgpu_get_pcie_lanes(adev);
6446 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6447 }
6448 }
6449
si_dpm_setup_asic(struct amdgpu_device * adev)6450 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6451 {
6452 si_read_clock_registers(adev);
6453 si_enable_acpi_power_management(adev);
6454 }
6455
si_thermal_enable_alert(struct amdgpu_device * adev,bool enable)6456 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6457 bool enable)
6458 {
6459 u32 thermal_int = RREG32(mmCG_THERMAL_INT);
6460
6461 if (enable) {
6462 PPSMC_Result result;
6463
6464 thermal_int &= ~(CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK);
6465 WREG32(mmCG_THERMAL_INT, thermal_int);
6466 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6467 if (result != PPSMC_Result_OK) {
6468 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6469 return -EINVAL;
6470 }
6471 } else {
6472 thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
6473 WREG32(mmCG_THERMAL_INT, thermal_int);
6474 }
6475
6476 return 0;
6477 }
6478
si_thermal_set_temperature_range(struct amdgpu_device * adev,int min_temp,int max_temp)6479 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6480 int min_temp, int max_temp)
6481 {
6482 int low_temp = 0 * 1000;
6483 int high_temp = 255 * 1000;
6484
6485 if (low_temp < min_temp)
6486 low_temp = min_temp;
6487 if (high_temp > max_temp)
6488 high_temp = max_temp;
6489 if (high_temp < low_temp) {
6490 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6491 return -EINVAL;
6492 }
6493
6494 WREG32_P(mmCG_THERMAL_INT, (high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTH_MASK);
6495 WREG32_P(mmCG_THERMAL_INT, (low_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTL_MASK);
6496 WREG32_P(mmCG_THERMAL_CTRL, (high_temp / 1000) << CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT, ~CG_THERMAL_CTRL__DIG_THERM_DPM_MASK);
6497
6498 adev->pm.dpm.thermal.min_temp = low_temp;
6499 adev->pm.dpm.thermal.max_temp = high_temp;
6500
6501 return 0;
6502 }
6503
si_fan_ctrl_set_static_mode(struct amdgpu_device * adev,u32 mode)6504 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6505 {
6506 struct si_power_info *si_pi = si_get_pi(adev);
6507 u32 tmp;
6508
6509 if (si_pi->fan_ctrl_is_in_default_mode) {
6510 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
6511 si_pi->fan_ctrl_default_mode = tmp;
6512 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) >> CG_FDO_CTRL2__TMIN__SHIFT;
6513 si_pi->t_min = tmp;
6514 si_pi->fan_ctrl_is_in_default_mode = false;
6515 }
6516
6517 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
6518 tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
6519 WREG32(mmCG_FDO_CTRL2, tmp);
6520
6521 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
6522 tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
6523 WREG32(mmCG_FDO_CTRL2, tmp);
6524 }
6525
si_thermal_setup_fan_table(struct amdgpu_device * adev)6526 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6527 {
6528 struct si_power_info *si_pi = si_get_pi(adev);
6529 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6530 u32 duty100;
6531 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6532 u16 fdo_min, slope1, slope2;
6533 u32 reference_clock, tmp;
6534 int ret;
6535 u64 tmp64;
6536
6537 if (!si_pi->fan_table_start) {
6538 adev->pm.dpm.fan.ucode_fan_control = false;
6539 return 0;
6540 }
6541
6542 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
6543
6544 if (duty100 == 0) {
6545 adev->pm.dpm.fan.ucode_fan_control = false;
6546 return 0;
6547 }
6548
6549 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6550 do_div(tmp64, 10000);
6551 fdo_min = (u16)tmp64;
6552
6553 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6554 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6555
6556 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6557 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6558
6559 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6560 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6561
6562 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6563 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6564 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6565 fan_table.slope1 = cpu_to_be16(slope1);
6566 fan_table.slope2 = cpu_to_be16(slope2);
6567 fan_table.fdo_min = cpu_to_be16(fdo_min);
6568 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6569 fan_table.hys_up = cpu_to_be16(1);
6570 fan_table.hys_slope = cpu_to_be16(1);
6571 fan_table.temp_resp_lim = cpu_to_be16(5);
6572 reference_clock = amdgpu_asic_get_xclk(adev);
6573
6574 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6575 reference_clock) / 1600);
6576 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6577
6578 tmp = (RREG32(mmCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
6579 fan_table.temp_src = (uint8_t)tmp;
6580
6581 ret = amdgpu_si_copy_bytes_to_smc(adev,
6582 si_pi->fan_table_start,
6583 (u8 *)(&fan_table),
6584 sizeof(fan_table),
6585 si_pi->sram_end);
6586
6587 if (ret) {
6588 DRM_ERROR("Failed to load fan table to the SMC.");
6589 adev->pm.dpm.fan.ucode_fan_control = false;
6590 }
6591
6592 return ret;
6593 }
6594
si_fan_ctrl_start_smc_fan_control(struct amdgpu_device * adev)6595 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6596 {
6597 struct si_power_info *si_pi = si_get_pi(adev);
6598 PPSMC_Result ret;
6599
6600 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6601 if (ret == PPSMC_Result_OK) {
6602 si_pi->fan_is_controlled_by_smc = true;
6603 return 0;
6604 } else {
6605 return -EINVAL;
6606 }
6607 }
6608
si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device * adev)6609 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6610 {
6611 struct si_power_info *si_pi = si_get_pi(adev);
6612 PPSMC_Result ret;
6613
6614 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6615
6616 if (ret == PPSMC_Result_OK) {
6617 si_pi->fan_is_controlled_by_smc = false;
6618 return 0;
6619 } else {
6620 return -EINVAL;
6621 }
6622 }
6623
si_dpm_get_fan_speed_pwm(void * handle,u32 * speed)6624 static int si_dpm_get_fan_speed_pwm(void *handle,
6625 u32 *speed)
6626 {
6627 u32 duty, duty100;
6628 u64 tmp64;
6629 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6630
6631 if (!speed)
6632 return -EINVAL;
6633
6634 if (adev->pm.no_fan)
6635 return -ENOENT;
6636
6637 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
6638 duty = (RREG32(mmCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK) >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
6639
6640 if (duty100 == 0)
6641 return -EINVAL;
6642
6643 tmp64 = (u64)duty * 255;
6644 do_div(tmp64, duty100);
6645 *speed = min_t(u32, tmp64, 255);
6646
6647 return 0;
6648 }
6649
si_dpm_set_fan_speed_pwm(void * handle,u32 speed)6650 static int si_dpm_set_fan_speed_pwm(void *handle,
6651 u32 speed)
6652 {
6653 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6654 struct si_power_info *si_pi = si_get_pi(adev);
6655 u32 tmp;
6656 u32 duty, duty100;
6657 u64 tmp64;
6658
6659 if (adev->pm.no_fan)
6660 return -ENOENT;
6661
6662 if (si_pi->fan_is_controlled_by_smc)
6663 return -EINVAL;
6664
6665 if (speed > 255)
6666 return -EINVAL;
6667
6668 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
6669
6670 if (duty100 == 0)
6671 return -EINVAL;
6672
6673 tmp64 = (u64)speed * duty100;
6674 do_div(tmp64, 255);
6675 duty = (u32)tmp64;
6676
6677 tmp = RREG32(mmCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
6678 tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
6679 WREG32(mmCG_FDO_CTRL0, tmp);
6680
6681 return 0;
6682 }
6683
si_dpm_set_fan_control_mode(void * handle,u32 mode)6684 static int si_dpm_set_fan_control_mode(void *handle, u32 mode)
6685 {
6686 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6687
6688 if (mode == U32_MAX)
6689 return -EINVAL;
6690
6691 if (mode) {
6692 /* stop auto-manage */
6693 if (adev->pm.dpm.fan.ucode_fan_control)
6694 si_fan_ctrl_stop_smc_fan_control(adev);
6695 si_fan_ctrl_set_static_mode(adev, mode);
6696 } else {
6697 /* restart auto-manage */
6698 if (adev->pm.dpm.fan.ucode_fan_control)
6699 si_thermal_start_smc_fan_control(adev);
6700 else
6701 si_fan_ctrl_set_default_mode(adev);
6702 }
6703
6704 return 0;
6705 }
6706
si_dpm_get_fan_control_mode(void * handle,u32 * fan_mode)6707 static int si_dpm_get_fan_control_mode(void *handle, u32 *fan_mode)
6708 {
6709 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6710 struct si_power_info *si_pi = si_get_pi(adev);
6711 u32 tmp;
6712
6713 if (!fan_mode)
6714 return -EINVAL;
6715
6716 if (si_pi->fan_is_controlled_by_smc)
6717 return 0;
6718
6719 tmp = RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
6720 *fan_mode = (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
6721
6722 return 0;
6723 }
6724
6725 #if 0
6726 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6727 u32 *speed)
6728 {
6729 u32 tach_period;
6730 u32 xclk = amdgpu_asic_get_xclk(adev);
6731
6732 if (adev->pm.no_fan)
6733 return -ENOENT;
6734
6735 if (adev->pm.fan_pulses_per_revolution == 0)
6736 return -ENOENT;
6737
6738 tach_period = (RREG32(mmCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK) >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
6739 if (tach_period == 0)
6740 return -ENOENT;
6741
6742 *speed = 60 * xclk * 10000 / tach_period;
6743
6744 return 0;
6745 }
6746
6747 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6748 u32 speed)
6749 {
6750 u32 tach_period, tmp;
6751 u32 xclk = amdgpu_asic_get_xclk(adev);
6752
6753 if (adev->pm.no_fan)
6754 return -ENOENT;
6755
6756 if (adev->pm.fan_pulses_per_revolution == 0)
6757 return -ENOENT;
6758
6759 if ((speed < adev->pm.fan_min_rpm) ||
6760 (speed > adev->pm.fan_max_rpm))
6761 return -EINVAL;
6762
6763 if (adev->pm.dpm.fan.ucode_fan_control)
6764 si_fan_ctrl_stop_smc_fan_control(adev);
6765
6766 tach_period = 60 * xclk * 10000 / (8 * speed);
6767 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
6768 tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
6769 WREG32(mmCG_TACH_CTRL, tmp);
6770
6771 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6772
6773 return 0;
6774 }
6775 #endif
6776
si_fan_ctrl_set_default_mode(struct amdgpu_device * adev)6777 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6778 {
6779 struct si_power_info *si_pi = si_get_pi(adev);
6780 u32 tmp;
6781
6782 if (!si_pi->fan_ctrl_is_in_default_mode) {
6783 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
6784 tmp |= si_pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
6785 WREG32(mmCG_FDO_CTRL2, tmp);
6786
6787 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
6788 tmp |= si_pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
6789 WREG32(mmCG_FDO_CTRL2, tmp);
6790 si_pi->fan_ctrl_is_in_default_mode = true;
6791 }
6792 }
6793
si_thermal_start_smc_fan_control(struct amdgpu_device * adev)6794 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6795 {
6796 if (adev->pm.dpm.fan.ucode_fan_control) {
6797 si_fan_ctrl_start_smc_fan_control(adev);
6798 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6799 }
6800 }
6801
si_thermal_initialize(struct amdgpu_device * adev)6802 static void si_thermal_initialize(struct amdgpu_device *adev)
6803 {
6804 u32 tmp;
6805
6806 if (adev->pm.fan_pulses_per_revolution) {
6807 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
6808 tmp |= (adev->pm.fan_pulses_per_revolution -1) << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
6809 WREG32(mmCG_TACH_CTRL, tmp);
6810 }
6811
6812 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
6813 tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
6814 WREG32(mmCG_FDO_CTRL2, tmp);
6815 }
6816
si_thermal_start_thermal_controller(struct amdgpu_device * adev)6817 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6818 {
6819 int ret;
6820
6821 si_thermal_initialize(adev);
6822 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6823 if (ret)
6824 return ret;
6825 ret = si_thermal_enable_alert(adev, true);
6826 if (ret)
6827 return ret;
6828 if (adev->pm.dpm.fan.ucode_fan_control) {
6829 ret = si_halt_smc(adev);
6830 if (ret)
6831 return ret;
6832 ret = si_thermal_setup_fan_table(adev);
6833 if (ret)
6834 return ret;
6835 ret = si_resume_smc(adev);
6836 if (ret)
6837 return ret;
6838 si_thermal_start_smc_fan_control(adev);
6839 }
6840
6841 return 0;
6842 }
6843
si_thermal_stop_thermal_controller(struct amdgpu_device * adev)6844 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6845 {
6846 if (!adev->pm.no_fan) {
6847 si_fan_ctrl_set_default_mode(adev);
6848 si_fan_ctrl_stop_smc_fan_control(adev);
6849 }
6850 }
6851
si_dpm_enable(struct amdgpu_device * adev)6852 static int si_dpm_enable(struct amdgpu_device *adev)
6853 {
6854 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6855 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6856 struct si_power_info *si_pi = si_get_pi(adev);
6857 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6858 int ret;
6859
6860 if (amdgpu_si_is_smc_running(adev))
6861 return -EINVAL;
6862 if (pi->voltage_control || si_pi->voltage_control_svi2)
6863 si_enable_voltage_control(adev, true);
6864 if (pi->mvdd_control)
6865 si_get_mvdd_configuration(adev);
6866 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6867 ret = si_construct_voltage_tables(adev);
6868 if (ret) {
6869 DRM_ERROR("si_construct_voltage_tables failed\n");
6870 return ret;
6871 }
6872 }
6873 if (eg_pi->dynamic_ac_timing) {
6874 ret = si_initialize_mc_reg_table(adev);
6875 if (ret)
6876 eg_pi->dynamic_ac_timing = false;
6877 }
6878 if (pi->dynamic_ss)
6879 si_enable_spread_spectrum(adev, true);
6880 if (pi->thermal_protection)
6881 si_enable_thermal_protection(adev, true);
6882 si_setup_bsp(adev);
6883 si_program_git(adev);
6884 si_program_tp(adev);
6885 si_program_tpp(adev);
6886 si_program_sstp(adev);
6887 si_enable_display_gap(adev);
6888 si_program_vc(adev);
6889 ret = si_upload_firmware(adev);
6890 if (ret) {
6891 DRM_ERROR("si_upload_firmware failed\n");
6892 return ret;
6893 }
6894 ret = si_process_firmware_header(adev);
6895 if (ret) {
6896 DRM_ERROR("si_process_firmware_header failed\n");
6897 return ret;
6898 }
6899 ret = si_initial_switch_from_arb_f0_to_f1(adev);
6900 if (ret) {
6901 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6902 return ret;
6903 }
6904 ret = si_init_smc_table(adev);
6905 if (ret) {
6906 DRM_ERROR("si_init_smc_table failed\n");
6907 return ret;
6908 }
6909 ret = si_init_smc_spll_table(adev);
6910 if (ret) {
6911 DRM_ERROR("si_init_smc_spll_table failed\n");
6912 return ret;
6913 }
6914 ret = si_init_arb_table_index(adev);
6915 if (ret) {
6916 DRM_ERROR("si_init_arb_table_index failed\n");
6917 return ret;
6918 }
6919 if (eg_pi->dynamic_ac_timing) {
6920 ret = si_populate_mc_reg_table(adev, boot_ps);
6921 if (ret) {
6922 DRM_ERROR("si_populate_mc_reg_table failed\n");
6923 return ret;
6924 }
6925 }
6926 ret = si_initialize_smc_cac_tables(adev);
6927 if (ret) {
6928 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6929 return ret;
6930 }
6931 ret = si_initialize_hardware_cac_manager(adev);
6932 if (ret) {
6933 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6934 return ret;
6935 }
6936 ret = si_initialize_smc_dte_tables(adev);
6937 if (ret) {
6938 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6939 return ret;
6940 }
6941 ret = si_populate_smc_tdp_limits(adev, boot_ps);
6942 if (ret) {
6943 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6944 return ret;
6945 }
6946 ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6947 if (ret) {
6948 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6949 return ret;
6950 }
6951 si_program_response_times(adev);
6952 si_program_ds_registers(adev);
6953 si_dpm_start_smc(adev);
6954 ret = si_notify_smc_display_change(adev, false);
6955 if (ret) {
6956 DRM_ERROR("si_notify_smc_display_change failed\n");
6957 return ret;
6958 }
6959 si_enable_sclk_control(adev, true);
6960 si_start_dpm(adev);
6961
6962 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6963 si_thermal_start_thermal_controller(adev);
6964
6965 ni_update_current_ps(adev, boot_ps);
6966
6967 return 0;
6968 }
6969
si_set_temperature_range(struct amdgpu_device * adev)6970 static int si_set_temperature_range(struct amdgpu_device *adev)
6971 {
6972 int ret;
6973
6974 ret = si_thermal_enable_alert(adev, false);
6975 if (ret)
6976 return ret;
6977 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6978 if (ret)
6979 return ret;
6980 ret = si_thermal_enable_alert(adev, true);
6981 if (ret)
6982 return ret;
6983
6984 return ret;
6985 }
6986
si_dpm_disable(struct amdgpu_device * adev)6987 static void si_dpm_disable(struct amdgpu_device *adev)
6988 {
6989 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6990 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6991
6992 if (!amdgpu_si_is_smc_running(adev))
6993 return;
6994 si_thermal_stop_thermal_controller(adev);
6995 si_disable_ulv(adev);
6996 si_clear_vc(adev);
6997 if (pi->thermal_protection)
6998 si_enable_thermal_protection(adev, false);
6999 si_enable_power_containment(adev, boot_ps, false);
7000 si_enable_smc_cac(adev, boot_ps, false);
7001 si_enable_spread_spectrum(adev, false);
7002 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
7003 si_stop_dpm(adev);
7004 si_reset_to_default(adev);
7005 si_dpm_stop_smc(adev);
7006 si_force_switch_to_arb_f0(adev);
7007
7008 ni_update_current_ps(adev, boot_ps);
7009 }
7010
si_dpm_pre_set_power_state(void * handle)7011 static int si_dpm_pre_set_power_state(void *handle)
7012 {
7013 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7014 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7015 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
7016 struct amdgpu_ps *new_ps = &requested_ps;
7017
7018 ni_update_requested_ps(adev, new_ps);
7019 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
7020
7021 return 0;
7022 }
7023
si_power_control_set_level(struct amdgpu_device * adev)7024 static int si_power_control_set_level(struct amdgpu_device *adev)
7025 {
7026 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
7027 int ret;
7028
7029 ret = si_restrict_performance_levels_before_switch(adev);
7030 if (ret)
7031 return ret;
7032 ret = si_halt_smc(adev);
7033 if (ret)
7034 return ret;
7035 ret = si_populate_smc_tdp_limits(adev, new_ps);
7036 if (ret)
7037 return ret;
7038 ret = si_populate_smc_tdp_limits_2(adev, new_ps);
7039 if (ret)
7040 return ret;
7041 ret = si_resume_smc(adev);
7042 if (ret)
7043 return ret;
7044 return si_set_sw_state(adev);
7045 }
7046
si_set_vce_clock(struct amdgpu_device * adev,struct amdgpu_ps * new_rps,struct amdgpu_ps * old_rps)7047 static void si_set_vce_clock(struct amdgpu_device *adev,
7048 struct amdgpu_ps *new_rps,
7049 struct amdgpu_ps *old_rps)
7050 {
7051 if ((old_rps->evclk != new_rps->evclk) ||
7052 (old_rps->ecclk != new_rps->ecclk)) {
7053 /* Turn the clocks on when encoding, off otherwise */
7054 if (new_rps->evclk || new_rps->ecclk) {
7055 /* Place holder for future VCE1.0 porting to amdgpu
7056 vce_v1_0_enable_mgcg(adev, false, false);*/
7057 } else {
7058 /* Place holder for future VCE1.0 porting to amdgpu
7059 vce_v1_0_enable_mgcg(adev, true, false);
7060 amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);*/
7061 }
7062 }
7063 }
7064
si_dpm_set_power_state(void * handle)7065 static int si_dpm_set_power_state(void *handle)
7066 {
7067 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7068 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7069 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7070 struct amdgpu_ps *old_ps = &eg_pi->current_rps;
7071 int ret;
7072
7073 ret = si_disable_ulv(adev);
7074 if (ret) {
7075 DRM_ERROR("si_disable_ulv failed\n");
7076 return ret;
7077 }
7078 ret = si_restrict_performance_levels_before_switch(adev);
7079 if (ret) {
7080 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7081 return ret;
7082 }
7083 if (eg_pi->pcie_performance_request)
7084 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7085 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7086 ret = si_enable_power_containment(adev, new_ps, false);
7087 if (ret) {
7088 DRM_ERROR("si_enable_power_containment failed\n");
7089 return ret;
7090 }
7091 ret = si_enable_smc_cac(adev, new_ps, false);
7092 if (ret) {
7093 DRM_ERROR("si_enable_smc_cac failed\n");
7094 return ret;
7095 }
7096 ret = si_halt_smc(adev);
7097 if (ret) {
7098 DRM_ERROR("si_halt_smc failed\n");
7099 return ret;
7100 }
7101 ret = si_upload_sw_state(adev, new_ps);
7102 if (ret) {
7103 DRM_ERROR("si_upload_sw_state failed\n");
7104 return ret;
7105 }
7106 ret = si_upload_smc_data(adev);
7107 if (ret) {
7108 DRM_ERROR("si_upload_smc_data failed\n");
7109 return ret;
7110 }
7111 ret = si_upload_ulv_state(adev);
7112 if (ret) {
7113 DRM_ERROR("si_upload_ulv_state failed\n");
7114 return ret;
7115 }
7116 if (eg_pi->dynamic_ac_timing) {
7117 ret = si_upload_mc_reg_table(adev, new_ps);
7118 if (ret) {
7119 DRM_ERROR("si_upload_mc_reg_table failed\n");
7120 return ret;
7121 }
7122 }
7123 ret = si_program_memory_timing_parameters(adev, new_ps);
7124 if (ret) {
7125 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7126 return ret;
7127 }
7128 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7129
7130 ret = si_resume_smc(adev);
7131 if (ret) {
7132 DRM_ERROR("si_resume_smc failed\n");
7133 return ret;
7134 }
7135 ret = si_set_sw_state(adev);
7136 if (ret) {
7137 DRM_ERROR("si_set_sw_state failed\n");
7138 return ret;
7139 }
7140 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7141 si_set_vce_clock(adev, new_ps, old_ps);
7142 if (eg_pi->pcie_performance_request)
7143 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7144 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7145 if (ret) {
7146 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7147 return ret;
7148 }
7149 ret = si_enable_smc_cac(adev, new_ps, true);
7150 if (ret) {
7151 DRM_ERROR("si_enable_smc_cac failed\n");
7152 return ret;
7153 }
7154 ret = si_enable_power_containment(adev, new_ps, true);
7155 if (ret) {
7156 DRM_ERROR("si_enable_power_containment failed\n");
7157 return ret;
7158 }
7159
7160 ret = si_power_control_set_level(adev);
7161 if (ret) {
7162 DRM_ERROR("si_power_control_set_level failed\n");
7163 return ret;
7164 }
7165
7166 return 0;
7167 }
7168
si_dpm_post_set_power_state(void * handle)7169 static void si_dpm_post_set_power_state(void *handle)
7170 {
7171 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7172 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7173 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7174
7175 ni_update_current_ps(adev, new_ps);
7176 }
7177
7178 #if 0
7179 void si_dpm_reset_asic(struct amdgpu_device *adev)
7180 {
7181 si_restrict_performance_levels_before_switch(adev);
7182 si_disable_ulv(adev);
7183 si_set_boot_state(adev);
7184 }
7185 #endif
7186
si_dpm_display_configuration_changed(void * handle)7187 static void si_dpm_display_configuration_changed(void *handle)
7188 {
7189 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7190
7191 si_program_display_gap(adev);
7192 }
7193
7194
si_parse_pplib_non_clock_info(struct amdgpu_device * adev,struct amdgpu_ps * rps,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info,u8 table_rev)7195 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7196 struct amdgpu_ps *rps,
7197 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7198 u8 table_rev)
7199 {
7200 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7201 rps->class = le16_to_cpu(non_clock_info->usClassification);
7202 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7203
7204 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7205 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7206 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7207 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7208 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7209 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7210 } else {
7211 rps->vclk = 0;
7212 rps->dclk = 0;
7213 }
7214
7215 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7216 adev->pm.dpm.boot_ps = rps;
7217 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7218 adev->pm.dpm.uvd_ps = rps;
7219 }
7220
si_parse_pplib_clock_info(struct amdgpu_device * adev,struct amdgpu_ps * rps,int index,union pplib_clock_info * clock_info)7221 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7222 struct amdgpu_ps *rps, int index,
7223 union pplib_clock_info *clock_info)
7224 {
7225 struct rv7xx_power_info *pi = rv770_get_pi(adev);
7226 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7227 struct si_power_info *si_pi = si_get_pi(adev);
7228 struct si_ps *ps = si_get_ps(rps);
7229 u16 leakage_voltage;
7230 struct rv7xx_pl *pl = &ps->performance_levels[index];
7231 int ret;
7232
7233 ps->performance_level_count = index + 1;
7234
7235 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7236 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7237 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7238 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7239
7240 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7241 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7242 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7243 pl->pcie_gen = si_gen_pcie_gen_support(adev,
7244 si_pi->sys_pcie_mask,
7245 si_pi->boot_pcie_gen,
7246 clock_info->si.ucPCIEGen);
7247
7248 /* patch up vddc if necessary */
7249 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7250 &leakage_voltage);
7251 if (ret == 0)
7252 pl->vddc = leakage_voltage;
7253
7254 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7255 pi->acpi_vddc = pl->vddc;
7256 eg_pi->acpi_vddci = pl->vddci;
7257 si_pi->acpi_pcie_gen = pl->pcie_gen;
7258 }
7259
7260 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7261 index == 0) {
7262 /* XXX disable for A0 tahiti */
7263 si_pi->ulv.supported = false;
7264 si_pi->ulv.pl = *pl;
7265 si_pi->ulv.one_pcie_lane_in_ulv = false;
7266 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7267 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7268 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7269 }
7270
7271 if (pi->min_vddc_in_table > pl->vddc)
7272 pi->min_vddc_in_table = pl->vddc;
7273
7274 if (pi->max_vddc_in_table < pl->vddc)
7275 pi->max_vddc_in_table = pl->vddc;
7276
7277 /* patch up boot state */
7278 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7279 u16 vddc, vddci, mvdd;
7280 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7281 pl->mclk = adev->clock.default_mclk;
7282 pl->sclk = adev->clock.default_sclk;
7283 pl->vddc = vddc;
7284 pl->vddci = vddci;
7285 si_pi->mvdd_bootup_value = mvdd;
7286 }
7287
7288 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7289 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7290 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7291 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7292 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7293 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7294 }
7295 }
7296
7297 union pplib_power_state {
7298 struct _ATOM_PPLIB_STATE v1;
7299 struct _ATOM_PPLIB_STATE_V2 v2;
7300 };
7301
si_parse_power_table(struct amdgpu_device * adev)7302 static int si_parse_power_table(struct amdgpu_device *adev)
7303 {
7304 struct amdgpu_mode_info *mode_info = &adev->mode_info;
7305 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7306 union pplib_power_state *power_state;
7307 int i, j, k, non_clock_array_index, clock_array_index;
7308 union pplib_clock_info *clock_info;
7309 struct _StateArray *state_array;
7310 struct _ClockInfoArray *clock_info_array;
7311 struct _NonClockInfoArray *non_clock_info_array;
7312 union power_info *power_info;
7313 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7314 u16 data_offset;
7315 u8 frev, crev;
7316 u8 *power_state_offset;
7317 struct si_ps *ps;
7318
7319 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7320 &frev, &crev, &data_offset))
7321 return -EINVAL;
7322 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7323
7324 amdgpu_add_thermal_controller(adev);
7325
7326 state_array = (struct _StateArray *)
7327 (mode_info->atom_context->bios + data_offset +
7328 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7329 clock_info_array = (struct _ClockInfoArray *)
7330 (mode_info->atom_context->bios + data_offset +
7331 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7332 non_clock_info_array = (struct _NonClockInfoArray *)
7333 (mode_info->atom_context->bios + data_offset +
7334 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7335
7336 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
7337 sizeof(struct amdgpu_ps),
7338 GFP_KERNEL);
7339 if (!adev->pm.dpm.ps)
7340 return -ENOMEM;
7341 power_state_offset = (u8 *)state_array->states;
7342 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) {
7343 u8 *idx;
7344 power_state = (union pplib_power_state *)power_state_offset;
7345 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7346 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7347 &non_clock_info_array->nonClockInfo[non_clock_array_index];
7348 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL);
7349 if (ps == NULL)
7350 return -ENOMEM;
7351 adev->pm.dpm.ps[i].ps_priv = ps;
7352 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7353 non_clock_info,
7354 non_clock_info_array->ucEntrySize);
7355 k = 0;
7356 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7357 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7358 clock_array_index = idx[j];
7359 if (clock_array_index >= clock_info_array->ucNumEntries)
7360 continue;
7361 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7362 break;
7363 clock_info = (union pplib_clock_info *)
7364 ((u8 *)&clock_info_array->clockInfo[0] +
7365 (clock_array_index * clock_info_array->ucEntrySize));
7366 si_parse_pplib_clock_info(adev,
7367 &adev->pm.dpm.ps[i], k,
7368 clock_info);
7369 k++;
7370 }
7371 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7372 adev->pm.dpm.num_ps++;
7373 }
7374
7375 /* fill in the vce power states */
7376 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7377 u32 sclk, mclk;
7378 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7379 clock_info = (union pplib_clock_info *)
7380 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7381 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7382 sclk |= clock_info->si.ucEngineClockHigh << 16;
7383 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7384 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7385 adev->pm.dpm.vce_states[i].sclk = sclk;
7386 adev->pm.dpm.vce_states[i].mclk = mclk;
7387 }
7388
7389 return 0;
7390 }
7391
si_dpm_init(struct amdgpu_device * adev)7392 static int si_dpm_init(struct amdgpu_device *adev)
7393 {
7394 struct rv7xx_power_info *pi;
7395 struct evergreen_power_info *eg_pi;
7396 struct ni_power_info *ni_pi;
7397 struct si_power_info *si_pi;
7398 struct atom_clock_dividers dividers;
7399 int ret;
7400
7401 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7402 if (si_pi == NULL)
7403 return -ENOMEM;
7404 adev->pm.dpm.priv = si_pi;
7405 ni_pi = &si_pi->ni;
7406 eg_pi = &ni_pi->eg;
7407 pi = &eg_pi->rv7xx;
7408
7409 si_pi->sys_pcie_mask =
7410 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
7411 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID;
7412 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7413
7414 si_set_max_cu_value(adev);
7415
7416 rv770_get_max_vddc(adev);
7417 si_get_leakage_vddc(adev);
7418 si_patch_dependency_tables_based_on_leakage(adev);
7419
7420 pi->acpi_vddc = 0;
7421 eg_pi->acpi_vddci = 0;
7422 pi->min_vddc_in_table = 0;
7423 pi->max_vddc_in_table = 0;
7424
7425 ret = amdgpu_get_platform_caps(adev);
7426 if (ret)
7427 return ret;
7428
7429 ret = amdgpu_parse_extended_power_table(adev);
7430 if (ret)
7431 return ret;
7432
7433 ret = si_parse_power_table(adev);
7434 if (ret)
7435 return ret;
7436
7437 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7438 kcalloc(4,
7439 sizeof(struct amdgpu_clock_voltage_dependency_entry),
7440 GFP_KERNEL);
7441 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries)
7442 return -ENOMEM;
7443
7444 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7445 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7446 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7447 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7448 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7449 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7450 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7451 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7452 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7453
7454 if (adev->pm.dpm.voltage_response_time == 0)
7455 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7456 if (adev->pm.dpm.backbias_response_time == 0)
7457 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7458
7459 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7460 0, false, ÷rs);
7461 if (ret)
7462 pi->ref_div = dividers.ref_div + 1;
7463 else
7464 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7465
7466 eg_pi->smu_uvd_hs = false;
7467
7468 pi->mclk_strobe_mode_threshold = 40000;
7469 if (si_is_special_1gb_platform(adev))
7470 pi->mclk_stutter_mode_threshold = 0;
7471 else
7472 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7473 pi->mclk_edc_enable_threshold = 40000;
7474 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7475
7476 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7477
7478 pi->voltage_control =
7479 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7480 VOLTAGE_OBJ_GPIO_LUT);
7481 if (!pi->voltage_control) {
7482 si_pi->voltage_control_svi2 =
7483 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7484 VOLTAGE_OBJ_SVID2);
7485 if (si_pi->voltage_control_svi2)
7486 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7487 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7488 }
7489
7490 pi->mvdd_control =
7491 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7492 VOLTAGE_OBJ_GPIO_LUT);
7493
7494 eg_pi->vddci_control =
7495 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7496 VOLTAGE_OBJ_GPIO_LUT);
7497 if (!eg_pi->vddci_control)
7498 si_pi->vddci_control_svi2 =
7499 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7500 VOLTAGE_OBJ_SVID2);
7501
7502 si_pi->vddc_phase_shed_control =
7503 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7504 VOLTAGE_OBJ_PHASE_LUT);
7505
7506 rv770_get_engine_memory_ss(adev);
7507
7508 pi->asi = RV770_ASI_DFLT;
7509 pi->pasi = CYPRESS_HASI_DFLT;
7510 pi->vrc = SISLANDS_VRC_DFLT;
7511
7512 pi->gfx_clock_gating = true;
7513
7514 eg_pi->sclk_deep_sleep = true;
7515 si_pi->sclk_deep_sleep_above_low = false;
7516
7517 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7518 pi->thermal_protection = true;
7519 else
7520 pi->thermal_protection = false;
7521
7522 eg_pi->dynamic_ac_timing = true;
7523
7524 eg_pi->light_sleep = true;
7525 #if defined(CONFIG_ACPI)
7526 eg_pi->pcie_performance_request =
7527 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7528 #else
7529 eg_pi->pcie_performance_request = false;
7530 #endif
7531
7532 si_pi->sram_end = SMC_RAM_END;
7533
7534 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7535 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7536 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7537 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7538 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7539 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7540 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7541
7542 si_initialize_powertune_defaults(adev);
7543
7544 /* make sure dc limits are valid */
7545 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7546 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7547 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7548 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7549
7550 si_pi->fan_ctrl_is_in_default_mode = true;
7551
7552 return 0;
7553 }
7554
si_dpm_fini(struct amdgpu_device * adev)7555 static void si_dpm_fini(struct amdgpu_device *adev)
7556 {
7557 int i;
7558
7559 if (adev->pm.dpm.ps)
7560 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7561 kfree(adev->pm.dpm.ps[i].ps_priv);
7562 kfree(adev->pm.dpm.ps);
7563 kfree(adev->pm.dpm.priv);
7564 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7565 amdgpu_free_extended_power_table(adev);
7566 }
7567
si_dpm_debugfs_print_current_performance_level(void * handle,struct seq_file * m)7568 static void si_dpm_debugfs_print_current_performance_level(void *handle,
7569 struct seq_file *m)
7570 {
7571 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7572 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7573 struct amdgpu_ps *rps = &eg_pi->current_rps;
7574 struct si_ps *ps = si_get_ps(rps);
7575 struct rv7xx_pl *pl;
7576 u32 current_index =
7577 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >>
7578 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT;
7579
7580 if (current_index >= ps->performance_level_count) {
7581 seq_printf(m, "invalid dpm profile %d\n", current_index);
7582 } else {
7583 pl = &ps->performance_levels[current_index];
7584 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7585 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7586 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7587 }
7588 }
7589
si_dpm_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)7590 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7591 struct amdgpu_irq_src *source,
7592 unsigned type,
7593 enum amdgpu_interrupt_state state)
7594 {
7595 u32 cg_thermal_int;
7596
7597 switch (type) {
7598 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7599 switch (state) {
7600 case AMDGPU_IRQ_STATE_DISABLE:
7601 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7602 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
7603 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
7604 break;
7605 case AMDGPU_IRQ_STATE_ENABLE:
7606 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7607 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
7608 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
7609 break;
7610 default:
7611 break;
7612 }
7613 break;
7614
7615 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7616 switch (state) {
7617 case AMDGPU_IRQ_STATE_DISABLE:
7618 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7619 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
7620 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
7621 break;
7622 case AMDGPU_IRQ_STATE_ENABLE:
7623 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7624 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
7625 WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
7626 break;
7627 default:
7628 break;
7629 }
7630 break;
7631
7632 default:
7633 break;
7634 }
7635 return 0;
7636 }
7637
si_dpm_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)7638 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7639 struct amdgpu_irq_src *source,
7640 struct amdgpu_iv_entry *entry)
7641 {
7642 bool queue_thermal = false;
7643
7644 if (entry == NULL)
7645 return -EINVAL;
7646
7647 switch (entry->src_id) {
7648 case 230: /* thermal low to high */
7649 DRM_DEBUG("IH: thermal low to high\n");
7650 adev->pm.dpm.thermal.high_to_low = false;
7651 queue_thermal = true;
7652 break;
7653 case 231: /* thermal high to low */
7654 DRM_DEBUG("IH: thermal high to low\n");
7655 adev->pm.dpm.thermal.high_to_low = true;
7656 queue_thermal = true;
7657 break;
7658 default:
7659 break;
7660 }
7661
7662 if (queue_thermal)
7663 schedule_work(&adev->pm.dpm.thermal.work);
7664
7665 return 0;
7666 }
7667
si_dpm_late_init(struct amdgpu_ip_block * ip_block)7668 static int si_dpm_late_init(struct amdgpu_ip_block *ip_block)
7669 {
7670 int ret;
7671 struct amdgpu_device *adev = ip_block->adev;
7672
7673 if (!adev->pm.dpm_enabled)
7674 return 0;
7675
7676 ret = si_set_temperature_range(adev);
7677 if (ret)
7678 return ret;
7679 #if 0 //TODO ?
7680 si_dpm_powergate_uvd(adev, true);
7681 #endif
7682 return 0;
7683 }
7684
7685 /**
7686 * si_dpm_init_microcode - load ucode images from disk
7687 *
7688 * @adev: amdgpu_device pointer
7689 *
7690 * Use the firmware interface to load the ucode images into
7691 * the driver (not loaded into hw).
7692 * Returns 0 on success, error on failure.
7693 */
si_dpm_init_microcode(struct amdgpu_device * adev)7694 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7695 {
7696 const char *chip_name;
7697 int err;
7698
7699 DRM_DEBUG("\n");
7700 switch (adev->asic_type) {
7701 case CHIP_TAHITI:
7702 chip_name = "tahiti";
7703 break;
7704 case CHIP_PITCAIRN:
7705 if ((adev->pdev->revision == 0x81) &&
7706 ((adev->pdev->device == 0x6810) ||
7707 (adev->pdev->device == 0x6811)))
7708 chip_name = "pitcairn_k";
7709 else
7710 chip_name = "pitcairn";
7711 break;
7712 case CHIP_VERDE:
7713 if (((adev->pdev->device == 0x6820) &&
7714 ((adev->pdev->revision == 0x81) ||
7715 (adev->pdev->revision == 0x83))) ||
7716 ((adev->pdev->device == 0x6821) &&
7717 ((adev->pdev->revision == 0x83) ||
7718 (adev->pdev->revision == 0x87))) ||
7719 ((adev->pdev->revision == 0x87) &&
7720 ((adev->pdev->device == 0x6823) ||
7721 (adev->pdev->device == 0x682b))))
7722 chip_name = "verde_k";
7723 else
7724 chip_name = "verde";
7725 break;
7726 case CHIP_OLAND:
7727 if (((adev->pdev->revision == 0x81) &&
7728 ((adev->pdev->device == 0x6600) ||
7729 (adev->pdev->device == 0x6604) ||
7730 (adev->pdev->device == 0x6605) ||
7731 (adev->pdev->device == 0x6610))) ||
7732 ((adev->pdev->revision == 0x83) &&
7733 (adev->pdev->device == 0x6610)))
7734 chip_name = "oland_k";
7735 else
7736 chip_name = "oland";
7737 break;
7738 case CHIP_HAINAN:
7739 if (((adev->pdev->revision == 0x81) &&
7740 (adev->pdev->device == 0x6660)) ||
7741 ((adev->pdev->revision == 0x83) &&
7742 ((adev->pdev->device == 0x6660) ||
7743 (adev->pdev->device == 0x6663) ||
7744 (adev->pdev->device == 0x6665) ||
7745 (adev->pdev->device == 0x6667))))
7746 chip_name = "hainan_k";
7747 else if ((adev->pdev->revision == 0xc3) &&
7748 (adev->pdev->device == 0x6665))
7749 chip_name = "banks_k_2";
7750 else
7751 chip_name = "hainan";
7752 break;
7753 default: BUG();
7754 }
7755
7756 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
7757 "amdgpu/%s_smc.bin", chip_name);
7758 if (err) {
7759 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s_smc.bin\"\n",
7760 err, chip_name);
7761 amdgpu_ucode_release(&adev->pm.fw);
7762 }
7763 return err;
7764 }
7765
si_dpm_sw_init(struct amdgpu_ip_block * ip_block)7766 static int si_dpm_sw_init(struct amdgpu_ip_block *ip_block)
7767 {
7768 int ret;
7769 struct amdgpu_device *adev = ip_block->adev;
7770
7771 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
7772 if (ret)
7773 return ret;
7774
7775 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
7776 if (ret)
7777 return ret;
7778
7779 /* default to balanced state */
7780 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7781 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7782 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
7783 adev->pm.default_sclk = adev->clock.default_sclk;
7784 adev->pm.default_mclk = adev->clock.default_mclk;
7785 adev->pm.current_sclk = adev->clock.default_sclk;
7786 adev->pm.current_mclk = adev->clock.default_mclk;
7787 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7788
7789 if (amdgpu_dpm == 0)
7790 return 0;
7791
7792 ret = si_dpm_init_microcode(adev);
7793 if (ret)
7794 return ret;
7795
7796 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7797 ret = si_dpm_init(adev);
7798 if (ret)
7799 goto dpm_failed;
7800 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7801 if (amdgpu_dpm == 1)
7802 amdgpu_pm_print_power_states(adev);
7803 DRM_INFO("amdgpu: dpm initialized\n");
7804
7805 return 0;
7806
7807 dpm_failed:
7808 si_dpm_fini(adev);
7809 DRM_ERROR("amdgpu: dpm initialization failed\n");
7810 return ret;
7811 }
7812
si_dpm_sw_fini(struct amdgpu_ip_block * ip_block)7813 static int si_dpm_sw_fini(struct amdgpu_ip_block *ip_block)
7814 {
7815 struct amdgpu_device *adev = ip_block->adev;
7816
7817 flush_work(&adev->pm.dpm.thermal.work);
7818
7819 si_dpm_fini(adev);
7820
7821 return 0;
7822 }
7823
si_dpm_hw_init(struct amdgpu_ip_block * ip_block)7824 static int si_dpm_hw_init(struct amdgpu_ip_block *ip_block)
7825 {
7826 int ret;
7827
7828 struct amdgpu_device *adev = ip_block->adev;
7829
7830 if (!amdgpu_dpm)
7831 return 0;
7832
7833 mutex_lock(&adev->pm.mutex);
7834 si_dpm_setup_asic(adev);
7835 ret = si_dpm_enable(adev);
7836 if (ret)
7837 adev->pm.dpm_enabled = false;
7838 else
7839 adev->pm.dpm_enabled = true;
7840 amdgpu_legacy_dpm_compute_clocks(adev);
7841 mutex_unlock(&adev->pm.mutex);
7842 return ret;
7843 }
7844
si_dpm_hw_fini(struct amdgpu_ip_block * ip_block)7845 static int si_dpm_hw_fini(struct amdgpu_ip_block *ip_block)
7846 {
7847 struct amdgpu_device *adev = ip_block->adev;
7848
7849 if (adev->pm.dpm_enabled)
7850 si_dpm_disable(adev);
7851
7852 return 0;
7853 }
7854
si_dpm_suspend(struct amdgpu_ip_block * ip_block)7855 static int si_dpm_suspend(struct amdgpu_ip_block *ip_block)
7856 {
7857 struct amdgpu_device *adev = ip_block->adev;
7858
7859 cancel_work_sync(&adev->pm.dpm.thermal.work);
7860
7861 if (adev->pm.dpm_enabled) {
7862 mutex_lock(&adev->pm.mutex);
7863 adev->pm.dpm_enabled = false;
7864 /* disable dpm */
7865 si_dpm_disable(adev);
7866 /* reset the power state */
7867 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7868 mutex_unlock(&adev->pm.mutex);
7869 }
7870
7871 return 0;
7872 }
7873
si_dpm_resume(struct amdgpu_ip_block * ip_block)7874 static int si_dpm_resume(struct amdgpu_ip_block *ip_block)
7875 {
7876 int ret = 0;
7877 struct amdgpu_device *adev = ip_block->adev;
7878
7879 if (!amdgpu_dpm)
7880 return 0;
7881
7882 if (!adev->pm.dpm_enabled) {
7883 /* asic init will reset to the boot state */
7884 mutex_lock(&adev->pm.mutex);
7885 si_dpm_setup_asic(adev);
7886 ret = si_dpm_enable(adev);
7887 if (ret) {
7888 adev->pm.dpm_enabled = false;
7889 } else {
7890 adev->pm.dpm_enabled = true;
7891 amdgpu_legacy_dpm_compute_clocks(adev);
7892 }
7893 mutex_unlock(&adev->pm.mutex);
7894 }
7895
7896 return ret;
7897 }
7898
si_dpm_is_idle(struct amdgpu_ip_block * ip_block)7899 static bool si_dpm_is_idle(struct amdgpu_ip_block *ip_block)
7900 {
7901 /* XXX */
7902 return true;
7903 }
7904
si_dpm_wait_for_idle(struct amdgpu_ip_block * ip_block)7905 static int si_dpm_wait_for_idle(struct amdgpu_ip_block *ip_block)
7906 {
7907 /* XXX */
7908 return 0;
7909 }
7910
si_dpm_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)7911 static int si_dpm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
7912 enum amd_clockgating_state state)
7913 {
7914 return 0;
7915 }
7916
si_dpm_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)7917 static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
7918 enum amd_powergating_state state)
7919 {
7920 return 0;
7921 }
7922
7923 /* get temperature in millidegrees */
si_dpm_get_temp(void * handle)7924 static int si_dpm_get_temp(void *handle)
7925 {
7926 u32 temp;
7927 int actual_temp = 0;
7928 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7929
7930 temp = (RREG32(mmCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
7931 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
7932
7933 if (temp & 0x200)
7934 actual_temp = 255;
7935 else
7936 actual_temp = temp & 0x1ff;
7937
7938 actual_temp = (actual_temp * 1000);
7939
7940 return actual_temp;
7941 }
7942
si_dpm_get_sclk(void * handle,bool low)7943 static u32 si_dpm_get_sclk(void *handle, bool low)
7944 {
7945 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7946 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7947 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7948
7949 if (low)
7950 return requested_state->performance_levels[0].sclk;
7951 else
7952 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7953 }
7954
si_dpm_get_mclk(void * handle,bool low)7955 static u32 si_dpm_get_mclk(void *handle, bool low)
7956 {
7957 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7958 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7959 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7960
7961 if (low)
7962 return requested_state->performance_levels[0].mclk;
7963 else
7964 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7965 }
7966
si_dpm_print_power_state(void * handle,void * current_ps)7967 static void si_dpm_print_power_state(void *handle,
7968 void *current_ps)
7969 {
7970 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7971 struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
7972 struct si_ps *ps = si_get_ps(rps);
7973 struct rv7xx_pl *pl;
7974 int i;
7975
7976 amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2);
7977 amdgpu_dpm_dbg_print_cap_info(adev, rps->caps);
7978 drm_dbg(adev_to_drm(adev), "\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7979 drm_dbg(adev_to_drm(adev), "\tvce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk);
7980 for (i = 0; i < ps->performance_level_count; i++) {
7981 pl = &ps->performance_levels[i];
7982 drm_dbg(adev_to_drm(adev), "\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7983 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7984 }
7985 amdgpu_dpm_dbg_print_ps_status(adev, rps);
7986 }
7987
si_dpm_early_init(struct amdgpu_ip_block * ip_block)7988 static int si_dpm_early_init(struct amdgpu_ip_block *ip_block)
7989 {
7990
7991 struct amdgpu_device *adev = ip_block->adev;
7992
7993 adev->powerplay.pp_funcs = &si_dpm_funcs;
7994 adev->powerplay.pp_handle = adev;
7995 si_dpm_set_irq_funcs(adev);
7996 return 0;
7997 }
7998
si_are_power_levels_equal(const struct rv7xx_pl * si_cpl1,const struct rv7xx_pl * si_cpl2)7999 static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1,
8000 const struct rv7xx_pl *si_cpl2)
8001 {
8002 return ((si_cpl1->mclk == si_cpl2->mclk) &&
8003 (si_cpl1->sclk == si_cpl2->sclk) &&
8004 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
8005 (si_cpl1->vddc == si_cpl2->vddc) &&
8006 (si_cpl1->vddci == si_cpl2->vddci));
8007 }
8008
si_check_state_equal(void * handle,void * current_ps,void * request_ps,bool * equal)8009 static int si_check_state_equal(void *handle,
8010 void *current_ps,
8011 void *request_ps,
8012 bool *equal)
8013 {
8014 struct si_ps *si_cps;
8015 struct si_ps *si_rps;
8016 int i;
8017 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
8018 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
8019 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8020
8021 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
8022 return -EINVAL;
8023
8024 si_cps = si_get_ps((struct amdgpu_ps *)cps);
8025 si_rps = si_get_ps((struct amdgpu_ps *)rps);
8026
8027 if (si_cps == NULL) {
8028 printk("si_cps is NULL\n");
8029 *equal = false;
8030 return 0;
8031 }
8032
8033 if (si_cps->performance_level_count != si_rps->performance_level_count) {
8034 *equal = false;
8035 return 0;
8036 }
8037
8038 for (i = 0; i < si_cps->performance_level_count; i++) {
8039 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
8040 &(si_rps->performance_levels[i]))) {
8041 *equal = false;
8042 return 0;
8043 }
8044 }
8045
8046 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
8047 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
8048 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
8049
8050 return 0;
8051 }
8052
si_dpm_read_sensor(void * handle,int idx,void * value,int * size)8053 static int si_dpm_read_sensor(void *handle, int idx,
8054 void *value, int *size)
8055 {
8056 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8057 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
8058 struct amdgpu_ps *rps = &eg_pi->current_rps;
8059 struct si_ps *ps = si_get_ps(rps);
8060 uint32_t sclk, mclk;
8061 u32 pl_index =
8062 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >>
8063 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT;
8064
8065 /* size must be at least 4 bytes for all sensors */
8066 if (*size < 4)
8067 return -EINVAL;
8068
8069 switch (idx) {
8070 case AMDGPU_PP_SENSOR_GFX_SCLK:
8071 if (pl_index < ps->performance_level_count) {
8072 sclk = ps->performance_levels[pl_index].sclk;
8073 *((uint32_t *)value) = sclk;
8074 *size = 4;
8075 return 0;
8076 }
8077 return -EINVAL;
8078 case AMDGPU_PP_SENSOR_GFX_MCLK:
8079 if (pl_index < ps->performance_level_count) {
8080 mclk = ps->performance_levels[pl_index].mclk;
8081 *((uint32_t *)value) = mclk;
8082 *size = 4;
8083 return 0;
8084 }
8085 return -EINVAL;
8086 case AMDGPU_PP_SENSOR_GPU_TEMP:
8087 *((uint32_t *)value) = si_dpm_get_temp(adev);
8088 *size = 4;
8089 return 0;
8090 default:
8091 return -EOPNOTSUPP;
8092 }
8093 }
8094
8095 static const struct amd_ip_funcs si_dpm_ip_funcs = {
8096 .name = "si_dpm",
8097 .early_init = si_dpm_early_init,
8098 .late_init = si_dpm_late_init,
8099 .sw_init = si_dpm_sw_init,
8100 .sw_fini = si_dpm_sw_fini,
8101 .hw_init = si_dpm_hw_init,
8102 .hw_fini = si_dpm_hw_fini,
8103 .suspend = si_dpm_suspend,
8104 .resume = si_dpm_resume,
8105 .is_idle = si_dpm_is_idle,
8106 .wait_for_idle = si_dpm_wait_for_idle,
8107 .set_clockgating_state = si_dpm_set_clockgating_state,
8108 .set_powergating_state = si_dpm_set_powergating_state,
8109 };
8110
8111 const struct amdgpu_ip_block_version si_smu_ip_block =
8112 {
8113 .type = AMD_IP_BLOCK_TYPE_SMC,
8114 .major = 6,
8115 .minor = 0,
8116 .rev = 0,
8117 .funcs = &si_dpm_ip_funcs,
8118 };
8119
8120 static const struct amd_pm_funcs si_dpm_funcs = {
8121 .pre_set_power_state = &si_dpm_pre_set_power_state,
8122 .set_power_state = &si_dpm_set_power_state,
8123 .post_set_power_state = &si_dpm_post_set_power_state,
8124 .display_configuration_changed = &si_dpm_display_configuration_changed,
8125 .get_sclk = &si_dpm_get_sclk,
8126 .get_mclk = &si_dpm_get_mclk,
8127 .print_power_state = &si_dpm_print_power_state,
8128 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8129 .force_performance_level = &si_dpm_force_performance_level,
8130 .vblank_too_short = &si_dpm_vblank_too_short,
8131 .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8132 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8133 .set_fan_speed_pwm = &si_dpm_set_fan_speed_pwm,
8134 .get_fan_speed_pwm = &si_dpm_get_fan_speed_pwm,
8135 .check_state_equal = &si_check_state_equal,
8136 .get_vce_clock_state = amdgpu_get_vce_clock_state,
8137 .read_sensor = &si_dpm_read_sensor,
8138 .pm_compute_clocks = amdgpu_legacy_dpm_compute_clocks,
8139 };
8140
8141 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8142 .set = si_dpm_set_interrupt_state,
8143 .process = si_dpm_process_interrupt,
8144 };
8145
si_dpm_set_irq_funcs(struct amdgpu_device * adev)8146 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8147 {
8148 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8149 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8150 }
8151
8152