1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Hisilicon Hibmc SoC drm driver
3 *
4 * Based on the bochs drm driver.
5 *
6 * Copyright (c) 2016 Huawei Limited.
7 *
8 * Author:
9 * Rongrong Zou <zourongrong@huawei.com>
10 * Rongrong Zou <zourongrong@gmail.com>
11 * Jianhua Li <lijianhua@huawei.com>
12 */
13
14 #include <linux/aperture.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17
18 #include <drm/clients/drm_client_setup.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_drv.h>
21 #include <drm/drm_fbdev_ttm.h>
22 #include <drm/drm_gem_framebuffer_helper.h>
23 #include <drm/drm_gem_vram_helper.h>
24 #include <drm/drm_managed.h>
25 #include <drm/drm_module.h>
26 #include <drm/drm_vblank.h>
27
28 #include "hibmc_drm_drv.h"
29 #include "hibmc_drm_regs.h"
30
31 #include "dp/dp_reg.h"
32
33 DEFINE_DRM_GEM_FOPS(hibmc_fops);
34
35 static const char *g_irqs_names_map[HIBMC_MAX_VECTORS] = { "hibmc-vblank", "hibmc-hpd" };
36
hibmc_interrupt(int irq,void * arg)37 static irqreturn_t hibmc_interrupt(int irq, void *arg)
38 {
39 struct drm_device *dev = (struct drm_device *)arg;
40 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
41 u32 status;
42
43 status = readl(priv->mmio + HIBMC_RAW_INTERRUPT);
44
45 if (status & HIBMC_RAW_INTERRUPT_VBLANK(1)) {
46 writel(HIBMC_RAW_INTERRUPT_VBLANK(1),
47 priv->mmio + HIBMC_RAW_INTERRUPT);
48 drm_handle_vblank(dev, 0);
49 }
50
51 return IRQ_HANDLED;
52 }
53
hibmc_dp_interrupt(int irq,void * arg)54 static irqreturn_t hibmc_dp_interrupt(int irq, void *arg)
55 {
56 struct drm_device *dev = (struct drm_device *)arg;
57 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
58 u32 status;
59
60 status = readl(priv->mmio + HIBMC_DP_INTSTAT);
61 if (status) {
62 priv->dp.irq_status = status;
63 writel(status, priv->mmio + HIBMC_DP_INTCLR);
64 return IRQ_WAKE_THREAD;
65 }
66
67 return IRQ_HANDLED;
68 }
69
hibmc_dumb_create(struct drm_file * file,struct drm_device * dev,struct drm_mode_create_dumb * args)70 static int hibmc_dumb_create(struct drm_file *file, struct drm_device *dev,
71 struct drm_mode_create_dumb *args)
72 {
73 return drm_gem_vram_fill_create_dumb(file, dev, 0, 128, args);
74 }
75
76 static const struct drm_driver hibmc_driver = {
77 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
78 .fops = &hibmc_fops,
79 .name = "hibmc",
80 .desc = "hibmc drm driver",
81 .major = 1,
82 .minor = 0,
83 .debugfs_init = drm_vram_mm_debugfs_init,
84 .dumb_create = hibmc_dumb_create,
85 .dumb_map_offset = drm_gem_ttm_dumb_map_offset,
86 DRM_FBDEV_TTM_DRIVER_OPS,
87 };
88
hibmc_pm_suspend(struct device * dev)89 static int __maybe_unused hibmc_pm_suspend(struct device *dev)
90 {
91 struct drm_device *drm_dev = dev_get_drvdata(dev);
92
93 return drm_mode_config_helper_suspend(drm_dev);
94 }
95
hibmc_pm_resume(struct device * dev)96 static int __maybe_unused hibmc_pm_resume(struct device *dev)
97 {
98 struct drm_device *drm_dev = dev_get_drvdata(dev);
99
100 return drm_mode_config_helper_resume(drm_dev);
101 }
102
103 static const struct dev_pm_ops hibmc_pm_ops = {
104 SET_SYSTEM_SLEEP_PM_OPS(hibmc_pm_suspend,
105 hibmc_pm_resume)
106 };
107
108 static const struct drm_mode_config_funcs hibmc_mode_funcs = {
109 .mode_valid = drm_vram_helper_mode_valid,
110 .atomic_check = drm_atomic_helper_check,
111 .atomic_commit = drm_atomic_helper_commit,
112 .fb_create = drm_gem_fb_create,
113 };
114
hibmc_kms_init(struct hibmc_drm_private * priv)115 static int hibmc_kms_init(struct hibmc_drm_private *priv)
116 {
117 struct drm_device *dev = &priv->dev;
118 struct drm_encoder *encoder;
119 u32 clone_mask = 0;
120 int ret;
121
122 ret = drmm_mode_config_init(dev);
123 if (ret)
124 return ret;
125
126 dev->mode_config.min_width = 0;
127 dev->mode_config.min_height = 0;
128 dev->mode_config.max_width = 1920;
129 dev->mode_config.max_height = 1200;
130
131 dev->mode_config.preferred_depth = 24;
132 dev->mode_config.prefer_shadow = 1;
133
134 dev->mode_config.funcs = (void *)&hibmc_mode_funcs;
135
136 ret = hibmc_de_init(priv);
137 if (ret) {
138 drm_err(dev, "failed to init de: %d\n", ret);
139 return ret;
140 }
141
142 /*
143 * If the serdes reg is readable and is not equal to 0,
144 * DP block exists and initializes it.
145 */
146 ret = readl(priv->mmio + HIBMC_DP_HOST_SERDES_CTRL);
147 if (ret) {
148 ret = hibmc_dp_init(priv);
149 if (ret)
150 drm_err(dev, "failed to init dp: %d\n", ret);
151 }
152
153 ret = hibmc_vdac_init(priv);
154 if (ret) {
155 drm_err(dev, "failed to init vdac: %d\n", ret);
156 return ret;
157 }
158
159 drm_for_each_encoder(encoder, dev)
160 clone_mask |= drm_encoder_mask(encoder);
161
162 drm_for_each_encoder(encoder, dev)
163 encoder->possible_clones = clone_mask;
164
165 return 0;
166 }
167
168 /*
169 * It can operate in one of three modes: 0, 1 or Sleep.
170 */
hibmc_set_power_mode(struct hibmc_drm_private * priv,u32 power_mode)171 void hibmc_set_power_mode(struct hibmc_drm_private *priv, u32 power_mode)
172 {
173 u32 control_value = 0;
174 void __iomem *mmio = priv->mmio;
175 u32 input = 1;
176
177 if (power_mode > HIBMC_PW_MODE_CTL_MODE_SLEEP)
178 return;
179
180 if (power_mode == HIBMC_PW_MODE_CTL_MODE_SLEEP)
181 input = 0;
182
183 control_value = readl(mmio + HIBMC_POWER_MODE_CTRL);
184 control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK |
185 HIBMC_PW_MODE_CTL_OSC_INPUT_MASK);
186 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode);
187 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input);
188 writel(control_value, mmio + HIBMC_POWER_MODE_CTRL);
189 }
190
hibmc_set_current_gate(struct hibmc_drm_private * priv,unsigned int gate)191 void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate)
192 {
193 u32 gate_reg;
194 u32 mode;
195 void __iomem *mmio = priv->mmio;
196
197 /* Get current power mode. */
198 mode = (readl(mmio + HIBMC_POWER_MODE_CTRL) &
199 HIBMC_PW_MODE_CTL_MODE_MASK) >> HIBMC_PW_MODE_CTL_MODE_SHIFT;
200
201 switch (mode) {
202 case HIBMC_PW_MODE_CTL_MODE_MODE0:
203 gate_reg = HIBMC_MODE0_GATE;
204 break;
205
206 case HIBMC_PW_MODE_CTL_MODE_MODE1:
207 gate_reg = HIBMC_MODE1_GATE;
208 break;
209
210 default:
211 gate_reg = HIBMC_MODE0_GATE;
212 break;
213 }
214 writel(gate, mmio + gate_reg);
215 }
216
hibmc_hw_config(struct hibmc_drm_private * priv)217 static void hibmc_hw_config(struct hibmc_drm_private *priv)
218 {
219 u32 reg;
220
221 /* On hardware reset, power mode 0 is default. */
222 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
223
224 /* Enable display power gate & LOCALMEM power gate*/
225 reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
226 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
227 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
228 reg |= HIBMC_CURR_GATE_DISPLAY(1);
229 reg |= HIBMC_CURR_GATE_LOCALMEM(1);
230
231 hibmc_set_current_gate(priv, reg);
232
233 /*
234 * Reset the memory controller. If the memory controller
235 * is not reset in chip,the system might hang when sw accesses
236 * the memory.The memory should be resetted after
237 * changing the MXCLK.
238 */
239 reg = readl(priv->mmio + HIBMC_MISC_CTRL);
240 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
241 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0);
242 writel(reg, priv->mmio + HIBMC_MISC_CTRL);
243
244 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
245 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1);
246
247 writel(reg, priv->mmio + HIBMC_MISC_CTRL);
248 }
249
hibmc_hw_map(struct hibmc_drm_private * priv)250 static int hibmc_hw_map(struct hibmc_drm_private *priv)
251 {
252 struct drm_device *dev = &priv->dev;
253 struct pci_dev *pdev = to_pci_dev(dev->dev);
254 resource_size_t ioaddr, iosize;
255
256 ioaddr = pci_resource_start(pdev, 1);
257 iosize = pci_resource_len(pdev, 1);
258 priv->mmio = devm_ioremap(dev->dev, ioaddr, iosize);
259 if (!priv->mmio) {
260 drm_err(dev, "Cannot map mmio region\n");
261 return -ENOMEM;
262 }
263
264 return 0;
265 }
266
hibmc_hw_init(struct hibmc_drm_private * priv)267 static int hibmc_hw_init(struct hibmc_drm_private *priv)
268 {
269 int ret;
270
271 ret = hibmc_hw_map(priv);
272 if (ret)
273 return ret;
274
275 hibmc_hw_config(priv);
276
277 return 0;
278 }
279
hibmc_unload(struct drm_device * dev)280 static void hibmc_unload(struct drm_device *dev)
281 {
282 drm_atomic_helper_shutdown(dev);
283 }
284
hibmc_msi_init(struct drm_device * dev)285 static int hibmc_msi_init(struct drm_device *dev)
286 {
287 struct pci_dev *pdev = to_pci_dev(dev->dev);
288 int valid_irq_num;
289 int irq;
290 int ret;
291
292 ret = pci_alloc_irq_vectors(pdev, HIBMC_MIN_VECTORS,
293 HIBMC_MAX_VECTORS, PCI_IRQ_MSI);
294 if (ret < 0) {
295 drm_err(dev, "enabling MSI failed: %d\n", ret);
296 return ret;
297 }
298
299 valid_irq_num = ret;
300
301 for (int i = 0; i < valid_irq_num; i++) {
302 irq = pci_irq_vector(pdev, i);
303
304 if (i)
305 /* PCI devices require shared interrupts. */
306 ret = devm_request_threaded_irq(&pdev->dev, irq,
307 hibmc_dp_interrupt,
308 hibmc_dp_hpd_isr,
309 IRQF_SHARED, g_irqs_names_map[i], dev);
310 else
311 ret = devm_request_irq(&pdev->dev, irq, hibmc_interrupt,
312 IRQF_SHARED, g_irqs_names_map[i], dev);
313 if (ret) {
314 drm_err(dev, "install irq failed: %d\n", ret);
315 return ret;
316 }
317 }
318
319 return 0;
320 }
321
hibmc_load(struct drm_device * dev)322 static int hibmc_load(struct drm_device *dev)
323 {
324 struct pci_dev *pdev = to_pci_dev(dev->dev);
325 struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
326 int ret;
327
328 ret = hibmc_hw_init(priv);
329 if (ret)
330 return ret;
331
332 ret = drmm_vram_helper_init(dev, pci_resource_start(pdev, 0),
333 pci_resource_len(pdev, 0));
334 if (ret) {
335 drm_err(dev, "Error initializing VRAM MM; %d\n", ret);
336 return ret;
337 }
338
339 ret = hibmc_kms_init(priv);
340 if (ret)
341 goto err;
342
343 ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
344 if (ret) {
345 drm_err(dev, "failed to initialize vblank: %d\n", ret);
346 goto err;
347 }
348
349 ret = hibmc_msi_init(dev);
350 if (ret) {
351 drm_err(dev, "hibmc msi init failed, ret:%d\n", ret);
352 goto err;
353 }
354
355 /* reset all the states of crtc/plane/encoder/connector */
356 drm_mode_config_reset(dev);
357
358 return 0;
359
360 err:
361 hibmc_unload(dev);
362 drm_err(dev, "failed to initialize drm driver: %d\n", ret);
363 return ret;
364 }
365
hibmc_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)366 static int hibmc_pci_probe(struct pci_dev *pdev,
367 const struct pci_device_id *ent)
368 {
369 struct hibmc_drm_private *priv;
370 struct drm_device *dev;
371 int ret;
372
373 ret = aperture_remove_conflicting_pci_devices(pdev, hibmc_driver.name);
374 if (ret)
375 return ret;
376
377 priv = devm_drm_dev_alloc(&pdev->dev, &hibmc_driver,
378 struct hibmc_drm_private, dev);
379 if (IS_ERR(priv)) {
380 DRM_ERROR("failed to allocate drm_device\n");
381 return PTR_ERR(priv);
382 }
383
384 dev = &priv->dev;
385 pci_set_drvdata(pdev, dev);
386
387 ret = pcim_enable_device(pdev);
388 if (ret) {
389 drm_err(dev, "failed to enable pci device: %d\n", ret);
390 goto err_return;
391 }
392
393 pci_set_master(pdev);
394
395 ret = hibmc_load(dev);
396 if (ret) {
397 drm_err(dev, "failed to load hibmc: %d\n", ret);
398 goto err_return;
399 }
400
401 ret = drm_dev_register(dev, 0);
402 if (ret) {
403 drm_err(dev, "failed to register drv for userspace access: %d\n",
404 ret);
405 goto err_unload;
406 }
407
408 drm_client_setup(dev, NULL);
409
410 return 0;
411
412 err_unload:
413 hibmc_unload(dev);
414 err_return:
415 return ret;
416 }
417
hibmc_pci_remove(struct pci_dev * pdev)418 static void hibmc_pci_remove(struct pci_dev *pdev)
419 {
420 struct drm_device *dev = pci_get_drvdata(pdev);
421
422 drm_dev_unregister(dev);
423 hibmc_unload(dev);
424 }
425
hibmc_pci_shutdown(struct pci_dev * pdev)426 static void hibmc_pci_shutdown(struct pci_dev *pdev)
427 {
428 hibmc_pci_remove(pdev);
429 }
430
431 static const struct pci_device_id hibmc_pci_table[] = {
432 { PCI_VDEVICE(HUAWEI, 0x1711) },
433 {0,}
434 };
435
436 static struct pci_driver hibmc_pci_driver = {
437 .name = "hibmc-drm",
438 .id_table = hibmc_pci_table,
439 .probe = hibmc_pci_probe,
440 .remove = hibmc_pci_remove,
441 .shutdown = hibmc_pci_shutdown,
442 .driver.pm = &hibmc_pm_ops,
443 };
444
445 drm_module_pci_driver(hibmc_pci_driver);
446
447 MODULE_DEVICE_TABLE(pci, hibmc_pci_table);
448 MODULE_AUTHOR("RongrongZou <zourongrong@huawei.com>");
449 MODULE_DESCRIPTION("DRM Driver for Hisilicon Hibmc");
450 MODULE_LICENSE("GPL v2");
451