1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 struct abm_save_restore; 50 51 /* forward declaration */ 52 struct aux_payload; 53 struct set_config_cmd_payload; 54 struct dmub_notification; 55 56 #define DC_VER "3.2.334" 57 58 /** 59 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC 60 */ 61 #define MAX_SURFACES 4 62 /** 63 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW 64 */ 65 #define MAX_PLANES 6 66 #define MAX_STREAMS 6 67 #define MIN_VIEWPORT_SIZE 12 68 #define MAX_NUM_EDP 2 69 #define MAX_HOST_ROUTERS_NUM 3 70 #define MAX_DPIA_PER_HOST_ROUTER 2 71 72 /* Display Core Interfaces */ 73 struct dc_versions { 74 const char *dc_ver; 75 struct dmcu_version dmcu_version; 76 }; 77 78 enum dp_protocol_version { 79 DP_VERSION_1_4 = 0, 80 DP_VERSION_2_1, 81 DP_VERSION_UNKNOWN, 82 }; 83 84 enum dc_plane_type { 85 DC_PLANE_TYPE_INVALID, 86 DC_PLANE_TYPE_DCE_RGB, 87 DC_PLANE_TYPE_DCE_UNDERLAY, 88 DC_PLANE_TYPE_DCN_UNIVERSAL, 89 }; 90 91 // Sizes defined as multiples of 64KB 92 enum det_size { 93 DET_SIZE_DEFAULT = 0, 94 DET_SIZE_192KB = 3, 95 DET_SIZE_256KB = 4, 96 DET_SIZE_320KB = 5, 97 DET_SIZE_384KB = 6 98 }; 99 100 101 struct dc_plane_cap { 102 enum dc_plane_type type; 103 uint32_t per_pixel_alpha : 1; 104 struct { 105 uint32_t argb8888 : 1; 106 uint32_t nv12 : 1; 107 uint32_t fp16 : 1; 108 uint32_t p010 : 1; 109 uint32_t ayuv : 1; 110 } pixel_format_support; 111 // max upscaling factor x1000 112 // upscaling factors are always >= 1 113 // for example, 1080p -> 8K is 4.0, or 4000 raw value 114 struct { 115 uint32_t argb8888; 116 uint32_t nv12; 117 uint32_t fp16; 118 } max_upscale_factor; 119 // max downscale factor x1000 120 // downscale factors are always <= 1 121 // for example, 8K -> 1080p is 0.25, or 250 raw value 122 struct { 123 uint32_t argb8888; 124 uint32_t nv12; 125 uint32_t fp16; 126 } max_downscale_factor; 127 // minimal width/height 128 uint32_t min_width; 129 uint32_t min_height; 130 }; 131 132 /** 133 * DOC: color-management-caps 134 * 135 * **Color management caps (DPP and MPC)** 136 * 137 * Modules/color calculates various color operations which are translated to 138 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 139 * DCN1, every new generation comes with fairly major differences in color 140 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 141 * decide mapping to HW block based on logical capabilities. 142 */ 143 144 /** 145 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 146 * @srgb: RGB color space transfer func 147 * @bt2020: BT.2020 transfer func 148 * @gamma2_2: standard gamma 149 * @pq: perceptual quantizer transfer function 150 * @hlg: hybrid log–gamma transfer function 151 */ 152 struct rom_curve_caps { 153 uint16_t srgb : 1; 154 uint16_t bt2020 : 1; 155 uint16_t gamma2_2 : 1; 156 uint16_t pq : 1; 157 uint16_t hlg : 1; 158 }; 159 160 /** 161 * struct dpp_color_caps - color pipeline capabilities for display pipe and 162 * plane blocks 163 * 164 * @dcn_arch: all DCE generations treated the same 165 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 166 * just plain 256-entry lookup 167 * @icsc: input color space conversion 168 * @dgam_ram: programmable degamma LUT 169 * @post_csc: post color space conversion, before gamut remap 170 * @gamma_corr: degamma correction 171 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 172 * with MPC by setting mpc:shared_3d_lut flag 173 * @ogam_ram: programmable out/blend gamma LUT 174 * @ocsc: output color space conversion 175 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 176 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 177 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 178 * 179 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 180 */ 181 struct dpp_color_caps { 182 uint16_t dcn_arch : 1; 183 uint16_t input_lut_shared : 1; 184 uint16_t icsc : 1; 185 uint16_t dgam_ram : 1; 186 uint16_t post_csc : 1; 187 uint16_t gamma_corr : 1; 188 uint16_t hw_3d_lut : 1; 189 uint16_t ogam_ram : 1; 190 uint16_t ocsc : 1; 191 uint16_t dgam_rom_for_yuv : 1; 192 struct rom_curve_caps dgam_rom_caps; 193 struct rom_curve_caps ogam_rom_caps; 194 }; 195 196 /** 197 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 198 * plane combined blocks 199 * 200 * @gamut_remap: color transformation matrix 201 * @ogam_ram: programmable out gamma LUT 202 * @ocsc: output color space conversion matrix 203 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 204 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 205 * instance 206 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 207 */ 208 struct mpc_color_caps { 209 uint16_t gamut_remap : 1; 210 uint16_t ogam_ram : 1; 211 uint16_t ocsc : 1; 212 uint16_t num_3dluts : 3; 213 uint16_t shared_3d_lut:1; 214 struct rom_curve_caps ogam_rom_caps; 215 }; 216 217 /** 218 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 219 * @dpp: color pipes caps for DPP 220 * @mpc: color pipes caps for MPC 221 */ 222 struct dc_color_caps { 223 struct dpp_color_caps dpp; 224 struct mpc_color_caps mpc; 225 }; 226 227 struct dc_dmub_caps { 228 bool psr; 229 bool mclk_sw; 230 bool subvp_psr; 231 bool gecc_enable; 232 uint8_t fams_ver; 233 bool aux_backlight_support; 234 }; 235 236 struct dc_scl_caps { 237 bool sharpener_support; 238 }; 239 240 struct dc_caps { 241 uint32_t max_streams; 242 uint32_t max_links; 243 uint32_t max_audios; 244 uint32_t max_slave_planes; 245 uint32_t max_slave_yuv_planes; 246 uint32_t max_slave_rgb_planes; 247 uint32_t max_planes; 248 uint32_t max_downscale_ratio; 249 uint32_t i2c_speed_in_khz; 250 uint32_t i2c_speed_in_khz_hdcp; 251 uint32_t dmdata_alloc_size; 252 unsigned int max_cursor_size; 253 unsigned int max_buffered_cursor_size; 254 unsigned int max_video_width; 255 /* 256 * max video plane width that can be safely assumed to be always 257 * supported by single DPP pipe. 258 */ 259 unsigned int max_optimizable_video_width; 260 unsigned int min_horizontal_blanking_period; 261 int linear_pitch_alignment; 262 bool dcc_const_color; 263 bool dynamic_audio; 264 bool is_apu; 265 bool dual_link_dvi; 266 bool post_blend_color_processing; 267 bool force_dp_tps4_for_cp2520; 268 bool disable_dp_clk_share; 269 bool psp_setup_panel_mode; 270 bool extended_aux_timeout_support; 271 bool dmcub_support; 272 bool zstate_support; 273 bool ips_support; 274 uint32_t num_of_internal_disp; 275 enum dp_protocol_version max_dp_protocol_version; 276 unsigned int mall_size_per_mem_channel; 277 unsigned int mall_size_total; 278 unsigned int cursor_cache_size; 279 struct dc_plane_cap planes[MAX_PLANES]; 280 struct dc_color_caps color; 281 struct dc_dmub_caps dmub_caps; 282 bool dp_hpo; 283 bool dp_hdmi21_pcon_support; 284 bool edp_dsc_support; 285 bool vbios_lttpr_aware; 286 bool vbios_lttpr_enable; 287 bool fused_io_supported; 288 uint32_t max_otg_num; 289 uint32_t max_cab_allocation_bytes; 290 uint32_t cache_line_size; 291 uint32_t cache_num_ways; 292 uint16_t subvp_fw_processing_delay_us; 293 uint8_t subvp_drr_max_vblank_margin_us; 294 uint16_t subvp_prefetch_end_to_mall_start_us; 295 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 296 uint16_t subvp_pstate_allow_width_us; 297 uint16_t subvp_vertical_int_margin_us; 298 bool seamless_odm; 299 uint32_t max_v_total; 300 bool vtotal_limited_by_fp2; 301 uint32_t max_disp_clock_khz_at_vmin; 302 uint8_t subvp_drr_vblank_start_margin_us; 303 bool cursor_not_scaled; 304 bool dcmode_power_limits_present; 305 bool sequential_ono; 306 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 307 uint32_t dcc_plane_width_limit; 308 struct dc_scl_caps scl_caps; 309 uint8_t num_of_host_routers; 310 uint8_t num_of_dpias_per_host_router; 311 }; 312 313 struct dc_bug_wa { 314 bool no_connect_phy_config; 315 bool dedcn20_305_wa; 316 bool skip_clock_update; 317 bool lt_early_cr_pattern; 318 struct { 319 uint8_t uclk : 1; 320 uint8_t fclk : 1; 321 uint8_t dcfclk : 1; 322 uint8_t dcfclk_ds: 1; 323 } clock_update_disable_mask; 324 bool skip_psr_ips_crtc_disable; 325 }; 326 struct dc_dcc_surface_param { 327 struct dc_size surface_size; 328 enum surface_pixel_format format; 329 unsigned int plane0_pitch; 330 struct dc_size plane1_size; 331 unsigned int plane1_pitch; 332 union { 333 enum swizzle_mode_values swizzle_mode; 334 enum swizzle_mode_addr3_values swizzle_mode_addr3; 335 }; 336 enum dc_scan_direction scan; 337 }; 338 339 struct dc_dcc_setting { 340 unsigned int max_compressed_blk_size; 341 unsigned int max_uncompressed_blk_size; 342 bool independent_64b_blks; 343 //These bitfields to be used starting with DCN 3.0 344 struct { 345 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 346 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 347 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 348 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 349 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 350 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 351 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 352 } dcc_controls; 353 }; 354 355 struct dc_surface_dcc_cap { 356 union { 357 struct { 358 struct dc_dcc_setting rgb; 359 } grph; 360 361 struct { 362 struct dc_dcc_setting luma; 363 struct dc_dcc_setting chroma; 364 } video; 365 }; 366 367 bool capable; 368 bool const_color_support; 369 }; 370 371 struct dc_static_screen_params { 372 struct { 373 bool force_trigger; 374 bool cursor_update; 375 bool surface_update; 376 bool overlay_update; 377 } triggers; 378 unsigned int num_frames; 379 }; 380 381 382 /* Surface update type is used by dc_update_surfaces_and_stream 383 * The update type is determined at the very beginning of the function based 384 * on parameters passed in and decides how much programming (or updating) is 385 * going to be done during the call. 386 * 387 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 388 * logical calculations or hardware register programming. This update MUST be 389 * ISR safe on windows. Currently fast update will only be used to flip surface 390 * address. 391 * 392 * UPDATE_TYPE_MED is used for slower updates which require significant hw 393 * re-programming however do not affect bandwidth consumption or clock 394 * requirements. At present, this is the level at which front end updates 395 * that do not require us to run bw_calcs happen. These are in/out transfer func 396 * updates, viewport offset changes, recout size changes and pixel depth changes. 397 * This update can be done at ISR, but we want to minimize how often this happens. 398 * 399 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 400 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 401 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 402 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 403 * a full update. This cannot be done at ISR level and should be a rare event. 404 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 405 * underscan we don't expect to see this call at all. 406 */ 407 408 enum surface_update_type { 409 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 410 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 411 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 412 }; 413 414 /* Forward declaration*/ 415 struct dc; 416 struct dc_plane_state; 417 struct dc_state; 418 419 struct dc_cap_funcs { 420 bool (*get_dcc_compression_cap)(const struct dc *dc, 421 const struct dc_dcc_surface_param *input, 422 struct dc_surface_dcc_cap *output); 423 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 424 }; 425 426 struct link_training_settings; 427 428 union allow_lttpr_non_transparent_mode { 429 struct { 430 bool DP1_4A : 1; 431 bool DP2_0 : 1; 432 } bits; 433 unsigned char raw; 434 }; 435 436 /* Structure to hold configuration flags set by dm at dc creation. */ 437 struct dc_config { 438 bool gpu_vm_support; 439 bool disable_disp_pll_sharing; 440 bool fbc_support; 441 bool disable_fractional_pwm; 442 bool allow_seamless_boot_optimization; 443 bool seamless_boot_edp_requested; 444 bool edp_not_connected; 445 bool edp_no_power_sequencing; 446 bool force_enum_edp; 447 bool forced_clocks; 448 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 449 bool multi_mon_pp_mclk_switch; 450 bool disable_dmcu; 451 bool enable_4to1MPC; 452 bool enable_windowed_mpo_odm; 453 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 454 uint32_t allow_edp_hotplug_detection; 455 bool skip_riommu_prefetch_wa; 456 bool clamp_min_dcfclk; 457 uint64_t vblank_alignment_dto_params; 458 uint8_t vblank_alignment_max_frame_time_diff; 459 bool is_asymmetric_memory; 460 bool is_single_rank_dimm; 461 bool is_vmin_only_asic; 462 bool use_spl; 463 bool prefer_easf; 464 bool use_pipe_ctx_sync_logic; 465 bool ignore_dpref_ss; 466 bool enable_mipi_converter_optimization; 467 bool use_default_clock_table; 468 bool force_bios_enable_lttpr; 469 uint8_t force_bios_fixed_vs; 470 int sdpif_request_limit_words_per_umc; 471 bool dc_mode_clk_limit_support; 472 bool EnableMinDispClkODM; 473 bool enable_auto_dpm_test_logs; 474 unsigned int disable_ips; 475 unsigned int disable_ips_in_vpb; 476 bool disable_ips_in_dpms_off; 477 bool usb4_bw_alloc_support; 478 bool allow_0_dtb_clk; 479 bool use_assr_psp_message; 480 bool support_edp0_on_dp1; 481 unsigned int enable_fpo_flicker_detection; 482 bool disable_hbr_audio_dp2; 483 bool consolidated_dpia_dp_lt; 484 bool set_pipe_unlock_order; 485 bool enable_dpia_pre_training; 486 bool unify_link_enc_assignment; 487 }; 488 489 enum visual_confirm { 490 VISUAL_CONFIRM_DISABLE = 0, 491 VISUAL_CONFIRM_SURFACE = 1, 492 VISUAL_CONFIRM_HDR = 2, 493 VISUAL_CONFIRM_MPCTREE = 4, 494 VISUAL_CONFIRM_PSR = 5, 495 VISUAL_CONFIRM_SWAPCHAIN = 6, 496 VISUAL_CONFIRM_FAMS = 7, 497 VISUAL_CONFIRM_SWIZZLE = 9, 498 VISUAL_CONFIRM_REPLAY = 12, 499 VISUAL_CONFIRM_SUBVP = 14, 500 VISUAL_CONFIRM_MCLK_SWITCH = 16, 501 VISUAL_CONFIRM_FAMS2 = 19, 502 VISUAL_CONFIRM_HW_CURSOR = 20, 503 VISUAL_CONFIRM_VABC = 21, 504 VISUAL_CONFIRM_DCC = 22, 505 VISUAL_CONFIRM_EXPLICIT = 0x80000000, 506 }; 507 508 enum dc_psr_power_opts { 509 psr_power_opt_invalid = 0x0, 510 psr_power_opt_smu_opt_static_screen = 0x1, 511 psr_power_opt_z10_static_screen = 0x10, 512 psr_power_opt_ds_disable_allow = 0x100, 513 }; 514 515 enum dml_hostvm_override_opts { 516 DML_HOSTVM_NO_OVERRIDE = 0x0, 517 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 518 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 519 }; 520 521 enum dc_replay_power_opts { 522 replay_power_opt_invalid = 0x0, 523 replay_power_opt_smu_opt_static_screen = 0x1, 524 replay_power_opt_z10_static_screen = 0x10, 525 }; 526 527 enum dcc_option { 528 DCC_ENABLE = 0, 529 DCC_DISABLE = 1, 530 DCC_HALF_REQ_DISALBE = 2, 531 }; 532 533 enum in_game_fams_config { 534 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 535 INGAME_FAMS_DISABLE, // disable in-game fams 536 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 537 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 538 }; 539 540 /** 541 * enum pipe_split_policy - Pipe split strategy supported by DCN 542 * 543 * This enum is used to define the pipe split policy supported by DCN. By 544 * default, DC favors MPC_SPLIT_DYNAMIC. 545 */ 546 enum pipe_split_policy { 547 /** 548 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 549 * pipe in order to bring the best trade-off between performance and 550 * power consumption. This is the recommended option. 551 */ 552 MPC_SPLIT_DYNAMIC = 0, 553 554 /** 555 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 556 * try any sort of split optimization. 557 */ 558 MPC_SPLIT_AVOID = 1, 559 560 /** 561 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 562 * optimize the pipe utilization when using a single display; if the 563 * user connects to a second display, DC will avoid pipe split. 564 */ 565 MPC_SPLIT_AVOID_MULT_DISP = 2, 566 }; 567 568 enum wm_report_mode { 569 WM_REPORT_DEFAULT = 0, 570 WM_REPORT_OVERRIDE = 1, 571 }; 572 enum dtm_pstate{ 573 dtm_level_p0 = 0,/*highest voltage*/ 574 dtm_level_p1, 575 dtm_level_p2, 576 dtm_level_p3, 577 dtm_level_p4,/*when active_display_count = 0*/ 578 }; 579 580 enum dcn_pwr_state { 581 DCN_PWR_STATE_UNKNOWN = -1, 582 DCN_PWR_STATE_MISSION_MODE = 0, 583 DCN_PWR_STATE_LOW_POWER = 3, 584 }; 585 586 enum dcn_zstate_support_state { 587 DCN_ZSTATE_SUPPORT_UNKNOWN, 588 DCN_ZSTATE_SUPPORT_ALLOW, 589 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 590 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 591 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 592 DCN_ZSTATE_SUPPORT_DISALLOW, 593 }; 594 595 /* 596 * struct dc_clocks - DC pipe clocks 597 * 598 * For any clocks that may differ per pipe only the max is stored in this 599 * structure 600 */ 601 struct dc_clocks { 602 int dispclk_khz; 603 int actual_dispclk_khz; 604 int dppclk_khz; 605 int actual_dppclk_khz; 606 int disp_dpp_voltage_level_khz; 607 int dcfclk_khz; 608 int socclk_khz; 609 int dcfclk_deep_sleep_khz; 610 int fclk_khz; 611 int phyclk_khz; 612 int dramclk_khz; 613 bool p_state_change_support; 614 enum dcn_zstate_support_state zstate_support; 615 bool dtbclk_en; 616 int ref_dtbclk_khz; 617 bool fclk_p_state_change_support; 618 enum dcn_pwr_state pwr_state; 619 /* 620 * Elements below are not compared for the purposes of 621 * optimization required 622 */ 623 bool prev_p_state_change_support; 624 bool fclk_prev_p_state_change_support; 625 int num_ways; 626 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 627 628 /* 629 * @fw_based_mclk_switching 630 * 631 * DC has a mechanism that leverage the variable refresh rate to switch 632 * memory clock in cases that we have a large latency to achieve the 633 * memory clock change and a short vblank window. DC has some 634 * requirements to enable this feature, and this field describes if the 635 * system support or not such a feature. 636 */ 637 bool fw_based_mclk_switching; 638 bool fw_based_mclk_switching_shut_down; 639 int prev_num_ways; 640 enum dtm_pstate dtm_level; 641 int max_supported_dppclk_khz; 642 int max_supported_dispclk_khz; 643 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 644 int bw_dispclk_khz; 645 int idle_dramclk_khz; 646 int idle_fclk_khz; 647 int subvp_prefetch_dramclk_khz; 648 int subvp_prefetch_fclk_khz; 649 }; 650 651 struct dc_bw_validation_profile { 652 bool enable; 653 654 unsigned long long total_ticks; 655 unsigned long long voltage_level_ticks; 656 unsigned long long watermark_ticks; 657 unsigned long long rq_dlg_ticks; 658 659 unsigned long long total_count; 660 unsigned long long skip_fast_count; 661 unsigned long long skip_pass_count; 662 unsigned long long skip_fail_count; 663 }; 664 665 #define BW_VAL_TRACE_SETUP() \ 666 unsigned long long end_tick = 0; \ 667 unsigned long long voltage_level_tick = 0; \ 668 unsigned long long watermark_tick = 0; \ 669 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 670 dm_get_timestamp(dc->ctx) : 0 671 672 #define BW_VAL_TRACE_COUNT() \ 673 if (dc->debug.bw_val_profile.enable) \ 674 dc->debug.bw_val_profile.total_count++ 675 676 #define BW_VAL_TRACE_SKIP(status) \ 677 if (dc->debug.bw_val_profile.enable) { \ 678 if (!voltage_level_tick) \ 679 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 680 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 681 } 682 683 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 684 if (dc->debug.bw_val_profile.enable) \ 685 voltage_level_tick = dm_get_timestamp(dc->ctx) 686 687 #define BW_VAL_TRACE_END_WATERMARKS() \ 688 if (dc->debug.bw_val_profile.enable) \ 689 watermark_tick = dm_get_timestamp(dc->ctx) 690 691 #define BW_VAL_TRACE_FINISH() \ 692 if (dc->debug.bw_val_profile.enable) { \ 693 end_tick = dm_get_timestamp(dc->ctx); \ 694 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 695 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 696 if (watermark_tick) { \ 697 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 698 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 699 } \ 700 } 701 702 union mem_low_power_enable_options { 703 struct { 704 bool vga: 1; 705 bool i2c: 1; 706 bool dmcu: 1; 707 bool dscl: 1; 708 bool cm: 1; 709 bool mpc: 1; 710 bool optc: 1; 711 bool vpg: 1; 712 bool afmt: 1; 713 } bits; 714 uint32_t u32All; 715 }; 716 717 union root_clock_optimization_options { 718 struct { 719 bool dpp: 1; 720 bool dsc: 1; 721 bool hdmistream: 1; 722 bool hdmichar: 1; 723 bool dpstream: 1; 724 bool symclk32_se: 1; 725 bool symclk32_le: 1; 726 bool symclk_fe: 1; 727 bool physymclk: 1; 728 bool dpiasymclk: 1; 729 uint32_t reserved: 22; 730 } bits; 731 uint32_t u32All; 732 }; 733 734 union fine_grain_clock_gating_enable_options { 735 struct { 736 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 737 bool dchub : 1; /* Display controller hub */ 738 bool dchubbub : 1; 739 bool dpp : 1; /* Display pipes and planes */ 740 bool opp : 1; /* Output pixel processing */ 741 bool optc : 1; /* Output pipe timing combiner */ 742 bool dio : 1; /* Display output */ 743 bool dwb : 1; /* Display writeback */ 744 bool mmhubbub : 1; /* Multimedia hub */ 745 bool dmu : 1; /* Display core management unit */ 746 bool az : 1; /* Azalia */ 747 bool dchvm : 1; 748 bool dsc : 1; /* Display stream compression */ 749 750 uint32_t reserved : 19; 751 } bits; 752 uint32_t u32All; 753 }; 754 755 enum pg_hw_pipe_resources { 756 PG_HUBP = 0, 757 PG_DPP, 758 PG_DSC, 759 PG_MPCC, 760 PG_OPP, 761 PG_OPTC, 762 PG_DPSTREAM, 763 PG_HDMISTREAM, 764 PG_PHYSYMCLK, 765 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 766 }; 767 768 enum pg_hw_resources { 769 PG_DCCG = 0, 770 PG_DCIO, 771 PG_DIO, 772 PG_DCHUBBUB, 773 PG_DCHVM, 774 PG_DWB, 775 PG_HPO, 776 PG_HW_RESOURCES_NUM_ELEMENT 777 }; 778 779 struct pg_block_update { 780 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 781 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 782 }; 783 784 union dpia_debug_options { 785 struct { 786 uint32_t disable_dpia:1; /* bit 0 */ 787 uint32_t force_non_lttpr:1; /* bit 1 */ 788 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 789 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 790 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 791 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 792 uint32_t enable_consolidated_dpia_dp_lt:1; /* bit 6 */ 793 uint32_t enable_dpia_pre_training:1; /* bit 7 */ 794 uint32_t unify_link_enc_assignment:1; /* bit 8 */ 795 uint32_t reserved:24; 796 } bits; 797 uint32_t raw; 798 }; 799 800 /* AUX wake work around options 801 * 0: enable/disable work around 802 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 803 * 15-2: reserved 804 * 31-16: timeout in ms 805 */ 806 union aux_wake_wa_options { 807 struct { 808 uint32_t enable_wa : 1; 809 uint32_t use_default_timeout : 1; 810 uint32_t rsvd: 14; 811 uint32_t timeout_ms : 16; 812 } bits; 813 uint32_t raw; 814 }; 815 816 struct dc_debug_data { 817 uint32_t ltFailCount; 818 uint32_t i2cErrorCount; 819 uint32_t auxErrorCount; 820 }; 821 822 struct dc_phy_addr_space_config { 823 struct { 824 uint64_t start_addr; 825 uint64_t end_addr; 826 uint64_t fb_top; 827 uint64_t fb_offset; 828 uint64_t fb_base; 829 uint64_t agp_top; 830 uint64_t agp_bot; 831 uint64_t agp_base; 832 } system_aperture; 833 834 struct { 835 uint64_t page_table_start_addr; 836 uint64_t page_table_end_addr; 837 uint64_t page_table_base_addr; 838 bool base_addr_is_mc_addr; 839 } gart_config; 840 841 bool valid; 842 bool is_hvm_enabled; 843 uint64_t page_table_default_page_addr; 844 }; 845 846 struct dc_virtual_addr_space_config { 847 uint64_t page_table_base_addr; 848 uint64_t page_table_start_addr; 849 uint64_t page_table_end_addr; 850 uint32_t page_table_block_size_in_bytes; 851 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 852 }; 853 854 struct dc_bounding_box_overrides { 855 int sr_exit_time_ns; 856 int sr_enter_plus_exit_time_ns; 857 int sr_exit_z8_time_ns; 858 int sr_enter_plus_exit_z8_time_ns; 859 int urgent_latency_ns; 860 int percent_of_ideal_drambw; 861 int dram_clock_change_latency_ns; 862 int dummy_clock_change_latency_ns; 863 int fclk_clock_change_latency_ns; 864 /* This forces a hard min on the DCFCLK we use 865 * for DML. Unlike the debug option for forcing 866 * DCFCLK, this override affects watermark calculations 867 */ 868 int min_dcfclk_mhz; 869 }; 870 871 struct dc_state; 872 struct resource_pool; 873 struct dce_hwseq; 874 struct link_service; 875 876 /* 877 * struct dc_debug_options - DC debug struct 878 * 879 * This struct provides a simple mechanism for developers to change some 880 * configurations, enable/disable features, and activate extra debug options. 881 * This can be very handy to narrow down whether some specific feature is 882 * causing an issue or not. 883 */ 884 struct dc_debug_options { 885 bool native422_support; 886 bool disable_dsc; 887 enum visual_confirm visual_confirm; 888 int visual_confirm_rect_height; 889 890 bool sanity_checks; 891 bool max_disp_clk; 892 bool surface_trace; 893 bool clock_trace; 894 bool validation_trace; 895 bool bandwidth_calcs_trace; 896 int max_downscale_src_width; 897 898 /* stutter efficiency related */ 899 bool disable_stutter; 900 bool use_max_lb; 901 enum dcc_option disable_dcc; 902 903 /* 904 * @pipe_split_policy: Define which pipe split policy is used by the 905 * display core. 906 */ 907 enum pipe_split_policy pipe_split_policy; 908 bool force_single_disp_pipe_split; 909 bool voltage_align_fclk; 910 bool disable_min_fclk; 911 912 bool hdcp_lc_force_fw_enable; 913 bool hdcp_lc_enable_sw_fallback; 914 915 bool disable_dfs_bypass; 916 bool disable_dpp_power_gate; 917 bool disable_hubp_power_gate; 918 bool disable_dsc_power_gate; 919 bool disable_optc_power_gate; 920 bool disable_hpo_power_gate; 921 int dsc_min_slice_height_override; 922 int dsc_bpp_increment_div; 923 bool disable_pplib_wm_range; 924 enum wm_report_mode pplib_wm_report_mode; 925 unsigned int min_disp_clk_khz; 926 unsigned int min_dpp_clk_khz; 927 unsigned int min_dram_clk_khz; 928 int sr_exit_time_dpm0_ns; 929 int sr_enter_plus_exit_time_dpm0_ns; 930 int sr_exit_time_ns; 931 int sr_enter_plus_exit_time_ns; 932 int sr_exit_z8_time_ns; 933 int sr_enter_plus_exit_z8_time_ns; 934 int urgent_latency_ns; 935 uint32_t underflow_assert_delay_us; 936 int percent_of_ideal_drambw; 937 int dram_clock_change_latency_ns; 938 bool optimized_watermark; 939 int always_scale; 940 bool disable_pplib_clock_request; 941 bool disable_clock_gate; 942 bool disable_mem_low_power; 943 bool pstate_enabled; 944 bool disable_dmcu; 945 bool force_abm_enable; 946 bool disable_stereo_support; 947 bool vsr_support; 948 bool performance_trace; 949 bool az_endpoint_mute_only; 950 bool always_use_regamma; 951 bool recovery_enabled; 952 bool avoid_vbios_exec_table; 953 bool scl_reset_length10; 954 bool hdmi20_disable; 955 bool skip_detection_link_training; 956 uint32_t edid_read_retry_times; 957 unsigned int force_odm_combine; //bit vector based on otg inst 958 unsigned int seamless_boot_odm_combine; 959 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 960 int minimum_z8_residency_time; 961 int minimum_z10_residency_time; 962 bool disable_z9_mpc; 963 unsigned int force_fclk_khz; 964 bool enable_tri_buf; 965 bool ips_disallow_entry; 966 bool dmub_offload_enabled; 967 bool dmcub_emulation; 968 bool disable_idle_power_optimizations; 969 unsigned int mall_size_override; 970 unsigned int mall_additional_timer_percent; 971 bool mall_error_as_fatal; 972 bool dmub_command_table; /* for testing only */ 973 struct dc_bw_validation_profile bw_val_profile; 974 bool disable_fec; 975 bool disable_48mhz_pwrdwn; 976 /* This forces a hard min on the DCFCLK requested to SMU/PP 977 * watermarks are not affected. 978 */ 979 unsigned int force_min_dcfclk_mhz; 980 int dwb_fi_phase; 981 bool disable_timing_sync; 982 bool cm_in_bypass; 983 int force_clock_mode;/*every mode change.*/ 984 985 bool disable_dram_clock_change_vactive_support; 986 bool validate_dml_output; 987 bool enable_dmcub_surface_flip; 988 bool usbc_combo_phy_reset_wa; 989 bool enable_dram_clock_change_one_display_vactive; 990 /* TODO - remove once tested */ 991 bool legacy_dp2_lt; 992 bool set_mst_en_for_sst; 993 bool disable_uhbr; 994 bool force_dp2_lt_fallback_method; 995 bool ignore_cable_id; 996 union mem_low_power_enable_options enable_mem_low_power; 997 union root_clock_optimization_options root_clock_optimization; 998 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 999 bool hpo_optimization; 1000 bool force_vblank_alignment; 1001 1002 /* Enable dmub aux for legacy ddc */ 1003 bool enable_dmub_aux_for_legacy_ddc; 1004 bool disable_fams; 1005 enum in_game_fams_config disable_fams_gaming; 1006 /* FEC/PSR1 sequence enable delay in 100us */ 1007 uint8_t fec_enable_delay_in100us; 1008 bool enable_driver_sequence_debug; 1009 enum det_size crb_alloc_policy; 1010 int crb_alloc_policy_min_disp_count; 1011 bool disable_z10; 1012 bool enable_z9_disable_interface; 1013 bool psr_skip_crtc_disable; 1014 uint32_t ips_skip_crtc_disable_mask; 1015 union dpia_debug_options dpia_debug; 1016 bool disable_fixed_vs_aux_timeout_wa; 1017 uint32_t fixed_vs_aux_delay_config_wa; 1018 bool force_disable_subvp; 1019 bool force_subvp_mclk_switch; 1020 bool allow_sw_cursor_fallback; 1021 unsigned int force_subvp_num_ways; 1022 unsigned int force_mall_ss_num_ways; 1023 bool alloc_extra_way_for_cursor; 1024 uint32_t subvp_extra_lines; 1025 bool force_usr_allow; 1026 /* uses value at boot and disables switch */ 1027 bool disable_dtb_ref_clk_switch; 1028 bool extended_blank_optimization; 1029 union aux_wake_wa_options aux_wake_wa; 1030 uint32_t mst_start_top_delay; 1031 uint8_t psr_power_use_phy_fsm; 1032 enum dml_hostvm_override_opts dml_hostvm_override; 1033 bool dml_disallow_alternate_prefetch_modes; 1034 bool use_legacy_soc_bb_mechanism; 1035 bool exit_idle_opt_for_cursor_updates; 1036 bool using_dml2; 1037 bool enable_single_display_2to1_odm_policy; 1038 bool enable_double_buffered_dsc_pg_support; 1039 bool enable_dp_dig_pixel_rate_div_policy; 1040 bool using_dml21; 1041 enum lttpr_mode lttpr_mode_override; 1042 unsigned int dsc_delay_factor_wa_x1000; 1043 unsigned int min_prefetch_in_strobe_ns; 1044 bool disable_unbounded_requesting; 1045 bool dig_fifo_off_in_blank; 1046 bool override_dispclk_programming; 1047 bool otg_crc_db; 1048 bool disallow_dispclk_dppclk_ds; 1049 bool disable_fpo_optimizations; 1050 bool support_eDP1_5; 1051 uint32_t fpo_vactive_margin_us; 1052 bool disable_fpo_vactive; 1053 bool disable_boot_optimizations; 1054 bool override_odm_optimization; 1055 bool minimize_dispclk_using_odm; 1056 bool disable_subvp_high_refresh; 1057 bool disable_dp_plus_plus_wa; 1058 uint32_t fpo_vactive_min_active_margin_us; 1059 uint32_t fpo_vactive_max_blank_us; 1060 bool enable_hpo_pg_support; 1061 bool enable_legacy_fast_update; 1062 bool disable_dc_mode_overwrite; 1063 bool replay_skip_crtc_disabled; 1064 bool ignore_pg;/*do nothing, let pmfw control it*/ 1065 bool psp_disabled_wa; 1066 unsigned int ips2_eval_delay_us; 1067 unsigned int ips2_entry_delay_us; 1068 bool optimize_ips_handshake; 1069 bool disable_dmub_reallow_idle; 1070 bool disable_timeout; 1071 bool disable_extblankadj; 1072 bool enable_idle_reg_checks; 1073 unsigned int static_screen_wait_frames; 1074 uint32_t pwm_freq; 1075 bool force_chroma_subsampling_1tap; 1076 unsigned int dcc_meta_propagation_delay_us; 1077 bool disable_422_left_edge_pixel; 1078 bool dml21_force_pstate_method; 1079 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1080 uint32_t dml21_disable_pstate_method_mask; 1081 union fw_assisted_mclk_switch_version fams_version; 1082 union dmub_fams2_global_feature_config fams2_config; 1083 unsigned int force_cositing; 1084 unsigned int disable_spl; 1085 unsigned int force_easf; 1086 unsigned int force_sharpness; 1087 unsigned int force_sharpness_level; 1088 unsigned int force_lls; 1089 bool notify_dpia_hr_bw; 1090 bool enable_ips_visual_confirm; 1091 unsigned int sharpen_policy; 1092 unsigned int scale_to_sharpness_policy; 1093 bool skip_full_updated_if_possible; 1094 unsigned int enable_oled_edp_power_up_opt; 1095 bool enable_hblank_borrow; 1096 bool force_subvp_df_throttle; 1097 uint32_t acpi_transition_bitmasks[MAX_PIPES]; 1098 }; 1099 1100 1101 /* Generic structure that can be used to query properties of DC. More fields 1102 * can be added as required. 1103 */ 1104 struct dc_current_properties { 1105 unsigned int cursor_size_limit; 1106 }; 1107 1108 enum frame_buffer_mode { 1109 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1110 FRAME_BUFFER_MODE_ZFB_ONLY, 1111 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1112 } ; 1113 1114 struct dchub_init_data { 1115 int64_t zfb_phys_addr_base; 1116 int64_t zfb_mc_base_addr; 1117 uint64_t zfb_size_in_byte; 1118 enum frame_buffer_mode fb_mode; 1119 bool dchub_initialzied; 1120 bool dchub_info_valid; 1121 }; 1122 1123 struct dml2_soc_bb; 1124 1125 struct dc_init_data { 1126 struct hw_asic_id asic_id; 1127 void *driver; /* ctx */ 1128 struct cgs_device *cgs_device; 1129 struct dc_bounding_box_overrides bb_overrides; 1130 1131 int num_virtual_links; 1132 /* 1133 * If 'vbios_override' not NULL, it will be called instead 1134 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1135 */ 1136 struct dc_bios *vbios_override; 1137 enum dce_environment dce_environment; 1138 1139 struct dmub_offload_funcs *dmub_if; 1140 struct dc_reg_helper_state *dmub_offload; 1141 1142 struct dc_config flags; 1143 uint64_t log_mask; 1144 1145 struct dpcd_vendor_signature vendor_signature; 1146 bool force_smu_not_present; 1147 /* 1148 * IP offset for run time initializaion of register addresses 1149 * 1150 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1151 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1152 * before them. 1153 */ 1154 uint32_t *dcn_reg_offsets; 1155 uint32_t *nbio_reg_offsets; 1156 uint32_t *clk_reg_offsets; 1157 struct dml2_soc_bb *bb_from_dmub; 1158 }; 1159 1160 struct dc_callback_init { 1161 struct cp_psp cp_psp; 1162 }; 1163 1164 struct dc *dc_create(const struct dc_init_data *init_params); 1165 void dc_hardware_init(struct dc *dc); 1166 1167 int dc_get_vmid_use_vector(struct dc *dc); 1168 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1169 /* Returns the number of vmids supported */ 1170 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1171 void dc_init_callbacks(struct dc *dc, 1172 const struct dc_callback_init *init_params); 1173 void dc_deinit_callbacks(struct dc *dc); 1174 void dc_destroy(struct dc **dc); 1175 1176 /* Surface Interfaces */ 1177 1178 enum { 1179 TRANSFER_FUNC_POINTS = 1025 1180 }; 1181 1182 struct dc_hdr_static_metadata { 1183 /* display chromaticities and white point in units of 0.00001 */ 1184 unsigned int chromaticity_green_x; 1185 unsigned int chromaticity_green_y; 1186 unsigned int chromaticity_blue_x; 1187 unsigned int chromaticity_blue_y; 1188 unsigned int chromaticity_red_x; 1189 unsigned int chromaticity_red_y; 1190 unsigned int chromaticity_white_point_x; 1191 unsigned int chromaticity_white_point_y; 1192 1193 uint32_t min_luminance; 1194 uint32_t max_luminance; 1195 uint32_t maximum_content_light_level; 1196 uint32_t maximum_frame_average_light_level; 1197 }; 1198 1199 enum dc_transfer_func_type { 1200 TF_TYPE_PREDEFINED, 1201 TF_TYPE_DISTRIBUTED_POINTS, 1202 TF_TYPE_BYPASS, 1203 TF_TYPE_HWPWL 1204 }; 1205 1206 struct dc_transfer_func_distributed_points { 1207 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1208 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1209 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1210 1211 uint16_t end_exponent; 1212 uint16_t x_point_at_y1_red; 1213 uint16_t x_point_at_y1_green; 1214 uint16_t x_point_at_y1_blue; 1215 }; 1216 1217 enum dc_transfer_func_predefined { 1218 TRANSFER_FUNCTION_SRGB, 1219 TRANSFER_FUNCTION_BT709, 1220 TRANSFER_FUNCTION_PQ, 1221 TRANSFER_FUNCTION_LINEAR, 1222 TRANSFER_FUNCTION_UNITY, 1223 TRANSFER_FUNCTION_HLG, 1224 TRANSFER_FUNCTION_HLG12, 1225 TRANSFER_FUNCTION_GAMMA22, 1226 TRANSFER_FUNCTION_GAMMA24, 1227 TRANSFER_FUNCTION_GAMMA26 1228 }; 1229 1230 1231 struct dc_transfer_func { 1232 struct kref refcount; 1233 enum dc_transfer_func_type type; 1234 enum dc_transfer_func_predefined tf; 1235 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1236 uint32_t sdr_ref_white_level; 1237 union { 1238 struct pwl_params pwl; 1239 struct dc_transfer_func_distributed_points tf_pts; 1240 }; 1241 }; 1242 1243 1244 union dc_3dlut_state { 1245 struct { 1246 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1247 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1248 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1249 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1250 uint32_t mpc_rmu1_mux:4; 1251 uint32_t mpc_rmu2_mux:4; 1252 uint32_t reserved:15; 1253 } bits; 1254 uint32_t raw; 1255 }; 1256 1257 1258 struct dc_3dlut { 1259 struct kref refcount; 1260 struct tetrahedral_params lut_3d; 1261 struct fixed31_32 hdr_multiplier; 1262 union dc_3dlut_state state; 1263 }; 1264 /* 1265 * This structure is filled in by dc_surface_get_status and contains 1266 * the last requested address and the currently active address so the called 1267 * can determine if there are any outstanding flips 1268 */ 1269 struct dc_plane_status { 1270 struct dc_plane_address requested_address; 1271 struct dc_plane_address current_address; 1272 bool is_flip_pending; 1273 bool is_right_eye; 1274 }; 1275 1276 union surface_update_flags { 1277 1278 struct { 1279 uint32_t addr_update:1; 1280 /* Medium updates */ 1281 uint32_t dcc_change:1; 1282 uint32_t color_space_change:1; 1283 uint32_t horizontal_mirror_change:1; 1284 uint32_t per_pixel_alpha_change:1; 1285 uint32_t global_alpha_change:1; 1286 uint32_t hdr_mult:1; 1287 uint32_t rotation_change:1; 1288 uint32_t swizzle_change:1; 1289 uint32_t scaling_change:1; 1290 uint32_t position_change:1; 1291 uint32_t in_transfer_func_change:1; 1292 uint32_t input_csc_change:1; 1293 uint32_t coeff_reduction_change:1; 1294 uint32_t output_tf_change:1; 1295 uint32_t pixel_format_change:1; 1296 uint32_t plane_size_change:1; 1297 uint32_t gamut_remap_change:1; 1298 1299 /* Full updates */ 1300 uint32_t new_plane:1; 1301 uint32_t bpp_change:1; 1302 uint32_t gamma_change:1; 1303 uint32_t bandwidth_change:1; 1304 uint32_t clock_change:1; 1305 uint32_t stereo_format_change:1; 1306 uint32_t lut_3d:1; 1307 uint32_t tmz_changed:1; 1308 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1309 uint32_t full_update:1; 1310 uint32_t sdr_white_level_nits:1; 1311 } bits; 1312 1313 uint32_t raw; 1314 }; 1315 1316 #define DC_REMOVE_PLANE_POINTERS 1 1317 1318 struct dc_plane_state { 1319 struct dc_plane_address address; 1320 struct dc_plane_flip_time time; 1321 bool triplebuffer_flips; 1322 struct scaling_taps scaling_quality; 1323 struct rect src_rect; 1324 struct rect dst_rect; 1325 struct rect clip_rect; 1326 1327 struct plane_size plane_size; 1328 struct dc_tiling_info tiling_info; 1329 1330 struct dc_plane_dcc_param dcc; 1331 1332 struct dc_gamma gamma_correction; 1333 struct dc_transfer_func in_transfer_func; 1334 struct dc_bias_and_scale bias_and_scale; 1335 struct dc_csc_transform input_csc_color_matrix; 1336 struct fixed31_32 coeff_reduction_factor; 1337 struct fixed31_32 hdr_mult; 1338 struct colorspace_transform gamut_remap_matrix; 1339 1340 // TODO: No longer used, remove 1341 struct dc_hdr_static_metadata hdr_static_ctx; 1342 1343 enum dc_color_space color_space; 1344 1345 struct dc_3dlut lut3d_func; 1346 struct dc_transfer_func in_shaper_func; 1347 struct dc_transfer_func blend_tf; 1348 1349 struct dc_transfer_func *gamcor_tf; 1350 enum surface_pixel_format format; 1351 enum dc_rotation_angle rotation; 1352 enum plane_stereo_format stereo_format; 1353 1354 bool is_tiling_rotated; 1355 bool per_pixel_alpha; 1356 bool pre_multiplied_alpha; 1357 bool global_alpha; 1358 int global_alpha_value; 1359 bool visible; 1360 bool flip_immediate; 1361 bool horizontal_mirror; 1362 int layer_index; 1363 1364 union surface_update_flags update_flags; 1365 bool flip_int_enabled; 1366 bool skip_manual_trigger; 1367 1368 /* private to DC core */ 1369 struct dc_plane_status status; 1370 struct dc_context *ctx; 1371 1372 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1373 bool force_full_update; 1374 1375 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1376 1377 /* private to dc_surface.c */ 1378 enum dc_irq_source irq_source; 1379 struct kref refcount; 1380 struct tg_color visual_confirm_color; 1381 1382 bool is_statically_allocated; 1383 enum chroma_cositing cositing; 1384 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1385 bool mcm_lut1d_enable; 1386 struct dc_cm2_func_luts mcm_luts; 1387 bool lut_bank_a; 1388 enum mpcc_movable_cm_location mcm_location; 1389 struct dc_csc_transform cursor_csc_color_matrix; 1390 bool adaptive_sharpness_en; 1391 int adaptive_sharpness_policy; 1392 int sharpness_level; 1393 enum linear_light_scaling linear_light_scaling; 1394 unsigned int sdr_white_level_nits; 1395 }; 1396 1397 struct dc_plane_info { 1398 struct plane_size plane_size; 1399 struct dc_tiling_info tiling_info; 1400 struct dc_plane_dcc_param dcc; 1401 enum surface_pixel_format format; 1402 enum dc_rotation_angle rotation; 1403 enum plane_stereo_format stereo_format; 1404 enum dc_color_space color_space; 1405 bool horizontal_mirror; 1406 bool visible; 1407 bool per_pixel_alpha; 1408 bool pre_multiplied_alpha; 1409 bool global_alpha; 1410 int global_alpha_value; 1411 bool input_csc_enabled; 1412 int layer_index; 1413 enum chroma_cositing cositing; 1414 }; 1415 1416 #include "dc_stream.h" 1417 1418 struct dc_scratch_space { 1419 /* used to temporarily backup plane states of a stream during 1420 * dc update. The reason is that plane states are overwritten 1421 * with surface updates in dc update. Once they are overwritten 1422 * current state is no longer valid. We want to temporarily 1423 * store current value in plane states so we can still recover 1424 * a valid current state during dc update. 1425 */ 1426 struct dc_plane_state plane_states[MAX_SURFACES]; 1427 1428 struct dc_stream_state stream_state; 1429 }; 1430 1431 /* 1432 * A link contains one or more sinks and their connected status. 1433 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1434 */ 1435 struct dc_link { 1436 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1437 unsigned int sink_count; 1438 struct dc_sink *local_sink; 1439 unsigned int link_index; 1440 enum dc_connection_type type; 1441 enum signal_type connector_signal; 1442 enum dc_irq_source irq_source_hpd; 1443 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1444 enum dc_irq_source irq_source_read_request;/* Read Request */ 1445 1446 bool is_hpd_filter_disabled; 1447 bool dp_ss_off; 1448 1449 /** 1450 * @link_state_valid: 1451 * 1452 * If there is no link and local sink, this variable should be set to 1453 * false. Otherwise, it should be set to true; usually, the function 1454 * core_link_enable_stream sets this field to true. 1455 */ 1456 bool link_state_valid; 1457 bool aux_access_disabled; 1458 bool sync_lt_in_progress; 1459 bool skip_stream_reenable; 1460 bool is_internal_display; 1461 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1462 bool is_dig_mapping_flexible; 1463 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1464 bool is_hpd_pending; /* Indicates a new received hpd */ 1465 1466 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1467 * for every link training. This is incompatible with DP LL compliance automation, 1468 * which expects the same link settings to be used every retry on a link loss. 1469 * This flag is used to skip the fallback when link loss occurs during automation. 1470 */ 1471 bool skip_fallback_on_link_loss; 1472 1473 bool edp_sink_present; 1474 1475 struct dp_trace dp_trace; 1476 1477 /* caps is the same as reported_link_cap. link_traing use 1478 * reported_link_cap. Will clean up. TODO 1479 */ 1480 struct dc_link_settings reported_link_cap; 1481 struct dc_link_settings verified_link_cap; 1482 struct dc_link_settings cur_link_settings; 1483 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1484 struct dc_link_settings preferred_link_setting; 1485 /* preferred_training_settings are override values that 1486 * come from DM. DM is responsible for the memory 1487 * management of the override pointers. 1488 */ 1489 struct dc_link_training_overrides preferred_training_settings; 1490 struct dp_audio_test_data audio_test_data; 1491 1492 uint8_t ddc_hw_inst; 1493 1494 uint8_t hpd_src; 1495 1496 uint8_t link_enc_hw_inst; 1497 /* DIG link encoder ID. Used as index in link encoder resource pool. 1498 * For links with fixed mapping to DIG, this is not changed after dc_link 1499 * object creation. 1500 */ 1501 enum engine_id eng_id; 1502 enum engine_id dpia_preferred_eng_id; 1503 1504 bool test_pattern_enabled; 1505 /* Pending/Current test pattern are only used to perform and track 1506 * FIXED_VS retimer test pattern/lane adjustment override state. 1507 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1508 * to perform specific lane adjust overrides before setting certain 1509 * PHY test patterns. In cases when lane adjust and set test pattern 1510 * calls are not performed atomically (i.e. performing link training), 1511 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1512 * and current_test_pattern will contain required context for any future 1513 * set pattern/set lane adjust to transition between override state(s). 1514 * */ 1515 enum dp_test_pattern current_test_pattern; 1516 enum dp_test_pattern pending_test_pattern; 1517 1518 union compliance_test_state compliance_test_state; 1519 1520 void *priv; 1521 1522 struct ddc_service *ddc; 1523 1524 enum dp_panel_mode panel_mode; 1525 bool aux_mode; 1526 1527 /* Private to DC core */ 1528 1529 const struct dc *dc; 1530 1531 struct dc_context *ctx; 1532 1533 struct panel_cntl *panel_cntl; 1534 struct link_encoder *link_enc; 1535 struct graphics_object_id link_id; 1536 /* Endpoint type distinguishes display endpoints which do not have entries 1537 * in the BIOS connector table from those that do. Helps when tracking link 1538 * encoder to display endpoint assignments. 1539 */ 1540 enum display_endpoint_type ep_type; 1541 union ddi_channel_mapping ddi_channel_mapping; 1542 struct connector_device_tag_info device_tag; 1543 struct dpcd_caps dpcd_caps; 1544 uint32_t dongle_max_pix_clk; 1545 unsigned short chip_caps; 1546 unsigned int dpcd_sink_count; 1547 struct hdcp_caps hdcp_caps; 1548 enum edp_revision edp_revision; 1549 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1550 1551 struct psr_settings psr_settings; 1552 struct replay_settings replay_settings; 1553 1554 /* Drive settings read from integrated info table */ 1555 struct dc_lane_settings bios_forced_drive_settings; 1556 1557 /* Vendor specific LTTPR workaround variables */ 1558 uint8_t vendor_specific_lttpr_link_rate_wa; 1559 bool apply_vendor_specific_lttpr_link_rate_wa; 1560 1561 /* MST record stream using this link */ 1562 struct link_flags { 1563 bool dp_keep_receiver_powered; 1564 bool dp_skip_DID2; 1565 bool dp_skip_reset_segment; 1566 bool dp_skip_fs_144hz; 1567 bool dp_mot_reset_segment; 1568 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1569 bool dpia_mst_dsc_always_on; 1570 /* Forced DPIA into TBT3 compatibility mode. */ 1571 bool dpia_forced_tbt3_mode; 1572 bool dongle_mode_timing_override; 1573 bool blank_stream_on_ocs_change; 1574 bool read_dpcd204h_on_irq_hpd; 1575 bool force_dp_ffe_preset; 1576 } wa_flags; 1577 union dc_dp_ffe_preset forced_dp_ffe_preset; 1578 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1579 1580 struct dc_link_status link_status; 1581 struct dprx_states dprx_states; 1582 1583 struct gpio *hpd_gpio; 1584 enum dc_link_fec_state fec_state; 1585 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1586 1587 struct dc_panel_config panel_config; 1588 struct phy_state phy_state; 1589 uint32_t phy_transition_bitmask; 1590 // BW ALLOCATON USB4 ONLY 1591 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1592 bool skip_implict_edp_power_control; 1593 enum backlight_control_type backlight_control_type; 1594 }; 1595 1596 struct dc { 1597 struct dc_debug_options debug; 1598 struct dc_versions versions; 1599 struct dc_caps caps; 1600 struct dc_cap_funcs cap_funcs; 1601 struct dc_config config; 1602 struct dc_bounding_box_overrides bb_overrides; 1603 struct dc_bug_wa work_arounds; 1604 struct dc_context *ctx; 1605 struct dc_phy_addr_space_config vm_pa_config; 1606 1607 uint8_t link_count; 1608 struct dc_link *links[MAX_LINKS]; 1609 uint8_t lowest_dpia_link_index; 1610 struct link_service *link_srv; 1611 1612 struct dc_state *current_state; 1613 struct resource_pool *res_pool; 1614 1615 struct clk_mgr *clk_mgr; 1616 1617 /* Display Engine Clock levels */ 1618 struct dm_pp_clock_levels sclk_lvls; 1619 1620 /* Inputs into BW and WM calculations. */ 1621 struct bw_calcs_dceip *bw_dceip; 1622 struct bw_calcs_vbios *bw_vbios; 1623 struct dcn_soc_bounding_box *dcn_soc; 1624 struct dcn_ip_params *dcn_ip; 1625 struct display_mode_lib dml; 1626 1627 /* HW functions */ 1628 struct hw_sequencer_funcs hwss; 1629 struct dce_hwseq *hwseq; 1630 1631 /* Require to optimize clocks and bandwidth for added/removed planes */ 1632 bool optimized_required; 1633 bool wm_optimized_required; 1634 bool idle_optimizations_allowed; 1635 bool enable_c20_dtm_b0; 1636 1637 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1638 1639 /* FBC compressor */ 1640 struct compressor *fbc_compressor; 1641 1642 struct dc_debug_data debug_data; 1643 struct dpcd_vendor_signature vendor_signature; 1644 1645 const char *build_id; 1646 struct vm_helper *vm_helper; 1647 1648 uint32_t *dcn_reg_offsets; 1649 uint32_t *nbio_reg_offsets; 1650 uint32_t *clk_reg_offsets; 1651 1652 /* Scratch memory */ 1653 struct { 1654 struct { 1655 /* 1656 * For matching clock_limits table in driver with table 1657 * from PMFW. 1658 */ 1659 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1660 } update_bw_bounding_box; 1661 struct dc_scratch_space current_state; 1662 struct dc_scratch_space new_state; 1663 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 1664 struct dc_link temp_link; 1665 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 1666 } scratch; 1667 1668 struct dml2_configuration_options dml2_options; 1669 struct dml2_configuration_options dml2_tmp; 1670 enum dc_acpi_cm_power_state power_state; 1671 1672 }; 1673 1674 struct dc_scaling_info { 1675 struct rect src_rect; 1676 struct rect dst_rect; 1677 struct rect clip_rect; 1678 struct scaling_taps scaling_quality; 1679 }; 1680 1681 struct dc_fast_update { 1682 const struct dc_flip_addrs *flip_addr; 1683 const struct dc_gamma *gamma; 1684 const struct colorspace_transform *gamut_remap_matrix; 1685 const struct dc_csc_transform *input_csc_color_matrix; 1686 const struct fixed31_32 *coeff_reduction_factor; 1687 struct dc_transfer_func *out_transfer_func; 1688 struct dc_csc_transform *output_csc_transform; 1689 const struct dc_csc_transform *cursor_csc_color_matrix; 1690 }; 1691 1692 struct dc_surface_update { 1693 struct dc_plane_state *surface; 1694 1695 /* isr safe update parameters. null means no updates */ 1696 const struct dc_flip_addrs *flip_addr; 1697 const struct dc_plane_info *plane_info; 1698 const struct dc_scaling_info *scaling_info; 1699 struct fixed31_32 hdr_mult; 1700 /* following updates require alloc/sleep/spin that is not isr safe, 1701 * null means no updates 1702 */ 1703 const struct dc_gamma *gamma; 1704 const struct dc_transfer_func *in_transfer_func; 1705 1706 const struct dc_csc_transform *input_csc_color_matrix; 1707 const struct fixed31_32 *coeff_reduction_factor; 1708 const struct dc_transfer_func *func_shaper; 1709 const struct dc_3dlut *lut3d_func; 1710 const struct dc_transfer_func *blend_tf; 1711 const struct colorspace_transform *gamut_remap_matrix; 1712 /* 1713 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT) 1714 * 1715 * change cm2_params.component_settings: Full update 1716 * change cm2_params.cm2_luts: Fast update 1717 */ 1718 const struct dc_cm2_parameters *cm2_params; 1719 const struct dc_csc_transform *cursor_csc_color_matrix; 1720 unsigned int sdr_white_level_nits; 1721 struct dc_bias_and_scale bias_and_scale; 1722 }; 1723 1724 /* 1725 * Create a new surface with default parameters; 1726 */ 1727 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1728 void dc_gamma_release(struct dc_gamma **dc_gamma); 1729 struct dc_gamma *dc_create_gamma(void); 1730 1731 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1732 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1733 struct dc_transfer_func *dc_create_transfer_func(void); 1734 1735 struct dc_3dlut *dc_create_3dlut_func(void); 1736 void dc_3dlut_func_release(struct dc_3dlut *lut); 1737 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1738 1739 void dc_post_update_surfaces_to_stream( 1740 struct dc *dc); 1741 1742 #include "dc_stream.h" 1743 1744 /** 1745 * struct dc_validation_set - Struct to store surface/stream associations for validation 1746 */ 1747 struct dc_validation_set { 1748 /** 1749 * @stream: Stream state properties 1750 */ 1751 struct dc_stream_state *stream; 1752 1753 /** 1754 * @plane_states: Surface state 1755 */ 1756 struct dc_plane_state *plane_states[MAX_SURFACES]; 1757 1758 /** 1759 * @plane_count: Total of active planes 1760 */ 1761 uint8_t plane_count; 1762 }; 1763 1764 bool dc_validate_boot_timing(const struct dc *dc, 1765 const struct dc_sink *sink, 1766 struct dc_crtc_timing *crtc_timing); 1767 1768 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1769 1770 enum dc_status dc_validate_with_context(struct dc *dc, 1771 const struct dc_validation_set set[], 1772 int set_count, 1773 struct dc_state *context, 1774 bool fast_validate); 1775 1776 bool dc_set_generic_gpio_for_stereo(bool enable, 1777 struct gpio_service *gpio_service); 1778 1779 /* 1780 * fast_validate: we return after determining if we can support the new state, 1781 * but before we populate the programming info 1782 */ 1783 enum dc_status dc_validate_global_state( 1784 struct dc *dc, 1785 struct dc_state *new_ctx, 1786 bool fast_validate); 1787 1788 bool dc_acquire_release_mpc_3dlut( 1789 struct dc *dc, bool acquire, 1790 struct dc_stream_state *stream, 1791 struct dc_3dlut **lut, 1792 struct dc_transfer_func **shaper); 1793 1794 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1795 void get_audio_check(struct audio_info *aud_modes, 1796 struct audio_check *aud_chk); 1797 1798 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 1799 void populate_fast_updates(struct dc_fast_update *fast_update, 1800 struct dc_surface_update *srf_updates, 1801 int surface_count, 1802 struct dc_stream_update *stream_update); 1803 /* 1804 * Set up streams and links associated to drive sinks 1805 * The streams parameter is an absolute set of all active streams. 1806 * 1807 * After this call: 1808 * Phy, Encoder, Timing Generator are programmed and enabled. 1809 * New streams are enabled with blank stream; no memory read. 1810 */ 1811 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 1812 1813 1814 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1815 struct dc_stream_state *stream, 1816 int mpcc_inst); 1817 1818 1819 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1820 1821 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1822 1823 /* The function returns minimum bandwidth required to drive a given timing 1824 * return - minimum required timing bandwidth in kbps. 1825 */ 1826 uint32_t dc_bandwidth_in_kbps_from_timing( 1827 const struct dc_crtc_timing *timing, 1828 const enum dc_link_encoding_format link_encoding); 1829 1830 /* Link Interfaces */ 1831 /* Return an enumerated dc_link. 1832 * dc_link order is constant and determined at 1833 * boot time. They cannot be created or destroyed. 1834 * Use dc_get_caps() to get number of links. 1835 */ 1836 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1837 1838 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1839 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1840 const struct dc_link *link, 1841 unsigned int *inst_out); 1842 1843 /* Return an array of link pointers to edp links. */ 1844 void dc_get_edp_links(const struct dc *dc, 1845 struct dc_link **edp_links, 1846 int *edp_num); 1847 1848 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1849 bool powerOn); 1850 1851 /* The function initiates detection handshake over the given link. It first 1852 * determines if there are display connections over the link. If so it initiates 1853 * detection protocols supported by the connected receiver device. The function 1854 * contains protocol specific handshake sequences which are sometimes mandatory 1855 * to establish a proper connection between TX and RX. So it is always 1856 * recommended to call this function as the first link operation upon HPD event 1857 * or power up event. Upon completion, the function will update link structure 1858 * in place based on latest RX capabilities. The function may also cause dpms 1859 * to be reset to off for all currently enabled streams to the link. It is DM's 1860 * responsibility to serialize detection and DPMS updates. 1861 * 1862 * @reason - Indicate which event triggers this detection. dc may customize 1863 * detection flow depending on the triggering events. 1864 * return false - if detection is not fully completed. This could happen when 1865 * there is an unrecoverable error during detection or detection is partially 1866 * completed (detection has been delegated to dm mst manager ie. 1867 * link->connection_type == dc_connection_mst_branch when returning false). 1868 * return true - detection is completed, link has been fully updated with latest 1869 * detection result. 1870 */ 1871 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1872 1873 struct dc_sink_init_data; 1874 1875 /* When link connection type is dc_connection_mst_branch, remote sink can be 1876 * added to the link. The interface creates a remote sink and associates it with 1877 * current link. The sink will be retained by link until remove remote sink is 1878 * called. 1879 * 1880 * @dc_link - link the remote sink will be added to. 1881 * @edid - byte array of EDID raw data. 1882 * @len - size of the edid in byte 1883 * @init_data - 1884 */ 1885 struct dc_sink *dc_link_add_remote_sink( 1886 struct dc_link *dc_link, 1887 const uint8_t *edid, 1888 int len, 1889 struct dc_sink_init_data *init_data); 1890 1891 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1892 * @link - link the sink should be removed from 1893 * @sink - sink to be removed. 1894 */ 1895 void dc_link_remove_remote_sink( 1896 struct dc_link *link, 1897 struct dc_sink *sink); 1898 1899 /* Enable HPD interrupt handler for a given link */ 1900 void dc_link_enable_hpd(const struct dc_link *link); 1901 1902 /* Disable HPD interrupt handler for a given link */ 1903 void dc_link_disable_hpd(const struct dc_link *link); 1904 1905 /* determine if there is a sink connected to the link 1906 * 1907 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1908 * return - false if an unexpected error occurs, true otherwise. 1909 * 1910 * NOTE: This function doesn't detect downstream sink connections i.e 1911 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1912 * return dc_connection_single if the branch device is connected despite of 1913 * downstream sink's connection status. 1914 */ 1915 bool dc_link_detect_connection_type(struct dc_link *link, 1916 enum dc_connection_type *type); 1917 1918 /* query current hpd pin value 1919 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1920 * 1921 */ 1922 bool dc_link_get_hpd_state(struct dc_link *link); 1923 1924 /* Getter for cached link status from given link */ 1925 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1926 1927 /* enable/disable hardware HPD filter. 1928 * 1929 * @link - The link the HPD pin is associated with. 1930 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1931 * handler once after no HPD change has been detected within dc default HPD 1932 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1933 * pulses within default HPD interval, no HPD event will be received until HPD 1934 * toggles have stopped. Then HPD event will be queued to irq handler once after 1935 * dc default HPD filtering interval since last HPD event. 1936 * 1937 * @enable = false - disable hardware HPD filter. HPD event will be queued 1938 * immediately to irq handler after no HPD change has been detected within 1939 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1940 */ 1941 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1942 1943 /* submit i2c read/write payloads through ddc channel 1944 * @link_index - index to a link with ddc in i2c mode 1945 * @cmd - i2c command structure 1946 * return - true if success, false otherwise. 1947 */ 1948 bool dc_submit_i2c( 1949 struct dc *dc, 1950 uint32_t link_index, 1951 struct i2c_command *cmd); 1952 1953 /* submit i2c read/write payloads through oem channel 1954 * @link_index - index to a link with ddc in i2c mode 1955 * @cmd - i2c command structure 1956 * return - true if success, false otherwise. 1957 */ 1958 bool dc_submit_i2c_oem( 1959 struct dc *dc, 1960 struct i2c_command *cmd); 1961 1962 enum aux_return_code_type; 1963 /* Attempt to transfer the given aux payload. This function does not perform 1964 * retries or handle error states. The reply is returned in the payload->reply 1965 * and the result through operation_result. Returns the number of bytes 1966 * transferred,or -1 on a failure. 1967 */ 1968 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1969 struct aux_payload *payload, 1970 enum aux_return_code_type *operation_result); 1971 1972 struct ddc_service * 1973 dc_get_oem_i2c_device(struct dc *dc); 1974 1975 bool dc_is_oem_i2c_device_present( 1976 struct dc *dc, 1977 size_t slave_address 1978 ); 1979 1980 /* return true if the connected receiver supports the hdcp version */ 1981 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1982 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1983 1984 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1985 * 1986 * TODO - When defer_handling is true the function will have a different purpose. 1987 * It no longer does complete hpd rx irq handling. We should create a separate 1988 * interface specifically for this case. 1989 * 1990 * Return: 1991 * true - Downstream port status changed. DM should call DC to do the 1992 * detection. 1993 * false - no change in Downstream port status. No further action required 1994 * from DM. 1995 */ 1996 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1997 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1998 bool defer_handling, bool *has_left_work); 1999 /* handle DP specs define test automation sequence*/ 2000 void dc_link_dp_handle_automated_test(struct dc_link *link); 2001 2002 /* handle DP Link loss sequence and try to recover RX link loss with best 2003 * effort 2004 */ 2005 void dc_link_dp_handle_link_loss(struct dc_link *link); 2006 2007 /* Determine if hpd rx irq should be handled or ignored 2008 * return true - hpd rx irq should be handled. 2009 * return false - it is safe to ignore hpd rx irq event 2010 */ 2011 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 2012 2013 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 2014 * @link - link the hpd irq data associated with 2015 * @hpd_irq_dpcd_data - input hpd irq data 2016 * return - true if hpd irq data indicates a link lost 2017 */ 2018 bool dc_link_check_link_loss_status(struct dc_link *link, 2019 union hpd_irq_data *hpd_irq_dpcd_data); 2020 2021 /* Read hpd rx irq data from a given link 2022 * @link - link where the hpd irq data should be read from 2023 * @irq_data - output hpd irq data 2024 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2025 * read has failed. 2026 */ 2027 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2028 struct dc_link *link, 2029 union hpd_irq_data *irq_data); 2030 2031 /* The function clears recorded DP RX states in the link. DM should call this 2032 * function when it is resuming from S3 power state to previously connected links. 2033 * 2034 * TODO - in the future we should consider to expand link resume interface to 2035 * support clearing previous rx states. So we don't have to rely on dm to call 2036 * this interface explicitly. 2037 */ 2038 void dc_link_clear_dprx_states(struct dc_link *link); 2039 2040 /* Destruct the mst topology of the link and reset the allocated payload table 2041 * 2042 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2043 * still wants to reset MST topology on an unplug event */ 2044 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2045 2046 /* The function calculates effective DP link bandwidth when a given link is 2047 * using the given link settings. 2048 * 2049 * return - total effective link bandwidth in kbps. 2050 */ 2051 uint32_t dc_link_bandwidth_kbps( 2052 const struct dc_link *link, 2053 const struct dc_link_settings *link_setting); 2054 2055 struct dp_audio_bandwidth_params { 2056 const struct dc_crtc_timing *crtc_timing; 2057 enum dp_link_encoding link_encoding; 2058 uint32_t channel_count; 2059 uint32_t sample_rate_hz; 2060 }; 2061 2062 /* The function calculates the minimum size of hblank (in bytes) needed to 2063 * support the specified channel count and sample rate combination, given the 2064 * link encoding and timing to be used. This calculation is not supported 2065 * for 8b/10b SST. 2066 * 2067 * return - min hblank size in bytes, 0 if 8b/10b SST. 2068 */ 2069 uint32_t dc_link_required_hblank_size_bytes( 2070 const struct dc_link *link, 2071 struct dp_audio_bandwidth_params *audio_params); 2072 2073 /* The function takes a snapshot of current link resource allocation state 2074 * @dc: pointer to dc of the dm calling this 2075 * @map: a dc link resource snapshot defined internally to dc. 2076 * 2077 * DM needs to capture a snapshot of current link resource allocation mapping 2078 * and store it in its persistent storage. 2079 * 2080 * Some of the link resource is using first come first serve policy. 2081 * The allocation mapping depends on original hotplug order. This information 2082 * is lost after driver is loaded next time. The snapshot is used in order to 2083 * restore link resource to its previous state so user will get consistent 2084 * link capability allocation across reboot. 2085 * 2086 */ 2087 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2088 2089 /* This function restores link resource allocation state from a snapshot 2090 * @dc: pointer to dc of the dm calling this 2091 * @map: a dc link resource snapshot defined internally to dc. 2092 * 2093 * DM needs to call this function after initial link detection on boot and 2094 * before first commit streams to restore link resource allocation state 2095 * from previous boot session. 2096 * 2097 * Some of the link resource is using first come first serve policy. 2098 * The allocation mapping depends on original hotplug order. This information 2099 * is lost after driver is loaded next time. The snapshot is used in order to 2100 * restore link resource to its previous state so user will get consistent 2101 * link capability allocation across reboot. 2102 * 2103 */ 2104 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2105 2106 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2107 * interface i.e stream_update->dsc_config 2108 */ 2109 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2110 2111 /* translate a raw link rate data to bandwidth in kbps */ 2112 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2113 2114 /* determine the optimal bandwidth given link and required bw. 2115 * @link - current detected link 2116 * @req_bw - requested bandwidth in kbps 2117 * @link_settings - returned most optimal link settings that can fit the 2118 * requested bandwidth 2119 * return - false if link can't support requested bandwidth, true if link 2120 * settings is found. 2121 */ 2122 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2123 struct dc_link_settings *link_settings, 2124 uint32_t req_bw); 2125 2126 /* return the max dp link settings can be driven by the link without considering 2127 * connected RX device and its capability 2128 */ 2129 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2130 struct dc_link_settings *max_link_enc_cap); 2131 2132 /* determine when the link is driving MST mode, what DP link channel coding 2133 * format will be used. The decision will remain unchanged until next HPD event. 2134 * 2135 * @link - a link with DP RX connection 2136 * return - if stream is committed to this link with MST signal type, type of 2137 * channel coding format dc will choose. 2138 */ 2139 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2140 const struct dc_link *link); 2141 2142 /* get max dp link settings the link can enable with all things considered. (i.e 2143 * TX/RX/Cable capabilities and dp override policies. 2144 * 2145 * @link - a link with DP RX connection 2146 * return - max dp link settings the link can enable. 2147 * 2148 */ 2149 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2150 2151 /* Get the highest encoding format that the link supports; highest meaning the 2152 * encoding format which supports the maximum bandwidth. 2153 * 2154 * @link - a link with DP RX connection 2155 * return - highest encoding format link supports. 2156 */ 2157 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2158 2159 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2160 * to a link with dp connector signal type. 2161 * @link - a link with dp connector signal type 2162 * return - true if connected, false otherwise 2163 */ 2164 bool dc_link_is_dp_sink_present(struct dc_link *link); 2165 2166 /* Force DP lane settings update to main-link video signal and notify the change 2167 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2168 * tuning purpose. The interface assumes link has already been enabled with DP 2169 * signal. 2170 * 2171 * @lt_settings - a container structure with desired hw_lane_settings 2172 */ 2173 void dc_link_set_drive_settings(struct dc *dc, 2174 struct link_training_settings *lt_settings, 2175 struct dc_link *link); 2176 2177 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2178 * test or debugging purpose. The test pattern will remain until next un-plug. 2179 * 2180 * @link - active link with DP signal output enabled. 2181 * @test_pattern - desired test pattern to output. 2182 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2183 * @test_pattern_color_space - for video test pattern choose a desired color 2184 * space. 2185 * @p_link_settings - For PHY pattern choose a desired link settings 2186 * @p_custom_pattern - some test pattern will require a custom input to 2187 * customize some pattern details. Otherwise keep it to NULL. 2188 * @cust_pattern_size - size of the custom pattern input. 2189 * 2190 */ 2191 bool dc_link_dp_set_test_pattern( 2192 struct dc_link *link, 2193 enum dp_test_pattern test_pattern, 2194 enum dp_test_pattern_color_space test_pattern_color_space, 2195 const struct link_training_settings *p_link_settings, 2196 const unsigned char *p_custom_pattern, 2197 unsigned int cust_pattern_size); 2198 2199 /* Force DP link settings to always use a specific value until reboot to a 2200 * specific link. If link has already been enabled, the interface will also 2201 * switch to desired link settings immediately. This is a debug interface to 2202 * generic dp issue trouble shooting. 2203 */ 2204 void dc_link_set_preferred_link_settings(struct dc *dc, 2205 struct dc_link_settings *link_setting, 2206 struct dc_link *link); 2207 2208 /* Force DP link to customize a specific link training behavior by overriding to 2209 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2210 * display specific link training issues or apply some display specific 2211 * workaround in link training. 2212 * 2213 * @link_settings - if not NULL, force preferred link settings to the link. 2214 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2215 * will apply this particular override in future link training. If NULL is 2216 * passed in, dc resets previous overrides. 2217 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2218 * training settings. 2219 */ 2220 void dc_link_set_preferred_training_settings(struct dc *dc, 2221 struct dc_link_settings *link_setting, 2222 struct dc_link_training_overrides *lt_overrides, 2223 struct dc_link *link, 2224 bool skip_immediate_retrain); 2225 2226 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2227 bool dc_link_is_fec_supported(const struct dc_link *link); 2228 2229 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2230 * link enablement. 2231 * return - true if FEC should be enabled, false otherwise. 2232 */ 2233 bool dc_link_should_enable_fec(const struct dc_link *link); 2234 2235 /* determine lttpr mode the current link should be enabled with a specific link 2236 * settings. 2237 */ 2238 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2239 struct dc_link_settings *link_setting); 2240 2241 /* Force DP RX to update its power state. 2242 * NOTE: this interface doesn't update dp main-link. Calling this function will 2243 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2244 * RX power state back upon finish DM specific execution requiring DP RX in a 2245 * specific power state. 2246 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2247 * state. 2248 */ 2249 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2250 2251 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2252 * current value read from extended receiver cap from 02200h - 0220Fh. 2253 * Some DP RX has problems of providing accurate DP receiver caps from extended 2254 * field, this interface is a workaround to revert link back to use base caps. 2255 */ 2256 void dc_link_overwrite_extended_receiver_cap( 2257 struct dc_link *link); 2258 2259 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2260 bool wait_for_hpd); 2261 2262 /* Set backlight level of an embedded panel (eDP, LVDS). 2263 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2264 * and 16 bit fractional, where 1.0 is max backlight value. 2265 */ 2266 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2267 struct set_backlight_level_params *backlight_level_params); 2268 2269 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2270 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2271 bool isHDR, 2272 uint32_t backlight_millinits, 2273 uint32_t transition_time_in_ms); 2274 2275 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2276 uint32_t *backlight_millinits, 2277 uint32_t *backlight_millinits_peak); 2278 2279 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2280 2281 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2282 2283 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2284 bool wait, bool force_static, const unsigned int *power_opts); 2285 2286 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2287 2288 bool dc_link_setup_psr(struct dc_link *dc_link, 2289 const struct dc_stream_state *stream, struct psr_config *psr_config, 2290 struct psr_context *psr_context); 2291 2292 /* 2293 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2294 * 2295 * @link: pointer to the dc_link struct instance 2296 * @enable: enable(active) or disable(inactive) replay 2297 * @wait: state transition need to wait the active set completed. 2298 * @force_static: force disable(inactive) the replay 2299 * @power_opts: set power optimazation parameters to DMUB. 2300 * 2301 * return: allow Replay active will return true, else will return false. 2302 */ 2303 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2304 bool wait, bool force_static, const unsigned int *power_opts); 2305 2306 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2307 2308 /* On eDP links this function call will stall until T12 has elapsed. 2309 * If the panel is not in power off state, this function will return 2310 * immediately. 2311 */ 2312 bool dc_link_wait_for_t12(struct dc_link *link); 2313 2314 /* Determine if dp trace has been initialized to reflect upto date result * 2315 * return - true if trace is initialized and has valid data. False dp trace 2316 * doesn't have valid result. 2317 */ 2318 bool dc_dp_trace_is_initialized(struct dc_link *link); 2319 2320 /* Query a dp trace flag to indicate if the current dp trace data has been 2321 * logged before 2322 */ 2323 bool dc_dp_trace_is_logged(struct dc_link *link, 2324 bool in_detection); 2325 2326 /* Set dp trace flag to indicate whether DM has already logged the current dp 2327 * trace data. DM can set is_logged to true upon logging and check 2328 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2329 */ 2330 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2331 bool in_detection, 2332 bool is_logged); 2333 2334 /* Obtain driver time stamp for last dp link training end. The time stamp is 2335 * formatted based on dm_get_timestamp DM function. 2336 * @in_detection - true to get link training end time stamp of last link 2337 * training in detection sequence. false to get link training end time stamp 2338 * of last link training in commit (dpms) sequence 2339 */ 2340 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2341 bool in_detection); 2342 2343 /* Get how many link training attempts dc has done with latest sequence. 2344 * @in_detection - true to get link training count of last link 2345 * training in detection sequence. false to get link training count of last link 2346 * training in commit (dpms) sequence 2347 */ 2348 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2349 bool in_detection); 2350 2351 /* Get how many link loss has happened since last link training attempts */ 2352 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2353 2354 /* 2355 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2356 */ 2357 /* 2358 * Send a request from DP-Tx requesting to allocate BW remotely after 2359 * allocating it locally. This will get processed by CM and a CB function 2360 * will be called. 2361 * 2362 * @link: pointer to the dc_link struct instance 2363 * @req_bw: The requested bw in Kbyte to allocated 2364 * 2365 * return: none 2366 */ 2367 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2368 2369 /* 2370 * Handle the USB4 BW Allocation related functionality here: 2371 * Plug => Try to allocate max bw from timing parameters supported by the sink 2372 * Unplug => de-allocate bw 2373 * 2374 * @link: pointer to the dc_link struct instance 2375 * @peak_bw: Peak bw used by the link/sink 2376 * 2377 */ 2378 void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2379 struct dc_link *link, int peak_bw); 2380 2381 /* 2382 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2383 * available BW for each host router 2384 * 2385 * @dc: pointer to dc struct 2386 * @stream: pointer to all possible streams 2387 * @count: number of valid DPIA streams 2388 * 2389 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2390 */ 2391 bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams, 2392 const unsigned int count); 2393 2394 /* Sink Interfaces - A sink corresponds to a display output device */ 2395 2396 struct dc_container_id { 2397 // 128bit GUID in binary form 2398 unsigned char guid[16]; 2399 // 8 byte port ID -> ELD.PortID 2400 unsigned int portId[2]; 2401 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2402 unsigned short manufacturerName; 2403 // 2 byte product code -> ELD.ProductCode 2404 unsigned short productCode; 2405 }; 2406 2407 2408 struct dc_sink_dsc_caps { 2409 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2410 // 'false' if they are sink's DSC caps 2411 bool is_virtual_dpcd_dsc; 2412 // 'true' if MST topology supports DSC passthrough for sink 2413 // 'false' if MST topology does not support DSC passthrough 2414 bool is_dsc_passthrough_supported; 2415 struct dsc_dec_dpcd_caps dsc_dec_caps; 2416 }; 2417 2418 struct dc_sink_hblank_expansion_caps { 2419 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 2420 // 'false' if they are sink's HBlank expansion caps 2421 bool is_virtual_dpcd_hblank_expansion; 2422 struct hblank_expansion_dpcd_caps dpcd_caps; 2423 }; 2424 2425 struct dc_sink_fec_caps { 2426 bool is_rx_fec_supported; 2427 bool is_topology_fec_supported; 2428 }; 2429 2430 struct scdc_caps { 2431 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2432 union hdmi_scdc_device_id_data device_id; 2433 }; 2434 2435 /* 2436 * The sink structure contains EDID and other display device properties 2437 */ 2438 struct dc_sink { 2439 enum signal_type sink_signal; 2440 struct dc_edid dc_edid; /* raw edid */ 2441 struct dc_edid_caps edid_caps; /* parse display caps */ 2442 struct dc_container_id *dc_container_id; 2443 uint32_t dongle_max_pix_clk; 2444 void *priv; 2445 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2446 bool converter_disable_audio; 2447 2448 struct scdc_caps scdc_caps; 2449 struct dc_sink_dsc_caps dsc_caps; 2450 struct dc_sink_fec_caps fec_caps; 2451 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 2452 2453 bool is_vsc_sdp_colorimetry_supported; 2454 2455 /* private to DC core */ 2456 struct dc_link *link; 2457 struct dc_context *ctx; 2458 2459 uint32_t sink_id; 2460 2461 /* private to dc_sink.c */ 2462 // refcount must be the last member in dc_sink, since we want the 2463 // sink structure to be logically cloneable up to (but not including) 2464 // refcount 2465 struct kref refcount; 2466 }; 2467 2468 void dc_sink_retain(struct dc_sink *sink); 2469 void dc_sink_release(struct dc_sink *sink); 2470 2471 struct dc_sink_init_data { 2472 enum signal_type sink_signal; 2473 struct dc_link *link; 2474 uint32_t dongle_max_pix_clk; 2475 bool converter_disable_audio; 2476 }; 2477 2478 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2479 2480 /* Newer interfaces */ 2481 struct dc_cursor { 2482 struct dc_plane_address address; 2483 struct dc_cursor_attributes attributes; 2484 }; 2485 2486 2487 /* Interrupt interfaces */ 2488 enum dc_irq_source dc_interrupt_to_irq_source( 2489 struct dc *dc, 2490 uint32_t src_id, 2491 uint32_t ext_id); 2492 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2493 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2494 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2495 struct dc *dc, uint32_t link_index); 2496 2497 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2498 2499 /* Power Interfaces */ 2500 2501 void dc_set_power_state( 2502 struct dc *dc, 2503 enum dc_acpi_cm_power_state power_state); 2504 void dc_resume(struct dc *dc); 2505 2506 void dc_power_down_on_boot(struct dc *dc); 2507 2508 /* 2509 * HDCP Interfaces 2510 */ 2511 enum hdcp_message_status dc_process_hdcp_msg( 2512 enum signal_type signal, 2513 struct dc_link *link, 2514 struct hdcp_protection_message *message_info); 2515 bool dc_is_dmcu_initialized(struct dc *dc); 2516 2517 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2518 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2519 2520 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 2521 unsigned int pitch, 2522 unsigned int height, 2523 enum surface_pixel_format format, 2524 struct dc_cursor_attributes *cursor_attr); 2525 2526 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 2527 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 2528 2529 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 2530 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 2531 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2532 2533 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2534 void dc_unlock_memory_clock_frequency(struct dc *dc); 2535 2536 /* set min memory clock to the min required for current mode, max to maxDPM */ 2537 void dc_lock_memory_clock_frequency(struct dc *dc); 2538 2539 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2540 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2541 2542 /* cleanup on driver unload */ 2543 void dc_hardware_release(struct dc *dc); 2544 2545 /* disables fw based mclk switch */ 2546 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2547 2548 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2549 2550 bool dc_set_replay_allow_active(struct dc *dc, bool active); 2551 2552 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 2553 2554 void dc_z10_restore(const struct dc *dc); 2555 void dc_z10_save_init(struct dc *dc); 2556 2557 bool dc_is_dmub_outbox_supported(struct dc *dc); 2558 bool dc_enable_dmub_notifications(struct dc *dc); 2559 2560 bool dc_abm_save_restore( 2561 struct dc *dc, 2562 struct dc_stream_state *stream, 2563 struct abm_save_restore *pData); 2564 2565 void dc_enable_dmub_outbox(struct dc *dc); 2566 2567 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2568 uint32_t link_index, 2569 struct aux_payload *payload); 2570 2571 /* Get dc link index from dpia port index */ 2572 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2573 uint8_t dpia_port_index); 2574 2575 bool dc_process_dmub_set_config_async(struct dc *dc, 2576 uint32_t link_index, 2577 struct set_config_cmd_payload *payload, 2578 struct dmub_notification *notify); 2579 2580 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2581 uint32_t link_index, 2582 uint8_t mst_alloc_slots, 2583 uint8_t *mst_slots_in_use); 2584 2585 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 2586 2587 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2588 uint32_t hpd_int_enable); 2589 2590 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2591 2592 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2593 2594 struct dc_power_profile { 2595 int power_level; /* Lower is better */ 2596 }; 2597 2598 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2599 2600 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 2601 2602 bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index); 2603 2604 /* DSC Interfaces */ 2605 #include "dc_dsc.h" 2606 2607 void dc_get_visual_confirm_for_stream( 2608 struct dc *dc, 2609 struct dc_stream_state *stream_state, 2610 struct tg_color *color); 2611 2612 /* Disable acc mode Interfaces */ 2613 void dc_disable_accelerated_mode(struct dc *dc); 2614 2615 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2616 struct dc_stream_state *new_stream); 2617 2618 bool dc_is_cursor_limit_pending(struct dc *dc); 2619 bool dc_can_clear_cursor_limit(struct dc *dc); 2620 2621 #endif /* DC_INTERFACE_H_ */ 2622