1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/irq.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/pci.h> 14 #include <linux/platform_device.h> 15 #include <linux/if_vlan.h> 16 #include <linux/crash_dump.h> 17 18 #include <net/rtnetlink.h> 19 #include "hclge_cmd.h" 20 #include "hclge_dcb.h" 21 #include "hclge_fd.h" 22 #include "hclge_main.h" 23 #include "hclge_mbx.h" 24 #include "hclge_mdio.h" 25 #include "hclge_regs.h" 26 #include "hclge_tm.h" 27 #include "hclge_err.h" 28 #include "hnae3.h" 29 #include "hclge_devlink.h" 30 #include "hclge_comm_cmd.h" 31 32 #include "hclge_trace.h" 33 34 #define HCLGE_NAME "hclge" 35 36 #define HCLGE_BUF_SIZE_UNIT 256U 37 #define HCLGE_BUF_MUL_BY 2 38 #define HCLGE_BUF_DIV_BY 2 39 #define NEED_RESERVE_TC_NUM 2 40 #define BUF_MAX_PERCENT 100 41 #define BUF_RESERVE_PERCENT 90 42 43 #define HCLGE_RESET_MAX_FAIL_CNT 5 44 #define HCLGE_RESET_SYNC_TIME 100 45 #define HCLGE_PF_RESET_SYNC_TIME 20 46 #define HCLGE_PF_RESET_SYNC_CNT 1500 47 48 #define HCLGE_LINK_STATUS_MS 10 49 50 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 51 static int hclge_init_vlan_config(struct hclge_dev *hdev); 52 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 53 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 54 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 55 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 56 unsigned long *addr); 57 static int hclge_set_default_loopback(struct hclge_dev *hdev); 58 59 static void hclge_sync_mac_table(struct hclge_dev *hdev); 60 static void hclge_restore_hw_table(struct hclge_dev *hdev); 61 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 62 static void hclge_update_fec_stats(struct hclge_dev *hdev); 63 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 64 int wait_cnt); 65 static int hclge_update_port_info(struct hclge_dev *hdev); 66 67 static struct hnae3_ae_algo ae_algo; 68 69 static struct workqueue_struct *hclge_wq; 70 71 static const struct pci_device_id ae_algo_pci_tbl[] = { 72 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE) }, 73 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE) }, 74 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA) }, 75 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC) }, 76 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA) }, 77 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC) }, 78 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC) }, 79 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA) }, 80 /* required last entry */ 81 { } 82 }; 83 84 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 85 86 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 87 "External Loopback test", 88 "App Loopback test", 89 "Serdes serial Loopback test", 90 "Serdes parallel Loopback test", 91 "Phy Loopback test" 92 }; 93 94 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 95 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 96 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 97 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 98 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 99 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 100 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 101 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 102 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 103 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 104 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 105 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 106 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 107 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 108 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 109 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 110 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 111 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 112 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 113 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 114 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 115 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 116 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 117 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 118 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 119 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 120 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 121 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 122 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 123 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 124 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 125 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 126 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 127 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 128 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 129 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 130 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 131 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 132 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 133 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 134 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 135 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 136 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 137 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 138 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 139 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 140 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 141 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 142 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 143 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 144 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 145 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 146 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 147 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 148 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 149 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 150 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 151 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 152 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 153 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 154 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 155 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 156 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 157 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 158 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 159 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 160 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 161 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 162 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 163 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 164 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 165 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 166 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 167 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 168 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 169 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 170 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 171 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 172 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 173 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 174 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 175 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 176 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 177 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 178 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 179 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 180 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 181 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 182 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 183 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 184 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 185 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 186 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 187 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 188 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 189 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 190 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 191 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 192 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 193 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 194 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 195 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 196 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 197 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 198 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 199 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 200 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 201 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 202 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 203 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 204 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 205 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 206 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 207 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 208 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 209 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 210 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 211 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 212 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 213 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 214 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 215 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 216 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 217 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 218 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 219 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 220 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 221 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 222 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 223 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 224 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 225 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 226 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 227 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 228 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 229 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 230 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 231 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 232 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 233 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 234 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 235 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 236 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 237 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 238 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 239 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 240 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 241 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 242 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 243 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 244 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 245 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 246 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 247 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 248 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 249 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 250 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 251 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 253 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 255 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 257 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 259 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 261 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 262 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 263 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 264 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 265 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 266 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 267 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 268 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 269 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 270 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 271 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 272 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 273 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 274 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 275 276 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 278 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 280 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 282 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 284 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 286 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 288 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 289 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 290 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 291 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 292 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 293 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 294 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 295 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 296 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 298 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 300 }; 301 302 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 303 { 304 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 305 .ethter_type = cpu_to_le16(ETH_P_LLDP), 306 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 307 .i_port_bitmap = 0x1, 308 }, 309 }; 310 311 /** 312 * hclge_cmd_send - send command to command queue 313 * @hw: pointer to the hw struct 314 * @desc: prefilled descriptor for describing the command 315 * @num : the number of descriptors to be sent 316 * 317 * This is the main send command for command queue, it 318 * sends the queue, cleans the queue, etc 319 **/ 320 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 321 { 322 return hclge_comm_cmd_send(&hw->hw, desc, num); 323 } 324 325 static void hclge_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, 326 int num, bool is_special) 327 { 328 int i; 329 330 trace_hclge_pf_cmd_send(hw, desc, 0, num); 331 332 if (!is_special) { 333 for (i = 1; i < num; i++) 334 trace_hclge_pf_cmd_send(hw, &desc[i], i, num); 335 } else { 336 for (i = 1; i < num; i++) 337 trace_hclge_pf_special_cmd_send(hw, (__le32 *)&desc[i], 338 i, num); 339 } 340 } 341 342 static void hclge_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc, 343 int num, bool is_special) 344 { 345 int i; 346 347 if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) 348 return; 349 350 trace_hclge_pf_cmd_get(hw, desc, 0, num); 351 352 if (!is_special) { 353 for (i = 1; i < num; i++) 354 trace_hclge_pf_cmd_get(hw, &desc[i], i, num); 355 } else { 356 for (i = 1; i < num; i++) 357 trace_hclge_pf_special_cmd_get(hw, (__le32 *)&desc[i], 358 i, num); 359 } 360 } 361 362 static const struct hclge_comm_cmq_ops hclge_cmq_ops = { 363 .trace_cmd_send = hclge_trace_cmd_send, 364 .trace_cmd_get = hclge_trace_cmd_get, 365 }; 366 367 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 368 { 369 #define HCLGE_MAC_CMD_NUM 21 370 371 u64 *data = (u64 *)(&hdev->mac_stats); 372 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 373 __le64 *desc_data; 374 u32 data_size; 375 int ret; 376 u32 i; 377 378 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 379 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 380 if (ret) { 381 dev_err(&hdev->pdev->dev, 382 "Get MAC pkt stats fail, status = %d.\n", ret); 383 384 return ret; 385 } 386 387 /* The first desc has a 64-bit header, so data size need to minus 1 */ 388 data_size = sizeof(desc) / (sizeof(u64)) - 1; 389 390 desc_data = (__le64 *)(&desc[0].data[0]); 391 for (i = 0; i < data_size; i++) { 392 /* data memory is continuous becase only the first desc has a 393 * header in this command 394 */ 395 *data += le64_to_cpu(*desc_data); 396 data++; 397 desc_data++; 398 } 399 400 return 0; 401 } 402 403 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 404 { 405 #define HCLGE_REG_NUM_PER_DESC 4 406 407 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 408 u64 *data = (u64 *)(&hdev->mac_stats); 409 struct hclge_desc *desc; 410 __le64 *desc_data; 411 u32 data_size; 412 u32 desc_num; 413 int ret; 414 u32 i; 415 416 /* The first desc has a 64-bit header, so need to consider it */ 417 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 418 419 /* This may be called inside atomic sections, 420 * so GFP_ATOMIC is more suitable here 421 */ 422 desc = kzalloc_objs(struct hclge_desc, desc_num, GFP_ATOMIC); 423 if (!desc) 424 return -ENOMEM; 425 426 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 427 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 428 if (ret) { 429 kfree(desc); 430 return ret; 431 } 432 433 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 434 435 desc_data = (__le64 *)(&desc[0].data[0]); 436 for (i = 0; i < data_size; i++) { 437 /* data memory is continuous becase only the first desc has a 438 * header in this command 439 */ 440 *data += le64_to_cpu(*desc_data); 441 data++; 442 desc_data++; 443 } 444 445 kfree(desc); 446 447 return 0; 448 } 449 450 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 451 { 452 struct hclge_desc desc; 453 int ret; 454 455 /* Driver needs total register number of both valid registers and 456 * reserved registers, but the old firmware only returns number 457 * of valid registers in device V2. To be compatible with these 458 * devices, driver uses a fixed value. 459 */ 460 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 461 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 462 return 0; 463 } 464 465 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 466 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 467 if (ret) { 468 dev_err(&hdev->pdev->dev, 469 "failed to query mac statistic reg number, ret = %d\n", 470 ret); 471 return ret; 472 } 473 474 *reg_num = le32_to_cpu(desc.data[0]); 475 if (*reg_num == 0) { 476 dev_err(&hdev->pdev->dev, 477 "mac statistic reg number is invalid!\n"); 478 return -ENODATA; 479 } 480 481 return 0; 482 } 483 484 int hclge_mac_update_stats(struct hclge_dev *hdev) 485 { 486 /* The firmware supports the new statistics acquisition method */ 487 if (hdev->ae_dev->dev_specs.mac_stats_num) 488 return hclge_mac_update_stats_complete(hdev); 489 else 490 return hclge_mac_update_stats_defective(hdev); 491 } 492 493 static int hclge_comm_get_count(struct hclge_dev *hdev, 494 const struct hclge_comm_stats_str strs[], 495 u32 size) 496 { 497 int count = 0; 498 u32 i; 499 500 for (i = 0; i < size; i++) 501 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 502 count++; 503 504 return count; 505 } 506 507 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 508 const struct hclge_comm_stats_str strs[], 509 int size, u64 *data) 510 { 511 u64 *buf = data; 512 int i; 513 514 for (i = 0; i < size; i++) { 515 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 516 continue; 517 518 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 519 buf++; 520 } 521 522 return buf; 523 } 524 525 static void hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 526 const struct hclge_comm_stats_str strs[], 527 int size, u8 **data) 528 { 529 int i; 530 531 if (stringset != ETH_SS_STATS) 532 return; 533 534 for (i = 0; i < size; i++) { 535 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 536 continue; 537 538 ethtool_puts(data, strs[i].desc); 539 } 540 } 541 542 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 543 { 544 struct hnae3_handle *handle; 545 int status; 546 547 handle = &hdev->vport[0].nic; 548 if (handle->client) { 549 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 550 if (status) { 551 dev_err(&hdev->pdev->dev, 552 "Update TQPS stats fail, status = %d.\n", 553 status); 554 } 555 } 556 557 hclge_update_fec_stats(hdev); 558 559 status = hclge_mac_update_stats(hdev); 560 if (status) 561 dev_err(&hdev->pdev->dev, 562 "Update MAC stats fail, status = %d.\n", status); 563 } 564 565 static void hclge_update_stats(struct hnae3_handle *handle) 566 { 567 struct hclge_vport *vport = hclge_get_vport(handle); 568 struct hclge_dev *hdev = vport->back; 569 int status; 570 571 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 572 return; 573 574 status = hclge_mac_update_stats(hdev); 575 if (status) 576 dev_err(&hdev->pdev->dev, 577 "Update MAC stats fail, status = %d.\n", 578 status); 579 580 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 581 if (status) 582 dev_err(&hdev->pdev->dev, 583 "Update TQPS stats fail, status = %d.\n", 584 status); 585 586 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 587 } 588 589 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 590 { 591 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 592 HNAE3_SUPPORT_PHY_LOOPBACK | \ 593 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 594 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 595 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 596 597 struct hclge_vport *vport = hclge_get_vport(handle); 598 struct hclge_dev *hdev = vport->back; 599 int count = 0; 600 601 /* Loopback test support rules: 602 * mac: only GE mode support 603 * serdes: all mac mode will support include GE/XGE/LGE/CGE 604 * phy: only support when phy device exist on board 605 */ 606 if (stringset == ETH_SS_TEST) { 607 /* clear loopback bit flags at first */ 608 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 609 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 610 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 611 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 612 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 613 count += 1; 614 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 615 } 616 617 if (hdev->ae_dev->dev_specs.hilink_version != 618 HCLGE_HILINK_H60) { 619 count += 1; 620 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 621 } 622 623 count += 1; 624 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 625 count += 1; 626 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 627 628 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 629 hdev->hw.mac.phydev->drv->set_loopback) || 630 hnae3_dev_phy_imp_supported(hdev)) { 631 count += 1; 632 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 633 } 634 } else if (stringset == ETH_SS_STATS) { 635 count = hclge_comm_get_count(hdev, g_mac_stats_string, 636 ARRAY_SIZE(g_mac_stats_string)) + 637 hclge_comm_tqps_get_sset_count(handle); 638 } 639 640 return count; 641 } 642 643 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 644 u8 **data) 645 { 646 struct hclge_vport *vport = hclge_get_vport(handle); 647 struct hclge_dev *hdev = vport->back; 648 const char *str; 649 int size; 650 651 if (stringset == ETH_SS_STATS) { 652 size = ARRAY_SIZE(g_mac_stats_string); 653 hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 654 size, data); 655 hclge_comm_tqps_get_strings(handle, data); 656 } else if (stringset == ETH_SS_TEST) { 657 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 658 str = hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL]; 659 ethtool_puts(data, str); 660 } 661 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 662 str = hns3_nic_test_strs[HNAE3_LOOP_APP]; 663 ethtool_puts(data, str); 664 } 665 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 666 str = hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES]; 667 ethtool_puts(data, str); 668 } 669 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 670 str = hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES]; 671 ethtool_puts(data, str); 672 } 673 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 674 str = hns3_nic_test_strs[HNAE3_LOOP_PHY]; 675 ethtool_puts(data, str); 676 } 677 } 678 } 679 680 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 681 { 682 struct hclge_vport *vport = hclge_get_vport(handle); 683 struct hclge_dev *hdev = vport->back; 684 u64 *p; 685 686 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 687 ARRAY_SIZE(g_mac_stats_string), data); 688 p = hclge_comm_tqps_get_stats(handle, p); 689 } 690 691 static void hclge_get_mac_stat(struct hnae3_handle *handle, 692 struct hns3_mac_stats *mac_stats) 693 { 694 struct hclge_vport *vport = hclge_get_vport(handle); 695 struct hclge_dev *hdev = vport->back; 696 697 hclge_update_stats(handle); 698 699 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 700 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 701 } 702 703 static int hclge_parse_func_status(struct hclge_dev *hdev, 704 struct hclge_func_status_cmd *status) 705 { 706 #define HCLGE_MAC_ID_MASK 0xF 707 708 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 709 return -EINVAL; 710 711 /* Set the pf to main pf */ 712 if (status->pf_state & HCLGE_PF_STATE_MAIN) 713 hdev->flag |= HCLGE_FLAG_MAIN; 714 else 715 hdev->flag &= ~HCLGE_FLAG_MAIN; 716 717 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 718 return 0; 719 } 720 721 static int hclge_query_function_status(struct hclge_dev *hdev) 722 { 723 #define HCLGE_QUERY_MAX_CNT 5 724 725 struct hclge_func_status_cmd *req; 726 struct hclge_desc desc; 727 int timeout = 0; 728 int ret; 729 730 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 731 req = (struct hclge_func_status_cmd *)desc.data; 732 733 do { 734 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 735 if (ret) { 736 dev_err(&hdev->pdev->dev, 737 "query function status failed %d.\n", ret); 738 return ret; 739 } 740 741 /* Check pf reset is done */ 742 if (req->pf_state) 743 break; 744 usleep_range(1000, 2000); 745 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 746 747 return hclge_parse_func_status(hdev, req); 748 } 749 750 static int hclge_query_pf_resource(struct hclge_dev *hdev) 751 { 752 struct hclge_pf_res_cmd *req; 753 struct hclge_desc desc; 754 int ret; 755 756 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 757 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 758 if (ret) { 759 dev_err(&hdev->pdev->dev, 760 "query pf resource failed %d.\n", ret); 761 return ret; 762 } 763 764 req = (struct hclge_pf_res_cmd *)desc.data; 765 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 766 le16_to_cpu(req->ext_tqp_num); 767 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 768 769 if (req->tx_buf_size) 770 hdev->tx_buf_size = 771 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 772 else 773 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 774 775 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 776 777 if (req->dv_buf_size) 778 hdev->dv_buf_size = 779 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 780 else 781 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 782 783 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 784 785 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 786 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 787 dev_err(&hdev->pdev->dev, 788 "only %u msi resources available, not enough for pf(min:2).\n", 789 hdev->num_nic_msi); 790 return -EINVAL; 791 } 792 793 if (hnae3_dev_roce_supported(hdev)) { 794 hdev->num_roce_msi = 795 le16_to_cpu(req->pf_intr_vector_number_roce); 796 797 /* PF should have NIC vectors and Roce vectors, 798 * NIC vectors are queued before Roce vectors. 799 */ 800 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 801 } else { 802 hdev->num_msi = hdev->num_nic_msi; 803 } 804 805 return 0; 806 } 807 808 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 809 { 810 switch (speed_cmd) { 811 case HCLGE_FW_MAC_SPEED_10M: 812 *speed = HCLGE_MAC_SPEED_10M; 813 break; 814 case HCLGE_FW_MAC_SPEED_100M: 815 *speed = HCLGE_MAC_SPEED_100M; 816 break; 817 case HCLGE_FW_MAC_SPEED_1G: 818 *speed = HCLGE_MAC_SPEED_1G; 819 break; 820 case HCLGE_FW_MAC_SPEED_10G: 821 *speed = HCLGE_MAC_SPEED_10G; 822 break; 823 case HCLGE_FW_MAC_SPEED_25G: 824 *speed = HCLGE_MAC_SPEED_25G; 825 break; 826 case HCLGE_FW_MAC_SPEED_40G: 827 *speed = HCLGE_MAC_SPEED_40G; 828 break; 829 case HCLGE_FW_MAC_SPEED_50G: 830 *speed = HCLGE_MAC_SPEED_50G; 831 break; 832 case HCLGE_FW_MAC_SPEED_100G: 833 *speed = HCLGE_MAC_SPEED_100G; 834 break; 835 case HCLGE_FW_MAC_SPEED_200G: 836 *speed = HCLGE_MAC_SPEED_200G; 837 break; 838 default: 839 return -EINVAL; 840 } 841 842 return 0; 843 } 844 845 static const struct hclge_speed_bit_map speed_bit_map[] = { 846 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 847 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 848 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 849 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 850 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 851 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 852 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS}, 853 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS}, 854 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BITS}, 855 }; 856 857 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 858 { 859 u16 i; 860 861 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 862 if (speed == speed_bit_map[i].speed) { 863 *speed_bit = speed_bit_map[i].speed_bit; 864 return 0; 865 } 866 } 867 868 return -EINVAL; 869 } 870 871 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 872 { 873 struct hclge_vport *vport = hclge_get_vport(handle); 874 struct hclge_dev *hdev = vport->back; 875 u32 speed_ability = hdev->hw.mac.speed_ability; 876 u32 speed_bit = 0; 877 int ret; 878 879 ret = hclge_get_speed_bit(speed, &speed_bit); 880 if (ret) 881 return ret; 882 883 if (speed_bit & speed_ability) 884 return 0; 885 886 return -EINVAL; 887 } 888 889 static void hclge_update_fec_support(struct hclge_mac *mac) 890 { 891 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 892 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 893 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 894 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 895 896 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 897 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 898 mac->supported); 899 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 900 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 901 mac->supported); 902 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 903 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 904 mac->supported); 905 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 906 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 907 mac->supported); 908 } 909 910 static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[] = { 911 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT}, 912 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT}, 913 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT}, 914 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT}, 915 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT}, 916 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT}, 917 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT}, 918 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 919 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 920 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 921 }; 922 923 static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[] = { 924 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT}, 925 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT}, 926 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT}, 927 {HCLGE_SUPPORT_100G_R4_BIT, 928 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT}, 929 {HCLGE_SUPPORT_100G_R2_BIT, 930 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT}, 931 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 932 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 933 {HCLGE_SUPPORT_200G_R4_BIT, 934 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 935 }; 936 937 static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[] = { 938 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT}, 939 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT}, 940 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT}, 941 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT}, 942 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT}, 943 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT}, 944 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT}, 945 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 946 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 947 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 948 }; 949 950 static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[] = { 951 {HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT}, 952 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT}, 953 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT}, 954 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT}, 955 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT}, 956 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT}, 957 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT}, 958 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT}, 959 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 960 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 961 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 962 }; 963 964 static void hclge_convert_setting_sr(u16 speed_ability, 965 unsigned long *link_mode) 966 { 967 int i; 968 969 for (i = 0; i < ARRAY_SIZE(hclge_sr_link_mode_bmap); i++) { 970 if (speed_ability & hclge_sr_link_mode_bmap[i].support_bit) 971 linkmode_set_bit(hclge_sr_link_mode_bmap[i].link_mode, 972 link_mode); 973 } 974 } 975 976 static void hclge_convert_setting_lr(u16 speed_ability, 977 unsigned long *link_mode) 978 { 979 int i; 980 981 for (i = 0; i < ARRAY_SIZE(hclge_lr_link_mode_bmap); i++) { 982 if (speed_ability & hclge_lr_link_mode_bmap[i].support_bit) 983 linkmode_set_bit(hclge_lr_link_mode_bmap[i].link_mode, 984 link_mode); 985 } 986 } 987 988 static void hclge_convert_setting_cr(u16 speed_ability, 989 unsigned long *link_mode) 990 { 991 int i; 992 993 for (i = 0; i < ARRAY_SIZE(hclge_cr_link_mode_bmap); i++) { 994 if (speed_ability & hclge_cr_link_mode_bmap[i].support_bit) 995 linkmode_set_bit(hclge_cr_link_mode_bmap[i].link_mode, 996 link_mode); 997 } 998 } 999 1000 static void hclge_convert_setting_kr(u16 speed_ability, 1001 unsigned long *link_mode) 1002 { 1003 int i; 1004 1005 for (i = 0; i < ARRAY_SIZE(hclge_kr_link_mode_bmap); i++) { 1006 if (speed_ability & hclge_kr_link_mode_bmap[i].support_bit) 1007 linkmode_set_bit(hclge_kr_link_mode_bmap[i].link_mode, 1008 link_mode); 1009 } 1010 } 1011 1012 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1013 { 1014 /* If firmware has reported fec_ability, don't need to convert by speed */ 1015 if (mac->fec_ability) 1016 goto out; 1017 1018 switch (mac->speed) { 1019 case HCLGE_MAC_SPEED_10G: 1020 case HCLGE_MAC_SPEED_40G: 1021 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1022 BIT(HNAE3_FEC_NONE); 1023 break; 1024 case HCLGE_MAC_SPEED_25G: 1025 case HCLGE_MAC_SPEED_50G: 1026 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1027 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1028 break; 1029 case HCLGE_MAC_SPEED_100G: 1030 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1031 BIT(HNAE3_FEC_NONE); 1032 break; 1033 case HCLGE_MAC_SPEED_200G: 1034 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1035 BIT(HNAE3_FEC_LLRS); 1036 break; 1037 default: 1038 mac->fec_ability = 0; 1039 break; 1040 } 1041 1042 out: 1043 hclge_update_fec_support(mac); 1044 } 1045 1046 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1047 u16 speed_ability) 1048 { 1049 struct hclge_mac *mac = &hdev->hw.mac; 1050 1051 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1052 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1053 mac->supported); 1054 1055 hclge_convert_setting_sr(speed_ability, mac->supported); 1056 hclge_convert_setting_lr(speed_ability, mac->supported); 1057 hclge_convert_setting_cr(speed_ability, mac->supported); 1058 if (hnae3_dev_fec_supported(hdev)) 1059 hclge_convert_setting_fec(mac); 1060 1061 if (hnae3_dev_pause_supported(hdev)) 1062 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1063 1064 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1065 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1066 } 1067 1068 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1069 u16 speed_ability) 1070 { 1071 struct hclge_mac *mac = &hdev->hw.mac; 1072 1073 hclge_convert_setting_kr(speed_ability, mac->supported); 1074 if (hnae3_dev_fec_supported(hdev)) 1075 hclge_convert_setting_fec(mac); 1076 1077 if (hnae3_dev_pause_supported(hdev)) 1078 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1079 1080 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1081 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1082 } 1083 1084 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1085 u16 speed_ability) 1086 { 1087 unsigned long *supported = hdev->hw.mac.supported; 1088 1089 /* default to support all speed for GE port */ 1090 if (!speed_ability) 1091 speed_ability = HCLGE_SUPPORT_GE; 1092 1093 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1094 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1095 supported); 1096 1097 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1098 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1099 supported); 1100 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1101 supported); 1102 } 1103 1104 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1105 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1106 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1107 } 1108 1109 if (hnae3_dev_pause_supported(hdev)) { 1110 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1111 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1112 } 1113 1114 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1115 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1116 } 1117 1118 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1119 { 1120 u8 media_type = hdev->hw.mac.media_type; 1121 1122 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1123 hclge_parse_fiber_link_mode(hdev, speed_ability); 1124 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1125 hclge_parse_copper_link_mode(hdev, speed_ability); 1126 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1127 hclge_parse_backplane_link_mode(hdev, speed_ability); 1128 } 1129 1130 static u32 hclge_get_max_speed(u16 speed_ability) 1131 { 1132 if (speed_ability & HCLGE_SUPPORT_200G_BITS) 1133 return HCLGE_MAC_SPEED_200G; 1134 1135 if (speed_ability & HCLGE_SUPPORT_100G_BITS) 1136 return HCLGE_MAC_SPEED_100G; 1137 1138 if (speed_ability & HCLGE_SUPPORT_50G_BITS) 1139 return HCLGE_MAC_SPEED_50G; 1140 1141 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1142 return HCLGE_MAC_SPEED_40G; 1143 1144 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1145 return HCLGE_MAC_SPEED_25G; 1146 1147 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1148 return HCLGE_MAC_SPEED_10G; 1149 1150 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1151 return HCLGE_MAC_SPEED_1G; 1152 1153 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1154 return HCLGE_MAC_SPEED_100M; 1155 1156 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1157 return HCLGE_MAC_SPEED_10M; 1158 1159 return HCLGE_MAC_SPEED_1G; 1160 } 1161 1162 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1163 { 1164 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1165 #define SPEED_ABILITY_EXT_SHIFT 8 1166 1167 struct hclge_cfg_param_cmd *req; 1168 u64 mac_addr_tmp_high; 1169 u16 speed_ability_ext; 1170 u64 mac_addr_tmp; 1171 unsigned int i; 1172 1173 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1174 1175 /* get the configuration */ 1176 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1177 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1178 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1179 HCLGE_CFG_TQP_DESC_N_M, 1180 HCLGE_CFG_TQP_DESC_N_S); 1181 1182 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1183 HCLGE_CFG_PHY_ADDR_M, 1184 HCLGE_CFG_PHY_ADDR_S); 1185 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1186 HCLGE_CFG_MEDIA_TP_M, 1187 HCLGE_CFG_MEDIA_TP_S); 1188 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1189 HCLGE_CFG_RX_BUF_LEN_M, 1190 HCLGE_CFG_RX_BUF_LEN_S); 1191 /* get mac_address */ 1192 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1193 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1194 HCLGE_CFG_MAC_ADDR_H_M, 1195 HCLGE_CFG_MAC_ADDR_H_S); 1196 1197 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1198 1199 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1200 HCLGE_CFG_DEFAULT_SPEED_M, 1201 HCLGE_CFG_DEFAULT_SPEED_S); 1202 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1203 HCLGE_CFG_RSS_SIZE_M, 1204 HCLGE_CFG_RSS_SIZE_S); 1205 1206 for (i = 0; i < ETH_ALEN; i++) 1207 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1208 1209 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1210 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1211 1212 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1213 HCLGE_CFG_SPEED_ABILITY_M, 1214 HCLGE_CFG_SPEED_ABILITY_S); 1215 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1216 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1217 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1218 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1219 1220 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1221 HCLGE_CFG_VLAN_FLTR_CAP_M, 1222 HCLGE_CFG_VLAN_FLTR_CAP_S); 1223 1224 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1225 HCLGE_CFG_UMV_TBL_SPACE_M, 1226 HCLGE_CFG_UMV_TBL_SPACE_S); 1227 1228 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1229 HCLGE_CFG_PF_RSS_SIZE_M, 1230 HCLGE_CFG_PF_RSS_SIZE_S); 1231 1232 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1233 * power of 2, instead of reading out directly. This would 1234 * be more flexible for future changes and expansions. 1235 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1236 * it does not make sense if PF's field is 0. In this case, PF and VF 1237 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1238 */ 1239 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1240 1U << cfg->pf_rss_size_max : 1241 cfg->vf_rss_size_max; 1242 1243 /* The unit of the tx spare buffer size queried from configuration 1244 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1245 * needed here. 1246 */ 1247 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1248 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1249 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1250 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1251 } 1252 1253 /* hclge_get_cfg: query the static parameter from flash 1254 * @hdev: pointer to struct hclge_dev 1255 * @hcfg: the config structure to be getted 1256 */ 1257 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1258 { 1259 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1260 struct hclge_cfg_param_cmd *req; 1261 unsigned int i; 1262 int ret; 1263 1264 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1265 u32 offset = 0; 1266 1267 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1268 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1269 true); 1270 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1271 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1272 /* Len should be united by 4 bytes when send to hardware */ 1273 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1274 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1275 req->offset = cpu_to_le32(offset); 1276 } 1277 1278 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1279 if (ret) { 1280 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1281 return ret; 1282 } 1283 1284 hclge_parse_cfg(hcfg, desc); 1285 1286 return 0; 1287 } 1288 1289 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1290 { 1291 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1292 1293 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1294 1295 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1296 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1297 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1298 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1299 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1300 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1301 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1302 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1303 ae_dev->dev_specs.tnl_num = 0; 1304 } 1305 1306 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1307 struct hclge_desc *desc) 1308 { 1309 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1310 struct hclge_dev_specs_0_cmd *req0; 1311 struct hclge_dev_specs_1_cmd *req1; 1312 1313 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1314 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1315 1316 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1317 ae_dev->dev_specs.rss_ind_tbl_size = 1318 le16_to_cpu(req0->rss_ind_tbl_size); 1319 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1320 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1321 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1322 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1323 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1324 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1325 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1326 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1327 ae_dev->dev_specs.tnl_num = req1->tnl_num; 1328 ae_dev->dev_specs.hilink_version = req1->hilink_version; 1329 } 1330 1331 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1332 { 1333 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1334 1335 if (!dev_specs->max_non_tso_bd_num) 1336 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1337 if (!dev_specs->rss_ind_tbl_size) 1338 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1339 if (!dev_specs->rss_key_size) 1340 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1341 if (!dev_specs->max_tm_rate) 1342 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1343 if (!dev_specs->max_qset_num) 1344 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1345 if (!dev_specs->max_int_gl) 1346 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1347 if (!dev_specs->max_frm_size) 1348 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1349 if (!dev_specs->umv_size) 1350 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1351 } 1352 1353 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1354 { 1355 u32 reg_num = 0; 1356 int ret; 1357 1358 ret = hclge_mac_query_reg_num(hdev, ®_num); 1359 if (ret && ret != -EOPNOTSUPP) 1360 return ret; 1361 1362 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1363 return 0; 1364 } 1365 1366 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1367 { 1368 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1369 int ret; 1370 int i; 1371 1372 ret = hclge_query_mac_stats_num(hdev); 1373 if (ret) 1374 return ret; 1375 1376 /* set default specifications as devices lower than version V3 do not 1377 * support querying specifications from firmware. 1378 */ 1379 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1380 hclge_set_default_dev_specs(hdev); 1381 return 0; 1382 } 1383 1384 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1385 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1386 true); 1387 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1388 } 1389 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1390 1391 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1392 if (ret) 1393 return ret; 1394 1395 hclge_parse_dev_specs(hdev, desc); 1396 hclge_check_dev_specs(hdev); 1397 1398 return 0; 1399 } 1400 1401 static int hclge_get_cap(struct hclge_dev *hdev) 1402 { 1403 int ret; 1404 1405 ret = hclge_query_function_status(hdev); 1406 if (ret) { 1407 dev_err(&hdev->pdev->dev, 1408 "query function status error %d.\n", ret); 1409 return ret; 1410 } 1411 1412 /* get pf resource */ 1413 return hclge_query_pf_resource(hdev); 1414 } 1415 1416 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1417 { 1418 #define HCLGE_MIN_TX_DESC 64 1419 #define HCLGE_MIN_RX_DESC 64 1420 1421 if (!is_kdump_kernel()) 1422 return; 1423 1424 dev_info(&hdev->pdev->dev, 1425 "Running kdump kernel. Using minimal resources\n"); 1426 1427 /* minimal queue pairs equals to the number of vports */ 1428 hdev->num_tqps = hdev->num_req_vfs + 1; 1429 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1430 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1431 } 1432 1433 static void hclge_init_tc_config(struct hclge_dev *hdev) 1434 { 1435 unsigned int i; 1436 1437 if (hdev->tc_max > HNAE3_MAX_TC || 1438 hdev->tc_max < 1) { 1439 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1440 hdev->tc_max); 1441 hdev->tc_max = 1; 1442 } 1443 1444 /* Dev does not support DCB */ 1445 if (!hnae3_dev_dcb_supported(hdev)) { 1446 hdev->tc_max = 1; 1447 hdev->pfc_max = 0; 1448 } else { 1449 hdev->pfc_max = hdev->tc_max; 1450 } 1451 1452 hdev->tm_info.num_tc = 1; 1453 1454 /* Currently not support uncontiuous tc */ 1455 for (i = 0; i < hdev->tm_info.num_tc; i++) 1456 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1457 1458 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1459 } 1460 1461 static int hclge_configure(struct hclge_dev *hdev) 1462 { 1463 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1464 struct hclge_cfg cfg; 1465 int ret; 1466 1467 ret = hclge_get_cfg(hdev, &cfg); 1468 if (ret) 1469 return ret; 1470 1471 hdev->base_tqp_pid = 0; 1472 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1473 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1474 hdev->rx_buf_len = cfg.rx_buf_len; 1475 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1476 hdev->hw.mac.media_type = cfg.media_type; 1477 hdev->hw.mac.phy_addr = cfg.phy_addr; 1478 hdev->num_tx_desc = cfg.tqp_desc_num; 1479 hdev->num_rx_desc = cfg.tqp_desc_num; 1480 hdev->tm_info.num_pg = 1; 1481 hdev->tc_max = cfg.tc_num; 1482 hdev->tm_info.hw_pfc_map = 0; 1483 if (cfg.umv_space) 1484 hdev->wanted_umv_size = cfg.umv_space; 1485 else 1486 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1487 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1488 hdev->gro_en = true; 1489 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1490 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1491 1492 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1493 hdev->fd_en = true; 1494 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1495 } 1496 1497 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1498 if (ret) { 1499 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1500 cfg.default_speed, ret); 1501 return ret; 1502 } 1503 hdev->hw.mac.req_speed = hdev->hw.mac.speed; 1504 hdev->hw.mac.req_autoneg = AUTONEG_ENABLE; 1505 hdev->hw.mac.req_duplex = DUPLEX_FULL; 1506 1507 /* When lane_num is 0, the firmware will automatically 1508 * select the appropriate lane_num based on the speed. 1509 */ 1510 hdev->hw.mac.req_lane_num = 0; 1511 1512 hclge_parse_link_mode(hdev, cfg.speed_ability); 1513 1514 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1515 1516 hclge_init_tc_config(hdev); 1517 hclge_init_kdump_kernel_config(hdev); 1518 1519 return ret; 1520 } 1521 1522 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1523 u16 tso_mss_max) 1524 { 1525 struct hclge_cfg_tso_status_cmd *req; 1526 struct hclge_desc desc; 1527 1528 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1529 1530 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1531 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1532 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1533 1534 return hclge_cmd_send(&hdev->hw, &desc, 1); 1535 } 1536 1537 static int hclge_config_gro(struct hclge_dev *hdev) 1538 { 1539 struct hclge_cfg_gro_status_cmd *req; 1540 struct hclge_desc desc; 1541 int ret; 1542 1543 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1544 return 0; 1545 1546 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1547 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1548 1549 req->gro_en = hdev->gro_en ? 1 : 0; 1550 1551 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1552 if (ret) 1553 dev_err(&hdev->pdev->dev, 1554 "GRO hardware config cmd failed, ret = %d\n", ret); 1555 1556 return ret; 1557 } 1558 1559 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1560 { 1561 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1562 struct hclge_comm_tqp *tqp; 1563 int i; 1564 1565 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1566 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1567 if (!hdev->htqp) 1568 return -ENOMEM; 1569 1570 tqp = hdev->htqp; 1571 1572 for (i = 0; i < hdev->num_tqps; i++) { 1573 tqp->dev = &hdev->pdev->dev; 1574 tqp->index = i; 1575 1576 tqp->q.ae_algo = &ae_algo; 1577 tqp->q.buf_size = hdev->rx_buf_len; 1578 tqp->q.tx_desc_num = hdev->num_tx_desc; 1579 tqp->q.rx_desc_num = hdev->num_rx_desc; 1580 1581 /* need an extended offset to configure queues >= 1582 * HCLGE_TQP_MAX_SIZE_DEV_V2 1583 */ 1584 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1585 tqp->q.io_base = hdev->hw.hw.io_base + 1586 HCLGE_TQP_REG_OFFSET + 1587 i * HCLGE_TQP_REG_SIZE; 1588 else 1589 tqp->q.io_base = hdev->hw.hw.io_base + 1590 HCLGE_TQP_REG_OFFSET + 1591 HCLGE_TQP_EXT_REG_OFFSET + 1592 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1593 HCLGE_TQP_REG_SIZE; 1594 1595 /* when device supports tx push and has device memory, 1596 * the queue can execute push mode or doorbell mode on 1597 * device memory. 1598 */ 1599 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1600 tqp->q.mem_base = hdev->hw.hw.mem_base + 1601 HCLGE_TQP_MEM_OFFSET(hdev, i); 1602 1603 tqp++; 1604 } 1605 1606 return 0; 1607 } 1608 1609 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1610 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1611 { 1612 struct hclge_tqp_map_cmd *req; 1613 struct hclge_desc desc; 1614 int ret; 1615 1616 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1617 1618 req = (struct hclge_tqp_map_cmd *)desc.data; 1619 req->tqp_id = cpu_to_le16(tqp_pid); 1620 req->tqp_vf = func_id; 1621 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1622 if (!is_pf) 1623 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1624 req->tqp_vid = cpu_to_le16(tqp_vid); 1625 1626 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1627 if (ret) 1628 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1629 1630 return ret; 1631 } 1632 1633 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1634 { 1635 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1636 struct hclge_dev *hdev = vport->back; 1637 int i, alloced; 1638 1639 for (i = 0, alloced = 0; i < hdev->num_tqps && 1640 alloced < num_tqps; i++) { 1641 if (!hdev->htqp[i].alloced) { 1642 hdev->htqp[i].q.handle = &vport->nic; 1643 hdev->htqp[i].q.tqp_index = alloced; 1644 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1645 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1646 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1647 hdev->htqp[i].alloced = true; 1648 alloced++; 1649 } 1650 } 1651 vport->alloc_tqps = alloced; 1652 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1653 vport->alloc_tqps / hdev->tm_info.num_tc); 1654 1655 /* ensure one to one mapping between irq and queue at default */ 1656 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1657 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1658 1659 return 0; 1660 } 1661 1662 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1663 u16 num_tx_desc, u16 num_rx_desc) 1664 1665 { 1666 struct hnae3_handle *nic = &vport->nic; 1667 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1668 struct hclge_dev *hdev = vport->back; 1669 int ret; 1670 1671 kinfo->num_tx_desc = num_tx_desc; 1672 kinfo->num_rx_desc = num_rx_desc; 1673 1674 kinfo->rx_buf_len = hdev->rx_buf_len; 1675 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1676 1677 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1678 sizeof(struct hnae3_queue *), GFP_KERNEL); 1679 if (!kinfo->tqp) 1680 return -ENOMEM; 1681 1682 ret = hclge_assign_tqp(vport, num_tqps); 1683 if (ret) 1684 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1685 1686 return ret; 1687 } 1688 1689 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1690 struct hclge_vport *vport) 1691 { 1692 struct hnae3_handle *nic = &vport->nic; 1693 struct hnae3_knic_private_info *kinfo; 1694 u16 i; 1695 1696 kinfo = &nic->kinfo; 1697 for (i = 0; i < vport->alloc_tqps; i++) { 1698 struct hclge_comm_tqp *q = 1699 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1700 bool is_pf; 1701 int ret; 1702 1703 is_pf = !(vport->vport_id); 1704 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1705 i, is_pf); 1706 if (ret) 1707 return ret; 1708 } 1709 1710 return 0; 1711 } 1712 1713 static int hclge_map_tqp(struct hclge_dev *hdev) 1714 { 1715 struct hclge_vport *vport = hdev->vport; 1716 u16 i, num_vport; 1717 1718 num_vport = hdev->num_req_vfs + 1; 1719 for (i = 0; i < num_vport; i++) { 1720 int ret; 1721 1722 ret = hclge_map_tqp_to_vport(hdev, vport); 1723 if (ret) 1724 return ret; 1725 1726 vport++; 1727 } 1728 1729 return 0; 1730 } 1731 1732 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1733 { 1734 struct hnae3_handle *nic = &vport->nic; 1735 struct hclge_dev *hdev = vport->back; 1736 int ret; 1737 1738 nic->pdev = hdev->pdev; 1739 nic->ae_algo = &ae_algo; 1740 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, 1741 MAX_NUMNODES); 1742 nic->kinfo.io_base = hdev->hw.hw.io_base; 1743 1744 ret = hclge_knic_setup(vport, num_tqps, 1745 hdev->num_tx_desc, hdev->num_rx_desc); 1746 if (ret) 1747 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1748 1749 return ret; 1750 } 1751 1752 static int hclge_alloc_vport(struct hclge_dev *hdev) 1753 { 1754 struct pci_dev *pdev = hdev->pdev; 1755 struct hclge_vport *vport; 1756 u32 tqp_main_vport; 1757 u32 tqp_per_vport; 1758 int num_vport, i; 1759 int ret; 1760 1761 /* We need to alloc a vport for main NIC of PF */ 1762 num_vport = hdev->num_req_vfs + 1; 1763 1764 if (hdev->num_tqps < num_vport) { 1765 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1766 hdev->num_tqps, num_vport); 1767 return -EINVAL; 1768 } 1769 1770 /* Alloc the same number of TQPs for every vport */ 1771 tqp_per_vport = hdev->num_tqps / num_vport; 1772 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1773 1774 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1775 GFP_KERNEL); 1776 if (!vport) 1777 return -ENOMEM; 1778 1779 hdev->vport = vport; 1780 hdev->num_alloc_vport = num_vport; 1781 1782 if (IS_ENABLED(CONFIG_PCI_IOV)) 1783 hdev->num_alloc_vfs = hdev->num_req_vfs; 1784 1785 for (i = 0; i < num_vport; i++) { 1786 vport->back = hdev; 1787 vport->vport_id = i; 1788 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1789 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1790 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1791 vport->port_base_vlan_cfg.tbl_sta = true; 1792 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1793 vport->req_vlan_fltr_en = true; 1794 INIT_LIST_HEAD(&vport->vlan_list); 1795 INIT_LIST_HEAD(&vport->uc_mac_list); 1796 INIT_LIST_HEAD(&vport->mc_mac_list); 1797 spin_lock_init(&vport->mac_list_lock); 1798 1799 if (i == 0) 1800 ret = hclge_vport_setup(vport, tqp_main_vport); 1801 else 1802 ret = hclge_vport_setup(vport, tqp_per_vport); 1803 if (ret) { 1804 dev_err(&pdev->dev, 1805 "vport setup failed for vport %d, %d\n", 1806 i, ret); 1807 return ret; 1808 } 1809 1810 vport++; 1811 } 1812 1813 return 0; 1814 } 1815 1816 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1817 struct hclge_pkt_buf_alloc *buf_alloc) 1818 { 1819 /* TX buffer size is unit by 128 byte */ 1820 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1821 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1822 struct hclge_tx_buff_alloc_cmd *req; 1823 struct hclge_desc desc; 1824 int ret; 1825 u8 i; 1826 1827 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1828 1829 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1830 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1831 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1832 1833 req->tx_pkt_buff[i] = 1834 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1835 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1836 } 1837 1838 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1839 if (ret) 1840 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1841 ret); 1842 1843 return ret; 1844 } 1845 1846 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1847 struct hclge_pkt_buf_alloc *buf_alloc) 1848 { 1849 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1850 1851 if (ret) 1852 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1853 1854 return ret; 1855 } 1856 1857 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1858 { 1859 unsigned int i; 1860 u32 cnt = 0; 1861 1862 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1863 if (hdev->hw_tc_map & BIT(i)) 1864 cnt++; 1865 return cnt; 1866 } 1867 1868 /* Get the number of pfc enabled TCs, which have private buffer */ 1869 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1870 struct hclge_pkt_buf_alloc *buf_alloc) 1871 { 1872 struct hclge_priv_buf *priv; 1873 unsigned int i; 1874 int cnt = 0; 1875 1876 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1877 priv = &buf_alloc->priv_buf[i]; 1878 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1879 priv->enable) 1880 cnt++; 1881 } 1882 1883 return cnt; 1884 } 1885 1886 /* Get the number of pfc disabled TCs, which have private buffer */ 1887 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1888 struct hclge_pkt_buf_alloc *buf_alloc) 1889 { 1890 struct hclge_priv_buf *priv; 1891 unsigned int i; 1892 int cnt = 0; 1893 1894 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1895 priv = &buf_alloc->priv_buf[i]; 1896 if (hdev->hw_tc_map & BIT(i) && 1897 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1898 priv->enable) 1899 cnt++; 1900 } 1901 1902 return cnt; 1903 } 1904 1905 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1906 { 1907 struct hclge_priv_buf *priv; 1908 u32 rx_priv = 0; 1909 int i; 1910 1911 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1912 priv = &buf_alloc->priv_buf[i]; 1913 if (priv->enable) 1914 rx_priv += priv->buf_size; 1915 } 1916 return rx_priv; 1917 } 1918 1919 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1920 { 1921 u32 i, total_tx_size = 0; 1922 1923 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1924 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1925 1926 return total_tx_size; 1927 } 1928 1929 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1930 struct hclge_pkt_buf_alloc *buf_alloc, 1931 u32 rx_all) 1932 { 1933 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 1934 u32 tc_num = hclge_get_tc_num(hdev); 1935 u32 shared_buf, aligned_mps; 1936 u32 rx_priv; 1937 int i; 1938 1939 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 1940 1941 if (hnae3_dev_dcb_supported(hdev)) 1942 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 1943 hdev->dv_buf_size; 1944 else 1945 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 1946 + hdev->dv_buf_size; 1947 1948 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 1949 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 1950 HCLGE_BUF_SIZE_UNIT); 1951 1952 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 1953 if (rx_all < rx_priv + shared_std) 1954 return false; 1955 1956 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 1957 buf_alloc->s_buf.buf_size = shared_buf; 1958 if (hnae3_dev_dcb_supported(hdev)) { 1959 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 1960 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 1961 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 1962 HCLGE_BUF_SIZE_UNIT); 1963 } else { 1964 buf_alloc->s_buf.self.high = aligned_mps + 1965 HCLGE_NON_DCB_ADDITIONAL_BUF; 1966 buf_alloc->s_buf.self.low = aligned_mps; 1967 } 1968 1969 if (hnae3_dev_dcb_supported(hdev)) { 1970 hi_thrd = shared_buf - hdev->dv_buf_size; 1971 1972 if (tc_num <= NEED_RESERVE_TC_NUM) 1973 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 1974 / BUF_MAX_PERCENT; 1975 1976 if (tc_num) 1977 hi_thrd = hi_thrd / tc_num; 1978 1979 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 1980 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 1981 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 1982 } else { 1983 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 1984 lo_thrd = aligned_mps; 1985 } 1986 1987 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1988 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 1989 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 1990 } 1991 1992 return true; 1993 } 1994 1995 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 1996 struct hclge_pkt_buf_alloc *buf_alloc) 1997 { 1998 u32 i, total_size; 1999 2000 total_size = hdev->pkt_buf_size; 2001 2002 /* alloc tx buffer for all enabled tc */ 2003 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2004 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2005 2006 if (hdev->hw_tc_map & BIT(i)) { 2007 if (total_size < hdev->tx_buf_size) 2008 return -ENOMEM; 2009 2010 priv->tx_buf_size = hdev->tx_buf_size; 2011 } else { 2012 priv->tx_buf_size = 0; 2013 } 2014 2015 total_size -= priv->tx_buf_size; 2016 } 2017 2018 return 0; 2019 } 2020 2021 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2022 struct hclge_pkt_buf_alloc *buf_alloc) 2023 { 2024 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2025 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2026 unsigned int i; 2027 2028 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2029 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2030 2031 priv->enable = 0; 2032 priv->wl.low = 0; 2033 priv->wl.high = 0; 2034 priv->buf_size = 0; 2035 2036 if (!(hdev->hw_tc_map & BIT(i))) 2037 continue; 2038 2039 priv->enable = 1; 2040 2041 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2042 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2043 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2044 HCLGE_BUF_SIZE_UNIT); 2045 } else { 2046 priv->wl.low = 0; 2047 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2048 aligned_mps; 2049 } 2050 2051 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2052 } 2053 2054 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2055 } 2056 2057 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2058 struct hclge_pkt_buf_alloc *buf_alloc) 2059 { 2060 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2061 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2062 int i; 2063 2064 /* let the last to be cleared first */ 2065 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2066 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2067 unsigned int mask = BIT((unsigned int)i); 2068 2069 if (hdev->hw_tc_map & mask && 2070 !(hdev->tm_info.hw_pfc_map & mask)) { 2071 /* Clear the no pfc TC private buffer */ 2072 priv->wl.low = 0; 2073 priv->wl.high = 0; 2074 priv->buf_size = 0; 2075 priv->enable = 0; 2076 no_pfc_priv_num--; 2077 } 2078 2079 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2080 no_pfc_priv_num == 0) 2081 break; 2082 } 2083 2084 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2085 } 2086 2087 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2088 struct hclge_pkt_buf_alloc *buf_alloc) 2089 { 2090 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2091 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2092 int i; 2093 2094 /* let the last to be cleared first */ 2095 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2096 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2097 unsigned int mask = BIT((unsigned int)i); 2098 2099 if (hdev->hw_tc_map & mask && 2100 hdev->tm_info.hw_pfc_map & mask) { 2101 /* Reduce the number of pfc TC with private buffer */ 2102 priv->wl.low = 0; 2103 priv->enable = 0; 2104 priv->wl.high = 0; 2105 priv->buf_size = 0; 2106 pfc_priv_num--; 2107 } 2108 2109 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2110 pfc_priv_num == 0) 2111 break; 2112 } 2113 2114 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2115 } 2116 2117 static bool hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2118 struct hclge_pkt_buf_alloc *buf_alloc) 2119 { 2120 #define COMPENSATE_BUFFER 0x3C00 2121 #define COMPENSATE_HALF_MPS_NUM 5 2122 #define PRIV_WL_GAP 0x1800 2123 2124 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2125 u32 tc_num = hclge_get_tc_num(hdev); 2126 u32 half_mps = hdev->mps >> 1; 2127 u32 min_rx_priv; 2128 unsigned int i; 2129 2130 if (tc_num) 2131 rx_priv = rx_priv / tc_num; 2132 2133 if (tc_num <= NEED_RESERVE_TC_NUM) 2134 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2135 2136 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2137 COMPENSATE_HALF_MPS_NUM * half_mps; 2138 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2139 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2140 if (rx_priv < min_rx_priv) 2141 return false; 2142 2143 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2144 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2145 2146 priv->enable = 0; 2147 priv->wl.low = 0; 2148 priv->wl.high = 0; 2149 priv->buf_size = 0; 2150 2151 if (!(hdev->hw_tc_map & BIT(i))) 2152 continue; 2153 2154 priv->enable = 1; 2155 priv->buf_size = rx_priv; 2156 priv->wl.high = rx_priv - hdev->dv_buf_size; 2157 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2158 } 2159 2160 buf_alloc->s_buf.buf_size = 0; 2161 2162 return true; 2163 } 2164 2165 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2166 * @hdev: pointer to struct hclge_dev 2167 * @buf_alloc: pointer to buffer calculation data 2168 * @return: 0: calculate successful, negative: fail 2169 */ 2170 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2171 struct hclge_pkt_buf_alloc *buf_alloc) 2172 { 2173 /* When DCB is not supported, rx private buffer is not allocated. */ 2174 if (!hnae3_dev_dcb_supported(hdev)) { 2175 u32 rx_all = hdev->pkt_buf_size; 2176 2177 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2178 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2179 return -ENOMEM; 2180 2181 return 0; 2182 } 2183 2184 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2185 return 0; 2186 2187 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2188 return 0; 2189 2190 /* try to decrease the buffer size */ 2191 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2192 return 0; 2193 2194 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2195 return 0; 2196 2197 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2198 return 0; 2199 2200 return -ENOMEM; 2201 } 2202 2203 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2204 struct hclge_pkt_buf_alloc *buf_alloc) 2205 { 2206 struct hclge_rx_priv_buff_cmd *req; 2207 struct hclge_desc desc; 2208 int ret; 2209 int i; 2210 2211 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2212 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2213 2214 /* Alloc private buffer TCs */ 2215 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2216 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2217 2218 req->buf_num[i] = 2219 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2220 req->buf_num[i] |= 2221 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2222 } 2223 2224 req->shared_buf = 2225 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2226 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2227 2228 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2229 if (ret) 2230 dev_err(&hdev->pdev->dev, 2231 "rx private buffer alloc cmd failed %d\n", ret); 2232 2233 return ret; 2234 } 2235 2236 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2237 struct hclge_pkt_buf_alloc *buf_alloc) 2238 { 2239 struct hclge_rx_priv_wl_buf *req; 2240 struct hclge_priv_buf *priv; 2241 struct hclge_desc desc[2]; 2242 int i, j; 2243 int ret; 2244 2245 for (i = 0; i < 2; i++) { 2246 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2247 false); 2248 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2249 2250 /* The first descriptor set the NEXT bit to 1 */ 2251 if (i == 0) 2252 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2253 else 2254 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2255 2256 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2257 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2258 2259 priv = &buf_alloc->priv_buf[idx]; 2260 req->tc_wl[j].high = 2261 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2262 req->tc_wl[j].high |= 2263 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2264 req->tc_wl[j].low = 2265 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2266 req->tc_wl[j].low |= 2267 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2268 } 2269 } 2270 2271 /* Send 2 descriptor at one time */ 2272 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2273 if (ret) 2274 dev_err(&hdev->pdev->dev, 2275 "rx private waterline config cmd failed %d\n", 2276 ret); 2277 return ret; 2278 } 2279 2280 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2281 struct hclge_pkt_buf_alloc *buf_alloc) 2282 { 2283 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2284 struct hclge_rx_com_thrd *req; 2285 struct hclge_desc desc[2]; 2286 struct hclge_tc_thrd *tc; 2287 int i, j; 2288 int ret; 2289 2290 for (i = 0; i < 2; i++) { 2291 hclge_cmd_setup_basic_desc(&desc[i], 2292 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2293 req = (struct hclge_rx_com_thrd *)desc[i].data; 2294 2295 /* The first descriptor set the NEXT bit to 1 */ 2296 if (i == 0) 2297 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2298 else 2299 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2300 2301 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2302 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2303 2304 req->com_thrd[j].high = 2305 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2306 req->com_thrd[j].high |= 2307 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2308 req->com_thrd[j].low = 2309 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2310 req->com_thrd[j].low |= 2311 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2312 } 2313 } 2314 2315 /* Send 2 descriptors at one time */ 2316 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2317 if (ret) 2318 dev_err(&hdev->pdev->dev, 2319 "common threshold config cmd failed %d\n", ret); 2320 return ret; 2321 } 2322 2323 static int hclge_common_wl_config(struct hclge_dev *hdev, 2324 struct hclge_pkt_buf_alloc *buf_alloc) 2325 { 2326 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2327 struct hclge_rx_com_wl *req; 2328 struct hclge_desc desc; 2329 int ret; 2330 2331 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2332 2333 req = (struct hclge_rx_com_wl *)desc.data; 2334 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2335 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2336 2337 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2338 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2339 2340 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2341 if (ret) 2342 dev_err(&hdev->pdev->dev, 2343 "common waterline config cmd failed %d\n", ret); 2344 2345 return ret; 2346 } 2347 2348 int hclge_buffer_alloc(struct hclge_dev *hdev) 2349 { 2350 struct hclge_pkt_buf_alloc *pkt_buf; 2351 int ret; 2352 2353 pkt_buf = kzalloc_obj(*pkt_buf); 2354 if (!pkt_buf) 2355 return -ENOMEM; 2356 2357 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2358 if (ret) { 2359 dev_err(&hdev->pdev->dev, 2360 "could not calc tx buffer size for all TCs %d\n", ret); 2361 goto out; 2362 } 2363 2364 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2365 if (ret) { 2366 dev_err(&hdev->pdev->dev, 2367 "could not alloc tx buffers %d\n", ret); 2368 goto out; 2369 } 2370 2371 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2372 if (ret) { 2373 dev_err(&hdev->pdev->dev, 2374 "could not calc rx priv buffer size for all TCs %d\n", 2375 ret); 2376 goto out; 2377 } 2378 2379 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2380 if (ret) { 2381 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2382 ret); 2383 goto out; 2384 } 2385 2386 if (hnae3_dev_dcb_supported(hdev)) { 2387 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2388 if (ret) { 2389 dev_err(&hdev->pdev->dev, 2390 "could not configure rx private waterline %d\n", 2391 ret); 2392 goto out; 2393 } 2394 2395 ret = hclge_common_thrd_config(hdev, pkt_buf); 2396 if (ret) { 2397 dev_err(&hdev->pdev->dev, 2398 "could not configure common threshold %d\n", 2399 ret); 2400 goto out; 2401 } 2402 } 2403 2404 ret = hclge_common_wl_config(hdev, pkt_buf); 2405 if (ret) 2406 dev_err(&hdev->pdev->dev, 2407 "could not configure common waterline %d\n", ret); 2408 2409 out: 2410 kfree(pkt_buf); 2411 return ret; 2412 } 2413 2414 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2415 { 2416 struct hnae3_handle *roce = &vport->roce; 2417 struct hnae3_handle *nic = &vport->nic; 2418 struct hclge_dev *hdev = vport->back; 2419 2420 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2421 2422 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2423 return -EINVAL; 2424 2425 roce->rinfo.base_vector = hdev->num_nic_msi; 2426 2427 roce->rinfo.netdev = nic->kinfo.netdev; 2428 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2429 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2430 2431 roce->pdev = nic->pdev; 2432 roce->ae_algo = nic->ae_algo; 2433 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, 2434 MAX_NUMNODES); 2435 2436 return 0; 2437 } 2438 2439 static int hclge_init_msi(struct hclge_dev *hdev) 2440 { 2441 struct pci_dev *pdev = hdev->pdev; 2442 int vectors; 2443 int i; 2444 2445 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2446 hdev->num_msi, 2447 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2448 if (vectors < 0) { 2449 dev_err(&pdev->dev, 2450 "failed(%d) to allocate MSI/MSI-X vectors\n", 2451 vectors); 2452 return vectors; 2453 } 2454 if (vectors < hdev->num_msi) 2455 dev_warn(&hdev->pdev->dev, 2456 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2457 hdev->num_msi, vectors); 2458 2459 hdev->num_msi = vectors; 2460 hdev->num_msi_left = vectors; 2461 2462 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2463 sizeof(u16), GFP_KERNEL); 2464 if (!hdev->vector_status) { 2465 pci_free_irq_vectors(pdev); 2466 return -ENOMEM; 2467 } 2468 2469 for (i = 0; i < hdev->num_msi; i++) 2470 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2471 2472 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2473 sizeof(int), GFP_KERNEL); 2474 if (!hdev->vector_irq) { 2475 pci_free_irq_vectors(pdev); 2476 return -ENOMEM; 2477 } 2478 2479 return 0; 2480 } 2481 2482 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2483 { 2484 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2485 duplex = HCLGE_MAC_FULL; 2486 2487 return duplex; 2488 } 2489 2490 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2491 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2492 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2493 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2494 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2495 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2496 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2497 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2498 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2499 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2500 }; 2501 2502 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2503 { 2504 u16 i; 2505 2506 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2507 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2508 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2509 return 0; 2510 } 2511 } 2512 2513 return -EINVAL; 2514 } 2515 2516 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2517 u8 duplex, u8 lane_num) 2518 { 2519 struct hclge_config_mac_speed_dup_cmd *req; 2520 struct hclge_desc desc; 2521 u32 speed_fw; 2522 int ret; 2523 2524 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2525 2526 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2527 2528 if (duplex) 2529 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2530 2531 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2532 if (ret) { 2533 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2534 return ret; 2535 } 2536 2537 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2538 speed_fw); 2539 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2540 1); 2541 req->lane_num = lane_num; 2542 2543 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2544 if (ret) { 2545 dev_err(&hdev->pdev->dev, 2546 "mac speed/duplex config cmd failed %d.\n", ret); 2547 return ret; 2548 } 2549 2550 return 0; 2551 } 2552 2553 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2554 { 2555 struct hclge_mac *mac = &hdev->hw.mac; 2556 int ret; 2557 2558 duplex = hclge_check_speed_dup(duplex, speed); 2559 if (!mac->support_autoneg && mac->speed == (u32)speed && 2560 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2561 return 0; 2562 2563 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2564 if (ret) 2565 return ret; 2566 2567 hdev->hw.mac.speed = speed; 2568 hdev->hw.mac.duplex = duplex; 2569 if (!lane_num) 2570 hdev->hw.mac.lane_num = lane_num; 2571 2572 return 0; 2573 } 2574 2575 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2576 u8 duplex, u8 lane_num) 2577 { 2578 struct hclge_vport *vport = hclge_get_vport(handle); 2579 struct hclge_dev *hdev = vport->back; 2580 int ret; 2581 2582 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2583 2584 if (ret) 2585 return ret; 2586 2587 hdev->hw.mac.req_lane_num = lane_num; 2588 if (speed != SPEED_UNKNOWN) 2589 hdev->hw.mac.req_speed = (u32)speed; 2590 if (duplex != DUPLEX_UNKNOWN) 2591 hdev->hw.mac.req_duplex = duplex; 2592 2593 return 0; 2594 } 2595 2596 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2597 { 2598 struct hclge_config_auto_neg_cmd *req; 2599 struct hclge_desc desc; 2600 u32 flag = 0; 2601 int ret; 2602 2603 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2604 2605 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2606 if (enable) 2607 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2608 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2609 2610 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2611 if (ret) 2612 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2613 ret); 2614 2615 return ret; 2616 } 2617 2618 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2619 { 2620 struct hclge_vport *vport = hclge_get_vport(handle); 2621 struct hclge_dev *hdev = vport->back; 2622 int ret; 2623 2624 if (!hdev->hw.mac.support_autoneg) { 2625 if (enable) { 2626 dev_err(&hdev->pdev->dev, 2627 "autoneg is not supported by current port\n"); 2628 return -EOPNOTSUPP; 2629 } else { 2630 return 0; 2631 } 2632 } 2633 2634 ret = hclge_set_autoneg_en(hdev, enable); 2635 if (!ret) 2636 hdev->hw.mac.req_autoneg = enable; 2637 return ret; 2638 } 2639 2640 static int hclge_get_autoneg(struct hnae3_handle *handle) 2641 { 2642 struct hclge_vport *vport = hclge_get_vport(handle); 2643 struct hclge_dev *hdev = vport->back; 2644 struct phy_device *phydev = hdev->hw.mac.phydev; 2645 2646 if (phydev) 2647 return phydev->autoneg; 2648 2649 return hdev->hw.mac.autoneg; 2650 } 2651 2652 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2653 { 2654 struct hclge_vport *vport = hclge_get_vport(handle); 2655 struct hclge_dev *hdev = vport->back; 2656 int ret; 2657 2658 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2659 2660 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2661 if (ret) 2662 return ret; 2663 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2664 } 2665 2666 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2667 { 2668 struct hclge_vport *vport = hclge_get_vport(handle); 2669 struct hclge_dev *hdev = vport->back; 2670 2671 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2672 return hclge_set_autoneg_en(hdev, !halt); 2673 2674 return 0; 2675 } 2676 2677 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2678 struct hclge_desc *desc, u32 desc_len) 2679 { 2680 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2681 u32 desc_index = 0; 2682 u32 data_index = 0; 2683 u32 i; 2684 2685 for (i = 0; i < lane_size; i++) { 2686 if (data_index >= HCLGE_DESC_DATA_LEN) { 2687 desc_index++; 2688 data_index = 0; 2689 } 2690 2691 if (desc_index >= desc_len) 2692 return; 2693 2694 hdev->fec_stats.per_lanes[i] += 2695 le32_to_cpu(desc[desc_index].data[data_index]); 2696 data_index++; 2697 } 2698 } 2699 2700 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2701 struct hclge_desc *desc, u32 desc_len) 2702 { 2703 struct hclge_query_fec_stats_cmd *req; 2704 2705 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2706 2707 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2708 hdev->fec_stats.rs_corr_blocks += 2709 le32_to_cpu(req->rs_fec_corr_blocks); 2710 hdev->fec_stats.rs_uncorr_blocks += 2711 le32_to_cpu(req->rs_fec_uncorr_blocks); 2712 hdev->fec_stats.rs_error_blocks += 2713 le32_to_cpu(req->rs_fec_error_blocks); 2714 hdev->fec_stats.base_r_corr_blocks += 2715 le32_to_cpu(req->base_r_fec_corr_blocks); 2716 hdev->fec_stats.base_r_uncorr_blocks += 2717 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2718 2719 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2720 } 2721 2722 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2723 { 2724 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2725 int ret; 2726 u32 i; 2727 2728 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2729 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2730 true); 2731 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2732 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2733 } 2734 2735 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2736 if (ret) 2737 return ret; 2738 2739 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2740 2741 return 0; 2742 } 2743 2744 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2745 { 2746 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2747 int ret; 2748 2749 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2750 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2751 return; 2752 2753 ret = hclge_update_fec_stats_hw(hdev); 2754 if (ret) 2755 dev_err(&hdev->pdev->dev, 2756 "failed to update fec stats, ret = %d\n", ret); 2757 2758 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2759 } 2760 2761 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2762 struct ethtool_fec_stats *fec_stats) 2763 { 2764 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2765 fec_stats->uncorrectable_blocks.total = 2766 hdev->fec_stats.rs_uncorr_blocks; 2767 } 2768 2769 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2770 struct ethtool_fec_stats *fec_stats) 2771 { 2772 u32 i; 2773 2774 if (hdev->fec_stats.base_r_lane_num == 0 || 2775 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2776 dev_err(&hdev->pdev->dev, 2777 "fec stats lane number(%llu) is invalid\n", 2778 hdev->fec_stats.base_r_lane_num); 2779 return; 2780 } 2781 2782 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2783 fec_stats->corrected_blocks.lanes[i] = 2784 hdev->fec_stats.base_r_corr_per_lanes[i]; 2785 fec_stats->uncorrectable_blocks.lanes[i] = 2786 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2787 } 2788 } 2789 2790 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2791 struct ethtool_fec_stats *fec_stats) 2792 { 2793 u32 fec_mode = hdev->hw.mac.fec_mode; 2794 2795 switch (fec_mode) { 2796 case BIT(HNAE3_FEC_RS): 2797 case BIT(HNAE3_FEC_LLRS): 2798 hclge_get_fec_stats_total(hdev, fec_stats); 2799 break; 2800 case BIT(HNAE3_FEC_BASER): 2801 hclge_get_fec_stats_lanes(hdev, fec_stats); 2802 break; 2803 default: 2804 dev_err(&hdev->pdev->dev, 2805 "fec stats is not supported by current fec mode(0x%x)\n", 2806 fec_mode); 2807 break; 2808 } 2809 } 2810 2811 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2812 struct ethtool_fec_stats *fec_stats) 2813 { 2814 struct hclge_vport *vport = hclge_get_vport(handle); 2815 struct hclge_dev *hdev = vport->back; 2816 u32 fec_mode = hdev->hw.mac.fec_mode; 2817 2818 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2819 fec_mode == BIT(HNAE3_FEC_AUTO) || 2820 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2821 return; 2822 2823 hclge_update_fec_stats(hdev); 2824 2825 hclge_comm_get_fec_stats(hdev, fec_stats); 2826 } 2827 2828 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2829 { 2830 struct hclge_config_fec_cmd *req; 2831 struct hclge_desc desc; 2832 int ret; 2833 2834 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2835 2836 req = (struct hclge_config_fec_cmd *)desc.data; 2837 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2838 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2839 if (fec_mode & BIT(HNAE3_FEC_RS)) 2840 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2841 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2842 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2843 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2844 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2845 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2846 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2847 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2848 2849 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2850 if (ret) 2851 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2852 2853 return ret; 2854 } 2855 2856 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2857 { 2858 struct hclge_vport *vport = hclge_get_vport(handle); 2859 struct hclge_dev *hdev = vport->back; 2860 struct hclge_mac *mac = &hdev->hw.mac; 2861 int ret; 2862 2863 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2864 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2865 return -EINVAL; 2866 } 2867 2868 ret = hclge_set_fec_hw(hdev, fec_mode); 2869 if (ret) 2870 return ret; 2871 2872 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2873 return 0; 2874 } 2875 2876 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2877 u8 *fec_mode) 2878 { 2879 struct hclge_vport *vport = hclge_get_vport(handle); 2880 struct hclge_dev *hdev = vport->back; 2881 struct hclge_mac *mac = &hdev->hw.mac; 2882 2883 if (fec_ability) 2884 *fec_ability = mac->fec_ability; 2885 if (fec_mode) 2886 *fec_mode = mac->fec_mode; 2887 } 2888 2889 static int hclge_mac_init(struct hclge_dev *hdev) 2890 { 2891 struct hclge_mac *mac = &hdev->hw.mac; 2892 int ret; 2893 2894 hdev->support_sfp_query = true; 2895 2896 if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2897 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2898 2899 mac->link = 0; 2900 2901 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2902 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2903 if (ret) 2904 return ret; 2905 } 2906 2907 ret = hclge_set_mac_mtu(hdev, hdev->mps); 2908 if (ret) { 2909 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 2910 return ret; 2911 } 2912 2913 ret = hclge_set_default_loopback(hdev); 2914 if (ret) 2915 return ret; 2916 2917 ret = hclge_buffer_alloc(hdev); 2918 if (ret) 2919 dev_err(&hdev->pdev->dev, 2920 "allocate buffer fail, ret=%d\n", ret); 2921 2922 return ret; 2923 } 2924 2925 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 2926 { 2927 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2928 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 2929 hdev->last_mbx_scheduled = jiffies; 2930 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2931 } 2932 } 2933 2934 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 2935 { 2936 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2937 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 2938 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 2939 hdev->last_rst_scheduled = jiffies; 2940 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2941 } 2942 } 2943 2944 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 2945 { 2946 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2947 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 2948 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2949 } 2950 2951 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 2952 { 2953 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2954 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 2955 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 2956 } 2957 2958 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 2959 { 2960 struct hclge_link_status_cmd *req; 2961 struct hclge_desc desc; 2962 int ret; 2963 2964 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2965 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2966 if (ret) { 2967 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2968 ret); 2969 return ret; 2970 } 2971 2972 req = (struct hclge_link_status_cmd *)desc.data; 2973 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 2974 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 2975 2976 return 0; 2977 } 2978 2979 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 2980 { 2981 struct phy_device *phydev = hdev->hw.mac.phydev; 2982 2983 *link_status = HCLGE_LINK_STATUS_DOWN; 2984 2985 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 2986 return 0; 2987 2988 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 2989 return 0; 2990 2991 return hclge_get_mac_link_status(hdev, link_status); 2992 } 2993 2994 static void hclge_push_link_status(struct hclge_dev *hdev) 2995 { 2996 struct hclge_vport *vport; 2997 int ret; 2998 u16 i; 2999 3000 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3001 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3002 3003 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3004 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3005 continue; 3006 3007 ret = hclge_push_vf_link_status(vport); 3008 if (ret) { 3009 dev_err(&hdev->pdev->dev, 3010 "failed to push link status to vf%u, ret = %d\n", 3011 i, ret); 3012 } 3013 } 3014 } 3015 3016 static void hclge_update_link_status(struct hclge_dev *hdev) 3017 { 3018 struct hnae3_handle *handle = &hdev->vport[0].nic; 3019 struct hnae3_client *client = hdev->nic_client; 3020 int state; 3021 int ret; 3022 3023 if (!client) 3024 return; 3025 3026 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3027 return; 3028 3029 ret = hclge_get_mac_phy_link(hdev, &state); 3030 if (ret) { 3031 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3032 return; 3033 } 3034 3035 if (state != hdev->hw.mac.link) { 3036 hdev->hw.mac.link = state; 3037 if (state == HCLGE_LINK_STATUS_UP) 3038 hclge_update_port_info(hdev); 3039 3040 client->ops->link_status_change(handle, state); 3041 hclge_config_mac_tnl_int(hdev, state); 3042 3043 if (test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state)) { 3044 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3045 struct hnae3_client *rclient = hdev->roce_client; 3046 3047 if (rclient && rclient->ops->link_status_change) 3048 rclient->ops->link_status_change(rhandle, 3049 state); 3050 } 3051 3052 hclge_push_link_status(hdev); 3053 } 3054 3055 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3056 } 3057 3058 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3059 { 3060 u32 speed_ability; 3061 3062 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3063 return; 3064 3065 switch (mac->module_type) { 3066 case HNAE3_MODULE_TYPE_FIBRE_LR: 3067 hclge_convert_setting_lr(speed_ability, mac->advertising); 3068 break; 3069 case HNAE3_MODULE_TYPE_FIBRE_SR: 3070 case HNAE3_MODULE_TYPE_AOC: 3071 hclge_convert_setting_sr(speed_ability, mac->advertising); 3072 break; 3073 case HNAE3_MODULE_TYPE_CR: 3074 hclge_convert_setting_cr(speed_ability, mac->advertising); 3075 break; 3076 case HNAE3_MODULE_TYPE_KR: 3077 hclge_convert_setting_kr(speed_ability, mac->advertising); 3078 break; 3079 default: 3080 break; 3081 } 3082 } 3083 3084 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3085 { 3086 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3087 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3088 mac->advertising); 3089 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3090 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3091 mac->advertising); 3092 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3093 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3094 mac->advertising); 3095 else 3096 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3097 mac->advertising); 3098 } 3099 3100 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3101 { 3102 struct hclge_mac *mac = &hdev->hw.mac; 3103 bool rx_en, tx_en; 3104 3105 switch (hdev->fc_mode_last_time) { 3106 case HCLGE_FC_RX_PAUSE: 3107 rx_en = true; 3108 tx_en = false; 3109 break; 3110 case HCLGE_FC_TX_PAUSE: 3111 rx_en = false; 3112 tx_en = true; 3113 break; 3114 case HCLGE_FC_FULL: 3115 rx_en = true; 3116 tx_en = true; 3117 break; 3118 default: 3119 rx_en = false; 3120 tx_en = false; 3121 break; 3122 } 3123 3124 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3125 } 3126 3127 static void hclge_update_advertising(struct hclge_dev *hdev) 3128 { 3129 struct hclge_mac *mac = &hdev->hw.mac; 3130 3131 linkmode_zero(mac->advertising); 3132 hclge_update_speed_advertising(mac); 3133 hclge_update_fec_advertising(mac); 3134 hclge_update_pause_advertising(hdev); 3135 } 3136 3137 static void hclge_update_port_capability(struct hclge_dev *hdev, 3138 struct hclge_mac *mac) 3139 { 3140 if (hnae3_dev_fec_supported(hdev)) 3141 hclge_convert_setting_fec(mac); 3142 3143 /* firmware can not identify back plane type, the media type 3144 * read from configuration can help deal it 3145 */ 3146 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3147 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3148 mac->module_type = HNAE3_MODULE_TYPE_KR; 3149 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3150 mac->module_type = HNAE3_MODULE_TYPE_TP; 3151 3152 if (mac->support_autoneg) { 3153 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3154 linkmode_copy(mac->advertising, mac->supported); 3155 } else { 3156 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3157 mac->supported); 3158 hclge_update_advertising(hdev); 3159 } 3160 } 3161 3162 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3163 { 3164 struct hclge_sfp_info_cmd *resp; 3165 struct hclge_desc desc; 3166 int ret; 3167 3168 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3169 resp = (struct hclge_sfp_info_cmd *)desc.data; 3170 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3171 if (ret == -EOPNOTSUPP) { 3172 dev_warn(&hdev->pdev->dev, 3173 "IMP do not support get SFP speed %d\n", ret); 3174 return ret; 3175 } else if (ret) { 3176 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3177 return ret; 3178 } 3179 3180 *speed = le32_to_cpu(resp->speed); 3181 3182 return 0; 3183 } 3184 3185 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3186 { 3187 struct hclge_sfp_info_cmd *resp; 3188 struct hclge_desc desc; 3189 int ret; 3190 3191 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3192 resp = (struct hclge_sfp_info_cmd *)desc.data; 3193 3194 resp->query_type = QUERY_ACTIVE_SPEED; 3195 3196 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3197 if (ret == -EOPNOTSUPP) { 3198 dev_warn(&hdev->pdev->dev, 3199 "IMP does not support get SFP info %d\n", ret); 3200 return ret; 3201 } else if (ret) { 3202 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3203 return ret; 3204 } 3205 3206 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3207 * set to mac->speed. 3208 */ 3209 if (!le32_to_cpu(resp->speed)) 3210 return 0; 3211 3212 mac->speed = le32_to_cpu(resp->speed); 3213 /* if resp->speed_ability is 0, it means it's an old version 3214 * firmware, do not update these params 3215 */ 3216 if (resp->speed_ability) { 3217 mac->module_type = le32_to_cpu(resp->module_type); 3218 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3219 mac->autoneg = resp->autoneg; 3220 mac->support_autoneg = resp->autoneg_ability; 3221 mac->speed_type = QUERY_ACTIVE_SPEED; 3222 mac->lane_num = resp->lane_num; 3223 if (!resp->active_fec) 3224 mac->fec_mode = 0; 3225 else 3226 mac->fec_mode = BIT(resp->active_fec); 3227 mac->fec_ability = resp->fec_ability; 3228 } else { 3229 mac->speed_type = QUERY_SFP_SPEED; 3230 } 3231 3232 return 0; 3233 } 3234 3235 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3236 struct ethtool_link_ksettings *cmd) 3237 { 3238 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3239 struct hclge_vport *vport = hclge_get_vport(handle); 3240 struct hclge_phy_link_ksetting_0_cmd *req0; 3241 struct hclge_phy_link_ksetting_1_cmd *req1; 3242 u32 supported, advertising, lp_advertising; 3243 struct hclge_dev *hdev = vport->back; 3244 int ret; 3245 3246 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3247 true); 3248 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3249 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3250 true); 3251 3252 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3253 if (ret) { 3254 dev_err(&hdev->pdev->dev, 3255 "failed to get phy link ksetting, ret = %d.\n", ret); 3256 return ret; 3257 } 3258 3259 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3260 cmd->base.autoneg = req0->autoneg; 3261 cmd->base.speed = le32_to_cpu(req0->speed); 3262 cmd->base.duplex = req0->duplex; 3263 cmd->base.port = req0->port; 3264 cmd->base.transceiver = req0->transceiver; 3265 cmd->base.phy_address = req0->phy_address; 3266 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3267 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3268 supported = le32_to_cpu(req0->supported); 3269 advertising = le32_to_cpu(req0->advertising); 3270 lp_advertising = le32_to_cpu(req0->lp_advertising); 3271 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3272 supported); 3273 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3274 advertising); 3275 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3276 lp_advertising); 3277 3278 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3279 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3280 cmd->base.master_slave_state = req1->master_slave_state; 3281 3282 return 0; 3283 } 3284 3285 static int 3286 hclge_ethtool_ksettings_set(struct hnae3_handle *handle, 3287 const struct ethtool_link_ksettings *cmd) 3288 { 3289 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3290 struct hclge_vport *vport = hclge_get_vport(handle); 3291 struct hclge_phy_link_ksetting_0_cmd *req0; 3292 struct hclge_phy_link_ksetting_1_cmd *req1; 3293 struct hclge_dev *hdev = vport->back; 3294 u32 advertising; 3295 int ret; 3296 3297 if (cmd->base.autoneg == AUTONEG_DISABLE && 3298 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3299 (cmd->base.duplex != DUPLEX_HALF && 3300 cmd->base.duplex != DUPLEX_FULL))) 3301 return -EINVAL; 3302 3303 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3304 false); 3305 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3306 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3307 false); 3308 3309 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3310 req0->autoneg = cmd->base.autoneg; 3311 req0->speed = cpu_to_le32(cmd->base.speed); 3312 req0->duplex = cmd->base.duplex; 3313 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3314 cmd->link_modes.advertising); 3315 req0->advertising = cpu_to_le32(advertising); 3316 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3317 3318 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3319 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3320 3321 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3322 if (ret) { 3323 dev_err(&hdev->pdev->dev, 3324 "failed to set phy link ksettings, ret = %d.\n", ret); 3325 return ret; 3326 } 3327 3328 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3329 return 0; 3330 } 3331 3332 static int 3333 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3334 const struct ethtool_link_ksettings *cmd) 3335 { 3336 struct hclge_vport *vport = hclge_get_vport(handle); 3337 struct hclge_dev *hdev = vport->back; 3338 int ret = -ENODEV; 3339 3340 if (hnae3_dev_phy_imp_supported(hdev)) { 3341 ret = hclge_ethtool_ksettings_set(handle, cmd); 3342 } else if (handle->netdev->phydev) { 3343 if (cmd->base.speed == SPEED_1000 && 3344 cmd->base.autoneg == AUTONEG_DISABLE) 3345 return -EINVAL; 3346 ret = phy_ethtool_ksettings_set(handle->netdev->phydev, cmd); 3347 } 3348 if (ret) 3349 return ret; 3350 3351 hdev->hw.mac.req_autoneg = cmd->base.autoneg; 3352 if (cmd->base.speed != SPEED_UNKNOWN) 3353 hdev->hw.mac.req_speed = cmd->base.speed; 3354 if (cmd->base.duplex != DUPLEX_UNKNOWN) 3355 hdev->hw.mac.req_duplex = cmd->base.duplex; 3356 3357 return 0; 3358 } 3359 3360 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3361 { 3362 struct ethtool_link_ksettings cmd; 3363 int ret; 3364 3365 if (!hnae3_dev_phy_imp_supported(hdev)) 3366 return 0; 3367 3368 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3369 if (ret) 3370 return ret; 3371 3372 hdev->hw.mac.autoneg = cmd.base.autoneg; 3373 hdev->hw.mac.speed = cmd.base.speed; 3374 hdev->hw.mac.duplex = cmd.base.duplex; 3375 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3376 3377 return 0; 3378 } 3379 3380 static int hclge_tp_port_init(struct hclge_dev *hdev) 3381 { 3382 struct ethtool_link_ksettings cmd; 3383 3384 if (!hnae3_dev_phy_imp_supported(hdev)) 3385 return 0; 3386 3387 cmd.base.autoneg = hdev->hw.mac.req_autoneg; 3388 cmd.base.speed = hdev->hw.mac.req_speed; 3389 cmd.base.duplex = hdev->hw.mac.req_duplex; 3390 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3391 3392 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3393 } 3394 3395 static int hclge_update_port_info(struct hclge_dev *hdev) 3396 { 3397 struct hclge_mac *mac = &hdev->hw.mac; 3398 u32 speed; 3399 int ret; 3400 3401 /* get the port info from SFP cmd if not copper port */ 3402 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3403 return hclge_update_tp_port_info(hdev); 3404 3405 /* if IMP does not support get SFP/qSFP info, return directly */ 3406 if (!hdev->support_sfp_query) 3407 return 0; 3408 3409 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3410 speed = mac->speed; 3411 ret = hclge_get_sfp_info(hdev, mac); 3412 } else { 3413 speed = HCLGE_MAC_SPEED_UNKNOWN; 3414 ret = hclge_get_sfp_speed(hdev, &speed); 3415 } 3416 3417 if (ret == -EOPNOTSUPP) { 3418 hdev->support_sfp_query = false; 3419 return ret; 3420 } else if (ret) { 3421 return ret; 3422 } 3423 3424 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3425 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3426 hclge_update_port_capability(hdev, mac); 3427 if (mac->speed != speed) 3428 (void)hclge_tm_port_shaper_cfg(hdev); 3429 return 0; 3430 } 3431 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3432 HCLGE_MAC_FULL, mac->lane_num); 3433 } else { 3434 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3435 return 0; /* do nothing if no SFP */ 3436 3437 /* must config full duplex for SFP */ 3438 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3439 } 3440 } 3441 3442 static int hclge_get_status(struct hnae3_handle *handle) 3443 { 3444 struct hclge_vport *vport = hclge_get_vport(handle); 3445 struct hclge_dev *hdev = vport->back; 3446 3447 hclge_update_link_status(hdev); 3448 3449 return hdev->hw.mac.link; 3450 } 3451 3452 struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3453 { 3454 if (!pci_num_vf(hdev->pdev)) { 3455 dev_err(&hdev->pdev->dev, 3456 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3457 return NULL; 3458 } 3459 3460 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3461 dev_err(&hdev->pdev->dev, 3462 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3463 vf, pci_num_vf(hdev->pdev)); 3464 return NULL; 3465 } 3466 3467 /* VF start from 1 in vport */ 3468 vf += HCLGE_VF_VPORT_START_NUM; 3469 return &hdev->vport[vf]; 3470 } 3471 3472 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3473 struct ifla_vf_info *ivf) 3474 { 3475 struct hclge_vport *vport = hclge_get_vport(handle); 3476 struct hclge_dev *hdev = vport->back; 3477 3478 vport = hclge_get_vf_vport(hdev, vf); 3479 if (!vport) 3480 return -EINVAL; 3481 3482 ivf->vf = vf; 3483 ivf->linkstate = vport->vf_info.link_state; 3484 ivf->spoofchk = vport->vf_info.spoofchk; 3485 ivf->trusted = vport->vf_info.trusted; 3486 ivf->min_tx_rate = 0; 3487 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3488 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3489 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3490 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3491 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3492 3493 return 0; 3494 } 3495 3496 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3497 int link_state) 3498 { 3499 struct hclge_vport *vport = hclge_get_vport(handle); 3500 struct hclge_dev *hdev = vport->back; 3501 int link_state_old; 3502 int ret; 3503 3504 vport = hclge_get_vf_vport(hdev, vf); 3505 if (!vport) 3506 return -EINVAL; 3507 3508 link_state_old = vport->vf_info.link_state; 3509 vport->vf_info.link_state = link_state; 3510 3511 /* return success directly if the VF is unalive, VF will 3512 * query link state itself when it starts work. 3513 */ 3514 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3515 return 0; 3516 3517 ret = hclge_push_vf_link_status(vport); 3518 if (ret) { 3519 vport->vf_info.link_state = link_state_old; 3520 dev_err(&hdev->pdev->dev, 3521 "failed to push vf%d link status, ret = %d\n", vf, ret); 3522 } 3523 3524 return ret; 3525 } 3526 3527 static void hclge_set_reset_pending(struct hclge_dev *hdev, 3528 enum hnae3_reset_type reset_type) 3529 { 3530 /* When an incorrect reset type is executed, the get_reset_level 3531 * function generates the HNAE3_NONE_RESET flag. As a result, this 3532 * type do not need to pending. 3533 */ 3534 if (reset_type != HNAE3_NONE_RESET) 3535 set_bit(reset_type, &hdev->reset_pending); 3536 } 3537 3538 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3539 { 3540 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3541 3542 /* fetch the events from their corresponding regs */ 3543 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3544 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3545 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3546 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3547 3548 /* Assumption: If by any chance reset and mailbox events are reported 3549 * together then we will only process reset event in this go and will 3550 * defer the processing of the mailbox events. Since, we would have not 3551 * cleared RX CMDQ event this time we would receive again another 3552 * interrupt from H/W just for the mailbox. 3553 * 3554 * check for vector0 reset event sources 3555 */ 3556 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3557 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3558 hclge_set_reset_pending(hdev, HNAE3_IMP_RESET); 3559 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3560 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3561 hdev->rst_stats.imp_rst_cnt++; 3562 return HCLGE_VECTOR0_EVENT_RST; 3563 } 3564 3565 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3566 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3567 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3568 hclge_set_reset_pending(hdev, HNAE3_GLOBAL_RESET); 3569 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3570 hdev->rst_stats.global_rst_cnt++; 3571 return HCLGE_VECTOR0_EVENT_RST; 3572 } 3573 3574 /* check for vector0 msix event and hardware error event source */ 3575 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3576 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3577 return HCLGE_VECTOR0_EVENT_ERR; 3578 3579 /* check for vector0 ptp event source */ 3580 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3581 *clearval = msix_src_reg; 3582 return HCLGE_VECTOR0_EVENT_PTP; 3583 } 3584 3585 /* check for vector0 mailbox(=CMDQ RX) event source */ 3586 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3587 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3588 *clearval = cmdq_src_reg; 3589 return HCLGE_VECTOR0_EVENT_MBX; 3590 } 3591 3592 /* print other vector0 event source */ 3593 dev_info(&hdev->pdev->dev, 3594 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3595 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3596 3597 return HCLGE_VECTOR0_EVENT_OTHER; 3598 } 3599 3600 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3601 u32 regclr) 3602 { 3603 #define HCLGE_IMP_RESET_DELAY 5 3604 3605 switch (event_type) { 3606 case HCLGE_VECTOR0_EVENT_PTP: 3607 case HCLGE_VECTOR0_EVENT_RST: 3608 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) 3609 mdelay(HCLGE_IMP_RESET_DELAY); 3610 3611 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3612 break; 3613 case HCLGE_VECTOR0_EVENT_MBX: 3614 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3615 break; 3616 default: 3617 break; 3618 } 3619 } 3620 3621 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3622 { 3623 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3624 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3625 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3626 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3627 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3628 } 3629 3630 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3631 { 3632 writel(enable ? 1 : 0, vector->addr); 3633 } 3634 3635 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3636 { 3637 struct hclge_dev *hdev = data; 3638 unsigned long flags; 3639 u32 clearval = 0; 3640 u32 event_cause; 3641 3642 hclge_enable_vector(&hdev->misc_vector, false); 3643 event_cause = hclge_check_event_cause(hdev, &clearval); 3644 3645 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3646 switch (event_cause) { 3647 case HCLGE_VECTOR0_EVENT_ERR: 3648 hclge_errhand_task_schedule(hdev); 3649 break; 3650 case HCLGE_VECTOR0_EVENT_RST: 3651 hclge_reset_task_schedule(hdev); 3652 break; 3653 case HCLGE_VECTOR0_EVENT_PTP: 3654 spin_lock_irqsave(&hdev->ptp->lock, flags); 3655 hclge_ptp_clean_tx_hwts(hdev); 3656 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3657 break; 3658 case HCLGE_VECTOR0_EVENT_MBX: 3659 /* If we are here then, 3660 * 1. Either we are not handling any mbx task and we are not 3661 * scheduled as well 3662 * OR 3663 * 2. We could be handling a mbx task but nothing more is 3664 * scheduled. 3665 * In both cases, we should schedule mbx task as there are more 3666 * mbx messages reported by this interrupt. 3667 */ 3668 hclge_mbx_task_schedule(hdev); 3669 break; 3670 default: 3671 dev_warn(&hdev->pdev->dev, 3672 "received unknown or unhandled event of vector0\n"); 3673 break; 3674 } 3675 3676 hclge_clear_event_cause(hdev, event_cause, clearval); 3677 3678 /* Enable interrupt if it is not caused by reset event or error event */ 3679 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3680 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3681 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3682 hclge_enable_vector(&hdev->misc_vector, true); 3683 3684 return IRQ_HANDLED; 3685 } 3686 3687 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3688 { 3689 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3690 dev_warn(&hdev->pdev->dev, 3691 "vector(vector_id %d) has been freed.\n", vector_id); 3692 return; 3693 } 3694 3695 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3696 hdev->num_msi_left += 1; 3697 hdev->num_msi_used -= 1; 3698 } 3699 3700 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3701 { 3702 struct hclge_misc_vector *vector = &hdev->misc_vector; 3703 3704 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3705 3706 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3707 hdev->vector_status[0] = 0; 3708 3709 hdev->num_msi_left -= 1; 3710 hdev->num_msi_used += 1; 3711 } 3712 3713 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3714 { 3715 int ret; 3716 3717 hclge_get_misc_vector(hdev); 3718 3719 /* this would be explicitly freed in the end */ 3720 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3721 HCLGE_NAME, pci_name(hdev->pdev)); 3722 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3723 IRQF_NO_AUTOEN, hdev->misc_vector.name, hdev); 3724 if (ret) { 3725 hclge_free_vector(hdev, 0); 3726 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3727 hdev->misc_vector.vector_irq); 3728 } 3729 3730 return ret; 3731 } 3732 3733 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3734 { 3735 free_irq(hdev->misc_vector.vector_irq, hdev); 3736 hclge_free_vector(hdev, 0); 3737 } 3738 3739 int hclge_notify_client(struct hclge_dev *hdev, 3740 enum hnae3_reset_notify_type type) 3741 { 3742 struct hnae3_handle *handle = &hdev->vport[0].nic; 3743 struct hnae3_client *client = hdev->nic_client; 3744 int ret; 3745 3746 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3747 return 0; 3748 3749 if (!client->ops->reset_notify) 3750 return -EOPNOTSUPP; 3751 3752 ret = client->ops->reset_notify(handle, type); 3753 if (ret) 3754 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3755 type, ret); 3756 3757 return ret; 3758 } 3759 3760 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3761 enum hnae3_reset_notify_type type) 3762 { 3763 struct hnae3_handle *handle = &hdev->vport[0].roce; 3764 struct hnae3_client *client = hdev->roce_client; 3765 int ret; 3766 3767 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3768 return 0; 3769 3770 if (!client->ops->reset_notify) 3771 return -EOPNOTSUPP; 3772 3773 ret = client->ops->reset_notify(handle, type); 3774 if (ret) 3775 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3776 type, ret); 3777 3778 return ret; 3779 } 3780 3781 static int hclge_reset_wait(struct hclge_dev *hdev) 3782 { 3783 #define HCLGE_RESET_WATI_MS 100 3784 #define HCLGE_RESET_WAIT_CNT 350 3785 3786 u32 val, reg, reg_bit; 3787 u32 cnt = 0; 3788 3789 switch (hdev->reset_type) { 3790 case HNAE3_IMP_RESET: 3791 reg = HCLGE_GLOBAL_RESET_REG; 3792 reg_bit = HCLGE_IMP_RESET_BIT; 3793 break; 3794 case HNAE3_GLOBAL_RESET: 3795 reg = HCLGE_GLOBAL_RESET_REG; 3796 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3797 break; 3798 case HNAE3_FUNC_RESET: 3799 reg = HCLGE_FUN_RST_ING; 3800 reg_bit = HCLGE_FUN_RST_ING_B; 3801 break; 3802 default: 3803 dev_err(&hdev->pdev->dev, 3804 "Wait for unsupported reset type: %d\n", 3805 hdev->reset_type); 3806 return -EINVAL; 3807 } 3808 3809 val = hclge_read_dev(&hdev->hw, reg); 3810 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3811 msleep(HCLGE_RESET_WATI_MS); 3812 val = hclge_read_dev(&hdev->hw, reg); 3813 cnt++; 3814 } 3815 3816 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3817 dev_warn(&hdev->pdev->dev, 3818 "Wait for reset timeout: %d\n", hdev->reset_type); 3819 return -EBUSY; 3820 } 3821 3822 return 0; 3823 } 3824 3825 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3826 { 3827 struct hclge_vf_rst_cmd *req; 3828 struct hclge_desc desc; 3829 3830 req = (struct hclge_vf_rst_cmd *)desc.data; 3831 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3832 req->dest_vfid = func_id; 3833 3834 if (reset) 3835 req->vf_rst = 0x1; 3836 3837 return hclge_cmd_send(&hdev->hw, &desc, 1); 3838 } 3839 3840 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3841 { 3842 int i; 3843 3844 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3845 struct hclge_vport *vport = &hdev->vport[i]; 3846 int ret; 3847 3848 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3849 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3850 if (ret) { 3851 dev_err(&hdev->pdev->dev, 3852 "set vf(%u) rst failed %d!\n", 3853 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3854 ret); 3855 return ret; 3856 } 3857 3858 if (!reset || 3859 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3860 continue; 3861 3862 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3863 hdev->reset_type == HNAE3_FUNC_RESET) { 3864 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3865 &vport->need_notify); 3866 continue; 3867 } 3868 3869 /* Inform VF to process the reset. 3870 * hclge_inform_reset_assert_to_vf may fail if VF 3871 * driver is not loaded. 3872 */ 3873 ret = hclge_inform_reset_assert_to_vf(vport); 3874 if (ret) 3875 dev_warn(&hdev->pdev->dev, 3876 "inform reset to vf(%u) failed %d!\n", 3877 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3878 ret); 3879 } 3880 3881 return 0; 3882 } 3883 3884 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3885 { 3886 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3887 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3888 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3889 return; 3890 3891 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3892 HCLGE_MBX_SCHED_TIMEOUT)) 3893 dev_warn(&hdev->pdev->dev, 3894 "mbx service task is scheduled after %ums on cpu%u!\n", 3895 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3896 smp_processor_id()); 3897 3898 hclge_mbx_handler(hdev); 3899 3900 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3901 } 3902 3903 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3904 { 3905 struct hclge_pf_rst_sync_cmd *req; 3906 struct hclge_desc desc; 3907 int cnt = 0; 3908 int ret; 3909 3910 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3911 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3912 3913 do { 3914 /* vf need to down netdev by mbx during PF or FLR reset */ 3915 hclge_mailbox_service_task(hdev); 3916 3917 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3918 /* for compatible with old firmware, wait 3919 * 100 ms for VF to stop IO 3920 */ 3921 if (ret == -EOPNOTSUPP) { 3922 msleep(HCLGE_RESET_SYNC_TIME); 3923 return; 3924 } else if (ret) { 3925 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3926 ret); 3927 return; 3928 } else if (req->all_vf_ready) { 3929 return; 3930 } 3931 msleep(HCLGE_PF_RESET_SYNC_TIME); 3932 hclge_comm_cmd_reuse_desc(&desc, true); 3933 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3934 3935 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3936 } 3937 3938 void hclge_report_hw_error(struct hclge_dev *hdev, 3939 enum hnae3_hw_error_type type) 3940 { 3941 struct hnae3_client *client = hdev->nic_client; 3942 3943 if (!client || !client->ops->process_hw_error || 3944 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3945 return; 3946 3947 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3948 } 3949 3950 static void hclge_handle_imp_error(struct hclge_dev *hdev) 3951 { 3952 u32 reg_val; 3953 3954 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3955 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 3956 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 3957 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 3958 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3959 } 3960 3961 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 3962 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 3963 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 3964 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3965 } 3966 } 3967 3968 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 3969 { 3970 struct hclge_desc desc; 3971 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 3972 int ret; 3973 3974 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 3975 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 3976 req->fun_reset_vfid = func_id; 3977 3978 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3979 if (ret) 3980 dev_err(&hdev->pdev->dev, 3981 "send function reset cmd fail, status =%d\n", ret); 3982 3983 return ret; 3984 } 3985 3986 static void hclge_do_reset(struct hclge_dev *hdev) 3987 { 3988 struct hnae3_handle *handle = &hdev->vport[0].nic; 3989 struct pci_dev *pdev = hdev->pdev; 3990 u32 val; 3991 3992 if (hclge_get_hw_reset_stat(handle)) { 3993 dev_info(&pdev->dev, "hardware reset not finish\n"); 3994 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 3995 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 3996 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 3997 return; 3998 } 3999 4000 switch (hdev->reset_type) { 4001 case HNAE3_IMP_RESET: 4002 dev_info(&pdev->dev, "IMP reset requested\n"); 4003 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4004 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 4005 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 4006 break; 4007 case HNAE3_GLOBAL_RESET: 4008 dev_info(&pdev->dev, "global reset requested\n"); 4009 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 4010 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 4011 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 4012 break; 4013 case HNAE3_FUNC_RESET: 4014 dev_info(&pdev->dev, "PF reset requested\n"); 4015 /* schedule again to check later */ 4016 hclge_set_reset_pending(hdev, HNAE3_FUNC_RESET); 4017 hclge_reset_task_schedule(hdev); 4018 break; 4019 default: 4020 dev_warn(&pdev->dev, 4021 "unsupported reset type: %d\n", hdev->reset_type); 4022 break; 4023 } 4024 } 4025 4026 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4027 unsigned long *addr) 4028 { 4029 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4030 struct hclge_dev *hdev = ae_dev->priv; 4031 4032 /* return the highest priority reset level amongst all */ 4033 if (test_bit(HNAE3_IMP_RESET, addr)) { 4034 rst_level = HNAE3_IMP_RESET; 4035 clear_bit(HNAE3_IMP_RESET, addr); 4036 clear_bit(HNAE3_GLOBAL_RESET, addr); 4037 clear_bit(HNAE3_FUNC_RESET, addr); 4038 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4039 rst_level = HNAE3_GLOBAL_RESET; 4040 clear_bit(HNAE3_GLOBAL_RESET, addr); 4041 clear_bit(HNAE3_FUNC_RESET, addr); 4042 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4043 rst_level = HNAE3_FUNC_RESET; 4044 clear_bit(HNAE3_FUNC_RESET, addr); 4045 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4046 rst_level = HNAE3_FLR_RESET; 4047 clear_bit(HNAE3_FLR_RESET, addr); 4048 } 4049 4050 clear_bit(HNAE3_NONE_RESET, addr); 4051 4052 if (hdev->reset_type != HNAE3_NONE_RESET && 4053 rst_level < hdev->reset_type) 4054 return HNAE3_NONE_RESET; 4055 4056 return rst_level; 4057 } 4058 4059 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4060 { 4061 u32 clearval = 0; 4062 4063 switch (hdev->reset_type) { 4064 case HNAE3_IMP_RESET: 4065 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4066 break; 4067 case HNAE3_GLOBAL_RESET: 4068 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4069 break; 4070 default: 4071 break; 4072 } 4073 4074 if (!clearval) 4075 return; 4076 4077 /* For revision 0x20, the reset interrupt source 4078 * can only be cleared after hardware reset done 4079 */ 4080 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4081 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4082 clearval); 4083 4084 hclge_enable_vector(&hdev->misc_vector, true); 4085 } 4086 4087 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4088 { 4089 u32 reg_val; 4090 4091 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4092 if (enable) 4093 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4094 else 4095 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4096 4097 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4098 } 4099 4100 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4101 { 4102 int ret; 4103 4104 ret = hclge_set_all_vf_rst(hdev, true); 4105 if (ret) 4106 return ret; 4107 4108 hclge_func_reset_sync_vf(hdev); 4109 4110 return 0; 4111 } 4112 4113 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4114 { 4115 u32 reg_val; 4116 int ret = 0; 4117 4118 switch (hdev->reset_type) { 4119 case HNAE3_FUNC_RESET: 4120 ret = hclge_func_reset_notify_vf(hdev); 4121 if (ret) 4122 return ret; 4123 4124 ret = hclge_func_reset_cmd(hdev, 0); 4125 if (ret) { 4126 dev_err(&hdev->pdev->dev, 4127 "asserting function reset fail %d!\n", ret); 4128 return ret; 4129 } 4130 4131 /* After performaning pf reset, it is not necessary to do the 4132 * mailbox handling or send any command to firmware, because 4133 * any mailbox handling or command to firmware is only valid 4134 * after hclge_comm_cmd_init is called. 4135 */ 4136 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4137 hdev->rst_stats.pf_rst_cnt++; 4138 break; 4139 case HNAE3_FLR_RESET: 4140 ret = hclge_func_reset_notify_vf(hdev); 4141 if (ret) 4142 return ret; 4143 break; 4144 case HNAE3_IMP_RESET: 4145 hclge_handle_imp_error(hdev); 4146 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4147 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4148 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4149 break; 4150 default: 4151 break; 4152 } 4153 4154 /* inform hardware that preparatory work is done */ 4155 msleep(HCLGE_RESET_SYNC_TIME); 4156 hclge_reset_handshake(hdev, true); 4157 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4158 4159 return ret; 4160 } 4161 4162 static void hclge_show_rst_info(struct hclge_dev *hdev) 4163 { 4164 char *buf; 4165 4166 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4167 if (!buf) 4168 return; 4169 4170 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4171 4172 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4173 4174 kfree(buf); 4175 } 4176 4177 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4178 { 4179 #define MAX_RESET_FAIL_CNT 5 4180 4181 if (hdev->reset_pending) { 4182 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4183 hdev->reset_pending); 4184 return true; 4185 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4186 HCLGE_RESET_INT_M) { 4187 dev_info(&hdev->pdev->dev, 4188 "reset failed because new reset interrupt\n"); 4189 hclge_clear_reset_cause(hdev); 4190 return false; 4191 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4192 hdev->rst_stats.reset_fail_cnt++; 4193 hclge_set_reset_pending(hdev, hdev->reset_type); 4194 dev_info(&hdev->pdev->dev, 4195 "re-schedule reset task(%u)\n", 4196 hdev->rst_stats.reset_fail_cnt); 4197 return true; 4198 } 4199 4200 hclge_clear_reset_cause(hdev); 4201 4202 /* recover the handshake status when reset fail */ 4203 hclge_reset_handshake(hdev, true); 4204 4205 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4206 4207 hclge_show_rst_info(hdev); 4208 4209 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4210 4211 return false; 4212 } 4213 4214 static void hclge_update_reset_level(struct hclge_dev *hdev) 4215 { 4216 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4217 enum hnae3_reset_type reset_level; 4218 4219 /* reset request will not be set during reset, so clear 4220 * pending reset request to avoid unnecessary reset 4221 * caused by the same reason. 4222 */ 4223 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4224 4225 /* if default_reset_request has a higher level reset request, 4226 * it should be handled as soon as possible. since some errors 4227 * need this kind of reset to fix. 4228 */ 4229 reset_level = hclge_get_reset_level(ae_dev, 4230 &hdev->default_reset_request); 4231 if (reset_level != HNAE3_NONE_RESET) 4232 set_bit(reset_level, &hdev->reset_request); 4233 } 4234 4235 static int hclge_set_rst_done(struct hclge_dev *hdev) 4236 { 4237 struct hclge_pf_rst_done_cmd *req; 4238 struct hclge_desc desc; 4239 int ret; 4240 4241 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4242 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4243 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4244 4245 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4246 /* To be compatible with the old firmware, which does not support 4247 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4248 * return success 4249 */ 4250 if (ret == -EOPNOTSUPP) { 4251 dev_warn(&hdev->pdev->dev, 4252 "current firmware does not support command(0x%x)!\n", 4253 HCLGE_OPC_PF_RST_DONE); 4254 return 0; 4255 } else if (ret) { 4256 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4257 ret); 4258 } 4259 4260 return ret; 4261 } 4262 4263 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4264 { 4265 int ret = 0; 4266 4267 switch (hdev->reset_type) { 4268 case HNAE3_FUNC_RESET: 4269 case HNAE3_FLR_RESET: 4270 ret = hclge_set_all_vf_rst(hdev, false); 4271 break; 4272 case HNAE3_GLOBAL_RESET: 4273 case HNAE3_IMP_RESET: 4274 ret = hclge_set_rst_done(hdev); 4275 break; 4276 default: 4277 break; 4278 } 4279 4280 /* clear up the handshake status after re-initialize done */ 4281 hclge_reset_handshake(hdev, false); 4282 4283 return ret; 4284 } 4285 4286 static int hclge_reset_stack(struct hclge_dev *hdev) 4287 { 4288 int ret; 4289 4290 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4291 if (ret) 4292 return ret; 4293 4294 ret = hclge_reset_ae_dev(hdev->ae_dev); 4295 if (ret) 4296 return ret; 4297 4298 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4299 } 4300 4301 static int hclge_reset_prepare(struct hclge_dev *hdev) 4302 { 4303 int ret; 4304 4305 hdev->rst_stats.reset_cnt++; 4306 /* perform reset of the stack & ae device for a client */ 4307 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4308 if (ret) 4309 return ret; 4310 4311 rtnl_lock(); 4312 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4313 rtnl_unlock(); 4314 if (ret) 4315 return ret; 4316 4317 return hclge_reset_prepare_wait(hdev); 4318 } 4319 4320 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4321 { 4322 int ret; 4323 4324 hdev->rst_stats.hw_reset_done_cnt++; 4325 4326 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4327 if (ret) 4328 return ret; 4329 4330 rtnl_lock(); 4331 ret = hclge_reset_stack(hdev); 4332 rtnl_unlock(); 4333 if (ret) 4334 return ret; 4335 4336 hclge_clear_reset_cause(hdev); 4337 4338 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4339 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4340 * times 4341 */ 4342 if (ret && 4343 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4344 return ret; 4345 4346 ret = hclge_reset_prepare_up(hdev); 4347 if (ret) 4348 return ret; 4349 4350 rtnl_lock(); 4351 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4352 rtnl_unlock(); 4353 if (ret) 4354 return ret; 4355 4356 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4357 if (ret) 4358 return ret; 4359 4360 hdev->last_reset_time = jiffies; 4361 hdev->rst_stats.reset_fail_cnt = 0; 4362 hdev->rst_stats.reset_done_cnt++; 4363 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4364 4365 hclge_update_reset_level(hdev); 4366 4367 return 0; 4368 } 4369 4370 static void hclge_reset(struct hclge_dev *hdev) 4371 { 4372 if (hclge_reset_prepare(hdev)) 4373 goto err_reset; 4374 4375 if (hclge_reset_wait(hdev)) 4376 goto err_reset; 4377 4378 if (hclge_reset_rebuild(hdev)) 4379 goto err_reset; 4380 4381 return; 4382 4383 err_reset: 4384 if (hclge_reset_err_handle(hdev)) 4385 hclge_reset_task_schedule(hdev); 4386 } 4387 4388 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4389 { 4390 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4391 struct hclge_dev *hdev = ae_dev->priv; 4392 4393 /* We might end up getting called broadly because of 2 below cases: 4394 * 1. Recoverable error was conveyed through APEI and only way to bring 4395 * normalcy is to reset. 4396 * 2. A new reset request from the stack due to timeout 4397 * 4398 * check if this is a new reset request and we are not here just because 4399 * last reset attempt did not succeed and watchdog hit us again. We will 4400 * know this if last reset request did not occur very recently (watchdog 4401 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4402 * In case of new request we reset the "reset level" to PF reset. 4403 * And if it is a repeat reset request of the most recent one then we 4404 * want to make sure we throttle the reset request. Therefore, we will 4405 * not allow it again before 3*HZ times. 4406 */ 4407 4408 if (time_before(jiffies, (hdev->last_reset_time + 4409 HCLGE_RESET_INTERVAL))) { 4410 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4411 return; 4412 } 4413 4414 if (hdev->default_reset_request) { 4415 hdev->reset_level = 4416 hclge_get_reset_level(ae_dev, 4417 &hdev->default_reset_request); 4418 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4419 hdev->reset_level = HNAE3_FUNC_RESET; 4420 } 4421 4422 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4423 hdev->reset_level); 4424 4425 /* request reset & schedule reset task */ 4426 set_bit(hdev->reset_level, &hdev->reset_request); 4427 hclge_reset_task_schedule(hdev); 4428 4429 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4430 hdev->reset_level++; 4431 } 4432 4433 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4434 enum hnae3_reset_type rst_type) 4435 { 4436 #define HCLGE_SUPPORT_RESET_TYPE \ 4437 (BIT(HNAE3_FLR_RESET) | BIT(HNAE3_FUNC_RESET) | \ 4438 BIT(HNAE3_GLOBAL_RESET) | BIT(HNAE3_IMP_RESET)) 4439 4440 struct hclge_dev *hdev = ae_dev->priv; 4441 4442 if (!(BIT(rst_type) & HCLGE_SUPPORT_RESET_TYPE)) { 4443 /* To prevent reset triggered by hclge_reset_event */ 4444 set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request); 4445 dev_warn(&hdev->pdev->dev, "unsupported reset type %d\n", 4446 rst_type); 4447 return; 4448 } 4449 4450 set_bit(rst_type, &hdev->default_reset_request); 4451 } 4452 4453 static void hclge_reset_timer(struct timer_list *t) 4454 { 4455 struct hclge_dev *hdev = timer_container_of(hdev, t, reset_timer); 4456 4457 /* if default_reset_request has no value, it means that this reset 4458 * request has already be handled, so just return here 4459 */ 4460 if (!hdev->default_reset_request) 4461 return; 4462 4463 dev_info(&hdev->pdev->dev, 4464 "triggering reset in reset timer\n"); 4465 hclge_reset_event(hdev->pdev, NULL); 4466 } 4467 4468 static void hclge_reset_subtask(struct hclge_dev *hdev) 4469 { 4470 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4471 4472 /* check if there is any ongoing reset in the hardware. This status can 4473 * be checked from reset_pending. If there is then, we need to wait for 4474 * hardware to complete reset. 4475 * a. If we are able to figure out in reasonable time that hardware 4476 * has fully resetted then, we can proceed with driver, client 4477 * reset. 4478 * b. else, we can come back later to check this status so re-sched 4479 * now. 4480 */ 4481 hdev->last_reset_time = jiffies; 4482 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4483 if (hdev->reset_type != HNAE3_NONE_RESET) 4484 hclge_reset(hdev); 4485 4486 /* check if we got any *new* reset requests to be honored */ 4487 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4488 if (hdev->reset_type != HNAE3_NONE_RESET) 4489 hclge_do_reset(hdev); 4490 4491 hdev->reset_type = HNAE3_NONE_RESET; 4492 } 4493 4494 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4495 { 4496 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4497 enum hnae3_reset_type reset_type; 4498 4499 if (ae_dev->hw_err_reset_req) { 4500 reset_type = hclge_get_reset_level(ae_dev, 4501 &ae_dev->hw_err_reset_req); 4502 hclge_set_def_reset_request(ae_dev, reset_type); 4503 } 4504 4505 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4506 ae_dev->ops->reset_event(hdev->pdev, NULL); 4507 4508 /* enable interrupt after error handling complete */ 4509 hclge_enable_vector(&hdev->misc_vector, true); 4510 } 4511 4512 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4513 { 4514 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4515 4516 ae_dev->hw_err_reset_req = 0; 4517 4518 if (hclge_find_error_source(hdev)) { 4519 hclge_handle_error_info_log(ae_dev); 4520 hclge_handle_mac_tnl(hdev); 4521 hclge_handle_vf_queue_err_ras(hdev); 4522 } 4523 4524 hclge_handle_err_reset_request(hdev); 4525 } 4526 4527 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4528 { 4529 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4530 struct device *dev = &hdev->pdev->dev; 4531 u32 msix_sts_reg; 4532 4533 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4534 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4535 if (hclge_handle_hw_msix_error 4536 (hdev, &hdev->default_reset_request)) 4537 dev_info(dev, "received msix interrupt 0x%x\n", 4538 msix_sts_reg); 4539 } 4540 4541 hclge_handle_hw_ras_error(ae_dev); 4542 4543 hclge_handle_err_reset_request(hdev); 4544 } 4545 4546 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4547 { 4548 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4549 return; 4550 4551 if (hnae3_dev_ras_imp_supported(hdev)) 4552 hclge_handle_err_recovery(hdev); 4553 else 4554 hclge_misc_err_recovery(hdev); 4555 } 4556 4557 static void hclge_reset_service_task(struct hclge_dev *hdev) 4558 { 4559 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4560 return; 4561 4562 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4563 HCLGE_RESET_SCHED_TIMEOUT)) 4564 dev_warn(&hdev->pdev->dev, 4565 "reset service task is scheduled after %ums on cpu%u!\n", 4566 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4567 smp_processor_id()); 4568 4569 down(&hdev->reset_sem); 4570 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4571 4572 hclge_reset_subtask(hdev); 4573 4574 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4575 up(&hdev->reset_sem); 4576 } 4577 4578 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4579 { 4580 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4581 4582 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4583 int i; 4584 4585 /* start from vport 1 for PF is always alive */ 4586 for (i = 1; i < hdev->num_alloc_vport; i++) { 4587 struct hclge_vport *vport = &hdev->vport[i]; 4588 4589 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4590 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4591 continue; 4592 if (time_after(jiffies, vport->last_active_jiffies + 4593 alive_time)) { 4594 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4595 dev_warn(&hdev->pdev->dev, 4596 "VF %u heartbeat timeout\n", 4597 i - HCLGE_VF_VPORT_START_NUM); 4598 } 4599 } 4600 } 4601 4602 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4603 { 4604 unsigned long delta = round_jiffies_relative(HZ); 4605 4606 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4607 return; 4608 4609 /* Always handle the link updating to make sure link state is 4610 * updated when it is triggered by mbx. 4611 */ 4612 hclge_update_link_status(hdev); 4613 hclge_sync_mac_table(hdev); 4614 hclge_sync_promisc_mode(hdev); 4615 hclge_sync_fd_table(hdev); 4616 4617 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4618 delta = jiffies - hdev->last_serv_processed; 4619 4620 if (delta < round_jiffies_relative(HZ)) { 4621 delta = round_jiffies_relative(HZ) - delta; 4622 goto out; 4623 } 4624 } 4625 4626 hdev->serv_processed_cnt++; 4627 hclge_update_vport_alive(hdev); 4628 4629 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4630 hdev->last_serv_processed = jiffies; 4631 goto out; 4632 } 4633 4634 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4635 hclge_update_stats_for_all(hdev); 4636 4637 hclge_update_port_info(hdev); 4638 hclge_sync_vlan_filter(hdev); 4639 4640 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4641 hclge_rfs_filter_expire(hdev); 4642 4643 hdev->last_serv_processed = jiffies; 4644 4645 out: 4646 hclge_task_schedule(hdev, delta); 4647 } 4648 4649 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4650 { 4651 unsigned long flags; 4652 4653 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4654 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4655 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4656 return; 4657 4658 /* to prevent concurrence with the irq handler */ 4659 spin_lock_irqsave(&hdev->ptp->lock, flags); 4660 4661 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4662 * handler may handle it just before spin_lock_irqsave(). 4663 */ 4664 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4665 hclge_ptp_clean_tx_hwts(hdev); 4666 4667 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4668 } 4669 4670 static void hclge_service_task(struct work_struct *work) 4671 { 4672 struct hclge_dev *hdev = 4673 container_of(work, struct hclge_dev, service_task.work); 4674 4675 hclge_errhand_service_task(hdev); 4676 hclge_reset_service_task(hdev); 4677 hclge_ptp_service_task(hdev); 4678 hclge_mailbox_service_task(hdev); 4679 hclge_periodic_service_task(hdev); 4680 4681 /* Handle error recovery, reset and mbx again in case periodical task 4682 * delays the handling by calling hclge_task_schedule() in 4683 * hclge_periodic_service_task(). 4684 */ 4685 hclge_errhand_service_task(hdev); 4686 hclge_reset_service_task(hdev); 4687 hclge_mailbox_service_task(hdev); 4688 } 4689 4690 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4691 { 4692 /* VF handle has no client */ 4693 if (!handle->client) 4694 return container_of(handle, struct hclge_vport, nic); 4695 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4696 return container_of(handle, struct hclge_vport, roce); 4697 else 4698 return container_of(handle, struct hclge_vport, nic); 4699 } 4700 4701 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4702 struct hnae3_vector_info *vector_info) 4703 { 4704 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4705 4706 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4707 4708 /* need an extend offset to config vector >= 64 */ 4709 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4710 vector_info->io_addr = hdev->hw.hw.io_base + 4711 HCLGE_VECTOR_REG_BASE + 4712 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4713 else 4714 vector_info->io_addr = hdev->hw.hw.io_base + 4715 HCLGE_VECTOR_EXT_REG_BASE + 4716 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4717 HCLGE_VECTOR_REG_OFFSET_H + 4718 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4719 HCLGE_VECTOR_REG_OFFSET; 4720 4721 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4722 hdev->vector_irq[idx] = vector_info->vector; 4723 } 4724 4725 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4726 struct hnae3_vector_info *vector_info) 4727 { 4728 struct hclge_vport *vport = hclge_get_vport(handle); 4729 struct hnae3_vector_info *vector = vector_info; 4730 struct hclge_dev *hdev = vport->back; 4731 int alloc = 0; 4732 u16 i = 0; 4733 u16 j; 4734 4735 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4736 vector_num = min(hdev->num_msi_left, vector_num); 4737 4738 for (j = 0; j < vector_num; j++) { 4739 while (++i < hdev->num_nic_msi) { 4740 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4741 hclge_get_vector_info(hdev, i, vector); 4742 vector++; 4743 alloc++; 4744 4745 break; 4746 } 4747 } 4748 } 4749 hdev->num_msi_left -= alloc; 4750 hdev->num_msi_used += alloc; 4751 4752 return alloc; 4753 } 4754 4755 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4756 { 4757 int i; 4758 4759 for (i = 0; i < hdev->num_msi; i++) 4760 if (vector == hdev->vector_irq[i]) 4761 return i; 4762 4763 return -EINVAL; 4764 } 4765 4766 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4767 { 4768 struct hclge_vport *vport = hclge_get_vport(handle); 4769 struct hclge_dev *hdev = vport->back; 4770 int vector_id; 4771 4772 vector_id = hclge_get_vector_index(hdev, vector); 4773 if (vector_id < 0) { 4774 dev_err(&hdev->pdev->dev, 4775 "Get vector index fail. vector = %d\n", vector); 4776 return vector_id; 4777 } 4778 4779 hclge_free_vector(hdev, vector_id); 4780 4781 return 0; 4782 } 4783 4784 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4785 u8 *key, u8 *hfunc) 4786 { 4787 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4788 struct hclge_vport *vport = hclge_get_vport(handle); 4789 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4790 4791 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4792 4793 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4794 ae_dev->dev_specs.rss_ind_tbl_size); 4795 4796 return 0; 4797 } 4798 4799 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4800 const u8 *key, const u8 hfunc) 4801 { 4802 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4803 struct hclge_vport *vport = hclge_get_vport(handle); 4804 struct hclge_dev *hdev = vport->back; 4805 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4806 int ret, i; 4807 4808 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4809 if (ret) { 4810 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4811 return ret; 4812 } 4813 4814 /* Update the shadow RSS table with user specified qids */ 4815 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4816 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4817 4818 /* Update the hardware */ 4819 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4820 rss_cfg->rss_indirection_tbl); 4821 } 4822 4823 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4824 const struct ethtool_rxfh_fields *nfc) 4825 { 4826 struct hclge_vport *vport = hclge_get_vport(handle); 4827 struct hclge_dev *hdev = vport->back; 4828 int ret; 4829 4830 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4831 &hdev->rss_cfg, nfc); 4832 if (ret) { 4833 dev_err(&hdev->pdev->dev, 4834 "failed to set rss tuple, ret = %d.\n", ret); 4835 return ret; 4836 } 4837 4838 return 0; 4839 } 4840 4841 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4842 struct ethtool_rxfh_fields *nfc) 4843 { 4844 struct hclge_vport *vport = hclge_get_vport(handle); 4845 u8 tuple_sets; 4846 int ret; 4847 4848 nfc->data = 0; 4849 4850 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4851 &tuple_sets); 4852 if (ret || !tuple_sets) 4853 return ret; 4854 4855 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4856 4857 return 0; 4858 } 4859 4860 static int hclge_get_tc_size(struct hnae3_handle *handle) 4861 { 4862 struct hclge_vport *vport = hclge_get_vport(handle); 4863 struct hclge_dev *hdev = vport->back; 4864 4865 return hdev->pf_rss_size_max; 4866 } 4867 4868 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4869 { 4870 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4871 struct hclge_vport *vport = hdev->vport; 4872 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4873 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4874 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4875 struct hnae3_tc_info *tc_info; 4876 u16 roundup_size; 4877 u16 rss_size; 4878 int i; 4879 4880 tc_info = &vport->nic.kinfo.tc_info; 4881 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4882 rss_size = tc_info->tqp_count[i]; 4883 tc_valid[i] = 0; 4884 4885 if (!(hdev->hw_tc_map & BIT(i))) 4886 continue; 4887 4888 /* tc_size set to hardware is the log2 of roundup power of two 4889 * of rss_size, the acutal queue size is limited by indirection 4890 * table. 4891 */ 4892 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4893 rss_size == 0) { 4894 dev_err(&hdev->pdev->dev, 4895 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4896 rss_size); 4897 return -EINVAL; 4898 } 4899 4900 roundup_size = roundup_pow_of_two(rss_size); 4901 roundup_size = ilog2(roundup_size); 4902 4903 tc_valid[i] = 1; 4904 tc_size[i] = roundup_size; 4905 tc_offset[i] = tc_info->tqp_offset[i]; 4906 } 4907 4908 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4909 tc_size); 4910 } 4911 4912 int hclge_rss_init_hw(struct hclge_dev *hdev) 4913 { 4914 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4915 u8 *key = hdev->rss_cfg.rss_hash_key; 4916 u8 hfunc = hdev->rss_cfg.rss_algo; 4917 int ret; 4918 4919 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4920 rss_indir); 4921 if (ret) 4922 return ret; 4923 4924 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4925 if (ret) 4926 return ret; 4927 4928 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 4929 if (ret) 4930 return ret; 4931 4932 return hclge_init_rss_tc_mode(hdev); 4933 } 4934 4935 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4936 int vector_id, bool en, 4937 struct hnae3_ring_chain_node *ring_chain) 4938 { 4939 struct hclge_dev *hdev = vport->back; 4940 struct hnae3_ring_chain_node *node; 4941 struct hclge_desc desc; 4942 struct hclge_ctrl_vector_chain_cmd *req = 4943 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4944 enum hclge_comm_cmd_status status; 4945 enum hclge_opcode_type op; 4946 u16 tqp_type_and_id; 4947 int i; 4948 4949 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4950 hclge_cmd_setup_basic_desc(&desc, op, false); 4951 req->int_vector_id_l = hnae3_get_field(vector_id, 4952 HCLGE_VECTOR_ID_L_M, 4953 HCLGE_VECTOR_ID_L_S); 4954 req->int_vector_id_h = hnae3_get_field(vector_id, 4955 HCLGE_VECTOR_ID_H_M, 4956 HCLGE_VECTOR_ID_H_S); 4957 4958 i = 0; 4959 for (node = ring_chain; node; node = node->next) { 4960 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 4961 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 4962 HCLGE_INT_TYPE_S, 4963 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 4964 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 4965 HCLGE_TQP_ID_S, node->tqp_index); 4966 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 4967 HCLGE_INT_GL_IDX_S, 4968 hnae3_get_field(node->int_gl_idx, 4969 HNAE3_RING_GL_IDX_M, 4970 HNAE3_RING_GL_IDX_S)); 4971 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 4972 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 4973 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 4974 req->vfid = vport->vport_id; 4975 4976 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4977 if (status) { 4978 dev_err(&hdev->pdev->dev, 4979 "Map TQP fail, status is %d.\n", 4980 status); 4981 return -EIO; 4982 } 4983 i = 0; 4984 4985 hclge_cmd_setup_basic_desc(&desc, 4986 op, 4987 false); 4988 req->int_vector_id_l = 4989 hnae3_get_field(vector_id, 4990 HCLGE_VECTOR_ID_L_M, 4991 HCLGE_VECTOR_ID_L_S); 4992 req->int_vector_id_h = 4993 hnae3_get_field(vector_id, 4994 HCLGE_VECTOR_ID_H_M, 4995 HCLGE_VECTOR_ID_H_S); 4996 } 4997 } 4998 4999 if (i > 0) { 5000 req->int_cause_num = i; 5001 req->vfid = vport->vport_id; 5002 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5003 if (status) { 5004 dev_err(&hdev->pdev->dev, 5005 "Map TQP fail, status is %d.\n", status); 5006 return -EIO; 5007 } 5008 } 5009 5010 return 0; 5011 } 5012 5013 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 5014 struct hnae3_ring_chain_node *ring_chain) 5015 { 5016 struct hclge_vport *vport = hclge_get_vport(handle); 5017 struct hclge_dev *hdev = vport->back; 5018 int vector_id; 5019 5020 vector_id = hclge_get_vector_index(hdev, vector); 5021 if (vector_id < 0) { 5022 dev_err(&hdev->pdev->dev, 5023 "failed to get vector index. vector=%d\n", vector); 5024 return vector_id; 5025 } 5026 5027 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5028 } 5029 5030 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5031 struct hnae3_ring_chain_node *ring_chain) 5032 { 5033 struct hclge_vport *vport = hclge_get_vport(handle); 5034 struct hclge_dev *hdev = vport->back; 5035 int vector_id, ret; 5036 5037 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5038 return 0; 5039 5040 vector_id = hclge_get_vector_index(hdev, vector); 5041 if (vector_id < 0) { 5042 dev_err(&handle->pdev->dev, 5043 "Get vector index fail. ret =%d\n", vector_id); 5044 return vector_id; 5045 } 5046 5047 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5048 if (ret) 5049 dev_err(&handle->pdev->dev, 5050 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5051 vector_id, ret); 5052 5053 return ret; 5054 } 5055 5056 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5057 bool en_uc, bool en_mc, bool en_bc) 5058 { 5059 struct hclge_vport *vport = &hdev->vport[vf_id]; 5060 struct hnae3_handle *handle = &vport->nic; 5061 struct hclge_promisc_cfg_cmd *req; 5062 struct hclge_desc desc; 5063 bool uc_tx_en = en_uc; 5064 u8 promisc_cfg = 0; 5065 int ret; 5066 5067 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5068 5069 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5070 req->vf_id = vf_id; 5071 5072 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5073 uc_tx_en = false; 5074 5075 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5076 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5077 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5078 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5079 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5080 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5081 req->extend_promisc = promisc_cfg; 5082 5083 /* to be compatible with DEVICE_VERSION_V1/2 */ 5084 promisc_cfg = 0; 5085 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5086 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5087 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5088 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5089 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5090 req->promisc = promisc_cfg; 5091 5092 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5093 if (ret) 5094 dev_err(&hdev->pdev->dev, 5095 "failed to set vport %u promisc mode, ret = %d.\n", 5096 vf_id, ret); 5097 5098 return ret; 5099 } 5100 5101 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5102 bool en_mc_pmc, bool en_bc_pmc) 5103 { 5104 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5105 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5106 } 5107 5108 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5109 bool en_mc_pmc) 5110 { 5111 struct hclge_vport *vport = hclge_get_vport(handle); 5112 struct hclge_dev *hdev = vport->back; 5113 bool en_bc_pmc = true; 5114 5115 /* For device whose version below V2, if broadcast promisc enabled, 5116 * vlan filter is always bypassed. So broadcast promisc should be 5117 * disabled until user enable promisc mode 5118 */ 5119 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5120 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5121 5122 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5123 en_bc_pmc); 5124 } 5125 5126 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5127 { 5128 struct hclge_vport *vport = hclge_get_vport(handle); 5129 5130 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5131 } 5132 5133 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 5134 { 5135 struct hclge_vport *vport = hclge_get_vport(handle); 5136 struct hclge_dev *hdev = vport->back; 5137 5138 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 5139 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 5140 } 5141 5142 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 5143 { 5144 struct hclge_vport *vport = hclge_get_vport(handle); 5145 struct hclge_dev *hdev = vport->back; 5146 5147 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 5148 } 5149 5150 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 5151 { 5152 struct hclge_vport *vport = hclge_get_vport(handle); 5153 struct hclge_dev *hdev = vport->back; 5154 5155 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 5156 } 5157 5158 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 5159 { 5160 struct hclge_vport *vport = hclge_get_vport(handle); 5161 struct hclge_dev *hdev = vport->back; 5162 5163 return hdev->rst_stats.hw_reset_done_cnt; 5164 } 5165 5166 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 5167 { 5168 #define HCLGE_LINK_STATUS_WAIT_CNT 3 5169 5170 struct hclge_desc desc; 5171 struct hclge_config_mac_mode_cmd *req = 5172 (struct hclge_config_mac_mode_cmd *)desc.data; 5173 u32 loop_en = 0; 5174 int ret; 5175 5176 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 5177 5178 if (enable) { 5179 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 5180 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 5181 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 5182 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 5183 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 5184 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 5185 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 5186 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 5187 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 5188 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 5189 } 5190 5191 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 5192 5193 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5194 if (ret) { 5195 dev_err(&hdev->pdev->dev, 5196 "mac enable fail, ret =%d.\n", ret); 5197 return; 5198 } 5199 5200 if (!enable) 5201 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, 5202 HCLGE_LINK_STATUS_WAIT_CNT); 5203 } 5204 5205 u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5206 u8 vf_id, u8 network_port_id) 5207 { 5208 u32 port_number = 0; 5209 5210 if (port_type == HOST_PORT) { 5211 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5212 pf_id); 5213 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5214 vf_id); 5215 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5216 } else { 5217 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5218 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5219 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5220 } 5221 5222 return port_number; 5223 } 5224 5225 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 5226 u8 switch_param, u8 param_mask) 5227 { 5228 struct hclge_mac_vlan_switch_cmd *req; 5229 struct hclge_desc desc; 5230 u32 func_id; 5231 int ret; 5232 5233 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 5234 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 5235 5236 /* read current config parameter */ 5237 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 5238 true); 5239 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 5240 req->func_id = cpu_to_le32(func_id); 5241 5242 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5243 if (ret) { 5244 dev_err(&hdev->pdev->dev, 5245 "read mac vlan switch parameter fail, ret = %d\n", ret); 5246 return ret; 5247 } 5248 5249 /* modify and write new config parameter */ 5250 hclge_comm_cmd_reuse_desc(&desc, false); 5251 req->switch_param = (req->switch_param & param_mask) | switch_param; 5252 req->param_mask = param_mask; 5253 5254 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5255 if (ret) 5256 dev_err(&hdev->pdev->dev, 5257 "set mac vlan switch parameter fail, ret = %d\n", ret); 5258 return ret; 5259 } 5260 5261 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 5262 int link_ret) 5263 { 5264 #define HCLGE_PHY_LINK_STATUS_NUM 200 5265 5266 struct phy_device *phydev = hdev->hw.mac.phydev; 5267 int i = 0; 5268 int ret; 5269 5270 do { 5271 ret = phy_read_status(phydev); 5272 if (ret) { 5273 dev_err(&hdev->pdev->dev, 5274 "phy update link status fail, ret = %d\n", ret); 5275 return; 5276 } 5277 5278 if (phydev->link == link_ret) 5279 break; 5280 5281 msleep(HCLGE_LINK_STATUS_MS); 5282 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 5283 } 5284 5285 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 5286 int wait_cnt) 5287 { 5288 int link_status; 5289 int i = 0; 5290 int ret; 5291 5292 do { 5293 ret = hclge_get_mac_link_status(hdev, &link_status); 5294 if (ret) 5295 return ret; 5296 if (link_status == link_ret) 5297 return 0; 5298 5299 msleep(HCLGE_LINK_STATUS_MS); 5300 } while (++i < wait_cnt); 5301 return -EBUSY; 5302 } 5303 5304 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 5305 bool is_phy) 5306 { 5307 #define HCLGE_MAC_LINK_STATUS_NUM 100 5308 5309 int link_ret; 5310 5311 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 5312 5313 if (is_phy) 5314 hclge_phy_link_status_wait(hdev, link_ret); 5315 5316 return hclge_mac_link_status_wait(hdev, link_ret, 5317 HCLGE_MAC_LINK_STATUS_NUM); 5318 } 5319 5320 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 5321 { 5322 struct hclge_config_mac_mode_cmd *req; 5323 struct hclge_desc desc; 5324 u32 loop_en; 5325 int ret; 5326 5327 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 5328 /* 1 Read out the MAC mode config at first */ 5329 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 5330 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5331 if (ret) { 5332 dev_err(&hdev->pdev->dev, 5333 "mac loopback get fail, ret =%d.\n", ret); 5334 return ret; 5335 } 5336 5337 /* 2 Then setup the loopback flag */ 5338 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 5339 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 5340 5341 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 5342 5343 /* 3 Config mac work mode with loopback flag 5344 * and its original configure parameters 5345 */ 5346 hclge_comm_cmd_reuse_desc(&desc, false); 5347 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5348 if (ret) 5349 dev_err(&hdev->pdev->dev, 5350 "mac loopback set fail, ret =%d.\n", ret); 5351 return ret; 5352 } 5353 5354 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 5355 enum hnae3_loop loop_mode) 5356 { 5357 struct hclge_common_lb_cmd *req; 5358 struct hclge_desc desc; 5359 u8 loop_mode_b; 5360 int ret; 5361 5362 req = (struct hclge_common_lb_cmd *)desc.data; 5363 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 5364 5365 switch (loop_mode) { 5366 case HNAE3_LOOP_SERIAL_SERDES: 5367 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 5368 break; 5369 case HNAE3_LOOP_PARALLEL_SERDES: 5370 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 5371 break; 5372 case HNAE3_LOOP_PHY: 5373 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 5374 break; 5375 default: 5376 dev_err(&hdev->pdev->dev, 5377 "unsupported loopback mode %d\n", loop_mode); 5378 return -ENOTSUPP; 5379 } 5380 5381 req->mask = loop_mode_b; 5382 if (en) 5383 req->enable = loop_mode_b; 5384 5385 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5386 if (ret) 5387 dev_err(&hdev->pdev->dev, 5388 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 5389 loop_mode, ret); 5390 5391 return ret; 5392 } 5393 5394 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 5395 { 5396 #define HCLGE_COMMON_LB_RETRY_MS 10 5397 #define HCLGE_COMMON_LB_RETRY_NUM 100 5398 5399 struct hclge_common_lb_cmd *req; 5400 struct hclge_desc desc; 5401 u32 i = 0; 5402 int ret; 5403 5404 req = (struct hclge_common_lb_cmd *)desc.data; 5405 5406 do { 5407 msleep(HCLGE_COMMON_LB_RETRY_MS); 5408 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 5409 true); 5410 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5411 if (ret) { 5412 dev_err(&hdev->pdev->dev, 5413 "failed to get loopback done status, ret = %d\n", 5414 ret); 5415 return ret; 5416 } 5417 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 5418 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 5419 5420 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 5421 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 5422 return -EBUSY; 5423 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 5424 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 5425 return -EIO; 5426 } 5427 5428 return 0; 5429 } 5430 5431 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 5432 enum hnae3_loop loop_mode) 5433 { 5434 int ret; 5435 5436 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 5437 if (ret) 5438 return ret; 5439 5440 return hclge_cfg_common_loopback_wait(hdev); 5441 } 5442 5443 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 5444 enum hnae3_loop loop_mode) 5445 { 5446 int ret; 5447 5448 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 5449 if (ret) 5450 return ret; 5451 5452 hclge_cfg_mac_mode(hdev, en); 5453 5454 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 5455 if (ret) 5456 dev_err(&hdev->pdev->dev, 5457 "serdes loopback config mac mode timeout\n"); 5458 5459 return ret; 5460 } 5461 5462 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 5463 struct phy_device *phydev) 5464 { 5465 int ret; 5466 5467 if (!phydev->suspended) { 5468 ret = phy_suspend(phydev); 5469 if (ret) 5470 return ret; 5471 } 5472 5473 ret = phy_resume(phydev); 5474 if (ret) 5475 return ret; 5476 5477 return phy_loopback(phydev, true, 0); 5478 } 5479 5480 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 5481 struct phy_device *phydev) 5482 { 5483 int ret; 5484 5485 ret = phy_loopback(phydev, false, 0); 5486 if (ret) 5487 return ret; 5488 5489 return phy_suspend(phydev); 5490 } 5491 5492 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 5493 { 5494 struct phy_device *phydev = hdev->hw.mac.phydev; 5495 int ret; 5496 5497 if (!phydev) { 5498 if (hnae3_dev_phy_imp_supported(hdev)) 5499 return hclge_set_common_loopback(hdev, en, 5500 HNAE3_LOOP_PHY); 5501 return -ENOTSUPP; 5502 } 5503 5504 if (en) 5505 ret = hclge_enable_phy_loopback(hdev, phydev); 5506 else 5507 ret = hclge_disable_phy_loopback(hdev, phydev); 5508 if (ret) { 5509 dev_err(&hdev->pdev->dev, 5510 "set phy loopback fail, ret = %d\n", ret); 5511 return ret; 5512 } 5513 5514 hclge_cfg_mac_mode(hdev, en); 5515 5516 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 5517 if (ret) 5518 dev_err(&hdev->pdev->dev, 5519 "phy loopback config mac mode timeout\n"); 5520 5521 return ret; 5522 } 5523 5524 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 5525 u16 stream_id, bool enable) 5526 { 5527 struct hclge_desc desc; 5528 struct hclge_cfg_com_tqp_queue_cmd *req = 5529 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 5530 5531 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 5532 req->tqp_id = cpu_to_le16(tqp_id); 5533 req->stream_id = cpu_to_le16(stream_id); 5534 if (enable) 5535 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 5536 5537 return hclge_cmd_send(&hdev->hw, &desc, 1); 5538 } 5539 5540 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 5541 { 5542 struct hclge_vport *vport = hclge_get_vport(handle); 5543 struct hclge_dev *hdev = vport->back; 5544 int ret; 5545 u16 i; 5546 5547 for (i = 0; i < handle->kinfo.num_tqps; i++) { 5548 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 5549 if (ret) 5550 return ret; 5551 } 5552 return 0; 5553 } 5554 5555 static int hclge_set_loopback(struct hnae3_handle *handle, 5556 enum hnae3_loop loop_mode, bool en) 5557 { 5558 struct hclge_vport *vport = hclge_get_vport(handle); 5559 struct hclge_dev *hdev = vport->back; 5560 int ret = 0; 5561 5562 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 5563 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 5564 * the same, the packets are looped back in the SSU. If SSU loopback 5565 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 5566 */ 5567 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 5568 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 5569 5570 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 5571 HCLGE_SWITCH_ALW_LPBK_MASK); 5572 if (ret) 5573 return ret; 5574 } 5575 5576 switch (loop_mode) { 5577 case HNAE3_LOOP_APP: 5578 ret = hclge_set_app_loopback(hdev, en); 5579 break; 5580 case HNAE3_LOOP_SERIAL_SERDES: 5581 case HNAE3_LOOP_PARALLEL_SERDES: 5582 ret = hclge_set_common_loopback(hdev, en, loop_mode); 5583 break; 5584 case HNAE3_LOOP_PHY: 5585 ret = hclge_set_phy_loopback(hdev, en); 5586 break; 5587 case HNAE3_LOOP_EXTERNAL: 5588 break; 5589 default: 5590 ret = -ENOTSUPP; 5591 dev_err(&hdev->pdev->dev, 5592 "loop_mode %d is not supported\n", loop_mode); 5593 break; 5594 } 5595 5596 if (ret) 5597 return ret; 5598 5599 ret = hclge_tqp_enable(handle, en); 5600 if (ret) 5601 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 5602 str_enable_disable(en), ret); 5603 5604 return ret; 5605 } 5606 5607 static int hclge_set_default_loopback(struct hclge_dev *hdev) 5608 { 5609 int ret; 5610 5611 ret = hclge_set_app_loopback(hdev, false); 5612 if (ret) 5613 return ret; 5614 5615 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 5616 if (ret) 5617 return ret; 5618 5619 return hclge_cfg_common_loopback(hdev, false, 5620 HNAE3_LOOP_PARALLEL_SERDES); 5621 } 5622 5623 static void hclge_flush_link_update(struct hclge_dev *hdev) 5624 { 5625 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 5626 5627 unsigned long last = hdev->serv_processed_cnt; 5628 int i = 0; 5629 5630 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 5631 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 5632 last == hdev->serv_processed_cnt) 5633 usleep_range(1, 1); 5634 } 5635 5636 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 5637 { 5638 struct hclge_vport *vport = hclge_get_vport(handle); 5639 struct hclge_dev *hdev = vport->back; 5640 5641 if (enable) { 5642 hclge_task_schedule(hdev, 0); 5643 } else { 5644 /* Set the DOWN flag here to disable link updating */ 5645 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5646 5647 smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */ 5648 hclge_flush_link_update(hdev); 5649 } 5650 } 5651 5652 static int hclge_ae_start(struct hnae3_handle *handle) 5653 { 5654 struct hclge_vport *vport = hclge_get_vport(handle); 5655 struct hclge_dev *hdev = vport->back; 5656 5657 /* mac enable */ 5658 hclge_cfg_mac_mode(hdev, true); 5659 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 5660 hdev->hw.mac.link = 0; 5661 5662 /* reset tqp stats */ 5663 hclge_comm_reset_tqp_stats(handle); 5664 5665 hclge_mac_start_phy(hdev); 5666 5667 return 0; 5668 } 5669 5670 static void hclge_ae_stop(struct hnae3_handle *handle) 5671 { 5672 struct hclge_vport *vport = hclge_get_vport(handle); 5673 struct hclge_dev *hdev = vport->back; 5674 5675 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5676 spin_lock_bh(&hdev->fd_rule_lock); 5677 hclge_clear_arfs_rules(hdev); 5678 spin_unlock_bh(&hdev->fd_rule_lock); 5679 5680 /* If it is not PF reset or FLR, the firmware will disable the MAC, 5681 * so it only need to stop phy here. 5682 */ 5683 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 5684 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 5685 HCLGE_PFC_DISABLE); 5686 if (hdev->reset_type != HNAE3_FUNC_RESET && 5687 hdev->reset_type != HNAE3_FLR_RESET) { 5688 hclge_mac_stop_phy(hdev); 5689 hclge_update_link_status(hdev); 5690 return; 5691 } 5692 } 5693 5694 hclge_reset_tqp(handle); 5695 5696 hclge_config_mac_tnl_int(hdev, false); 5697 5698 /* Mac disable */ 5699 hclge_cfg_mac_mode(hdev, false); 5700 5701 hclge_mac_stop_phy(hdev); 5702 5703 /* reset tqp stats */ 5704 hclge_comm_reset_tqp_stats(handle); 5705 hclge_update_link_status(hdev); 5706 } 5707 5708 int hclge_vport_start(struct hclge_vport *vport) 5709 { 5710 struct hclge_dev *hdev = vport->back; 5711 5712 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 5713 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 5714 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5715 vport->last_active_jiffies = jiffies; 5716 vport->need_notify = 0; 5717 5718 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 5719 if (vport->vport_id) { 5720 hclge_restore_mac_table_common(vport); 5721 hclge_restore_vport_vlan_table(vport); 5722 } else { 5723 hclge_restore_hw_table(hdev); 5724 } 5725 } 5726 5727 clear_bit(vport->vport_id, hdev->vport_config_block); 5728 5729 return 0; 5730 } 5731 5732 void hclge_vport_stop(struct hclge_vport *vport) 5733 { 5734 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 5735 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 5736 vport->need_notify = 0; 5737 } 5738 5739 static int hclge_client_start(struct hnae3_handle *handle) 5740 { 5741 struct hclge_vport *vport = hclge_get_vport(handle); 5742 5743 return hclge_vport_start(vport); 5744 } 5745 5746 static void hclge_client_stop(struct hnae3_handle *handle) 5747 { 5748 struct hclge_vport *vport = hclge_get_vport(handle); 5749 5750 hclge_vport_stop(vport); 5751 } 5752 5753 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 5754 u16 cmdq_resp, u8 resp_code, 5755 enum hclge_mac_vlan_tbl_opcode op) 5756 { 5757 struct hclge_dev *hdev = vport->back; 5758 5759 if (cmdq_resp) { 5760 dev_err(&hdev->pdev->dev, 5761 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 5762 cmdq_resp); 5763 return -EIO; 5764 } 5765 5766 if (op == HCLGE_MAC_VLAN_ADD) { 5767 if (!resp_code || resp_code == 1) 5768 return 0; 5769 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 5770 resp_code == HCLGE_ADD_MC_OVERFLOW) 5771 return -ENOSPC; 5772 5773 dev_err(&hdev->pdev->dev, 5774 "add mac addr failed for undefined, code=%u.\n", 5775 resp_code); 5776 return -EIO; 5777 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 5778 if (!resp_code) { 5779 return 0; 5780 } else if (resp_code == 1) { 5781 dev_dbg(&hdev->pdev->dev, 5782 "remove mac addr failed for miss.\n"); 5783 return -ENOENT; 5784 } 5785 5786 dev_err(&hdev->pdev->dev, 5787 "remove mac addr failed for undefined, code=%u.\n", 5788 resp_code); 5789 return -EIO; 5790 } else if (op == HCLGE_MAC_VLAN_LKUP) { 5791 if (!resp_code) { 5792 return 0; 5793 } else if (resp_code == 1) { 5794 dev_dbg(&hdev->pdev->dev, 5795 "lookup mac addr failed for miss.\n"); 5796 return -ENOENT; 5797 } 5798 5799 dev_err(&hdev->pdev->dev, 5800 "lookup mac addr failed for undefined, code=%u.\n", 5801 resp_code); 5802 return -EIO; 5803 } 5804 5805 dev_err(&hdev->pdev->dev, 5806 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 5807 5808 return -EINVAL; 5809 } 5810 5811 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 5812 { 5813 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 5814 5815 unsigned int word_num; 5816 unsigned int bit_num; 5817 5818 if (vfid > 255 || vfid < 0) 5819 return -EIO; 5820 5821 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 5822 word_num = vfid / 32; 5823 bit_num = vfid % 32; 5824 if (clr) 5825 desc[1].data[word_num] &= cpu_to_le32(~(1U << bit_num)); 5826 else 5827 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 5828 } else { 5829 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 5830 bit_num = vfid % 32; 5831 if (clr) 5832 desc[2].data[word_num] &= cpu_to_le32(~(1U << bit_num)); 5833 else 5834 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 5835 } 5836 5837 return 0; 5838 } 5839 5840 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 5841 { 5842 #define HCLGE_DESC_NUMBER 3 5843 #define HCLGE_FUNC_NUMBER_PER_DESC 6 5844 int i, j; 5845 5846 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 5847 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 5848 if (desc[i].data[j]) 5849 return false; 5850 5851 return true; 5852 } 5853 5854 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 5855 const u8 *addr, bool is_mc) 5856 { 5857 const unsigned char *mac_addr = addr; 5858 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 5859 (mac_addr[0]) | (mac_addr[1] << 8); 5860 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 5861 5862 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5863 if (is_mc) { 5864 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 5865 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5866 } 5867 5868 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 5869 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 5870 } 5871 5872 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 5873 struct hclge_mac_vlan_tbl_entry_cmd *req) 5874 { 5875 struct hclge_dev *hdev = vport->back; 5876 struct hclge_desc desc; 5877 u8 resp_code; 5878 u16 retval; 5879 int ret; 5880 5881 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 5882 5883 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5884 5885 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5886 if (ret) { 5887 dev_err(&hdev->pdev->dev, 5888 "del mac addr failed for cmd_send, ret =%d.\n", 5889 ret); 5890 return ret; 5891 } 5892 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 5893 retval = le16_to_cpu(desc.retval); 5894 5895 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 5896 HCLGE_MAC_VLAN_REMOVE); 5897 } 5898 5899 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 5900 struct hclge_mac_vlan_tbl_entry_cmd *req, 5901 struct hclge_desc *desc, 5902 bool is_mc) 5903 { 5904 struct hclge_dev *hdev = vport->back; 5905 u8 resp_code; 5906 u16 retval; 5907 int ret; 5908 5909 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 5910 if (is_mc) { 5911 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5912 memcpy(desc[0].data, 5913 req, 5914 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5915 hclge_cmd_setup_basic_desc(&desc[1], 5916 HCLGE_OPC_MAC_VLAN_ADD, 5917 true); 5918 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5919 hclge_cmd_setup_basic_desc(&desc[2], 5920 HCLGE_OPC_MAC_VLAN_ADD, 5921 true); 5922 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5923 } else { 5924 memcpy(desc[0].data, 5925 req, 5926 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5927 ret = hclge_cmd_send(&hdev->hw, desc, 1); 5928 } 5929 if (ret) { 5930 dev_err(&hdev->pdev->dev, 5931 "lookup mac addr failed for cmd_send, ret =%d.\n", 5932 ret); 5933 return ret; 5934 } 5935 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 5936 retval = le16_to_cpu(desc[0].retval); 5937 5938 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 5939 HCLGE_MAC_VLAN_LKUP); 5940 } 5941 5942 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 5943 struct hclge_mac_vlan_tbl_entry_cmd *req, 5944 struct hclge_desc *mc_desc) 5945 { 5946 struct hclge_dev *hdev = vport->back; 5947 int cfg_status; 5948 u8 resp_code; 5949 u16 retval; 5950 int ret; 5951 5952 if (!mc_desc) { 5953 struct hclge_desc desc; 5954 5955 hclge_cmd_setup_basic_desc(&desc, 5956 HCLGE_OPC_MAC_VLAN_ADD, 5957 false); 5958 memcpy(desc.data, req, 5959 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5960 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5961 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 5962 retval = le16_to_cpu(desc.retval); 5963 5964 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 5965 resp_code, 5966 HCLGE_MAC_VLAN_ADD); 5967 } else { 5968 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 5969 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5970 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 5971 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5972 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 5973 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 5974 memcpy(mc_desc[0].data, req, 5975 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5976 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 5977 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 5978 retval = le16_to_cpu(mc_desc[0].retval); 5979 5980 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 5981 resp_code, 5982 HCLGE_MAC_VLAN_ADD); 5983 } 5984 5985 if (ret) { 5986 dev_err(&hdev->pdev->dev, 5987 "add mac addr failed for cmd_send, ret =%d.\n", 5988 ret); 5989 return ret; 5990 } 5991 5992 return cfg_status; 5993 } 5994 5995 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 5996 u16 *allocated_size) 5997 { 5998 struct hclge_umv_spc_alc_cmd *req; 5999 struct hclge_desc desc; 6000 int ret; 6001 6002 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 6003 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 6004 6005 req->space_size = cpu_to_le32(space_size); 6006 6007 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6008 if (ret) { 6009 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 6010 ret); 6011 return ret; 6012 } 6013 6014 *allocated_size = le32_to_cpu(desc.data[1]); 6015 6016 return 0; 6017 } 6018 6019 static int hclge_init_umv_space(struct hclge_dev *hdev) 6020 { 6021 u16 allocated_size = 0; 6022 int ret; 6023 6024 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 6025 if (ret) 6026 return ret; 6027 6028 if (allocated_size < hdev->wanted_umv_size) 6029 dev_warn(&hdev->pdev->dev, 6030 "failed to alloc umv space, want %u, get %u\n", 6031 hdev->wanted_umv_size, allocated_size); 6032 6033 hdev->max_umv_size = allocated_size; 6034 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 6035 hdev->share_umv_size = hdev->priv_umv_size + 6036 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 6037 6038 if (hdev->ae_dev->dev_specs.mc_mac_size) 6039 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 6040 6041 return 0; 6042 } 6043 6044 static void hclge_reset_umv_space(struct hclge_dev *hdev) 6045 { 6046 struct hclge_vport *vport; 6047 int i; 6048 6049 for (i = 0; i < hdev->num_alloc_vport; i++) { 6050 vport = &hdev->vport[i]; 6051 vport->used_umv_num = 0; 6052 } 6053 6054 mutex_lock(&hdev->vport_lock); 6055 hdev->share_umv_size = hdev->priv_umv_size + 6056 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 6057 mutex_unlock(&hdev->vport_lock); 6058 6059 hdev->used_mc_mac_num = 0; 6060 } 6061 6062 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 6063 { 6064 struct hclge_dev *hdev = vport->back; 6065 bool is_full; 6066 6067 if (need_lock) 6068 mutex_lock(&hdev->vport_lock); 6069 6070 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 6071 hdev->share_umv_size == 0); 6072 6073 if (need_lock) 6074 mutex_unlock(&hdev->vport_lock); 6075 6076 return is_full; 6077 } 6078 6079 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 6080 { 6081 struct hclge_dev *hdev = vport->back; 6082 6083 if (is_free) { 6084 if (vport->used_umv_num > hdev->priv_umv_size) 6085 hdev->share_umv_size++; 6086 6087 if (vport->used_umv_num > 0) 6088 vport->used_umv_num--; 6089 } else { 6090 if (vport->used_umv_num >= hdev->priv_umv_size && 6091 hdev->share_umv_size > 0) 6092 hdev->share_umv_size--; 6093 vport->used_umv_num++; 6094 } 6095 } 6096 6097 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 6098 const u8 *mac_addr) 6099 { 6100 struct hclge_mac_node *mac_node, *tmp; 6101 6102 list_for_each_entry_safe(mac_node, tmp, list, node) 6103 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 6104 return mac_node; 6105 6106 return NULL; 6107 } 6108 6109 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 6110 enum HCLGE_MAC_NODE_STATE state) 6111 { 6112 switch (state) { 6113 /* from set_rx_mode or tmp_add_list */ 6114 case HCLGE_MAC_TO_ADD: 6115 if (mac_node->state == HCLGE_MAC_TO_DEL) 6116 mac_node->state = HCLGE_MAC_ACTIVE; 6117 break; 6118 /* only from set_rx_mode */ 6119 case HCLGE_MAC_TO_DEL: 6120 if (mac_node->state == HCLGE_MAC_TO_ADD) { 6121 list_del(&mac_node->node); 6122 kfree(mac_node); 6123 } else { 6124 mac_node->state = HCLGE_MAC_TO_DEL; 6125 } 6126 break; 6127 /* only from tmp_add_list, the mac_node->state won't be 6128 * ACTIVE. 6129 */ 6130 case HCLGE_MAC_ACTIVE: 6131 if (mac_node->state == HCLGE_MAC_TO_ADD) 6132 mac_node->state = HCLGE_MAC_ACTIVE; 6133 6134 break; 6135 } 6136 } 6137 6138 int hclge_update_mac_list(struct hclge_vport *vport, 6139 enum HCLGE_MAC_NODE_STATE state, 6140 enum HCLGE_MAC_ADDR_TYPE mac_type, 6141 const unsigned char *addr) 6142 { 6143 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6144 struct hclge_dev *hdev = vport->back; 6145 struct hclge_mac_node *mac_node; 6146 struct list_head *list; 6147 6148 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 6149 &vport->uc_mac_list : &vport->mc_mac_list; 6150 6151 spin_lock_bh(&vport->mac_list_lock); 6152 6153 /* if the mac addr is already in the mac list, no need to add a new 6154 * one into it, just check the mac addr state, convert it to a new 6155 * state, or just remove it, or do nothing. 6156 */ 6157 mac_node = hclge_find_mac_node(list, addr); 6158 if (mac_node) { 6159 hclge_update_mac_node(mac_node, state); 6160 spin_unlock_bh(&vport->mac_list_lock); 6161 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 6162 return 0; 6163 } 6164 6165 /* if this address is never added, unnecessary to delete */ 6166 if (state == HCLGE_MAC_TO_DEL) { 6167 spin_unlock_bh(&vport->mac_list_lock); 6168 hnae3_format_mac_addr(format_mac_addr, addr); 6169 dev_err(&hdev->pdev->dev, 6170 "failed to delete address %s from mac list\n", 6171 format_mac_addr); 6172 return -ENOENT; 6173 } 6174 6175 mac_node = kzalloc_obj(*mac_node, GFP_ATOMIC); 6176 if (!mac_node) { 6177 spin_unlock_bh(&vport->mac_list_lock); 6178 return -ENOMEM; 6179 } 6180 6181 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 6182 6183 mac_node->state = state; 6184 ether_addr_copy(mac_node->mac_addr, addr); 6185 list_add_tail(&mac_node->node, list); 6186 6187 spin_unlock_bh(&vport->mac_list_lock); 6188 6189 return 0; 6190 } 6191 6192 static int hclge_add_uc_addr(struct hnae3_handle *handle, 6193 const unsigned char *addr) 6194 { 6195 struct hclge_vport *vport = hclge_get_vport(handle); 6196 6197 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 6198 addr); 6199 } 6200 6201 int hclge_add_uc_addr_common(struct hclge_vport *vport, 6202 const unsigned char *addr) 6203 { 6204 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6205 struct hclge_dev *hdev = vport->back; 6206 struct hclge_mac_vlan_tbl_entry_cmd req; 6207 struct hclge_desc desc; 6208 u16 egress_port = 0; 6209 int ret; 6210 6211 /* mac addr check */ 6212 if (is_zero_ether_addr(addr) || 6213 is_broadcast_ether_addr(addr) || 6214 is_multicast_ether_addr(addr)) { 6215 hnae3_format_mac_addr(format_mac_addr, addr); 6216 dev_err(&hdev->pdev->dev, 6217 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 6218 format_mac_addr, is_zero_ether_addr(addr), 6219 is_broadcast_ether_addr(addr), 6220 is_multicast_ether_addr(addr)); 6221 return -EINVAL; 6222 } 6223 6224 memset(&req, 0, sizeof(req)); 6225 6226 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 6227 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 6228 6229 req.egress_port = cpu_to_le16(egress_port); 6230 6231 hclge_prepare_mac_addr(&req, addr, false); 6232 6233 /* Lookup the mac address in the mac_vlan table, and add 6234 * it if the entry is inexistent. Repeated unicast entry 6235 * is not allowed in the mac vlan table. 6236 */ 6237 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 6238 if (ret == -ENOENT) { 6239 mutex_lock(&hdev->vport_lock); 6240 if (!hclge_is_umv_space_full(vport, false)) { 6241 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 6242 if (!ret) 6243 hclge_update_umv_space(vport, false); 6244 mutex_unlock(&hdev->vport_lock); 6245 return ret; 6246 } 6247 mutex_unlock(&hdev->vport_lock); 6248 6249 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 6250 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 6251 hdev->priv_umv_size); 6252 6253 return -ENOSPC; 6254 } 6255 6256 /* check if we just hit the duplicate */ 6257 if (!ret) 6258 return -EEXIST; 6259 6260 return ret; 6261 } 6262 6263 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 6264 const unsigned char *addr) 6265 { 6266 struct hclge_vport *vport = hclge_get_vport(handle); 6267 6268 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 6269 addr); 6270 } 6271 6272 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 6273 const unsigned char *addr) 6274 { 6275 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6276 struct hclge_dev *hdev = vport->back; 6277 struct hclge_mac_vlan_tbl_entry_cmd req; 6278 int ret; 6279 6280 /* mac addr check */ 6281 if (is_zero_ether_addr(addr) || 6282 is_broadcast_ether_addr(addr) || 6283 is_multicast_ether_addr(addr)) { 6284 hnae3_format_mac_addr(format_mac_addr, addr); 6285 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 6286 format_mac_addr); 6287 return -EINVAL; 6288 } 6289 6290 memset(&req, 0, sizeof(req)); 6291 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 6292 hclge_prepare_mac_addr(&req, addr, false); 6293 ret = hclge_remove_mac_vlan_tbl(vport, &req); 6294 if (!ret || ret == -ENOENT) { 6295 mutex_lock(&hdev->vport_lock); 6296 hclge_update_umv_space(vport, true); 6297 mutex_unlock(&hdev->vport_lock); 6298 return 0; 6299 } 6300 6301 return ret; 6302 } 6303 6304 static int hclge_add_mc_addr(struct hnae3_handle *handle, 6305 const unsigned char *addr) 6306 { 6307 struct hclge_vport *vport = hclge_get_vport(handle); 6308 6309 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 6310 addr); 6311 } 6312 6313 int hclge_add_mc_addr_common(struct hclge_vport *vport, 6314 const unsigned char *addr) 6315 { 6316 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6317 struct hclge_dev *hdev = vport->back; 6318 struct hclge_mac_vlan_tbl_entry_cmd req; 6319 struct hclge_desc desc[3]; 6320 bool is_new_addr = false; 6321 int status; 6322 6323 /* mac addr check */ 6324 if (!is_multicast_ether_addr(addr)) { 6325 hnae3_format_mac_addr(format_mac_addr, addr); 6326 dev_err(&hdev->pdev->dev, 6327 "Add mc mac err! invalid mac:%s.\n", 6328 format_mac_addr); 6329 return -EINVAL; 6330 } 6331 memset(&req, 0, sizeof(req)); 6332 hclge_prepare_mac_addr(&req, addr, true); 6333 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 6334 if (status) { 6335 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 6336 hdev->used_mc_mac_num >= 6337 hdev->ae_dev->dev_specs.mc_mac_size) 6338 goto err_no_space; 6339 6340 is_new_addr = true; 6341 6342 /* This mac addr do not exist, add new entry for it */ 6343 memset(desc[0].data, 0, sizeof(desc[0].data)); 6344 memset(desc[1].data, 0, sizeof(desc[0].data)); 6345 memset(desc[2].data, 0, sizeof(desc[0].data)); 6346 } 6347 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 6348 if (status) 6349 return status; 6350 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 6351 if (status == -ENOSPC) 6352 goto err_no_space; 6353 else if (!status && is_new_addr) 6354 hdev->used_mc_mac_num++; 6355 6356 return status; 6357 6358 err_no_space: 6359 /* if already overflow, not to print each time */ 6360 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 6361 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 6362 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 6363 } 6364 6365 return -ENOSPC; 6366 } 6367 6368 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 6369 const unsigned char *addr) 6370 { 6371 struct hclge_vport *vport = hclge_get_vport(handle); 6372 6373 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 6374 addr); 6375 } 6376 6377 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 6378 const unsigned char *addr) 6379 { 6380 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6381 struct hclge_dev *hdev = vport->back; 6382 struct hclge_mac_vlan_tbl_entry_cmd req; 6383 enum hclge_comm_cmd_status status; 6384 struct hclge_desc desc[3]; 6385 6386 /* mac addr check */ 6387 if (!is_multicast_ether_addr(addr)) { 6388 hnae3_format_mac_addr(format_mac_addr, addr); 6389 dev_dbg(&hdev->pdev->dev, 6390 "Remove mc mac err! invalid mac:%s.\n", 6391 format_mac_addr); 6392 return -EINVAL; 6393 } 6394 6395 memset(&req, 0, sizeof(req)); 6396 hclge_prepare_mac_addr(&req, addr, true); 6397 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 6398 if (!status) { 6399 /* This mac addr exist, remove this handle's VFID for it */ 6400 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 6401 if (status) 6402 return status; 6403 6404 if (hclge_is_all_function_id_zero(desc)) { 6405 /* All the vfid is zero, so need to delete this entry */ 6406 status = hclge_remove_mac_vlan_tbl(vport, &req); 6407 if (!status) 6408 hdev->used_mc_mac_num--; 6409 } else { 6410 /* Not all the vfid is zero, update the vfid */ 6411 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 6412 } 6413 } else if (status == -ENOENT) { 6414 status = 0; 6415 } 6416 6417 return status; 6418 } 6419 6420 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 6421 struct list_head *list, 6422 enum HCLGE_MAC_ADDR_TYPE mac_type) 6423 { 6424 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 6425 struct hclge_mac_node *mac_node, *tmp; 6426 int ret; 6427 6428 if (mac_type == HCLGE_MAC_ADDR_UC) 6429 sync = hclge_add_uc_addr_common; 6430 else 6431 sync = hclge_add_mc_addr_common; 6432 6433 list_for_each_entry_safe(mac_node, tmp, list, node) { 6434 ret = sync(vport, mac_node->mac_addr); 6435 if (!ret) { 6436 mac_node->state = HCLGE_MAC_ACTIVE; 6437 } else { 6438 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 6439 &vport->state); 6440 6441 /* If one unicast mac address is existing in hardware, 6442 * we need to try whether other unicast mac addresses 6443 * are new addresses that can be added. 6444 * Multicast mac address can be reusable, even though 6445 * there is no space to add new multicast mac address, 6446 * we should check whether other mac addresses are 6447 * existing in hardware for reuse. 6448 */ 6449 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 6450 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 6451 break; 6452 } 6453 } 6454 } 6455 6456 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 6457 struct list_head *list, 6458 enum HCLGE_MAC_ADDR_TYPE mac_type) 6459 { 6460 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 6461 struct hclge_mac_node *mac_node, *tmp; 6462 int ret; 6463 6464 if (mac_type == HCLGE_MAC_ADDR_UC) 6465 unsync = hclge_rm_uc_addr_common; 6466 else 6467 unsync = hclge_rm_mc_addr_common; 6468 6469 list_for_each_entry_safe(mac_node, tmp, list, node) { 6470 ret = unsync(vport, mac_node->mac_addr); 6471 if (!ret || ret == -ENOENT) { 6472 list_del(&mac_node->node); 6473 kfree(mac_node); 6474 } else { 6475 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 6476 &vport->state); 6477 break; 6478 } 6479 } 6480 } 6481 6482 static bool hclge_sync_from_add_list(struct list_head *add_list, 6483 struct list_head *mac_list) 6484 { 6485 struct hclge_mac_node *mac_node, *tmp, *new_node; 6486 bool all_added = true; 6487 6488 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 6489 if (mac_node->state == HCLGE_MAC_TO_ADD) 6490 all_added = false; 6491 6492 /* if the mac address from tmp_add_list is not in the 6493 * uc/mc_mac_list, it means have received a TO_DEL request 6494 * during the time window of adding the mac address into mac 6495 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 6496 * then it will be removed at next time. else it must be TO_ADD, 6497 * this address hasn't been added into mac table, 6498 * so just remove the mac node. 6499 */ 6500 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 6501 if (new_node) { 6502 hclge_update_mac_node(new_node, mac_node->state); 6503 list_del(&mac_node->node); 6504 kfree(mac_node); 6505 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 6506 mac_node->state = HCLGE_MAC_TO_DEL; 6507 list_move_tail(&mac_node->node, mac_list); 6508 } else { 6509 list_del(&mac_node->node); 6510 kfree(mac_node); 6511 } 6512 } 6513 6514 return all_added; 6515 } 6516 6517 static void hclge_sync_from_del_list(struct list_head *del_list, 6518 struct list_head *mac_list) 6519 { 6520 struct hclge_mac_node *mac_node, *tmp, *new_node; 6521 6522 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 6523 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 6524 if (new_node) { 6525 /* If the mac addr exists in the mac list, it means 6526 * received a new TO_ADD request during the time window 6527 * of configuring the mac address. For the mac node 6528 * state is TO_ADD, and the address is already in the 6529 * in the hardware(due to delete fail), so we just need 6530 * to change the mac node state to ACTIVE. 6531 */ 6532 new_node->state = HCLGE_MAC_ACTIVE; 6533 list_del(&mac_node->node); 6534 kfree(mac_node); 6535 } else { 6536 list_move_tail(&mac_node->node, mac_list); 6537 } 6538 } 6539 } 6540 6541 static void hclge_update_overflow_flags(struct hclge_vport *vport, 6542 enum HCLGE_MAC_ADDR_TYPE mac_type, 6543 bool is_all_added) 6544 { 6545 if (mac_type == HCLGE_MAC_ADDR_UC) { 6546 if (is_all_added) 6547 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 6548 else if (hclge_is_umv_space_full(vport, true)) 6549 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 6550 } else { 6551 if (is_all_added) 6552 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 6553 else 6554 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 6555 } 6556 } 6557 6558 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 6559 enum HCLGE_MAC_ADDR_TYPE mac_type) 6560 { 6561 struct hclge_mac_node *mac_node, *tmp, *new_node; 6562 struct list_head tmp_add_list, tmp_del_list; 6563 struct list_head *list; 6564 bool all_added; 6565 6566 INIT_LIST_HEAD(&tmp_add_list); 6567 INIT_LIST_HEAD(&tmp_del_list); 6568 6569 /* move the mac addr to the tmp_add_list and tmp_del_list, then 6570 * we can add/delete these mac addr outside the spin lock 6571 */ 6572 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 6573 &vport->uc_mac_list : &vport->mc_mac_list; 6574 6575 spin_lock_bh(&vport->mac_list_lock); 6576 6577 list_for_each_entry_safe(mac_node, tmp, list, node) { 6578 switch (mac_node->state) { 6579 case HCLGE_MAC_TO_DEL: 6580 list_move_tail(&mac_node->node, &tmp_del_list); 6581 break; 6582 case HCLGE_MAC_TO_ADD: 6583 new_node = kzalloc_obj(*new_node, GFP_ATOMIC); 6584 if (!new_node) 6585 goto stop_traverse; 6586 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 6587 new_node->state = mac_node->state; 6588 list_add_tail(&new_node->node, &tmp_add_list); 6589 break; 6590 default: 6591 break; 6592 } 6593 } 6594 6595 stop_traverse: 6596 spin_unlock_bh(&vport->mac_list_lock); 6597 6598 /* delete first, in order to get max mac table space for adding */ 6599 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 6600 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 6601 6602 /* if some mac addresses were added/deleted fail, move back to the 6603 * mac_list, and retry at next time. 6604 */ 6605 spin_lock_bh(&vport->mac_list_lock); 6606 6607 hclge_sync_from_del_list(&tmp_del_list, list); 6608 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 6609 6610 spin_unlock_bh(&vport->mac_list_lock); 6611 6612 hclge_update_overflow_flags(vport, mac_type, all_added); 6613 } 6614 6615 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 6616 { 6617 struct hclge_dev *hdev = vport->back; 6618 6619 if (test_bit(vport->vport_id, hdev->vport_config_block)) 6620 return false; 6621 6622 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 6623 return true; 6624 6625 return false; 6626 } 6627 6628 static void hclge_sync_mac_table(struct hclge_dev *hdev) 6629 { 6630 int i; 6631 6632 for (i = 0; i < hdev->num_alloc_vport; i++) { 6633 struct hclge_vport *vport = &hdev->vport[i]; 6634 6635 if (!hclge_need_sync_mac_table(vport)) 6636 continue; 6637 6638 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 6639 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 6640 } 6641 } 6642 6643 static void hclge_build_del_list(struct list_head *list, 6644 bool is_del_list, 6645 struct list_head *tmp_del_list) 6646 { 6647 struct hclge_mac_node *mac_cfg, *tmp; 6648 6649 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 6650 switch (mac_cfg->state) { 6651 case HCLGE_MAC_TO_DEL: 6652 case HCLGE_MAC_ACTIVE: 6653 list_move_tail(&mac_cfg->node, tmp_del_list); 6654 break; 6655 case HCLGE_MAC_TO_ADD: 6656 if (is_del_list) { 6657 list_del(&mac_cfg->node); 6658 kfree(mac_cfg); 6659 } 6660 break; 6661 } 6662 } 6663 } 6664 6665 static void hclge_unsync_del_list(struct hclge_vport *vport, 6666 int (*unsync)(struct hclge_vport *vport, 6667 const unsigned char *addr), 6668 bool is_del_list, 6669 struct list_head *tmp_del_list) 6670 { 6671 struct hclge_mac_node *mac_cfg, *tmp; 6672 int ret; 6673 6674 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 6675 ret = unsync(vport, mac_cfg->mac_addr); 6676 if (!ret || ret == -ENOENT) { 6677 /* clear all mac addr from hardware, but remain these 6678 * mac addr in the mac list, and restore them after 6679 * vf reset finished. 6680 */ 6681 if (!is_del_list && 6682 mac_cfg->state == HCLGE_MAC_ACTIVE) { 6683 mac_cfg->state = HCLGE_MAC_TO_ADD; 6684 } else { 6685 list_del(&mac_cfg->node); 6686 kfree(mac_cfg); 6687 } 6688 } else if (is_del_list) { 6689 mac_cfg->state = HCLGE_MAC_TO_DEL; 6690 } 6691 } 6692 } 6693 6694 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 6695 enum HCLGE_MAC_ADDR_TYPE mac_type) 6696 { 6697 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 6698 struct hclge_dev *hdev = vport->back; 6699 struct list_head tmp_del_list, *list; 6700 6701 if (mac_type == HCLGE_MAC_ADDR_UC) { 6702 list = &vport->uc_mac_list; 6703 unsync = hclge_rm_uc_addr_common; 6704 } else { 6705 list = &vport->mc_mac_list; 6706 unsync = hclge_rm_mc_addr_common; 6707 } 6708 6709 INIT_LIST_HEAD(&tmp_del_list); 6710 6711 if (!is_del_list) 6712 set_bit(vport->vport_id, hdev->vport_config_block); 6713 6714 spin_lock_bh(&vport->mac_list_lock); 6715 6716 hclge_build_del_list(list, is_del_list, &tmp_del_list); 6717 6718 spin_unlock_bh(&vport->mac_list_lock); 6719 6720 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 6721 6722 spin_lock_bh(&vport->mac_list_lock); 6723 6724 hclge_sync_from_del_list(&tmp_del_list, list); 6725 6726 spin_unlock_bh(&vport->mac_list_lock); 6727 } 6728 6729 /* remove all mac address when uninitailize */ 6730 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 6731 enum HCLGE_MAC_ADDR_TYPE mac_type) 6732 { 6733 struct hclge_mac_node *mac_node, *tmp; 6734 struct hclge_dev *hdev = vport->back; 6735 struct list_head tmp_del_list, *list; 6736 6737 INIT_LIST_HEAD(&tmp_del_list); 6738 6739 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 6740 &vport->uc_mac_list : &vport->mc_mac_list; 6741 6742 spin_lock_bh(&vport->mac_list_lock); 6743 6744 list_for_each_entry_safe(mac_node, tmp, list, node) { 6745 switch (mac_node->state) { 6746 case HCLGE_MAC_TO_DEL: 6747 case HCLGE_MAC_ACTIVE: 6748 list_move_tail(&mac_node->node, &tmp_del_list); 6749 break; 6750 case HCLGE_MAC_TO_ADD: 6751 list_del(&mac_node->node); 6752 kfree(mac_node); 6753 break; 6754 } 6755 } 6756 6757 spin_unlock_bh(&vport->mac_list_lock); 6758 6759 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 6760 6761 if (!list_empty(&tmp_del_list)) 6762 dev_warn(&hdev->pdev->dev, 6763 "uninit %s mac list for vport %u not completely.\n", 6764 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 6765 vport->vport_id); 6766 6767 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 6768 list_del(&mac_node->node); 6769 kfree(mac_node); 6770 } 6771 } 6772 6773 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 6774 { 6775 struct hclge_vport *vport; 6776 int i; 6777 6778 for (i = 0; i < hdev->num_alloc_vport; i++) { 6779 vport = &hdev->vport[i]; 6780 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 6781 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 6782 } 6783 } 6784 6785 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 6786 u16 cmdq_resp, u8 resp_code) 6787 { 6788 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 6789 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 6790 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 6791 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 6792 6793 int return_status; 6794 6795 if (cmdq_resp) { 6796 dev_err(&hdev->pdev->dev, 6797 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 6798 cmdq_resp); 6799 return -EIO; 6800 } 6801 6802 switch (resp_code) { 6803 case HCLGE_ETHERTYPE_SUCCESS_ADD: 6804 case HCLGE_ETHERTYPE_ALREADY_ADD: 6805 return_status = 0; 6806 break; 6807 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 6808 dev_err(&hdev->pdev->dev, 6809 "add mac ethertype failed for manager table overflow.\n"); 6810 return_status = -EIO; 6811 break; 6812 case HCLGE_ETHERTYPE_KEY_CONFLICT: 6813 dev_err(&hdev->pdev->dev, 6814 "add mac ethertype failed for key conflict.\n"); 6815 return_status = -EIO; 6816 break; 6817 default: 6818 dev_err(&hdev->pdev->dev, 6819 "add mac ethertype failed for undefined, code=%u.\n", 6820 resp_code); 6821 return_status = -EIO; 6822 } 6823 6824 return return_status; 6825 } 6826 6827 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 6828 u8 *mac_addr) 6829 { 6830 struct hclge_vport *vport = hclge_get_vport(handle); 6831 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6832 struct hclge_dev *hdev = vport->back; 6833 6834 vport = hclge_get_vf_vport(hdev, vf); 6835 if (!vport) 6836 return -EINVAL; 6837 6838 hnae3_format_mac_addr(format_mac_addr, mac_addr); 6839 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 6840 dev_info(&hdev->pdev->dev, 6841 "Specified MAC(=%s) is same as before, no change committed!\n", 6842 format_mac_addr); 6843 return 0; 6844 } 6845 6846 ether_addr_copy(vport->vf_info.mac, mac_addr); 6847 6848 /* there is a timewindow for PF to know VF unalive, it may 6849 * cause send mailbox fail, but it doesn't matter, VF will 6850 * query it when reinit. 6851 */ 6852 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 6853 dev_info(&hdev->pdev->dev, 6854 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 6855 vf, format_mac_addr); 6856 (void)hclge_inform_reset_assert_to_vf(vport); 6857 return 0; 6858 } 6859 6860 dev_info(&hdev->pdev->dev, 6861 "MAC of VF %d has been set to %s, will be active after VF reset\n", 6862 vf, format_mac_addr); 6863 return 0; 6864 } 6865 6866 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 6867 const struct hclge_mac_mgr_tbl_entry_cmd *req) 6868 { 6869 struct hclge_desc desc; 6870 u8 resp_code; 6871 u16 retval; 6872 int ret; 6873 6874 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 6875 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 6876 6877 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6878 if (ret) { 6879 dev_err(&hdev->pdev->dev, 6880 "add mac ethertype failed for cmd_send, ret =%d.\n", 6881 ret); 6882 return ret; 6883 } 6884 6885 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 6886 retval = le16_to_cpu(desc.retval); 6887 6888 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 6889 } 6890 6891 static int init_mgr_tbl(struct hclge_dev *hdev) 6892 { 6893 int ret; 6894 u32 i; 6895 6896 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 6897 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 6898 if (ret) { 6899 dev_err(&hdev->pdev->dev, 6900 "add mac ethertype failed, ret =%d.\n", 6901 ret); 6902 return ret; 6903 } 6904 } 6905 6906 return 0; 6907 } 6908 6909 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 6910 { 6911 struct hclge_vport *vport = hclge_get_vport(handle); 6912 struct hclge_dev *hdev = vport->back; 6913 6914 ether_addr_copy(p, hdev->hw.mac.mac_addr); 6915 } 6916 6917 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 6918 const u8 *old_addr, const u8 *new_addr) 6919 { 6920 struct list_head *list = &vport->uc_mac_list; 6921 struct hclge_mac_node *old_node, *new_node; 6922 6923 new_node = hclge_find_mac_node(list, new_addr); 6924 if (!new_node) { 6925 new_node = kzalloc_obj(*new_node, GFP_ATOMIC); 6926 if (!new_node) 6927 return -ENOMEM; 6928 6929 new_node->state = HCLGE_MAC_TO_ADD; 6930 ether_addr_copy(new_node->mac_addr, new_addr); 6931 list_add(&new_node->node, list); 6932 } else { 6933 if (new_node->state == HCLGE_MAC_TO_DEL) 6934 new_node->state = HCLGE_MAC_ACTIVE; 6935 6936 /* make sure the new addr is in the list head, avoid dev 6937 * addr may be not re-added into mac table for the umv space 6938 * limitation after global/imp reset which will clear mac 6939 * table by hardware. 6940 */ 6941 list_move(&new_node->node, list); 6942 } 6943 6944 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 6945 old_node = hclge_find_mac_node(list, old_addr); 6946 if (old_node) { 6947 if (old_node->state == HCLGE_MAC_TO_ADD) { 6948 list_del(&old_node->node); 6949 kfree(old_node); 6950 } else { 6951 old_node->state = HCLGE_MAC_TO_DEL; 6952 } 6953 } 6954 } 6955 6956 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 6957 6958 return 0; 6959 } 6960 6961 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 6962 bool is_first) 6963 { 6964 const unsigned char *new_addr = (const unsigned char *)p; 6965 struct hclge_vport *vport = hclge_get_vport(handle); 6966 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6967 struct hclge_dev *hdev = vport->back; 6968 unsigned char *old_addr = NULL; 6969 int ret; 6970 6971 /* mac addr check */ 6972 if (is_zero_ether_addr(new_addr) || 6973 is_broadcast_ether_addr(new_addr) || 6974 is_multicast_ether_addr(new_addr)) { 6975 hnae3_format_mac_addr(format_mac_addr, new_addr); 6976 dev_err(&hdev->pdev->dev, 6977 "change uc mac err! invalid mac: %s.\n", 6978 format_mac_addr); 6979 return -EINVAL; 6980 } 6981 6982 ret = hclge_pause_addr_cfg(hdev, new_addr); 6983 if (ret) { 6984 dev_err(&hdev->pdev->dev, 6985 "failed to configure mac pause address, ret = %d\n", 6986 ret); 6987 return ret; 6988 } 6989 6990 if (!is_first) 6991 old_addr = hdev->hw.mac.mac_addr; 6992 6993 spin_lock_bh(&vport->mac_list_lock); 6994 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 6995 if (ret) { 6996 hnae3_format_mac_addr(format_mac_addr, new_addr); 6997 dev_err(&hdev->pdev->dev, 6998 "failed to change the mac addr:%s, ret = %d\n", 6999 format_mac_addr, ret); 7000 spin_unlock_bh(&vport->mac_list_lock); 7001 7002 if (!is_first) 7003 hclge_pause_addr_cfg(hdev, old_addr); 7004 7005 return ret; 7006 } 7007 /* we must update dev addr with spin lock protect, preventing dev addr 7008 * being removed by set_rx_mode path. 7009 */ 7010 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 7011 spin_unlock_bh(&vport->mac_list_lock); 7012 7013 hclge_task_schedule(hdev, 0); 7014 7015 return 0; 7016 } 7017 7018 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 7019 { 7020 struct mii_ioctl_data *data = if_mii(ifr); 7021 7022 if (!hnae3_dev_phy_imp_supported(hdev)) 7023 return -EOPNOTSUPP; 7024 7025 switch (cmd) { 7026 case SIOCGMIIPHY: 7027 data->phy_id = hdev->hw.mac.phy_addr; 7028 /* this command reads phy id and register at the same time */ 7029 fallthrough; 7030 case SIOCGMIIREG: 7031 return hclge_read_phy_reg(hdev, data->reg_num, &data->val_out); 7032 7033 case SIOCSMIIREG: 7034 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 7035 default: 7036 return -EOPNOTSUPP; 7037 } 7038 } 7039 7040 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 7041 int cmd) 7042 { 7043 struct hclge_vport *vport = hclge_get_vport(handle); 7044 struct hclge_dev *hdev = vport->back; 7045 7046 if (!hdev->hw.mac.phydev) 7047 return hclge_mii_ioctl(hdev, ifr, cmd); 7048 7049 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 7050 } 7051 7052 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 7053 bool bypass_en) 7054 { 7055 struct hclge_port_vlan_filter_bypass_cmd *req; 7056 struct hclge_desc desc; 7057 int ret; 7058 7059 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 7060 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 7061 req->vf_id = vf_id; 7062 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 7063 bypass_en ? 1 : 0); 7064 7065 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7066 if (ret) 7067 dev_err(&hdev->pdev->dev, 7068 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 7069 vf_id, ret); 7070 7071 return ret; 7072 } 7073 7074 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 7075 u8 fe_type, bool filter_en, u8 vf_id) 7076 { 7077 struct hclge_vlan_filter_ctrl_cmd *req; 7078 struct hclge_desc desc; 7079 int ret; 7080 7081 /* read current vlan filter parameter */ 7082 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 7083 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 7084 req->vlan_type = vlan_type; 7085 req->vf_id = vf_id; 7086 7087 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7088 if (ret) { 7089 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 7090 vf_id, ret); 7091 return ret; 7092 } 7093 7094 /* modify and write new config parameter */ 7095 hclge_comm_cmd_reuse_desc(&desc, false); 7096 req->vlan_fe = filter_en ? 7097 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 7098 7099 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7100 if (ret) 7101 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 7102 vf_id, ret); 7103 7104 return ret; 7105 } 7106 7107 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 7108 { 7109 struct hclge_dev *hdev = vport->back; 7110 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 7111 int ret; 7112 7113 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 7114 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 7115 HCLGE_FILTER_FE_EGRESS_V1_B, 7116 enable, vport->vport_id); 7117 7118 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 7119 HCLGE_FILTER_FE_EGRESS, enable, 7120 vport->vport_id); 7121 if (ret) 7122 return ret; 7123 7124 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 7125 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 7126 !enable); 7127 } else if (!vport->vport_id) { 7128 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 7129 enable = false; 7130 7131 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 7132 HCLGE_FILTER_FE_INGRESS, 7133 enable, 0); 7134 } 7135 7136 return ret; 7137 } 7138 7139 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 7140 { 7141 struct hnae3_handle *handle = &vport->nic; 7142 struct hclge_vport_vlan_cfg *vlan, *tmp; 7143 struct hclge_dev *hdev = vport->back; 7144 7145 if (vport->vport_id) { 7146 if (vport->port_base_vlan_cfg.state != 7147 HNAE3_PORT_BASE_VLAN_DISABLE) 7148 return true; 7149 7150 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 7151 return false; 7152 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 7153 return false; 7154 } 7155 7156 if (!vport->req_vlan_fltr_en) 7157 return false; 7158 7159 /* compatible with former device, always enable vlan filter */ 7160 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 7161 return true; 7162 7163 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 7164 if (vlan->vlan_id != 0) 7165 return true; 7166 7167 return false; 7168 } 7169 7170 static int __hclge_enable_vport_vlan_filter(struct hclge_vport *vport, 7171 bool request_en) 7172 { 7173 bool need_en; 7174 int ret; 7175 7176 need_en = hclge_need_enable_vport_vlan_filter(vport); 7177 if (need_en == vport->cur_vlan_fltr_en) 7178 return 0; 7179 7180 ret = hclge_set_vport_vlan_filter(vport, need_en); 7181 if (ret) 7182 return ret; 7183 7184 vport->cur_vlan_fltr_en = need_en; 7185 7186 return 0; 7187 } 7188 7189 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 7190 { 7191 struct hclge_dev *hdev = vport->back; 7192 int ret; 7193 7194 mutex_lock(&hdev->vport_lock); 7195 vport->req_vlan_fltr_en = request_en; 7196 ret = __hclge_enable_vport_vlan_filter(vport, request_en); 7197 mutex_unlock(&hdev->vport_lock); 7198 7199 return ret; 7200 } 7201 7202 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 7203 { 7204 struct hclge_vport *vport = hclge_get_vport(handle); 7205 7206 return hclge_enable_vport_vlan_filter(vport, enable); 7207 } 7208 7209 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 7210 bool is_kill, u16 vlan, 7211 struct hclge_desc *desc) 7212 { 7213 struct hclge_vlan_filter_vf_cfg_cmd *req0; 7214 struct hclge_vlan_filter_vf_cfg_cmd *req1; 7215 u8 vf_byte_val; 7216 u8 vf_byte_off; 7217 int ret; 7218 7219 hclge_cmd_setup_basic_desc(&desc[0], 7220 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 7221 hclge_cmd_setup_basic_desc(&desc[1], 7222 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 7223 7224 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 7225 7226 vf_byte_off = vfid / 8; 7227 vf_byte_val = 1 << (vfid % 8); 7228 7229 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 7230 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 7231 7232 req0->vlan_id = cpu_to_le16(vlan); 7233 req0->vlan_cfg = is_kill; 7234 7235 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 7236 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 7237 else 7238 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 7239 7240 ret = hclge_cmd_send(&hdev->hw, desc, 2); 7241 if (ret) { 7242 dev_err(&hdev->pdev->dev, 7243 "Send vf vlan command fail, ret =%d.\n", 7244 ret); 7245 return ret; 7246 } 7247 7248 return 0; 7249 } 7250 7251 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 7252 bool is_kill, struct hclge_desc *desc) 7253 { 7254 struct hclge_vlan_filter_vf_cfg_cmd *req; 7255 7256 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 7257 7258 if (!is_kill) { 7259 #define HCLGE_VF_VLAN_NO_ENTRY 2 7260 if (!req->resp_code || req->resp_code == 1) 7261 return 0; 7262 7263 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 7264 set_bit(vfid, hdev->vf_vlan_full); 7265 dev_warn(&hdev->pdev->dev, 7266 "vf vlan table is full, vf vlan filter is disabled\n"); 7267 return 0; 7268 } 7269 7270 dev_err(&hdev->pdev->dev, 7271 "Add vf vlan filter fail, ret =%u.\n", 7272 req->resp_code); 7273 } else { 7274 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 7275 if (!req->resp_code) 7276 return 0; 7277 7278 /* vf vlan filter is disabled when vf vlan table is full, 7279 * then new vlan id will not be added into vf vlan table. 7280 * Just return 0 without warning, avoid massive verbose 7281 * print logs when unload. 7282 */ 7283 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 7284 return 0; 7285 7286 dev_err(&hdev->pdev->dev, 7287 "Kill vf vlan filter fail, ret =%u.\n", 7288 req->resp_code); 7289 } 7290 7291 return -EIO; 7292 } 7293 7294 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 7295 bool is_kill, u16 vlan) 7296 { 7297 struct hclge_vport *vport = &hdev->vport[vfid]; 7298 struct hclge_desc desc[2]; 7299 int ret; 7300 7301 /* if vf vlan table is full, firmware will close vf vlan filter, it 7302 * is unable and unnecessary to add new vlan id to vf vlan filter. 7303 * If spoof check is enable, and vf vlan is full, it shouldn't add 7304 * new vlan, because tx packets with these vlan id will be dropped. 7305 */ 7306 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 7307 if (vport->vf_info.spoofchk && vlan) { 7308 dev_err(&hdev->pdev->dev, 7309 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 7310 return -EPERM; 7311 } 7312 return 0; 7313 } 7314 7315 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 7316 if (ret) 7317 return ret; 7318 7319 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 7320 } 7321 7322 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 7323 u16 vlan_id, bool is_kill) 7324 { 7325 struct hclge_vlan_filter_pf_cfg_cmd *req; 7326 struct hclge_desc desc; 7327 u8 vlan_offset_byte_val; 7328 u8 vlan_offset_byte; 7329 u8 vlan_offset_160; 7330 int ret; 7331 7332 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 7333 7334 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 7335 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 7336 HCLGE_VLAN_BYTE_SIZE; 7337 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 7338 7339 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 7340 req->vlan_offset = vlan_offset_160; 7341 req->vlan_cfg = is_kill; 7342 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 7343 7344 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7345 if (ret) 7346 dev_err(&hdev->pdev->dev, 7347 "port vlan command, send fail, ret =%d.\n", ret); 7348 return ret; 7349 } 7350 7351 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 7352 u16 vlan_id, bool is_kill) 7353 { 7354 /* vlan 0 may be added twice when 8021q module is enabled */ 7355 if (!is_kill && !vlan_id && 7356 test_bit(vport_id, hdev->vlan_table[vlan_id])) 7357 return false; 7358 7359 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 7360 dev_warn(&hdev->pdev->dev, 7361 "Add port vlan failed, vport %u is already in vlan %u\n", 7362 vport_id, vlan_id); 7363 return false; 7364 } 7365 7366 if (is_kill && 7367 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 7368 dev_warn(&hdev->pdev->dev, 7369 "Delete port vlan failed, vport %u is not in vlan %u\n", 7370 vport_id, vlan_id); 7371 return false; 7372 } 7373 7374 return true; 7375 } 7376 7377 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 7378 u16 vport_id, u16 vlan_id, 7379 bool is_kill) 7380 { 7381 u16 vport_idx, vport_num = 0; 7382 int ret; 7383 7384 if (is_kill && !vlan_id) 7385 return 0; 7386 7387 if (vlan_id >= VLAN_N_VID) 7388 return -EINVAL; 7389 7390 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 7391 if (ret) { 7392 dev_err(&hdev->pdev->dev, 7393 "Set %u vport vlan filter config fail, ret =%d.\n", 7394 vport_id, ret); 7395 return ret; 7396 } 7397 7398 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 7399 return 0; 7400 7401 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 7402 vport_num++; 7403 7404 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 7405 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 7406 is_kill); 7407 7408 return ret; 7409 } 7410 7411 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 7412 { 7413 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 7414 struct hclge_vport_vtag_tx_cfg_cmd *req; 7415 struct hclge_dev *hdev = vport->back; 7416 struct hclge_desc desc; 7417 u16 bmap_index; 7418 int status; 7419 7420 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 7421 7422 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 7423 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 7424 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 7425 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 7426 vcfg->accept_tag1 ? 1 : 0); 7427 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 7428 vcfg->accept_untag1 ? 1 : 0); 7429 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 7430 vcfg->accept_tag2 ? 1 : 0); 7431 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 7432 vcfg->accept_untag2 ? 1 : 0); 7433 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 7434 vcfg->insert_tag1_en ? 1 : 0); 7435 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 7436 vcfg->insert_tag2_en ? 1 : 0); 7437 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 7438 vcfg->tag_shift_mode_en ? 1 : 0); 7439 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 7440 7441 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 7442 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 7443 HCLGE_VF_NUM_PER_BYTE; 7444 req->vf_bitmap[bmap_index] = 7445 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 7446 7447 status = hclge_cmd_send(&hdev->hw, &desc, 1); 7448 if (status) 7449 dev_err(&hdev->pdev->dev, 7450 "Send port txvlan cfg command fail, ret =%d\n", 7451 status); 7452 7453 return status; 7454 } 7455 7456 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 7457 { 7458 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 7459 struct hclge_vport_vtag_rx_cfg_cmd *req; 7460 struct hclge_dev *hdev = vport->back; 7461 struct hclge_desc desc; 7462 u16 bmap_index; 7463 int status; 7464 7465 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 7466 7467 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 7468 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 7469 vcfg->strip_tag1_en ? 1 : 0); 7470 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 7471 vcfg->strip_tag2_en ? 1 : 0); 7472 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 7473 vcfg->vlan1_vlan_prionly ? 1 : 0); 7474 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 7475 vcfg->vlan2_vlan_prionly ? 1 : 0); 7476 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 7477 vcfg->strip_tag1_discard_en ? 1 : 0); 7478 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 7479 vcfg->strip_tag2_discard_en ? 1 : 0); 7480 7481 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 7482 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 7483 HCLGE_VF_NUM_PER_BYTE; 7484 req->vf_bitmap[bmap_index] = 7485 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 7486 7487 status = hclge_cmd_send(&hdev->hw, &desc, 1); 7488 if (status) 7489 dev_err(&hdev->pdev->dev, 7490 "Send port rxvlan cfg command fail, ret =%d\n", 7491 status); 7492 7493 return status; 7494 } 7495 7496 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 7497 u16 port_base_vlan_state, 7498 u16 vlan_tag, u8 qos) 7499 { 7500 int ret; 7501 7502 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 7503 vport->txvlan_cfg.accept_tag1 = true; 7504 vport->txvlan_cfg.insert_tag1_en = false; 7505 vport->txvlan_cfg.default_tag1 = 0; 7506 } else { 7507 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 7508 7509 vport->txvlan_cfg.accept_tag1 = 7510 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 7511 vport->txvlan_cfg.insert_tag1_en = true; 7512 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 7513 vlan_tag; 7514 } 7515 7516 vport->txvlan_cfg.accept_untag1 = true; 7517 7518 /* accept_tag2 and accept_untag2 are not supported on 7519 * pdev revision(0x20), new revision support them, 7520 * this two fields can not be configured by user. 7521 */ 7522 vport->txvlan_cfg.accept_tag2 = true; 7523 vport->txvlan_cfg.accept_untag2 = true; 7524 vport->txvlan_cfg.insert_tag2_en = false; 7525 vport->txvlan_cfg.default_tag2 = 0; 7526 vport->txvlan_cfg.tag_shift_mode_en = true; 7527 7528 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 7529 vport->rxvlan_cfg.strip_tag1_en = false; 7530 vport->rxvlan_cfg.strip_tag2_en = 7531 vport->rxvlan_cfg.rx_vlan_offload_en; 7532 vport->rxvlan_cfg.strip_tag2_discard_en = false; 7533 } else { 7534 vport->rxvlan_cfg.strip_tag1_en = 7535 vport->rxvlan_cfg.rx_vlan_offload_en; 7536 vport->rxvlan_cfg.strip_tag2_en = true; 7537 vport->rxvlan_cfg.strip_tag2_discard_en = true; 7538 } 7539 7540 vport->rxvlan_cfg.strip_tag1_discard_en = false; 7541 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 7542 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 7543 7544 ret = hclge_set_vlan_tx_offload_cfg(vport); 7545 if (ret) 7546 return ret; 7547 7548 return hclge_set_vlan_rx_offload_cfg(vport); 7549 } 7550 7551 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 7552 { 7553 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 7554 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 7555 struct hclge_desc desc; 7556 int status; 7557 7558 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 7559 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 7560 rx_req->ot_fst_vlan_type = 7561 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 7562 rx_req->ot_sec_vlan_type = 7563 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 7564 rx_req->in_fst_vlan_type = 7565 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 7566 rx_req->in_sec_vlan_type = 7567 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 7568 7569 status = hclge_cmd_send(&hdev->hw, &desc, 1); 7570 if (status) { 7571 dev_err(&hdev->pdev->dev, 7572 "Send rxvlan protocol type command fail, ret =%d\n", 7573 status); 7574 return status; 7575 } 7576 7577 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 7578 7579 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 7580 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 7581 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 7582 7583 status = hclge_cmd_send(&hdev->hw, &desc, 1); 7584 if (status) 7585 dev_err(&hdev->pdev->dev, 7586 "Send txvlan protocol type command fail, ret =%d\n", 7587 status); 7588 7589 return status; 7590 } 7591 7592 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 7593 { 7594 struct hclge_vport *vport; 7595 bool enable = true; 7596 int ret; 7597 int i; 7598 7599 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 7600 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 7601 HCLGE_FILTER_FE_EGRESS_V1_B, 7602 true, 0); 7603 7604 /* for revision 0x21, vf vlan filter is per function */ 7605 for (i = 0; i < hdev->num_alloc_vport; i++) { 7606 vport = &hdev->vport[i]; 7607 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 7608 HCLGE_FILTER_FE_EGRESS, true, 7609 vport->vport_id); 7610 if (ret) 7611 return ret; 7612 vport->cur_vlan_fltr_en = true; 7613 } 7614 7615 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps) && 7616 !test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps)) 7617 enable = false; 7618 7619 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 7620 HCLGE_FILTER_FE_INGRESS, enable, 0); 7621 } 7622 7623 static int hclge_init_vlan_type(struct hclge_dev *hdev) 7624 { 7625 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 7626 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 7627 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 7628 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 7629 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 7630 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 7631 7632 return hclge_set_vlan_protocol_type(hdev); 7633 } 7634 7635 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 7636 { 7637 struct hclge_port_base_vlan_config *cfg; 7638 struct hclge_vport *vport; 7639 int ret; 7640 int i; 7641 7642 for (i = 0; i < hdev->num_alloc_vport; i++) { 7643 vport = &hdev->vport[i]; 7644 cfg = &vport->port_base_vlan_cfg; 7645 7646 ret = hclge_vlan_offload_cfg(vport, cfg->state, 7647 cfg->vlan_info.vlan_tag, 7648 cfg->vlan_info.qos); 7649 if (ret) 7650 return ret; 7651 } 7652 return 0; 7653 } 7654 7655 static int hclge_init_vlan_config(struct hclge_dev *hdev) 7656 { 7657 struct hnae3_handle *handle = &hdev->vport[0].nic; 7658 int ret; 7659 7660 ret = hclge_init_vlan_filter(hdev); 7661 if (ret) 7662 return ret; 7663 7664 ret = hclge_init_vlan_type(hdev); 7665 if (ret) 7666 return ret; 7667 7668 ret = hclge_init_vport_vlan_offload(hdev); 7669 if (ret) 7670 return ret; 7671 7672 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 7673 } 7674 7675 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 7676 bool writen_to_tbl) 7677 { 7678 struct hclge_vport_vlan_cfg *vlan, *tmp; 7679 struct hclge_dev *hdev = vport->back; 7680 7681 mutex_lock(&hdev->vport_lock); 7682 7683 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7684 if (vlan->vlan_id == vlan_id) { 7685 mutex_unlock(&hdev->vport_lock); 7686 return; 7687 } 7688 } 7689 7690 vlan = kzalloc_obj(*vlan); 7691 if (!vlan) { 7692 mutex_unlock(&hdev->vport_lock); 7693 return; 7694 } 7695 7696 vlan->hd_tbl_status = writen_to_tbl; 7697 vlan->vlan_id = vlan_id; 7698 7699 list_add_tail(&vlan->node, &vport->vlan_list); 7700 mutex_unlock(&hdev->vport_lock); 7701 } 7702 7703 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 7704 { 7705 struct hclge_vport_vlan_cfg *vlan, *tmp; 7706 struct hclge_dev *hdev = vport->back; 7707 int ret; 7708 7709 mutex_lock(&hdev->vport_lock); 7710 7711 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7712 if (!vlan->hd_tbl_status) { 7713 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 7714 vport->vport_id, 7715 vlan->vlan_id, false); 7716 if (ret) { 7717 dev_err(&hdev->pdev->dev, 7718 "restore vport vlan list failed, ret=%d\n", 7719 ret); 7720 7721 mutex_unlock(&hdev->vport_lock); 7722 return ret; 7723 } 7724 } 7725 vlan->hd_tbl_status = true; 7726 } 7727 7728 mutex_unlock(&hdev->vport_lock); 7729 7730 return 0; 7731 } 7732 7733 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 7734 bool is_write_tbl) 7735 { 7736 struct hclge_vport_vlan_cfg *vlan, *tmp; 7737 struct hclge_dev *hdev = vport->back; 7738 7739 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7740 if (vlan->vlan_id == vlan_id) { 7741 if (is_write_tbl && vlan->hd_tbl_status) 7742 hclge_set_vlan_filter_hw(hdev, 7743 htons(ETH_P_8021Q), 7744 vport->vport_id, 7745 vlan_id, 7746 true); 7747 7748 list_del(&vlan->node); 7749 kfree(vlan); 7750 break; 7751 } 7752 } 7753 } 7754 7755 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 7756 { 7757 struct hclge_vport_vlan_cfg *vlan, *tmp; 7758 struct hclge_dev *hdev = vport->back; 7759 7760 mutex_lock(&hdev->vport_lock); 7761 7762 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7763 if (vlan->hd_tbl_status) 7764 hclge_set_vlan_filter_hw(hdev, 7765 htons(ETH_P_8021Q), 7766 vport->vport_id, 7767 vlan->vlan_id, 7768 true); 7769 7770 vlan->hd_tbl_status = false; 7771 if (is_del_list) { 7772 list_del(&vlan->node); 7773 kfree(vlan); 7774 } 7775 } 7776 clear_bit(vport->vport_id, hdev->vf_vlan_full); 7777 mutex_unlock(&hdev->vport_lock); 7778 } 7779 7780 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 7781 { 7782 struct hclge_vport_vlan_cfg *vlan, *tmp; 7783 struct hclge_vport *vport; 7784 int i; 7785 7786 mutex_lock(&hdev->vport_lock); 7787 7788 for (i = 0; i < hdev->num_alloc_vport; i++) { 7789 vport = &hdev->vport[i]; 7790 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7791 list_del(&vlan->node); 7792 kfree(vlan); 7793 } 7794 } 7795 7796 mutex_unlock(&hdev->vport_lock); 7797 } 7798 7799 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 7800 { 7801 struct hclge_vlan_info *vlan_info; 7802 struct hclge_vport *vport; 7803 u16 vlan_proto; 7804 u16 vlan_id; 7805 u16 state; 7806 int vf_id; 7807 int ret; 7808 7809 /* PF should restore all vfs port base vlan */ 7810 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 7811 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 7812 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 7813 &vport->port_base_vlan_cfg.vlan_info : 7814 &vport->port_base_vlan_cfg.old_vlan_info; 7815 7816 vlan_id = vlan_info->vlan_tag; 7817 vlan_proto = vlan_info->vlan_proto; 7818 state = vport->port_base_vlan_cfg.state; 7819 7820 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 7821 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 7822 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 7823 vport->vport_id, 7824 vlan_id, false); 7825 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 7826 } 7827 } 7828 } 7829 7830 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 7831 { 7832 struct hclge_vport_vlan_cfg *vlan, *tmp; 7833 struct hclge_dev *hdev = vport->back; 7834 int ret; 7835 7836 mutex_lock(&hdev->vport_lock); 7837 7838 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 7839 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7840 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 7841 vport->vport_id, 7842 vlan->vlan_id, false); 7843 if (ret) 7844 break; 7845 vlan->hd_tbl_status = true; 7846 } 7847 } 7848 7849 mutex_unlock(&hdev->vport_lock); 7850 } 7851 7852 /* For global reset and imp reset, hardware will clear the mac table, 7853 * so we change the mac address state from ACTIVE to TO_ADD, then they 7854 * can be restored in the service task after reset complete. Furtherly, 7855 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 7856 * be restored after reset, so just remove these mac nodes from mac_list. 7857 */ 7858 static void hclge_mac_node_convert_for_reset(struct list_head *list) 7859 { 7860 struct hclge_mac_node *mac_node, *tmp; 7861 7862 list_for_each_entry_safe(mac_node, tmp, list, node) { 7863 if (mac_node->state == HCLGE_MAC_ACTIVE) { 7864 mac_node->state = HCLGE_MAC_TO_ADD; 7865 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 7866 list_del(&mac_node->node); 7867 kfree(mac_node); 7868 } 7869 } 7870 } 7871 7872 void hclge_restore_mac_table_common(struct hclge_vport *vport) 7873 { 7874 spin_lock_bh(&vport->mac_list_lock); 7875 7876 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 7877 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 7878 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 7879 7880 spin_unlock_bh(&vport->mac_list_lock); 7881 } 7882 7883 static void hclge_restore_hw_table(struct hclge_dev *hdev) 7884 { 7885 struct hclge_vport *vport = &hdev->vport[0]; 7886 struct hnae3_handle *handle = &vport->nic; 7887 7888 hclge_restore_mac_table_common(vport); 7889 hclge_restore_vport_port_base_vlan_config(hdev); 7890 hclge_restore_vport_vlan_table(vport); 7891 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 7892 hclge_restore_fd_entries(handle); 7893 } 7894 7895 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 7896 { 7897 struct hclge_vport *vport = hclge_get_vport(handle); 7898 7899 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 7900 vport->rxvlan_cfg.strip_tag1_en = false; 7901 vport->rxvlan_cfg.strip_tag2_en = enable; 7902 vport->rxvlan_cfg.strip_tag2_discard_en = false; 7903 } else { 7904 vport->rxvlan_cfg.strip_tag1_en = enable; 7905 vport->rxvlan_cfg.strip_tag2_en = true; 7906 vport->rxvlan_cfg.strip_tag2_discard_en = true; 7907 } 7908 7909 vport->rxvlan_cfg.strip_tag1_discard_en = false; 7910 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 7911 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 7912 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 7913 7914 return hclge_set_vlan_rx_offload_cfg(vport); 7915 } 7916 7917 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 7918 { 7919 struct hclge_dev *hdev = vport->back; 7920 7921 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 7922 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 7923 } 7924 7925 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 7926 u16 port_base_vlan_state, 7927 struct hclge_vlan_info *new_info, 7928 struct hclge_vlan_info *old_info) 7929 { 7930 struct hclge_dev *hdev = vport->back; 7931 int ret; 7932 7933 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 7934 hclge_rm_vport_all_vlan_table(vport, false); 7935 /* force clear VLAN 0 */ 7936 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 7937 if (ret) 7938 return ret; 7939 return hclge_set_vlan_filter_hw(hdev, 7940 htons(new_info->vlan_proto), 7941 vport->vport_id, 7942 new_info->vlan_tag, 7943 false); 7944 } 7945 7946 vport->port_base_vlan_cfg.tbl_sta = false; 7947 7948 /* force add VLAN 0 */ 7949 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 7950 if (ret) 7951 return ret; 7952 7953 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 7954 vport->vport_id, old_info->vlan_tag, 7955 true); 7956 if (ret) 7957 return ret; 7958 7959 return hclge_add_vport_all_vlan_table(vport); 7960 } 7961 7962 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 7963 const struct hclge_vlan_info *old_cfg) 7964 { 7965 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 7966 return true; 7967 7968 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 7969 return true; 7970 7971 return false; 7972 } 7973 7974 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 7975 struct hclge_vlan_info *new_info, 7976 struct hclge_vlan_info *old_info) 7977 { 7978 struct hclge_dev *hdev = vport->back; 7979 int ret; 7980 7981 /* add new VLAN tag */ 7982 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 7983 vport->vport_id, new_info->vlan_tag, 7984 false); 7985 if (ret) 7986 return ret; 7987 7988 vport->port_base_vlan_cfg.tbl_sta = false; 7989 /* remove old VLAN tag */ 7990 if (old_info->vlan_tag == 0) 7991 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 7992 true, 0); 7993 else 7994 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 7995 vport->vport_id, 7996 old_info->vlan_tag, true); 7997 if (ret) 7998 dev_err(&hdev->pdev->dev, 7999 "failed to clear vport%u port base vlan %u, ret = %d.\n", 8000 vport->vport_id, old_info->vlan_tag, ret); 8001 8002 return ret; 8003 } 8004 8005 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 8006 struct hclge_vlan_info *vlan_info) 8007 { 8008 struct hnae3_handle *nic = &vport->nic; 8009 struct hclge_vlan_info *old_vlan_info; 8010 int ret; 8011 8012 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 8013 8014 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 8015 vlan_info->qos); 8016 if (ret) 8017 return ret; 8018 8019 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 8020 goto out; 8021 8022 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 8023 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 8024 old_vlan_info); 8025 else 8026 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 8027 old_vlan_info); 8028 if (ret) 8029 return ret; 8030 8031 out: 8032 vport->port_base_vlan_cfg.state = state; 8033 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 8034 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 8035 else 8036 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 8037 8038 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 8039 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 8040 vport->port_base_vlan_cfg.tbl_sta = true; 8041 hclge_set_vport_vlan_fltr_change(vport); 8042 8043 return 0; 8044 } 8045 8046 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 8047 enum hnae3_port_base_vlan_state state, 8048 u16 vlan, u8 qos) 8049 { 8050 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 8051 if (!vlan && !qos) 8052 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 8053 8054 return HNAE3_PORT_BASE_VLAN_ENABLE; 8055 } 8056 8057 if (!vlan && !qos) 8058 return HNAE3_PORT_BASE_VLAN_DISABLE; 8059 8060 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 8061 vport->port_base_vlan_cfg.vlan_info.qos == qos) 8062 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 8063 8064 return HNAE3_PORT_BASE_VLAN_MODIFY; 8065 } 8066 8067 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 8068 u16 vlan, u8 qos, __be16 proto) 8069 { 8070 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 8071 struct hclge_vport *vport = hclge_get_vport(handle); 8072 struct hclge_dev *hdev = vport->back; 8073 struct hclge_vlan_info vlan_info; 8074 u16 state; 8075 int ret; 8076 8077 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 8078 return -EOPNOTSUPP; 8079 8080 vport = hclge_get_vf_vport(hdev, vfid); 8081 if (!vport) 8082 return -EINVAL; 8083 8084 /* qos is a 3 bits value, so can not be bigger than 7 */ 8085 if (vlan > VLAN_N_VID - 1 || qos > 7) 8086 return -EINVAL; 8087 if (proto != htons(ETH_P_8021Q)) 8088 return -EPROTONOSUPPORT; 8089 8090 state = hclge_get_port_base_vlan_state(vport, 8091 vport->port_base_vlan_cfg.state, 8092 vlan, qos); 8093 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 8094 return 0; 8095 8096 vlan_info.vlan_tag = vlan; 8097 vlan_info.qos = qos; 8098 vlan_info.vlan_proto = ntohs(proto); 8099 8100 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 8101 if (ret) { 8102 dev_err(&hdev->pdev->dev, 8103 "failed to update port base vlan for vf %d, ret = %d\n", 8104 vfid, ret); 8105 return ret; 8106 } 8107 8108 /* there is a timewindow for PF to know VF unalive, it may 8109 * cause send mailbox fail, but it doesn't matter, VF will 8110 * query it when reinit. 8111 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 8112 * VLAN state. 8113 */ 8114 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 8115 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 8116 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 8117 vport->vport_id, 8118 state, 8119 &vlan_info); 8120 else 8121 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 8122 &vport->need_notify); 8123 } 8124 return 0; 8125 } 8126 8127 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 8128 { 8129 struct hclge_vlan_info *vlan_info; 8130 struct hclge_vport *vport; 8131 int ret; 8132 int vf; 8133 8134 /* clear port base vlan for all vf */ 8135 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 8136 vport = &hdev->vport[vf]; 8137 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 8138 8139 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 8140 vport->vport_id, 8141 vlan_info->vlan_tag, true); 8142 if (ret) 8143 dev_err(&hdev->pdev->dev, 8144 "failed to clear vf vlan for vf%d, ret = %d\n", 8145 vf - HCLGE_VF_VPORT_START_NUM, ret); 8146 } 8147 } 8148 8149 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 8150 u16 vlan_id, bool is_kill) 8151 { 8152 struct hclge_vport *vport = hclge_get_vport(handle); 8153 struct hclge_dev *hdev = vport->back; 8154 bool writen_to_tbl = false; 8155 int ret = 0; 8156 8157 if (vlan_id >= VLAN_N_VID) 8158 return -EINVAL; 8159 8160 /* When device is resetting or reset failed, firmware is unable to 8161 * handle mailbox. Just record the vlan id, and remove it after 8162 * reset finished. 8163 */ 8164 mutex_lock(&hdev->vport_lock); 8165 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 8166 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 8167 set_bit(vlan_id, vport->vlan_del_fail_bmap); 8168 mutex_unlock(&hdev->vport_lock); 8169 return -EBUSY; 8170 } else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) { 8171 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 8172 } 8173 mutex_unlock(&hdev->vport_lock); 8174 8175 /* when port base vlan enabled, we use port base vlan as the vlan 8176 * filter entry. In this case, we don't update vlan filter table 8177 * when user add new vlan or remove exist vlan, just update the vport 8178 * vlan list. The vlan id in vlan list will be writen in vlan filter 8179 * table until port base vlan disabled 8180 */ 8181 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 8182 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 8183 vlan_id, is_kill); 8184 writen_to_tbl = true; 8185 } 8186 8187 if (!ret) { 8188 if (!is_kill) { 8189 hclge_add_vport_vlan_table(vport, vlan_id, 8190 writen_to_tbl); 8191 } else if (is_kill && vlan_id != 0) { 8192 mutex_lock(&hdev->vport_lock); 8193 hclge_rm_vport_vlan_table(vport, vlan_id, false); 8194 mutex_unlock(&hdev->vport_lock); 8195 } 8196 } else if (is_kill) { 8197 /* when remove hw vlan filter failed, record the vlan id, 8198 * and try to remove it from hw later, to be consistence 8199 * with stack 8200 */ 8201 mutex_lock(&hdev->vport_lock); 8202 set_bit(vlan_id, vport->vlan_del_fail_bmap); 8203 mutex_unlock(&hdev->vport_lock); 8204 } 8205 8206 hclge_set_vport_vlan_fltr_change(vport); 8207 8208 return ret; 8209 } 8210 8211 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 8212 { 8213 struct hclge_vport *vport; 8214 int ret; 8215 u16 i; 8216 8217 for (i = 0; i < hdev->num_alloc_vport; i++) { 8218 vport = &hdev->vport[i]; 8219 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 8220 &vport->state)) 8221 continue; 8222 8223 mutex_lock(&hdev->vport_lock); 8224 ret = __hclge_enable_vport_vlan_filter(vport, 8225 vport->req_vlan_fltr_en); 8226 if (ret) { 8227 dev_err(&hdev->pdev->dev, 8228 "failed to sync vlan filter state for vport%u, ret = %d\n", 8229 vport->vport_id, ret); 8230 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 8231 &vport->state); 8232 mutex_unlock(&hdev->vport_lock); 8233 return; 8234 } 8235 mutex_unlock(&hdev->vport_lock); 8236 } 8237 } 8238 8239 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 8240 { 8241 #define HCLGE_MAX_SYNC_COUNT 60 8242 8243 int i, ret, sync_cnt = 0; 8244 u16 vlan_id; 8245 8246 mutex_lock(&hdev->vport_lock); 8247 /* start from vport 1 for PF is always alive */ 8248 for (i = 0; i < hdev->num_alloc_vport; i++) { 8249 struct hclge_vport *vport = &hdev->vport[i]; 8250 8251 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 8252 VLAN_N_VID); 8253 while (vlan_id != VLAN_N_VID) { 8254 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 8255 vport->vport_id, vlan_id, 8256 true); 8257 if (ret && ret != -EINVAL) { 8258 mutex_unlock(&hdev->vport_lock); 8259 return; 8260 } 8261 8262 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 8263 hclge_rm_vport_vlan_table(vport, vlan_id, false); 8264 hclge_set_vport_vlan_fltr_change(vport); 8265 8266 sync_cnt++; 8267 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) { 8268 mutex_unlock(&hdev->vport_lock); 8269 return; 8270 } 8271 8272 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 8273 VLAN_N_VID); 8274 } 8275 } 8276 mutex_unlock(&hdev->vport_lock); 8277 8278 hclge_sync_vlan_fltr_state(hdev); 8279 } 8280 8281 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 8282 { 8283 struct hclge_config_max_frm_size_cmd *req; 8284 struct hclge_desc desc; 8285 8286 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 8287 8288 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 8289 req->max_frm_size = cpu_to_le16(new_mps); 8290 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 8291 8292 return hclge_cmd_send(&hdev->hw, &desc, 1); 8293 } 8294 8295 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 8296 { 8297 struct hclge_vport *vport = hclge_get_vport(handle); 8298 8299 return hclge_set_vport_mtu(vport, new_mtu); 8300 } 8301 8302 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 8303 { 8304 struct hclge_dev *hdev = vport->back; 8305 int i, max_frm_size, ret; 8306 8307 /* HW supprt 2 layer vlan */ 8308 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 8309 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 8310 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 8311 return -EINVAL; 8312 8313 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 8314 mutex_lock(&hdev->vport_lock); 8315 /* VF's mps must fit within hdev->mps */ 8316 if (vport->vport_id && (u32)max_frm_size > hdev->mps) { 8317 mutex_unlock(&hdev->vport_lock); 8318 return -EINVAL; 8319 } else if (vport->vport_id) { 8320 vport->mps = max_frm_size; 8321 mutex_unlock(&hdev->vport_lock); 8322 return 0; 8323 } 8324 8325 /* PF's mps must be greater then VF's mps */ 8326 for (i = 1; i < hdev->num_alloc_vport; i++) 8327 if ((u32)max_frm_size < hdev->vport[i].mps) { 8328 dev_err(&hdev->pdev->dev, 8329 "failed to set pf mtu for less than vport %d, mps = %u.\n", 8330 i, hdev->vport[i].mps); 8331 mutex_unlock(&hdev->vport_lock); 8332 return -EINVAL; 8333 } 8334 8335 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 8336 8337 ret = hclge_set_mac_mtu(hdev, max_frm_size); 8338 if (ret) { 8339 dev_err(&hdev->pdev->dev, 8340 "Change mtu fail, ret =%d\n", ret); 8341 goto out; 8342 } 8343 8344 hdev->mps = max_frm_size; 8345 vport->mps = max_frm_size; 8346 8347 ret = hclge_buffer_alloc(hdev); 8348 if (ret) 8349 dev_err(&hdev->pdev->dev, 8350 "Allocate buffer fail, ret =%d\n", ret); 8351 8352 out: 8353 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 8354 mutex_unlock(&hdev->vport_lock); 8355 return ret; 8356 } 8357 8358 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 8359 bool enable) 8360 { 8361 struct hclge_reset_tqp_queue_cmd *req; 8362 struct hclge_desc desc; 8363 int ret; 8364 8365 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 8366 8367 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 8368 req->tqp_id = cpu_to_le16(queue_id); 8369 if (enable) 8370 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 8371 8372 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8373 if (ret) { 8374 dev_err(&hdev->pdev->dev, 8375 "Send tqp reset cmd error, status =%d\n", ret); 8376 return ret; 8377 } 8378 8379 return 0; 8380 } 8381 8382 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 8383 u8 *reset_status) 8384 { 8385 struct hclge_reset_tqp_queue_cmd *req; 8386 struct hclge_desc desc; 8387 int ret; 8388 8389 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 8390 8391 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 8392 req->tqp_id = cpu_to_le16(queue_id); 8393 8394 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8395 if (ret) { 8396 dev_err(&hdev->pdev->dev, 8397 "Get reset status error, status =%d\n", ret); 8398 return ret; 8399 } 8400 8401 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 8402 8403 return 0; 8404 } 8405 8406 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 8407 { 8408 struct hclge_comm_tqp *tqp; 8409 struct hnae3_queue *queue; 8410 8411 queue = handle->kinfo.tqp[queue_id]; 8412 tqp = container_of(queue, struct hclge_comm_tqp, q); 8413 8414 return tqp->index; 8415 } 8416 8417 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 8418 { 8419 struct hclge_vport *vport = hclge_get_vport(handle); 8420 struct hclge_dev *hdev = vport->back; 8421 u16 reset_try_times = 0; 8422 u8 reset_status; 8423 u16 queue_gid; 8424 int ret; 8425 u16 i; 8426 8427 for (i = 0; i < handle->kinfo.num_tqps; i++) { 8428 queue_gid = hclge_covert_handle_qid_global(handle, i); 8429 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 8430 if (ret) { 8431 dev_err(&hdev->pdev->dev, 8432 "failed to send reset tqp cmd, ret = %d\n", 8433 ret); 8434 return ret; 8435 } 8436 8437 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 8438 ret = hclge_get_reset_status(hdev, queue_gid, 8439 &reset_status); 8440 if (ret) 8441 return ret; 8442 8443 if (reset_status) 8444 break; 8445 8446 /* Wait for tqp hw reset */ 8447 usleep_range(1000, 1200); 8448 } 8449 8450 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 8451 dev_err(&hdev->pdev->dev, 8452 "wait for tqp hw reset timeout\n"); 8453 return -ETIME; 8454 } 8455 8456 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 8457 if (ret) { 8458 dev_err(&hdev->pdev->dev, 8459 "failed to deassert soft reset, ret = %d\n", 8460 ret); 8461 return ret; 8462 } 8463 reset_try_times = 0; 8464 } 8465 return 0; 8466 } 8467 8468 static int hclge_reset_rcb(struct hnae3_handle *handle) 8469 { 8470 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 8471 #define HCLGE_RESET_RCB_SUCCESS 1U 8472 8473 struct hclge_vport *vport = hclge_get_vport(handle); 8474 struct hclge_dev *hdev = vport->back; 8475 struct hclge_reset_cmd *req; 8476 struct hclge_desc desc; 8477 u8 return_status; 8478 u16 queue_gid; 8479 int ret; 8480 8481 queue_gid = hclge_covert_handle_qid_global(handle, 0); 8482 8483 req = (struct hclge_reset_cmd *)desc.data; 8484 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 8485 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 8486 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 8487 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 8488 8489 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8490 if (ret) { 8491 dev_err(&hdev->pdev->dev, 8492 "failed to send rcb reset cmd, ret = %d\n", ret); 8493 return ret; 8494 } 8495 8496 return_status = req->fun_reset_rcb_return_status; 8497 if (return_status == HCLGE_RESET_RCB_SUCCESS) 8498 return 0; 8499 8500 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 8501 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 8502 return_status); 8503 return -EIO; 8504 } 8505 8506 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 8507 * again to reset all tqps 8508 */ 8509 return hclge_reset_tqp_cmd(handle); 8510 } 8511 8512 int hclge_reset_tqp(struct hnae3_handle *handle) 8513 { 8514 struct hclge_vport *vport = hclge_get_vport(handle); 8515 struct hclge_dev *hdev = vport->back; 8516 int ret; 8517 8518 /* only need to disable PF's tqp */ 8519 if (!vport->vport_id) { 8520 ret = hclge_tqp_enable(handle, false); 8521 if (ret) { 8522 dev_err(&hdev->pdev->dev, 8523 "failed to disable tqp, ret = %d\n", ret); 8524 return ret; 8525 } 8526 } 8527 8528 return hclge_reset_rcb(handle); 8529 } 8530 8531 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 8532 { 8533 struct hclge_vport *vport = hclge_get_vport(handle); 8534 struct hclge_dev *hdev = vport->back; 8535 8536 return hdev->fw_version; 8537 } 8538 8539 int hclge_query_scc_version(struct hclge_dev *hdev, u32 *scc_version) 8540 { 8541 struct hclge_comm_query_scc_cmd *resp; 8542 struct hclge_desc desc; 8543 int ret; 8544 8545 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_SCC_VER, 1); 8546 resp = (struct hclge_comm_query_scc_cmd *)desc.data; 8547 8548 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8549 if (ret) 8550 return ret; 8551 8552 *scc_version = le32_to_cpu(resp->scc_version); 8553 8554 return 0; 8555 } 8556 8557 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 8558 { 8559 struct phy_device *phydev = hdev->hw.mac.phydev; 8560 8561 if (!phydev) 8562 return; 8563 8564 phy_set_asym_pause(phydev, rx_en, tx_en); 8565 } 8566 8567 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 8568 { 8569 int ret; 8570 8571 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 8572 return 0; 8573 8574 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 8575 if (ret) 8576 dev_err(&hdev->pdev->dev, 8577 "configure pauseparam error, ret = %d.\n", ret); 8578 8579 return ret; 8580 } 8581 8582 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 8583 { 8584 struct phy_device *phydev = hdev->hw.mac.phydev; 8585 u16 remote_advertising = 0; 8586 u16 local_advertising; 8587 u32 rx_pause, tx_pause; 8588 u8 flowctl; 8589 8590 if (!phydev->link) 8591 return 0; 8592 8593 if (!phydev->autoneg) 8594 return hclge_mac_pause_setup_hw(hdev); 8595 8596 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 8597 8598 if (phydev->pause) 8599 remote_advertising = LPA_PAUSE_CAP; 8600 8601 if (phydev->asym_pause) 8602 remote_advertising |= LPA_PAUSE_ASYM; 8603 8604 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 8605 remote_advertising); 8606 tx_pause = flowctl & FLOW_CTRL_TX; 8607 rx_pause = flowctl & FLOW_CTRL_RX; 8608 8609 if (phydev->duplex == HCLGE_MAC_HALF) { 8610 tx_pause = 0; 8611 rx_pause = 0; 8612 } 8613 8614 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 8615 } 8616 8617 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 8618 u32 *rx_en, u32 *tx_en) 8619 { 8620 struct hclge_vport *vport = hclge_get_vport(handle); 8621 struct hclge_dev *hdev = vport->back; 8622 u8 media_type = hdev->hw.mac.media_type; 8623 8624 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 8625 hclge_get_autoneg(handle) : 0; 8626 8627 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 8628 *rx_en = 0; 8629 *tx_en = 0; 8630 return; 8631 } 8632 8633 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 8634 *rx_en = 1; 8635 *tx_en = 0; 8636 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 8637 *tx_en = 1; 8638 *rx_en = 0; 8639 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 8640 *rx_en = 1; 8641 *tx_en = 1; 8642 } else { 8643 *rx_en = 0; 8644 *tx_en = 0; 8645 } 8646 } 8647 8648 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 8649 u32 rx_en, u32 tx_en) 8650 { 8651 if (rx_en && tx_en) 8652 hdev->fc_mode_last_time = HCLGE_FC_FULL; 8653 else if (rx_en && !tx_en) 8654 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 8655 else if (!rx_en && tx_en) 8656 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 8657 else 8658 hdev->fc_mode_last_time = HCLGE_FC_NONE; 8659 8660 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 8661 } 8662 8663 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 8664 u32 rx_en, u32 tx_en) 8665 { 8666 struct hclge_vport *vport = hclge_get_vport(handle); 8667 struct hclge_dev *hdev = vport->back; 8668 struct phy_device *phydev = hdev->hw.mac.phydev; 8669 u32 fc_autoneg; 8670 8671 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 8672 fc_autoneg = hclge_get_autoneg(handle); 8673 if (auto_neg != fc_autoneg) { 8674 dev_info(&hdev->pdev->dev, 8675 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 8676 return -EOPNOTSUPP; 8677 } 8678 } 8679 8680 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 8681 dev_info(&hdev->pdev->dev, 8682 "Priority flow control enabled. Cannot set link flow control.\n"); 8683 return -EOPNOTSUPP; 8684 } 8685 8686 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 8687 8688 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 8689 8690 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 8691 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 8692 8693 if (phydev) 8694 return phy_start_aneg(phydev); 8695 8696 return -EOPNOTSUPP; 8697 } 8698 8699 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 8700 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 8701 { 8702 struct hclge_vport *vport = hclge_get_vport(handle); 8703 struct hclge_dev *hdev = vport->back; 8704 8705 if (speed) 8706 *speed = hdev->hw.mac.speed; 8707 if (duplex) 8708 *duplex = hdev->hw.mac.duplex; 8709 if (auto_neg) 8710 *auto_neg = hdev->hw.mac.autoneg; 8711 if (lane_num) 8712 *lane_num = hdev->hw.mac.lane_num; 8713 } 8714 8715 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 8716 u8 *module_type) 8717 { 8718 struct hclge_vport *vport = hclge_get_vport(handle); 8719 struct hclge_dev *hdev = vport->back; 8720 8721 /* When nic is down, the service task is not running, doesn't update 8722 * the port information per second. Query the port information before 8723 * return the media type, ensure getting the correct media information. 8724 */ 8725 hclge_update_port_info(hdev); 8726 8727 if (media_type) 8728 *media_type = hdev->hw.mac.media_type; 8729 8730 if (module_type) 8731 *module_type = hdev->hw.mac.module_type; 8732 } 8733 8734 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 8735 u8 *tp_mdix_ctrl, u8 *tp_mdix) 8736 { 8737 struct hclge_vport *vport = hclge_get_vport(handle); 8738 struct hclge_dev *hdev = vport->back; 8739 struct phy_device *phydev = hdev->hw.mac.phydev; 8740 int mdix_ctrl, mdix, is_resolved; 8741 unsigned int retval; 8742 8743 if (!phydev) { 8744 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 8745 *tp_mdix = ETH_TP_MDI_INVALID; 8746 return; 8747 } 8748 8749 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 8750 8751 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 8752 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 8753 HCLGE_PHY_MDIX_CTRL_S); 8754 8755 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 8756 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 8757 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 8758 8759 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 8760 8761 switch (mdix_ctrl) { 8762 case 0x0: 8763 *tp_mdix_ctrl = ETH_TP_MDI; 8764 break; 8765 case 0x1: 8766 *tp_mdix_ctrl = ETH_TP_MDI_X; 8767 break; 8768 case 0x3: 8769 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 8770 break; 8771 default: 8772 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 8773 break; 8774 } 8775 8776 if (!is_resolved) 8777 *tp_mdix = ETH_TP_MDI_INVALID; 8778 else if (mdix) 8779 *tp_mdix = ETH_TP_MDI_X; 8780 else 8781 *tp_mdix = ETH_TP_MDI; 8782 } 8783 8784 static void hclge_info_show(struct hclge_dev *hdev) 8785 { 8786 struct hnae3_handle *handle = &hdev->vport->nic; 8787 struct device *dev = &hdev->pdev->dev; 8788 8789 dev_info(dev, "PF info begin:\n"); 8790 8791 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 8792 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 8793 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 8794 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 8795 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 8796 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 8797 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 8798 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 8799 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 8800 dev_info(dev, "This is %s PF\n", 8801 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 8802 dev_info(dev, "DCB %s\n", 8803 str_enable_disable(handle->kinfo.tc_info.dcb_ets_active)); 8804 dev_info(dev, "MQPRIO %s\n", 8805 str_enable_disable(handle->kinfo.tc_info.mqprio_active)); 8806 dev_info(dev, "Default tx spare buffer size: %u\n", 8807 hdev->tx_spare_buf_size); 8808 8809 dev_info(dev, "PF info end.\n"); 8810 } 8811 8812 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 8813 struct hclge_vport *vport) 8814 { 8815 struct hnae3_client *client = vport->nic.client; 8816 struct hclge_dev *hdev = ae_dev->priv; 8817 u32 rst_cnt = hdev->rst_stats.reset_cnt; 8818 int ret; 8819 8820 ret = client->ops->init_instance(&vport->nic); 8821 if (ret) 8822 return ret; 8823 8824 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 8825 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 8826 rst_cnt != hdev->rst_stats.reset_cnt) { 8827 ret = -EBUSY; 8828 goto init_nic_err; 8829 } 8830 8831 /* Enable nic hw error interrupts */ 8832 ret = hclge_config_nic_hw_error(hdev, true); 8833 if (ret) { 8834 dev_err(&ae_dev->pdev->dev, 8835 "fail(%d) to enable hw error interrupts\n", ret); 8836 goto init_nic_err; 8837 } 8838 8839 hnae3_set_client_init_flag(client, ae_dev, 1); 8840 8841 if (netif_msg_drv(&hdev->vport->nic)) 8842 hclge_info_show(hdev); 8843 8844 return ret; 8845 8846 init_nic_err: 8847 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 8848 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 8849 msleep(HCLGE_WAIT_RESET_DONE); 8850 8851 client->ops->uninit_instance(&vport->nic, 0); 8852 8853 return ret; 8854 } 8855 8856 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 8857 struct hclge_vport *vport) 8858 { 8859 struct hclge_dev *hdev = ae_dev->priv; 8860 struct hnae3_client *client; 8861 u32 rst_cnt; 8862 int ret; 8863 8864 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 8865 !hdev->nic_client) 8866 return 0; 8867 8868 client = hdev->roce_client; 8869 ret = hclge_init_roce_base_info(vport); 8870 if (ret) 8871 return ret; 8872 8873 rst_cnt = hdev->rst_stats.reset_cnt; 8874 ret = client->ops->init_instance(&vport->roce); 8875 if (ret) 8876 return ret; 8877 8878 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 8879 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 8880 rst_cnt != hdev->rst_stats.reset_cnt) { 8881 ret = -EBUSY; 8882 goto init_roce_err; 8883 } 8884 8885 /* Enable roce ras interrupts */ 8886 ret = hclge_config_rocee_ras_interrupt(hdev, true); 8887 if (ret) { 8888 dev_err(&ae_dev->pdev->dev, 8889 "fail(%d) to enable roce ras interrupts\n", ret); 8890 goto init_roce_err; 8891 } 8892 8893 hnae3_set_client_init_flag(client, ae_dev, 1); 8894 8895 return 0; 8896 8897 init_roce_err: 8898 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 8899 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 8900 msleep(HCLGE_WAIT_RESET_DONE); 8901 8902 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 8903 8904 return ret; 8905 } 8906 8907 static int hclge_init_client_instance(struct hnae3_client *client, 8908 struct hnae3_ae_dev *ae_dev) 8909 { 8910 struct hclge_dev *hdev = ae_dev->priv; 8911 struct hclge_vport *vport = &hdev->vport[0]; 8912 int ret; 8913 8914 switch (client->type) { 8915 case HNAE3_CLIENT_KNIC: 8916 hdev->nic_client = client; 8917 vport->nic.client = client; 8918 ret = hclge_init_nic_client_instance(ae_dev, vport); 8919 if (ret) 8920 goto clear_nic; 8921 8922 ret = hclge_init_roce_client_instance(ae_dev, vport); 8923 if (ret) 8924 goto clear_roce; 8925 8926 break; 8927 case HNAE3_CLIENT_ROCE: 8928 if (hnae3_dev_roce_supported(hdev)) { 8929 hdev->roce_client = client; 8930 vport->roce.client = client; 8931 } 8932 8933 ret = hclge_init_roce_client_instance(ae_dev, vport); 8934 if (ret) 8935 goto clear_roce; 8936 8937 break; 8938 default: 8939 return -EINVAL; 8940 } 8941 8942 return 0; 8943 8944 clear_nic: 8945 hdev->nic_client = NULL; 8946 vport->nic.client = NULL; 8947 return ret; 8948 clear_roce: 8949 hdev->roce_client = NULL; 8950 vport->roce.client = NULL; 8951 return ret; 8952 } 8953 8954 static bool hclge_uninit_need_wait(struct hclge_dev *hdev) 8955 { 8956 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 8957 test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 8958 } 8959 8960 static void hclge_uninit_client_instance(struct hnae3_client *client, 8961 struct hnae3_ae_dev *ae_dev) 8962 { 8963 struct hclge_dev *hdev = ae_dev->priv; 8964 struct hclge_vport *vport = &hdev->vport[0]; 8965 8966 if (hdev->roce_client) { 8967 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 8968 while (hclge_uninit_need_wait(hdev)) 8969 msleep(HCLGE_WAIT_RESET_DONE); 8970 8971 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 8972 hdev->roce_client = NULL; 8973 vport->roce.client = NULL; 8974 } 8975 if (client->type == HNAE3_CLIENT_ROCE) 8976 return; 8977 if (hdev->nic_client && client->ops->uninit_instance) { 8978 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 8979 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 8980 msleep(HCLGE_WAIT_RESET_DONE); 8981 8982 client->ops->uninit_instance(&vport->nic, 0); 8983 hdev->nic_client = NULL; 8984 vport->nic.client = NULL; 8985 } 8986 } 8987 8988 static int hclge_dev_mem_map(struct hclge_dev *hdev) 8989 { 8990 struct pci_dev *pdev = hdev->pdev; 8991 struct hclge_hw *hw = &hdev->hw; 8992 8993 /* for device does not have device memory, return directly */ 8994 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 8995 return 0; 8996 8997 hw->hw.mem_base = 8998 devm_ioremap_wc(&pdev->dev, 8999 pci_resource_start(pdev, HCLGE_MEM_BAR), 9000 pci_resource_len(pdev, HCLGE_MEM_BAR)); 9001 if (!hw->hw.mem_base) { 9002 dev_err(&pdev->dev, "failed to map device memory\n"); 9003 return -EFAULT; 9004 } 9005 9006 return 0; 9007 } 9008 9009 static int hclge_pci_init(struct hclge_dev *hdev) 9010 { 9011 struct pci_dev *pdev = hdev->pdev; 9012 struct hclge_hw *hw; 9013 int ret; 9014 9015 ret = pci_enable_device(pdev); 9016 if (ret) { 9017 dev_err(&pdev->dev, "failed to enable PCI device\n"); 9018 return ret; 9019 } 9020 9021 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 9022 if (ret) { 9023 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 9024 if (ret) { 9025 dev_err(&pdev->dev, 9026 "can't set consistent PCI DMA\n"); 9027 goto err_disable_device; 9028 } 9029 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 9030 } 9031 9032 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 9033 if (ret) { 9034 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 9035 goto err_disable_device; 9036 } 9037 9038 pci_set_master(pdev); 9039 hw = &hdev->hw; 9040 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 9041 if (!hw->hw.io_base) { 9042 dev_err(&pdev->dev, "Can't map configuration register space\n"); 9043 ret = -ENOMEM; 9044 goto err_release_regions; 9045 } 9046 9047 ret = hclge_dev_mem_map(hdev); 9048 if (ret) 9049 goto err_unmap_io_base; 9050 9051 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 9052 9053 return 0; 9054 9055 err_unmap_io_base: 9056 pcim_iounmap(pdev, hdev->hw.hw.io_base); 9057 err_release_regions: 9058 pci_release_regions(pdev); 9059 err_disable_device: 9060 pci_disable_device(pdev); 9061 9062 return ret; 9063 } 9064 9065 static void hclge_pci_uninit(struct hclge_dev *hdev) 9066 { 9067 struct pci_dev *pdev = hdev->pdev; 9068 9069 if (hdev->hw.hw.mem_base) 9070 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 9071 9072 pcim_iounmap(pdev, hdev->hw.hw.io_base); 9073 pci_free_irq_vectors(pdev); 9074 pci_release_regions(pdev); 9075 pci_disable_device(pdev); 9076 } 9077 9078 static void hclge_state_init(struct hclge_dev *hdev) 9079 { 9080 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 9081 set_bit(HCLGE_STATE_DOWN, &hdev->state); 9082 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 9083 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 9084 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 9085 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 9086 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 9087 } 9088 9089 static void hclge_state_uninit(struct hclge_dev *hdev) 9090 { 9091 set_bit(HCLGE_STATE_DOWN, &hdev->state); 9092 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 9093 9094 if (hdev->reset_timer.function) 9095 timer_delete_sync(&hdev->reset_timer); 9096 if (hdev->service_task.work.func) 9097 cancel_delayed_work_sync(&hdev->service_task); 9098 } 9099 9100 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 9101 enum hnae3_reset_type rst_type) 9102 { 9103 #define HCLGE_RESET_RETRY_WAIT_MS 500 9104 #define HCLGE_RESET_RETRY_CNT 5 9105 9106 struct hclge_dev *hdev = ae_dev->priv; 9107 int retry_cnt = 0; 9108 int ret; 9109 9110 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 9111 down(&hdev->reset_sem); 9112 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 9113 hdev->reset_type = rst_type; 9114 ret = hclge_reset_prepare(hdev); 9115 if (!ret && !hdev->reset_pending) 9116 break; 9117 9118 dev_err(&hdev->pdev->dev, 9119 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 9120 ret, hdev->reset_pending, retry_cnt); 9121 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 9122 up(&hdev->reset_sem); 9123 msleep(HCLGE_RESET_RETRY_WAIT_MS); 9124 } 9125 9126 /* disable misc vector before reset done */ 9127 hclge_enable_vector(&hdev->misc_vector, false); 9128 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 9129 9130 if (hdev->reset_type == HNAE3_FLR_RESET) 9131 hdev->rst_stats.flr_rst_cnt++; 9132 } 9133 9134 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 9135 { 9136 struct hclge_dev *hdev = ae_dev->priv; 9137 int ret; 9138 9139 hclge_enable_vector(&hdev->misc_vector, true); 9140 9141 ret = hclge_reset_rebuild(hdev); 9142 if (ret) 9143 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 9144 9145 hdev->reset_type = HNAE3_NONE_RESET; 9146 if (test_and_clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 9147 up(&hdev->reset_sem); 9148 } 9149 9150 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 9151 { 9152 u16 i; 9153 9154 for (i = 0; i < hdev->num_alloc_vport; i++) { 9155 struct hclge_vport *vport = &hdev->vport[i]; 9156 int ret; 9157 9158 /* Send cmd to clear vport's FUNC_RST_ING */ 9159 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 9160 if (ret) 9161 dev_warn(&hdev->pdev->dev, 9162 "clear vport(%u) rst failed %d!\n", 9163 vport->vport_id, ret); 9164 } 9165 } 9166 9167 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 9168 { 9169 struct hclge_desc desc; 9170 int ret; 9171 9172 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 9173 9174 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9175 /* This new command is only supported by new firmware, it will 9176 * fail with older firmware. Error value -EOPNOSUPP can only be 9177 * returned by older firmware running this command, to keep code 9178 * backward compatible we will override this value and return 9179 * success. 9180 */ 9181 if (ret && ret != -EOPNOTSUPP) { 9182 dev_err(&hdev->pdev->dev, 9183 "failed to clear hw resource, ret = %d\n", ret); 9184 return ret; 9185 } 9186 return 0; 9187 } 9188 9189 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 9190 { 9191 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 9192 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 9193 } 9194 9195 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 9196 { 9197 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 9198 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 9199 } 9200 9201 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 9202 { 9203 struct hclge_vport *vport = hclge_get_vport(handle); 9204 9205 return &vport->back->hw.mac.wol; 9206 } 9207 9208 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 9209 u32 *wol_supported) 9210 { 9211 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 9212 struct hclge_desc desc; 9213 int ret; 9214 9215 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 9216 true); 9217 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 9218 9219 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9220 if (ret) { 9221 dev_err(&hdev->pdev->dev, 9222 "failed to query wol supported, ret = %d\n", ret); 9223 return ret; 9224 } 9225 9226 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 9227 9228 return 0; 9229 } 9230 9231 static int hclge_set_wol_cfg(struct hclge_dev *hdev, 9232 struct hclge_wol_info *wol_info) 9233 { 9234 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 9235 struct hclge_desc desc; 9236 int ret; 9237 9238 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 9239 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 9240 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 9241 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 9242 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 9243 9244 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9245 if (ret) 9246 dev_err(&hdev->pdev->dev, 9247 "failed to set wol config, ret = %d\n", ret); 9248 9249 return ret; 9250 } 9251 9252 static int hclge_update_wol(struct hclge_dev *hdev) 9253 { 9254 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 9255 9256 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 9257 return 0; 9258 9259 return hclge_set_wol_cfg(hdev, wol_info); 9260 } 9261 9262 static int hclge_init_wol(struct hclge_dev *hdev) 9263 { 9264 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 9265 int ret; 9266 9267 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 9268 return 0; 9269 9270 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 9271 ret = hclge_get_wol_supported_mode(hdev, 9272 &wol_info->wol_support_mode); 9273 if (ret) { 9274 wol_info->wol_support_mode = 0; 9275 return ret; 9276 } 9277 9278 return hclge_update_wol(hdev); 9279 } 9280 9281 static void hclge_get_wol(struct hnae3_handle *handle, 9282 struct ethtool_wolinfo *wol) 9283 { 9284 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 9285 9286 wol->supported = wol_info->wol_support_mode; 9287 wol->wolopts = wol_info->wol_current_mode; 9288 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 9289 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 9290 } 9291 9292 static int hclge_set_wol(struct hnae3_handle *handle, 9293 struct ethtool_wolinfo *wol) 9294 { 9295 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 9296 struct hclge_vport *vport = hclge_get_vport(handle); 9297 u32 wol_mode; 9298 int ret; 9299 9300 wol_mode = wol->wolopts; 9301 if (wol_mode & ~wol_info->wol_support_mode) 9302 return -EINVAL; 9303 9304 wol_info->wol_current_mode = wol_mode; 9305 if (wol_mode & WAKE_MAGICSECURE) { 9306 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 9307 wol_info->wol_sopass_size = SOPASS_MAX; 9308 } else { 9309 wol_info->wol_sopass_size = 0; 9310 } 9311 9312 ret = hclge_set_wol_cfg(vport->back, wol_info); 9313 if (ret) 9314 wol_info->wol_current_mode = 0; 9315 9316 return ret; 9317 } 9318 9319 static int hclge_set_autoneg_speed_dup(struct hclge_dev *hdev) 9320 { 9321 int ret; 9322 9323 if (hdev->hw.mac.support_autoneg) { 9324 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.req_autoneg); 9325 if (ret) 9326 return ret; 9327 } 9328 9329 if (!hdev->hw.mac.req_autoneg) { 9330 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.req_speed, 9331 hdev->hw.mac.req_duplex, 9332 hdev->hw.mac.req_lane_num); 9333 if (ret) 9334 return ret; 9335 } 9336 9337 return 0; 9338 } 9339 9340 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 9341 { 9342 struct pci_dev *pdev = ae_dev->pdev; 9343 struct hclge_dev *hdev; 9344 int ret; 9345 9346 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 9347 if (!hdev) 9348 return -ENOMEM; 9349 9350 hdev->pdev = pdev; 9351 hdev->ae_dev = ae_dev; 9352 hdev->reset_type = HNAE3_NONE_RESET; 9353 hdev->reset_level = HNAE3_FUNC_RESET; 9354 ae_dev->priv = hdev; 9355 9356 /* HW supprt 2 layer vlan */ 9357 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 9358 9359 mutex_init(&hdev->vport_lock); 9360 spin_lock_init(&hdev->fd_rule_lock); 9361 sema_init(&hdev->reset_sem, 1); 9362 9363 ret = hclge_pci_init(hdev); 9364 if (ret) 9365 goto out; 9366 9367 /* Firmware command queue initialize */ 9368 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 9369 if (ret) 9370 goto err_pci_uninit; 9371 9372 /* Firmware command initialize */ 9373 hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclge_cmq_ops); 9374 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 9375 true, hdev->reset_pending); 9376 if (ret) 9377 goto err_cmd_uninit; 9378 9379 ret = hclge_clear_hw_resource(hdev); 9380 if (ret) 9381 goto err_cmd_uninit; 9382 9383 ret = hclge_get_cap(hdev); 9384 if (ret) 9385 goto err_cmd_uninit; 9386 9387 ret = hclge_query_dev_specs(hdev); 9388 if (ret) { 9389 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 9390 ret); 9391 goto err_cmd_uninit; 9392 } 9393 9394 ret = hclge_configure(hdev); 9395 if (ret) { 9396 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 9397 goto err_cmd_uninit; 9398 } 9399 9400 ret = hclge_init_msi(hdev); 9401 if (ret) { 9402 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 9403 goto err_cmd_uninit; 9404 } 9405 9406 ret = hclge_misc_irq_init(hdev); 9407 if (ret) 9408 goto err_msi_uninit; 9409 9410 ret = hclge_alloc_tqps(hdev); 9411 if (ret) { 9412 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 9413 goto err_msi_irq_uninit; 9414 } 9415 9416 ret = hclge_alloc_vport(hdev); 9417 if (ret) 9418 goto err_msi_irq_uninit; 9419 9420 ret = hclge_map_tqp(hdev); 9421 if (ret) 9422 goto err_msi_irq_uninit; 9423 9424 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 9425 clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps); 9426 if (hnae3_dev_phy_imp_supported(hdev)) 9427 ret = hclge_update_tp_port_info(hdev); 9428 else 9429 ret = hclge_mac_mdio_config(hdev); 9430 9431 if (ret) 9432 goto err_msi_irq_uninit; 9433 } 9434 9435 ret = hclge_init_umv_space(hdev); 9436 if (ret) 9437 goto err_mdiobus_unreg; 9438 9439 ret = hclge_mac_init(hdev); 9440 if (ret) { 9441 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 9442 goto err_mdiobus_unreg; 9443 } 9444 9445 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 9446 if (ret) { 9447 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 9448 goto err_mdiobus_unreg; 9449 } 9450 9451 ret = hclge_config_gro(hdev); 9452 if (ret) 9453 goto err_mdiobus_unreg; 9454 9455 ret = hclge_init_vlan_config(hdev); 9456 if (ret) { 9457 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 9458 goto err_mdiobus_unreg; 9459 } 9460 9461 ret = hclge_tm_schd_init(hdev); 9462 if (ret) { 9463 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 9464 goto err_mdiobus_unreg; 9465 } 9466 9467 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 9468 &hdev->rss_cfg); 9469 if (ret) { 9470 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 9471 goto err_mdiobus_unreg; 9472 } 9473 9474 ret = hclge_rss_init_hw(hdev); 9475 if (ret) { 9476 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 9477 goto err_mdiobus_unreg; 9478 } 9479 9480 ret = init_mgr_tbl(hdev); 9481 if (ret) { 9482 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 9483 goto err_mdiobus_unreg; 9484 } 9485 9486 ret = hclge_init_fd_config(hdev); 9487 if (ret) { 9488 dev_err(&pdev->dev, 9489 "fd table init fail, ret=%d\n", ret); 9490 goto err_mdiobus_unreg; 9491 } 9492 9493 ret = hclge_ptp_init(hdev); 9494 if (ret) 9495 goto err_mdiobus_unreg; 9496 9497 ret = hclge_update_port_info(hdev); 9498 if (ret) 9499 goto err_ptp_uninit; 9500 9501 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_COPPER) { 9502 hdev->hw.mac.req_autoneg = hdev->hw.mac.autoneg; 9503 if (hdev->hw.mac.autoneg == AUTONEG_DISABLE && 9504 hdev->hw.mac.speed != SPEED_UNKNOWN) 9505 hdev->hw.mac.req_speed = hdev->hw.mac.speed; 9506 } 9507 9508 ret = hclge_set_autoneg_speed_dup(hdev); 9509 if (ret) { 9510 dev_err(&pdev->dev, 9511 "failed to set autoneg speed duplex, ret = %d\n", ret); 9512 goto err_ptp_uninit; 9513 } 9514 9515 INIT_KFIFO(hdev->mac_tnl_log); 9516 9517 hclge_dcb_ops_set(hdev); 9518 9519 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 9520 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 9521 9522 hclge_clear_all_event_cause(hdev); 9523 hclge_clear_resetting_state(hdev); 9524 9525 /* Log and clear the hw errors those already occurred */ 9526 if (hnae3_dev_ras_imp_supported(hdev)) 9527 hclge_handle_occurred_error(hdev); 9528 else 9529 hclge_handle_all_hns_hw_errors(ae_dev); 9530 9531 /* request delayed reset for the error recovery because an immediate 9532 * global reset on a PF affecting pending initialization of other PFs 9533 */ 9534 if (ae_dev->hw_err_reset_req) { 9535 enum hnae3_reset_type reset_level; 9536 9537 reset_level = hclge_get_reset_level(ae_dev, 9538 &ae_dev->hw_err_reset_req); 9539 hclge_set_def_reset_request(ae_dev, reset_level); 9540 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 9541 } 9542 9543 hclge_init_rxd_adv_layout(hdev); 9544 9545 ret = hclge_init_wol(hdev); 9546 if (ret) 9547 dev_warn(&pdev->dev, 9548 "failed to wake on lan init, ret = %d\n", ret); 9549 9550 ret = hclge_devlink_init(hdev); 9551 if (ret) 9552 goto err_ptp_uninit; 9553 9554 hclge_state_init(hdev); 9555 hdev->last_reset_time = jiffies; 9556 9557 /* Enable MISC vector(vector0) */ 9558 enable_irq(hdev->misc_vector.vector_irq); 9559 hclge_enable_vector(&hdev->misc_vector, true); 9560 9561 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 9562 HCLGE_DRIVER_NAME); 9563 9564 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 9565 return 0; 9566 9567 err_ptp_uninit: 9568 hclge_ptp_uninit(hdev); 9569 err_mdiobus_unreg: 9570 if (hdev->hw.mac.phydev) 9571 mdiobus_unregister(hdev->hw.mac.mdio_bus); 9572 err_msi_irq_uninit: 9573 hclge_misc_irq_uninit(hdev); 9574 err_msi_uninit: 9575 pci_free_irq_vectors(pdev); 9576 err_cmd_uninit: 9577 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 9578 err_pci_uninit: 9579 pcim_iounmap(pdev, hdev->hw.hw.io_base); 9580 pci_release_regions(pdev); 9581 pci_disable_device(pdev); 9582 out: 9583 mutex_destroy(&hdev->vport_lock); 9584 return ret; 9585 } 9586 9587 static void hclge_stats_clear(struct hclge_dev *hdev) 9588 { 9589 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 9590 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 9591 } 9592 9593 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 9594 { 9595 return hclge_config_switch_param(hdev, vf, enable, 9596 HCLGE_SWITCH_ANTI_SPOOF_MASK); 9597 } 9598 9599 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 9600 { 9601 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9602 HCLGE_FILTER_FE_NIC_INGRESS_B, 9603 enable, vf); 9604 } 9605 9606 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 9607 { 9608 int ret; 9609 9610 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 9611 if (ret) { 9612 dev_err(&hdev->pdev->dev, 9613 "Set vf %d mac spoof check %s failed, ret=%d\n", 9614 vf, str_on_off(enable), ret); 9615 return ret; 9616 } 9617 9618 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 9619 if (ret) 9620 dev_err(&hdev->pdev->dev, 9621 "Set vf %d vlan spoof check %s failed, ret=%d\n", 9622 vf, str_on_off(enable), ret); 9623 9624 return ret; 9625 } 9626 9627 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 9628 bool enable) 9629 { 9630 struct hclge_vport *vport = hclge_get_vport(handle); 9631 struct hclge_dev *hdev = vport->back; 9632 u32 new_spoofchk = enable ? 1 : 0; 9633 int ret; 9634 9635 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9636 return -EOPNOTSUPP; 9637 9638 vport = hclge_get_vf_vport(hdev, vf); 9639 if (!vport) 9640 return -EINVAL; 9641 9642 if (vport->vf_info.spoofchk == new_spoofchk) 9643 return 0; 9644 9645 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 9646 dev_warn(&hdev->pdev->dev, 9647 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 9648 vf); 9649 else if (enable && hclge_is_umv_space_full(vport, true)) 9650 dev_warn(&hdev->pdev->dev, 9651 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 9652 vf); 9653 9654 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 9655 if (ret) 9656 return ret; 9657 9658 vport->vf_info.spoofchk = new_spoofchk; 9659 return 0; 9660 } 9661 9662 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 9663 { 9664 struct hclge_vport *vport = hdev->vport; 9665 int ret; 9666 int i; 9667 9668 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9669 return 0; 9670 9671 /* resume the vf spoof check state after reset */ 9672 for (i = 0; i < hdev->num_alloc_vport; i++) { 9673 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 9674 vport->vf_info.spoofchk); 9675 if (ret) 9676 return ret; 9677 9678 vport++; 9679 } 9680 9681 return 0; 9682 } 9683 9684 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 9685 { 9686 struct hclge_vport *vport = hclge_get_vport(handle); 9687 struct hclge_dev *hdev = vport->back; 9688 u32 new_trusted = enable ? 1 : 0; 9689 9690 vport = hclge_get_vf_vport(hdev, vf); 9691 if (!vport) 9692 return -EINVAL; 9693 9694 if (vport->vf_info.trusted == new_trusted) 9695 return 0; 9696 9697 vport->vf_info.trusted = new_trusted; 9698 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 9699 hclge_task_schedule(hdev, 0); 9700 9701 return 0; 9702 } 9703 9704 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 9705 { 9706 int ret; 9707 int vf; 9708 9709 /* reset vf rate to default value */ 9710 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 9711 struct hclge_vport *vport = &hdev->vport[vf]; 9712 9713 vport->vf_info.max_tx_rate = 0; 9714 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 9715 if (ret) 9716 dev_err(&hdev->pdev->dev, 9717 "vf%d failed to reset to default, ret=%d\n", 9718 vf - HCLGE_VF_VPORT_START_NUM, ret); 9719 } 9720 } 9721 9722 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 9723 int min_tx_rate, int max_tx_rate) 9724 { 9725 if (min_tx_rate != 0 || 9726 max_tx_rate < 0 || (u32)max_tx_rate > hdev->hw.mac.max_speed) { 9727 dev_err(&hdev->pdev->dev, 9728 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 9729 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 9730 return -EINVAL; 9731 } 9732 9733 return 0; 9734 } 9735 9736 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 9737 int min_tx_rate, int max_tx_rate, bool force) 9738 { 9739 struct hclge_vport *vport = hclge_get_vport(handle); 9740 struct hclge_dev *hdev = vport->back; 9741 int ret; 9742 9743 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 9744 if (ret) 9745 return ret; 9746 9747 vport = hclge_get_vf_vport(hdev, vf); 9748 if (!vport) 9749 return -EINVAL; 9750 9751 if (!force && (u32)max_tx_rate == vport->vf_info.max_tx_rate) 9752 return 0; 9753 9754 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 9755 if (ret) 9756 return ret; 9757 9758 vport->vf_info.max_tx_rate = max_tx_rate; 9759 9760 return 0; 9761 } 9762 9763 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 9764 { 9765 struct hnae3_handle *handle = &hdev->vport->nic; 9766 struct hclge_vport *vport; 9767 int ret; 9768 int vf; 9769 9770 /* resume the vf max_tx_rate after reset */ 9771 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 9772 vport = hclge_get_vf_vport(hdev, vf); 9773 if (!vport) 9774 return -EINVAL; 9775 9776 /* zero means max rate, after reset, firmware already set it to 9777 * max rate, so just continue. 9778 */ 9779 if (!vport->vf_info.max_tx_rate) 9780 continue; 9781 9782 ret = hclge_set_vf_rate(handle, vf, 0, 9783 vport->vf_info.max_tx_rate, true); 9784 if (ret) { 9785 dev_err(&hdev->pdev->dev, 9786 "vf%d failed to resume tx_rate:%u, ret=%d\n", 9787 vf, vport->vf_info.max_tx_rate, ret); 9788 return ret; 9789 } 9790 } 9791 9792 return 0; 9793 } 9794 9795 static void hclge_reset_vport_state(struct hclge_dev *hdev) 9796 { 9797 struct hclge_vport *vport = hdev->vport; 9798 int i; 9799 9800 for (i = 0; i < hdev->num_alloc_vport; i++) { 9801 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 9802 vport++; 9803 } 9804 } 9805 9806 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 9807 { 9808 struct hclge_dev *hdev = ae_dev->priv; 9809 struct pci_dev *pdev = ae_dev->pdev; 9810 int ret; 9811 9812 set_bit(HCLGE_STATE_DOWN, &hdev->state); 9813 9814 hclge_stats_clear(hdev); 9815 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 9816 * so here should not clean table in memory. 9817 */ 9818 if (hdev->reset_type == HNAE3_IMP_RESET || 9819 hdev->reset_type == HNAE3_GLOBAL_RESET) { 9820 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 9821 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 9822 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 9823 hclge_reset_umv_space(hdev); 9824 } 9825 9826 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 9827 true, hdev->reset_pending); 9828 if (ret) { 9829 dev_err(&pdev->dev, "Cmd queue init failed\n"); 9830 return ret; 9831 } 9832 9833 ret = hclge_map_tqp(hdev); 9834 if (ret) { 9835 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 9836 return ret; 9837 } 9838 9839 ret = hclge_mac_init(hdev); 9840 if (ret) { 9841 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 9842 return ret; 9843 } 9844 9845 ret = hclge_set_autoneg_speed_dup(hdev); 9846 if (ret) { 9847 dev_err(&pdev->dev, 9848 "failed to set autoneg speed duplex, ret = %d\n", ret); 9849 return ret; 9850 } 9851 9852 ret = hclge_tp_port_init(hdev); 9853 if (ret) { 9854 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 9855 ret); 9856 return ret; 9857 } 9858 9859 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 9860 if (ret) { 9861 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 9862 return ret; 9863 } 9864 9865 ret = hclge_config_gro(hdev); 9866 if (ret) 9867 return ret; 9868 9869 ret = hclge_init_vlan_config(hdev); 9870 if (ret) { 9871 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 9872 return ret; 9873 } 9874 9875 hclge_reset_tc_config(hdev); 9876 9877 ret = hclge_tm_init_hw(hdev, true); 9878 if (ret) { 9879 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 9880 return ret; 9881 } 9882 9883 ret = hclge_rss_init_hw(hdev); 9884 if (ret) { 9885 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 9886 return ret; 9887 } 9888 9889 ret = init_mgr_tbl(hdev); 9890 if (ret) { 9891 dev_err(&pdev->dev, 9892 "failed to reinit manager table, ret = %d\n", ret); 9893 return ret; 9894 } 9895 9896 ret = hclge_init_fd_config(hdev); 9897 if (ret) { 9898 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 9899 return ret; 9900 } 9901 9902 ret = hclge_ptp_init(hdev); 9903 if (ret) 9904 return ret; 9905 9906 /* Log and clear the hw errors those already occurred */ 9907 if (hnae3_dev_ras_imp_supported(hdev)) 9908 hclge_handle_occurred_error(hdev); 9909 else 9910 hclge_handle_all_hns_hw_errors(ae_dev); 9911 9912 /* Re-enable the hw error interrupts because 9913 * the interrupts get disabled on global reset. 9914 */ 9915 ret = hclge_config_nic_hw_error(hdev, true); 9916 if (ret) { 9917 dev_err(&pdev->dev, 9918 "fail(%d) to re-enable NIC hw error interrupts\n", 9919 ret); 9920 return ret; 9921 } 9922 9923 if (hdev->roce_client) { 9924 ret = hclge_config_rocee_ras_interrupt(hdev, true); 9925 if (ret) { 9926 dev_err(&pdev->dev, 9927 "fail(%d) to re-enable roce ras interrupts\n", 9928 ret); 9929 return ret; 9930 } 9931 } 9932 9933 hclge_reset_vport_state(hdev); 9934 ret = hclge_reset_vport_spoofchk(hdev); 9935 if (ret) 9936 return ret; 9937 9938 ret = hclge_resume_vf_rate(hdev); 9939 if (ret) 9940 return ret; 9941 9942 hclge_init_rxd_adv_layout(hdev); 9943 9944 ret = hclge_update_wol(hdev); 9945 if (ret) 9946 dev_warn(&pdev->dev, 9947 "failed to update wol config, ret = %d\n", ret); 9948 9949 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 9950 HCLGE_DRIVER_NAME); 9951 9952 return 0; 9953 } 9954 9955 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 9956 { 9957 struct hclge_dev *hdev = ae_dev->priv; 9958 struct hclge_mac *mac = &hdev->hw.mac; 9959 9960 hclge_reset_vf_rate(hdev); 9961 hclge_clear_vf_vlan(hdev); 9962 hclge_state_uninit(hdev); 9963 hclge_ptp_uninit(hdev); 9964 hclge_uninit_rxd_adv_layout(hdev); 9965 hclge_uninit_mac_table(hdev); 9966 hclge_del_all_fd_entries(hdev); 9967 9968 if (mac->phydev) 9969 mdiobus_unregister(mac->mdio_bus); 9970 9971 /* Disable MISC vector(vector0) */ 9972 hclge_enable_vector(&hdev->misc_vector, false); 9973 disable_irq(hdev->misc_vector.vector_irq); 9974 9975 /* Disable all hw interrupts */ 9976 hclge_config_mac_tnl_int(hdev, false); 9977 hclge_config_nic_hw_error(hdev, false); 9978 hclge_config_rocee_ras_interrupt(hdev, false); 9979 9980 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 9981 hclge_misc_irq_uninit(hdev); 9982 hclge_devlink_uninit(hdev); 9983 hclge_pci_uninit(hdev); 9984 hclge_uninit_vport_vlan_table(hdev); 9985 mutex_destroy(&hdev->vport_lock); 9986 ae_dev->priv = NULL; 9987 } 9988 9989 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 9990 { 9991 struct hclge_vport *vport = hclge_get_vport(handle); 9992 struct hclge_dev *hdev = vport->back; 9993 9994 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 9995 } 9996 9997 static void hclge_get_channels(struct hnae3_handle *handle, 9998 struct ethtool_channels *ch) 9999 { 10000 ch->max_combined = hclge_get_max_channels(handle); 10001 ch->other_count = 1; 10002 ch->max_other = 1; 10003 ch->combined_count = handle->kinfo.rss_size; 10004 } 10005 10006 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 10007 u16 *alloc_tqps, u16 *max_rss_size) 10008 { 10009 struct hclge_vport *vport = hclge_get_vport(handle); 10010 struct hclge_dev *hdev = vport->back; 10011 10012 *alloc_tqps = vport->alloc_tqps; 10013 *max_rss_size = hdev->pf_rss_size_max; 10014 } 10015 10016 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 10017 { 10018 struct hclge_vport *vport = hclge_get_vport(handle); 10019 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 10020 struct hclge_dev *hdev = vport->back; 10021 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 10022 u16 tc_valid[HCLGE_MAX_TC_NUM]; 10023 u16 roundup_size; 10024 unsigned int i; 10025 10026 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 10027 roundup_size = ilog2(roundup_size); 10028 /* Set the RSS TC mode according to the new RSS size */ 10029 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 10030 tc_valid[i] = 0; 10031 10032 if (!(hdev->hw_tc_map & BIT(i))) 10033 continue; 10034 10035 tc_valid[i] = 1; 10036 tc_size[i] = roundup_size; 10037 tc_offset[i] = vport->nic.kinfo.rss_size * i; 10038 } 10039 10040 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 10041 tc_size); 10042 } 10043 10044 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 10045 bool rxfh_configured) 10046 { 10047 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10048 struct hclge_vport *vport = hclge_get_vport(handle); 10049 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 10050 struct hclge_dev *hdev = vport->back; 10051 u16 cur_rss_size = kinfo->rss_size; 10052 u16 cur_tqps = kinfo->num_tqps; 10053 u32 *rss_indir; 10054 unsigned int i; 10055 int ret; 10056 10057 kinfo->req_rss_size = new_tqps_num; 10058 10059 ret = hclge_tm_vport_map_update(hdev); 10060 if (ret) { 10061 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 10062 return ret; 10063 } 10064 10065 ret = hclge_set_rss_tc_mode_cfg(handle); 10066 if (ret) 10067 return ret; 10068 10069 /* RSS indirection table has been configured by user */ 10070 if (rxfh_configured) 10071 goto out; 10072 10073 /* Reinitializes the rss indirect table according to the new RSS size */ 10074 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 10075 GFP_KERNEL); 10076 if (!rss_indir) 10077 return -ENOMEM; 10078 10079 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 10080 rss_indir[i] = i % kinfo->rss_size; 10081 10082 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 10083 if (ret) 10084 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 10085 ret); 10086 10087 kfree(rss_indir); 10088 10089 out: 10090 if (!ret) 10091 dev_info(&hdev->pdev->dev, 10092 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 10093 cur_rss_size, kinfo->rss_size, 10094 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 10095 10096 return ret; 10097 } 10098 10099 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 10100 { 10101 struct hclge_set_led_state_cmd *req; 10102 struct hclge_desc desc; 10103 int ret; 10104 10105 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 10106 10107 req = (struct hclge_set_led_state_cmd *)desc.data; 10108 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 10109 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 10110 10111 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10112 if (ret) 10113 dev_err(&hdev->pdev->dev, 10114 "Send set led state cmd error, ret =%d\n", ret); 10115 10116 return ret; 10117 } 10118 10119 enum hclge_led_status { 10120 HCLGE_LED_OFF, 10121 HCLGE_LED_ON, 10122 HCLGE_LED_NO_CHANGE = 0xFF, 10123 }; 10124 10125 static int hclge_set_led_id(struct hnae3_handle *handle, 10126 enum ethtool_phys_id_state status) 10127 { 10128 struct hclge_vport *vport = hclge_get_vport(handle); 10129 struct hclge_dev *hdev = vport->back; 10130 10131 switch (status) { 10132 case ETHTOOL_ID_ACTIVE: 10133 return hclge_set_led_status(hdev, HCLGE_LED_ON); 10134 case ETHTOOL_ID_INACTIVE: 10135 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 10136 default: 10137 return -EINVAL; 10138 } 10139 } 10140 10141 static void hclge_get_link_mode(struct hnae3_handle *handle, 10142 unsigned long *supported, 10143 unsigned long *advertising) 10144 { 10145 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 10146 struct hclge_vport *vport = hclge_get_vport(handle); 10147 struct hclge_dev *hdev = vport->back; 10148 unsigned int idx = 0; 10149 10150 for (; idx < size; idx++) { 10151 supported[idx] = hdev->hw.mac.supported[idx]; 10152 advertising[idx] = hdev->hw.mac.advertising[idx]; 10153 } 10154 } 10155 10156 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 10157 { 10158 struct hclge_vport *vport = hclge_get_vport(handle); 10159 struct hclge_dev *hdev = vport->back; 10160 bool gro_en_old = hdev->gro_en; 10161 int ret; 10162 10163 hdev->gro_en = enable; 10164 ret = hclge_config_gro(hdev); 10165 if (ret) 10166 hdev->gro_en = gro_en_old; 10167 10168 return ret; 10169 } 10170 10171 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 10172 { 10173 struct hnae3_handle *handle = &vport->nic; 10174 struct hclge_dev *hdev = vport->back; 10175 bool uc_en = false; 10176 bool mc_en = false; 10177 u8 tmp_flags; 10178 bool bc_en; 10179 int ret; 10180 10181 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 10182 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 10183 vport->last_promisc_flags = vport->overflow_promisc_flags; 10184 } 10185 10186 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 10187 &vport->state)) 10188 return 0; 10189 10190 /* for PF */ 10191 if (!vport->vport_id) { 10192 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 10193 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 10194 tmp_flags & HNAE3_MPE); 10195 if (!ret) 10196 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10197 &vport->state); 10198 else 10199 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 10200 &vport->state); 10201 return ret; 10202 } 10203 10204 /* for VF */ 10205 if (vport->vf_info.trusted) { 10206 uc_en = vport->vf_info.request_uc_en > 0 || 10207 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 10208 mc_en = vport->vf_info.request_mc_en > 0 || 10209 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 10210 } 10211 bc_en = vport->vf_info.request_bc_en > 0; 10212 10213 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 10214 mc_en, bc_en); 10215 if (ret) { 10216 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 10217 return ret; 10218 } 10219 hclge_set_vport_vlan_fltr_change(vport); 10220 10221 return 0; 10222 } 10223 10224 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 10225 { 10226 struct hclge_vport *vport; 10227 int ret; 10228 u16 i; 10229 10230 for (i = 0; i < hdev->num_alloc_vport; i++) { 10231 vport = &hdev->vport[i]; 10232 10233 ret = hclge_sync_vport_promisc_mode(vport); 10234 if (ret) 10235 return; 10236 } 10237 } 10238 10239 static bool hclge_module_existed(struct hclge_dev *hdev) 10240 { 10241 struct hclge_desc desc; 10242 u32 existed; 10243 int ret; 10244 10245 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 10246 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10247 if (ret) { 10248 dev_err(&hdev->pdev->dev, 10249 "failed to get SFP exist state, ret = %d\n", ret); 10250 return false; 10251 } 10252 10253 existed = le32_to_cpu(desc.data[0]); 10254 10255 return existed != 0; 10256 } 10257 10258 /* need 6 bds(total 140 bytes) in one reading 10259 * return the number of bytes actually read, 0 means read failed. 10260 */ 10261 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 10262 u32 len, u8 *data) 10263 { 10264 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 10265 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 10266 u16 read_len; 10267 u16 copy_len; 10268 int ret; 10269 int i; 10270 10271 /* setup all 6 bds to read module eeprom info. */ 10272 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 10273 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 10274 true); 10275 10276 /* bd0~bd4 need next flag */ 10277 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 10278 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 10279 } 10280 10281 /* setup bd0, this bd contains offset and read length. */ 10282 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 10283 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 10284 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 10285 sfp_info_bd0->read_len = cpu_to_le16(read_len); 10286 10287 ret = hclge_cmd_send(&hdev->hw, desc, i); 10288 if (ret) { 10289 dev_err(&hdev->pdev->dev, 10290 "failed to get SFP eeprom info, ret = %d\n", ret); 10291 return 0; 10292 } 10293 10294 /* copy sfp info from bd0 to out buffer. */ 10295 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 10296 memcpy(data, sfp_info_bd0->data, copy_len); 10297 read_len = copy_len; 10298 10299 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 10300 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 10301 if (read_len >= len) 10302 return read_len; 10303 10304 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 10305 memcpy(data + read_len, desc[i].data, copy_len); 10306 read_len += copy_len; 10307 } 10308 10309 return read_len; 10310 } 10311 10312 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 10313 u32 len, u8 *data) 10314 { 10315 struct hclge_vport *vport = hclge_get_vport(handle); 10316 struct hclge_dev *hdev = vport->back; 10317 u32 read_len = 0; 10318 u16 data_len; 10319 10320 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 10321 return -EOPNOTSUPP; 10322 10323 if (!hclge_module_existed(hdev)) 10324 return -ENXIO; 10325 10326 while (read_len < len) { 10327 data_len = hclge_get_sfp_eeprom_info(hdev, 10328 offset + read_len, 10329 len - read_len, 10330 data + read_len); 10331 if (!data_len) 10332 return -EIO; 10333 10334 read_len += data_len; 10335 } 10336 10337 return 0; 10338 } 10339 10340 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 10341 u32 *status_code) 10342 { 10343 struct hclge_vport *vport = hclge_get_vport(handle); 10344 struct hclge_dev *hdev = vport->back; 10345 struct hclge_desc desc; 10346 int ret; 10347 10348 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 10349 return -EOPNOTSUPP; 10350 10351 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 10352 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10353 if (ret) { 10354 dev_err(&hdev->pdev->dev, 10355 "failed to query link diagnosis info, ret = %d\n", ret); 10356 return ret; 10357 } 10358 10359 *status_code = le32_to_cpu(desc.data[0]); 10360 return 0; 10361 } 10362 10363 /* After disable sriov, VF still has some config and info need clean, 10364 * which configed by PF. 10365 */ 10366 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 10367 { 10368 struct hclge_dev *hdev = vport->back; 10369 struct hclge_vlan_info vlan_info; 10370 int ret; 10371 10372 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 10373 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 10374 vport->need_notify = 0; 10375 vport->mps = 0; 10376 10377 /* after disable sriov, clean VF rate configured by PF */ 10378 ret = hclge_tm_qs_shaper_cfg(vport, 0); 10379 if (ret) 10380 dev_err(&hdev->pdev->dev, 10381 "failed to clean vf%d rate config, ret = %d\n", 10382 vfid, ret); 10383 10384 vlan_info.vlan_tag = 0; 10385 vlan_info.qos = 0; 10386 vlan_info.vlan_proto = ETH_P_8021Q; 10387 ret = hclge_update_port_base_vlan_cfg(vport, 10388 HNAE3_PORT_BASE_VLAN_DISABLE, 10389 &vlan_info); 10390 if (ret) 10391 dev_err(&hdev->pdev->dev, 10392 "failed to clean vf%d port base vlan, ret = %d\n", 10393 vfid, ret); 10394 10395 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 10396 if (ret) 10397 dev_err(&hdev->pdev->dev, 10398 "failed to clean vf%d spoof config, ret = %d\n", 10399 vfid, ret); 10400 10401 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 10402 } 10403 10404 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 10405 { 10406 struct hclge_dev *hdev = ae_dev->priv; 10407 struct hclge_vport *vport; 10408 int i; 10409 10410 for (i = 0; i < num_vfs; i++) { 10411 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 10412 10413 hclge_clear_vport_vf_info(vport, i); 10414 } 10415 } 10416 10417 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 10418 u8 *priority) 10419 { 10420 struct hclge_vport *vport = hclge_get_vport(h); 10421 10422 if (dscp >= HNAE3_MAX_DSCP) 10423 return -EINVAL; 10424 10425 if (tc_mode) 10426 *tc_mode = vport->nic.kinfo.tc_map_mode; 10427 if (priority) 10428 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 10429 vport->nic.kinfo.dscp_prio[dscp]; 10430 10431 return 0; 10432 } 10433 10434 static const struct hnae3_ae_ops hclge_ops = { 10435 .init_ae_dev = hclge_init_ae_dev, 10436 .uninit_ae_dev = hclge_uninit_ae_dev, 10437 .reset_prepare = hclge_reset_prepare_general, 10438 .reset_done = hclge_reset_done, 10439 .init_client_instance = hclge_init_client_instance, 10440 .uninit_client_instance = hclge_uninit_client_instance, 10441 .map_ring_to_vector = hclge_map_ring_to_vector, 10442 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 10443 .get_vector = hclge_get_vector, 10444 .put_vector = hclge_put_vector, 10445 .set_promisc_mode = hclge_set_promisc_mode, 10446 .request_update_promisc_mode = hclge_request_update_promisc_mode, 10447 .set_loopback = hclge_set_loopback, 10448 .start = hclge_ae_start, 10449 .stop = hclge_ae_stop, 10450 .client_start = hclge_client_start, 10451 .client_stop = hclge_client_stop, 10452 .get_status = hclge_get_status, 10453 .get_ksettings_an_result = hclge_get_ksettings_an_result, 10454 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 10455 .get_media_type = hclge_get_media_type, 10456 .check_port_speed = hclge_check_port_speed, 10457 .get_fec_stats = hclge_get_fec_stats, 10458 .get_fec = hclge_get_fec, 10459 .set_fec = hclge_set_fec, 10460 .get_rss_key_size = hclge_comm_get_rss_key_size, 10461 .get_rss = hclge_get_rss, 10462 .set_rss = hclge_set_rss, 10463 .set_rss_tuple = hclge_set_rss_tuple, 10464 .get_rss_tuple = hclge_get_rss_tuple, 10465 .get_tc_size = hclge_get_tc_size, 10466 .get_mac_addr = hclge_get_mac_addr, 10467 .set_mac_addr = hclge_set_mac_addr, 10468 .do_ioctl = hclge_do_ioctl, 10469 .add_uc_addr = hclge_add_uc_addr, 10470 .rm_uc_addr = hclge_rm_uc_addr, 10471 .add_mc_addr = hclge_add_mc_addr, 10472 .rm_mc_addr = hclge_rm_mc_addr, 10473 .set_autoneg = hclge_set_autoneg, 10474 .get_autoneg = hclge_get_autoneg, 10475 .restart_autoneg = hclge_restart_autoneg, 10476 .halt_autoneg = hclge_halt_autoneg, 10477 .get_pauseparam = hclge_get_pauseparam, 10478 .set_pauseparam = hclge_set_pauseparam, 10479 .set_mtu = hclge_set_mtu, 10480 .reset_queue = hclge_reset_tqp, 10481 .get_stats = hclge_get_stats, 10482 .get_mac_stats = hclge_get_mac_stat, 10483 .update_stats = hclge_update_stats, 10484 .get_strings = hclge_get_strings, 10485 .get_sset_count = hclge_get_sset_count, 10486 .get_fw_version = hclge_get_fw_version, 10487 .get_mdix_mode = hclge_get_mdix_mode, 10488 .enable_vlan_filter = hclge_enable_vlan_filter, 10489 .set_vlan_filter = hclge_set_vlan_filter, 10490 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 10491 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 10492 .reset_event = hclge_reset_event, 10493 .get_reset_level = hclge_get_reset_level, 10494 .set_default_reset_request = hclge_set_def_reset_request, 10495 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 10496 .set_channels = hclge_set_channels, 10497 .get_channels = hclge_get_channels, 10498 .get_regs_len = hclge_get_regs_len, 10499 .get_regs = hclge_get_regs, 10500 .set_led_id = hclge_set_led_id, 10501 .get_link_mode = hclge_get_link_mode, 10502 .add_fd_entry = hclge_add_fd_entry, 10503 .del_fd_entry = hclge_del_fd_entry, 10504 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 10505 .get_fd_rule_info = hclge_get_fd_rule_info, 10506 .get_fd_all_rules = hclge_get_all_rules, 10507 .enable_fd = hclge_enable_fd, 10508 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 10509 .dbg_get_read_func = hclge_dbg_get_read_func, 10510 .handle_hw_ras_error = hclge_handle_hw_ras_error, 10511 .get_hw_reset_stat = hclge_get_hw_reset_stat, 10512 .ae_dev_resetting = hclge_ae_dev_resetting, 10513 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 10514 .set_gro_en = hclge_gro_en, 10515 .get_global_queue_id = hclge_covert_handle_qid_global, 10516 .set_timer_task = hclge_set_timer_task, 10517 .mac_connect_phy = hclge_mac_connect_phy, 10518 .mac_disconnect_phy = hclge_mac_disconnect_phy, 10519 .get_vf_config = hclge_get_vf_config, 10520 .set_vf_link_state = hclge_set_vf_link_state, 10521 .set_vf_spoofchk = hclge_set_vf_spoofchk, 10522 .set_vf_trust = hclge_set_vf_trust, 10523 .set_vf_rate = hclge_set_vf_rate, 10524 .set_vf_mac = hclge_set_vf_mac, 10525 .get_module_eeprom = hclge_get_module_eeprom, 10526 .get_cmdq_stat = hclge_get_cmdq_stat, 10527 .add_cls_flower = hclge_add_cls_flower, 10528 .del_cls_flower = hclge_del_cls_flower, 10529 .cls_flower_active = hclge_is_cls_flower_active, 10530 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 10531 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 10532 .set_tx_hwts_info = hclge_ptp_set_tx_info, 10533 .get_rx_hwts = hclge_ptp_get_rx_hwts, 10534 .get_ts_info = hclge_ptp_get_ts_info, 10535 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 10536 .clean_vf_config = hclge_clean_vport_config, 10537 .get_dscp_prio = hclge_get_dscp_prio, 10538 .get_wol = hclge_get_wol, 10539 .set_wol = hclge_set_wol, 10540 .hwtstamp_get = hclge_ptp_get_cfg, 10541 .hwtstamp_set = hclge_ptp_set_cfg, 10542 }; 10543 10544 static struct hnae3_ae_algo ae_algo = { 10545 .ops = &hclge_ops, 10546 .pdev_id_table = ae_algo_pci_tbl, 10547 }; 10548 10549 static int __init hclge_init(void) 10550 { 10551 pr_debug("%s is initializing\n", HCLGE_NAME); 10552 10553 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, 10554 HCLGE_NAME); 10555 if (!hclge_wq) { 10556 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 10557 return -ENOMEM; 10558 } 10559 10560 hnae3_register_ae_algo(&ae_algo); 10561 10562 return 0; 10563 } 10564 10565 static void __exit hclge_exit(void) 10566 { 10567 hnae3_acquire_unload_lock(); 10568 hnae3_unregister_ae_algo_prepare(&ae_algo); 10569 hnae3_unregister_ae_algo(&ae_algo); 10570 destroy_workqueue(hclge_wq); 10571 hnae3_release_unload_lock(); 10572 } 10573 module_init(hclge_init); 10574 module_exit(hclge_exit); 10575 10576 MODULE_LICENSE("GPL"); 10577 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 10578 MODULE_DESCRIPTION("HCLGE Driver"); 10579 MODULE_VERSION(HCLGE_MOD_VERSION); 10580