1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2023 Hisilicon Limited. */ 3 4 #ifndef __KUNPENG_HCCS_H__ 5 #define __KUNPENG_HCCS_H__ 6 7 /* 8 * |--------------- Chip0 ---------------|---------------- ChipN -------------| 9 * |--------Die0-------|--------DieN-------|--------Die0-------|-------DieN-------| 10 * | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 |P0 | P1 | P2 | P3 | 11 */ 12 13 enum hccs_port_type { 14 HCCS_V1 = 1, 15 HCCS_V2, 16 }; 17 18 #define HCCS_IP_PREFIX "HCCS-v" 19 #define HCCS_IP_MAX 255 20 #define HCCS_NAME_MAX_LEN 9 21 struct hccs_type_name_map { 22 u8 type; 23 char name[HCCS_NAME_MAX_LEN + 1]; 24 }; 25 26 /* 27 * This value cannot be 255, otherwise the loop of the multi-BD communication 28 * case cannot end. 29 */ 30 #define HCCS_DIE_MAX_PORT_ID 254 31 32 struct hccs_port_info { 33 u8 port_id; 34 u8 port_type; 35 u8 max_lane_num; 36 bool enable; /* if the port is enabled */ 37 struct kobject kobj; 38 bool dir_created; 39 struct hccs_die_info *die; /* point to the die the port is located */ 40 }; 41 42 struct hccs_die_info { 43 u8 die_id; 44 u8 port_num; 45 u8 min_port_id; 46 u8 max_port_id; 47 struct hccs_port_info *ports; 48 struct kobject kobj; 49 bool dir_created; 50 struct hccs_chip_info *chip; /* point to the chip the die is located */ 51 }; 52 53 struct hccs_chip_info { 54 u8 chip_id; 55 u8 die_num; 56 struct hccs_die_info *dies; 57 struct kobject kobj; 58 struct hccs_dev *hdev; 59 }; 60 61 struct hccs_mbox_client_info { 62 struct mbox_client client; 63 struct pcc_mbox_chan *pcc_chan; 64 u64 deadline_us; 65 struct completion done; 66 }; 67 68 struct hccs_desc; 69 70 struct hccs_verspecific_data { 71 void (*rx_callback)(struct mbox_client *cl, void *mssg); 72 int (*wait_cmd_complete)(struct hccs_dev *hdev); 73 void (*fill_pcc_shared_mem)(struct hccs_dev *hdev, 74 u8 cmd, struct hccs_desc *desc, 75 void __iomem *comm_space, 76 u16 space_size); 77 u16 shared_mem_size; 78 bool has_txdone_irq; 79 }; 80 81 #define HCCS_CAPS_HCCS_V2_PM BIT_ULL(0) 82 83 struct hccs_dev { 84 struct device *dev; 85 struct acpi_device *acpi_dev; 86 const struct hccs_verspecific_data *verspec_data; 87 /* device capabilities from firmware, like HCCS_CAPS_xxx. */ 88 u64 caps; 89 u8 chip_num; 90 struct hccs_chip_info *chips; 91 u16 used_type_num; 92 struct hccs_type_name_map *type_name_maps; 93 u8 chan_id; 94 struct mutex lock; 95 struct hccs_mbox_client_info cl_info; 96 }; 97 98 #define HCCS_SERDES_MODULE_CODE 0x32 99 enum hccs_subcmd_type { 100 HCCS_GET_CHIP_NUM = 0x1, 101 HCCS_GET_DIE_NUM, 102 HCCS_GET_DIE_INFO, 103 HCCS_GET_DIE_PORT_INFO, 104 HCCS_GET_DEV_CAP, 105 HCCS_GET_PORT_LINK_STATUS, 106 HCCS_GET_PORT_CRC_ERR_CNT, 107 HCCS_GET_DIE_PORTS_LANE_STA, 108 HCCS_GET_DIE_PORTS_LINK_STA, 109 HCCS_GET_DIE_PORTS_CRC_ERR_CNT, 110 HCCS_GET_PORT_IDLE_STATUS, 111 HCCS_PM_DEC_LANE, 112 HCCS_PM_INC_LANE, 113 HCCS_SUB_CMD_MAX = 255, 114 }; 115 116 struct hccs_die_num_req_param { 117 u8 chip_id; 118 }; 119 120 struct hccs_die_info_req_param { 121 u8 chip_id; 122 u8 die_idx; 123 }; 124 125 struct hccs_die_info_rsp_data { 126 u8 die_id; 127 u8 port_num; 128 u8 min_port_id; 129 u8 max_port_id; 130 }; 131 132 struct hccs_port_attr { 133 u8 port_id; 134 u8 port_type; 135 u8 max_lane_num; 136 u8 enable : 1; /* if the port is enabled */ 137 u16 rsv[2]; 138 }; 139 140 /* 141 * The common command request for getting the information of all HCCS port on 142 * specified DIE. 143 */ 144 struct hccs_die_comm_req_param { 145 u8 chip_id; 146 u8 die_id; /* id in hardware */ 147 }; 148 149 /* The common command request for getting the information of a specific port */ 150 struct hccs_port_comm_req_param { 151 u8 chip_id; 152 u8 die_id; 153 u8 port_id; 154 }; 155 156 #define HCCS_PREPARE_INC_LANE 1 157 #define HCCS_GET_ADAPT_RES 2 158 #define HCCS_START_RETRAINING 3 159 struct hccs_inc_lane_req_param { 160 u8 port_type; 161 u8 opt_type; 162 }; 163 164 #define HCCS_PORT_RESET 1 165 #define HCCS_PORT_SETUP 2 166 #define HCCS_PORT_CONFIG 3 167 #define HCCS_PORT_READY 4 168 struct hccs_link_status { 169 u8 lane_mask; /* indicate which lanes are used. */ 170 u8 link_fsm : 3; /* link fsm, 1: reset 2: setup 3: config 4: link-up */ 171 u8 lane_num : 5; /* current lane number */ 172 }; 173 174 struct hccs_req_head { 175 u8 module_code; /* set to 0x32 for serdes */ 176 u8 start_id; 177 u8 rsv[2]; 178 }; 179 180 struct hccs_rsp_head { 181 u8 data_len; 182 u8 next_id; 183 u8 rsv[2]; 184 }; 185 186 struct hccs_fw_inner_head { 187 u8 retStatus; /* 0: success, other: failure */ 188 u8 rsv[7]; 189 }; 190 191 #define HCCS_PCC_SHARE_MEM_BYTES 64 192 #define HCCS_FW_INNER_HEAD_BYTES 8 193 #define HCCS_RSP_HEAD_BYTES 4 194 195 #define HCCS_MAX_RSP_DATA_BYTES (HCCS_PCC_SHARE_MEM_BYTES - \ 196 HCCS_FW_INNER_HEAD_BYTES - \ 197 HCCS_RSP_HEAD_BYTES) 198 #define HCCS_MAX_RSP_DATA_SIZE_MAX (HCCS_MAX_RSP_DATA_BYTES / 4) 199 200 /* 201 * Note: Actual available size of data field also depands on the PCC header 202 * bytes of the specific type. Driver needs to copy the response data in the 203 * communication space based on the real length. 204 */ 205 struct hccs_rsp_desc { 206 struct hccs_fw_inner_head fw_inner_head; /* 8 Bytes */ 207 struct hccs_rsp_head rsp_head; /* 4 Bytes */ 208 u32 data[HCCS_MAX_RSP_DATA_SIZE_MAX]; 209 }; 210 211 #define HCCS_REQ_HEAD_BYTES 4 212 #define HCCS_MAX_REQ_DATA_BYTES (HCCS_PCC_SHARE_MEM_BYTES - \ 213 HCCS_REQ_HEAD_BYTES) 214 #define HCCS_MAX_REQ_DATA_SIZE_MAX (HCCS_MAX_REQ_DATA_BYTES / 4) 215 216 /* 217 * Note: Actual available size of data field also depands on the PCC header 218 * bytes of the specific type. Driver needs to copy the request data to the 219 * communication space based on the real length. 220 */ 221 struct hccs_req_desc { 222 struct hccs_req_head req_head; /* 4 Bytes */ 223 u32 data[HCCS_MAX_REQ_DATA_SIZE_MAX]; 224 }; 225 226 struct hccs_desc { 227 union { 228 struct hccs_req_desc req; 229 struct hccs_rsp_desc rsp; 230 }; 231 }; 232 233 #endif /* __KUNPENG_HCCS_H__ */ 234