1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2024 Intel Corporation 4 */ 5 6 #include <linux/genalloc.h> 7 #include <linux/highmem.h> 8 #include <linux/pm_runtime.h> 9 #include <linux/wait.h> 10 11 #include "ivpu_drv.h" 12 #include "ivpu_gem.h" 13 #include "ivpu_hw.h" 14 #include "ivpu_hw_reg_io.h" 15 #include "ivpu_ipc.h" 16 #include "ivpu_jsm_msg.h" 17 #include "ivpu_pm.h" 18 #include "ivpu_trace.h" 19 20 #define IPC_MAX_RX_MSG 128 21 22 struct ivpu_ipc_tx_buf { 23 struct ivpu_ipc_hdr ipc; 24 struct vpu_jsm_msg jsm; 25 }; 26 27 static void ivpu_ipc_msg_dump(struct ivpu_device *vdev, char *c, 28 struct ivpu_ipc_hdr *ipc_hdr, u32 vpu_addr) 29 { 30 ivpu_dbg(vdev, IPC, 31 "%s: vpu:0x%x (data_addr:0x%08x, data_size:0x%x, channel:0x%x, src_node:0x%x, dst_node:0x%x, status:0x%x)", 32 c, vpu_addr, ipc_hdr->data_addr, ipc_hdr->data_size, ipc_hdr->channel, 33 ipc_hdr->src_node, ipc_hdr->dst_node, ipc_hdr->status); 34 } 35 36 static void ivpu_jsm_msg_dump(struct ivpu_device *vdev, char *c, 37 struct vpu_jsm_msg *jsm_msg, u32 vpu_addr) 38 { 39 u32 *payload = (u32 *)&jsm_msg->payload; 40 41 ivpu_dbg(vdev, JSM, 42 "%s: vpu:0x%08x (type:%s, status:0x%x, id: 0x%x, result: 0x%x, payload:0x%x 0x%x 0x%x 0x%x 0x%x)\n", 43 c, vpu_addr, ivpu_jsm_msg_type_to_str(jsm_msg->type), 44 jsm_msg->status, jsm_msg->request_id, jsm_msg->result, 45 payload[0], payload[1], payload[2], payload[3], payload[4]); 46 } 47 48 static void 49 ivpu_ipc_rx_mark_free(struct ivpu_device *vdev, struct ivpu_ipc_hdr *ipc_hdr, 50 struct vpu_jsm_msg *jsm_msg) 51 { 52 ipc_hdr->status = IVPU_IPC_HDR_FREE; 53 if (jsm_msg) 54 jsm_msg->status = VPU_JSM_MSG_FREE; 55 wmb(); /* Flush WC buffers for message statuses */ 56 } 57 58 static void ivpu_ipc_mem_fini(struct ivpu_device *vdev) 59 { 60 struct ivpu_ipc_info *ipc = vdev->ipc; 61 62 ivpu_bo_free(ipc->mem_rx); 63 ivpu_bo_free(ipc->mem_tx); 64 } 65 66 static int 67 ivpu_ipc_tx_prepare(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 68 struct vpu_jsm_msg *req) 69 { 70 struct ivpu_ipc_info *ipc = vdev->ipc; 71 struct ivpu_ipc_tx_buf *tx_buf; 72 u32 tx_buf_vpu_addr; 73 u32 jsm_vpu_addr; 74 75 tx_buf_vpu_addr = gen_pool_alloc(ipc->mm_tx, sizeof(*tx_buf)); 76 if (!tx_buf_vpu_addr) { 77 ivpu_err_ratelimited(vdev, "Failed to reserve IPC buffer, size %ld\n", 78 sizeof(*tx_buf)); 79 return -ENOMEM; 80 } 81 82 tx_buf = ivpu_to_cpu_addr(ipc->mem_tx, tx_buf_vpu_addr); 83 if (drm_WARN_ON(&vdev->drm, !tx_buf)) { 84 gen_pool_free(ipc->mm_tx, tx_buf_vpu_addr, sizeof(*tx_buf)); 85 return -EIO; 86 } 87 88 jsm_vpu_addr = tx_buf_vpu_addr + offsetof(struct ivpu_ipc_tx_buf, jsm); 89 90 if (tx_buf->ipc.status != IVPU_IPC_HDR_FREE) 91 ivpu_warn_ratelimited(vdev, "IPC message vpu:0x%x not released by firmware\n", 92 tx_buf_vpu_addr); 93 94 if (tx_buf->jsm.status != VPU_JSM_MSG_FREE) 95 ivpu_warn_ratelimited(vdev, "JSM message vpu:0x%x not released by firmware\n", 96 jsm_vpu_addr); 97 98 memset(tx_buf, 0, sizeof(*tx_buf)); 99 tx_buf->ipc.data_addr = jsm_vpu_addr; 100 /* 101 * Firmware expects full JSM message size regardless of the payload size. 102 * Unused fields must be zeroed to allow future extensions of existing 103 * commands without breaking compatibility. 104 */ 105 tx_buf->ipc.data_size = sizeof(*req); 106 tx_buf->ipc.channel = cons->channel; 107 tx_buf->ipc.src_node = 0; 108 tx_buf->ipc.dst_node = 1; 109 tx_buf->ipc.status = IVPU_IPC_HDR_ALLOCATED; 110 tx_buf->jsm.type = req->type; 111 tx_buf->jsm.status = VPU_JSM_MSG_ALLOCATED; 112 tx_buf->jsm.payload = req->payload; 113 114 req->request_id = atomic_inc_return(&ipc->request_id); 115 tx_buf->jsm.request_id = req->request_id; 116 cons->request_id = req->request_id; 117 wmb(); /* Flush WC buffers for IPC, JSM msgs */ 118 119 cons->tx_vpu_addr = tx_buf_vpu_addr; 120 121 ivpu_jsm_msg_dump(vdev, "TX", &tx_buf->jsm, jsm_vpu_addr); 122 ivpu_ipc_msg_dump(vdev, "TX", &tx_buf->ipc, tx_buf_vpu_addr); 123 124 return 0; 125 } 126 127 static void ivpu_ipc_tx_release(struct ivpu_device *vdev, u32 vpu_addr) 128 { 129 struct ivpu_ipc_info *ipc = vdev->ipc; 130 131 if (vpu_addr) 132 gen_pool_free(ipc->mm_tx, vpu_addr, sizeof(struct ivpu_ipc_tx_buf)); 133 } 134 135 static void ivpu_ipc_tx(struct ivpu_device *vdev, u32 vpu_addr) 136 { 137 ivpu_hw_ipc_tx_set(vdev, vpu_addr); 138 } 139 140 static void 141 ivpu_ipc_rx_msg_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 142 struct ivpu_ipc_hdr *ipc_hdr, struct vpu_jsm_msg *jsm_msg) 143 { 144 struct ivpu_ipc_info *ipc = vdev->ipc; 145 struct ivpu_ipc_rx_msg *rx_msg; 146 147 lockdep_assert_held(&ipc->cons_lock); 148 149 rx_msg = kzalloc_obj(*rx_msg, GFP_ATOMIC); 150 if (!rx_msg) { 151 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg); 152 return; 153 } 154 155 atomic_inc(&ipc->rx_msg_count); 156 157 rx_msg->ipc_hdr = ipc_hdr; 158 rx_msg->jsm_msg = jsm_msg; 159 rx_msg->callback = cons->rx_callback; 160 161 if (rx_msg->callback) { 162 list_add_tail(&rx_msg->link, &ipc->cb_msg_list); 163 } else { 164 spin_lock(&cons->rx_lock); 165 list_add_tail(&rx_msg->link, &cons->rx_msg_list); 166 spin_unlock(&cons->rx_lock); 167 wake_up(&cons->rx_msg_wq); 168 } 169 } 170 171 static void 172 ivpu_ipc_rx_msg_del(struct ivpu_device *vdev, struct ivpu_ipc_rx_msg *rx_msg) 173 { 174 list_del(&rx_msg->link); 175 ivpu_ipc_rx_mark_free(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg); 176 atomic_dec(&vdev->ipc->rx_msg_count); 177 kfree(rx_msg); 178 } 179 180 void ivpu_ipc_consumer_add(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 181 u32 channel, ivpu_ipc_rx_callback_t rx_callback) 182 { 183 struct ivpu_ipc_info *ipc = vdev->ipc; 184 185 INIT_LIST_HEAD(&cons->link); 186 cons->channel = channel; 187 cons->tx_vpu_addr = 0; 188 cons->request_id = 0; 189 cons->aborted = false; 190 cons->rx_callback = rx_callback; 191 spin_lock_init(&cons->rx_lock); 192 INIT_LIST_HEAD(&cons->rx_msg_list); 193 init_waitqueue_head(&cons->rx_msg_wq); 194 195 spin_lock_irq(&ipc->cons_lock); 196 list_add_tail(&cons->link, &ipc->cons_list); 197 spin_unlock_irq(&ipc->cons_lock); 198 } 199 200 void ivpu_ipc_consumer_del(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons) 201 { 202 struct ivpu_ipc_info *ipc = vdev->ipc; 203 struct ivpu_ipc_rx_msg *rx_msg, *r; 204 205 spin_lock_irq(&ipc->cons_lock); 206 list_del(&cons->link); 207 spin_unlock_irq(&ipc->cons_lock); 208 209 spin_lock_irq(&cons->rx_lock); 210 list_for_each_entry_safe(rx_msg, r, &cons->rx_msg_list, link) 211 ivpu_ipc_rx_msg_del(vdev, rx_msg); 212 spin_unlock_irq(&cons->rx_lock); 213 214 ivpu_ipc_tx_release(vdev, cons->tx_vpu_addr); 215 } 216 217 int ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, struct vpu_jsm_msg *req) 218 { 219 struct ivpu_ipc_info *ipc = vdev->ipc; 220 int ret; 221 222 mutex_lock(&ipc->lock); 223 224 if (!ipc->on) { 225 ret = -EAGAIN; 226 goto unlock; 227 } 228 229 ret = ivpu_ipc_tx_prepare(vdev, cons, req); 230 if (ret) 231 goto unlock; 232 233 ivpu_ipc_tx(vdev, cons->tx_vpu_addr); 234 trace_jsm("[tx]", req); 235 236 unlock: 237 mutex_unlock(&ipc->lock); 238 return ret; 239 } 240 241 static bool ivpu_ipc_rx_need_wakeup(struct ivpu_ipc_consumer *cons) 242 { 243 bool ret; 244 245 spin_lock_irq(&cons->rx_lock); 246 ret = !list_empty(&cons->rx_msg_list) || cons->aborted; 247 spin_unlock_irq(&cons->rx_lock); 248 249 return ret; 250 } 251 252 int ivpu_ipc_receive(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 253 struct ivpu_ipc_hdr *ipc_buf, 254 struct vpu_jsm_msg *jsm_msg, unsigned long timeout_ms) 255 { 256 struct ivpu_ipc_rx_msg *rx_msg; 257 int wait_ret, ret = 0; 258 259 if (drm_WARN_ONCE(&vdev->drm, cons->rx_callback, "Consumer works only in async mode\n")) 260 return -EINVAL; 261 262 wait_ret = wait_event_timeout(cons->rx_msg_wq, 263 ivpu_ipc_rx_need_wakeup(cons), 264 msecs_to_jiffies(timeout_ms)); 265 266 if (wait_ret == 0) 267 return -ETIMEDOUT; 268 269 spin_lock_irq(&cons->rx_lock); 270 if (cons->aborted) { 271 spin_unlock_irq(&cons->rx_lock); 272 return -ECANCELED; 273 } 274 rx_msg = list_first_entry_or_null(&cons->rx_msg_list, struct ivpu_ipc_rx_msg, link); 275 if (!rx_msg) { 276 spin_unlock_irq(&cons->rx_lock); 277 return -EAGAIN; 278 } 279 280 if (ipc_buf) 281 memcpy(ipc_buf, rx_msg->ipc_hdr, sizeof(*ipc_buf)); 282 if (rx_msg->jsm_msg) { 283 u32 size = min(rx_msg->ipc_hdr->data_size, sizeof(*jsm_msg)); 284 285 if (rx_msg->jsm_msg->result != VPU_JSM_STATUS_SUCCESS) { 286 ivpu_err(vdev, "IPC resp result error: %d\n", rx_msg->jsm_msg->result); 287 ret = -EBADMSG; 288 } 289 290 if (jsm_msg) 291 memcpy(jsm_msg, rx_msg->jsm_msg, size); 292 trace_jsm("[rx]", rx_msg->jsm_msg); 293 } 294 295 ivpu_ipc_rx_msg_del(vdev, rx_msg); 296 spin_unlock_irq(&cons->rx_lock); 297 return ret; 298 } 299 300 int 301 ivpu_ipc_send_receive_internal(struct ivpu_device *vdev, struct vpu_jsm_msg *req, 302 enum vpu_ipc_msg_type expected_resp_type, 303 struct vpu_jsm_msg *resp, u32 channel, unsigned long timeout_ms) 304 { 305 struct ivpu_ipc_consumer cons; 306 int ret; 307 308 drm_WARN_ON(&vdev->drm, pm_runtime_status_suspended(vdev->drm.dev) && 309 pm_runtime_enabled(vdev->drm.dev)); 310 311 ivpu_ipc_consumer_add(vdev, &cons, channel, NULL); 312 313 ret = ivpu_ipc_send(vdev, &cons, req); 314 if (ret) { 315 ivpu_warn_ratelimited(vdev, "IPC send failed: %d\n", ret); 316 goto consumer_del; 317 } 318 319 ret = ivpu_ipc_receive(vdev, &cons, NULL, resp, timeout_ms); 320 if (ret) { 321 ivpu_warn_ratelimited(vdev, "IPC receive failed: type %s, ret %d\n", 322 ivpu_jsm_msg_type_to_str(req->type), ret); 323 goto consumer_del; 324 } 325 326 if (resp->type != expected_resp_type) { 327 ivpu_warn_ratelimited(vdev, "Invalid JSM response type: 0x%x\n", resp->type); 328 ret = -EBADE; 329 } 330 331 consumer_del: 332 ivpu_ipc_consumer_del(vdev, &cons); 333 return ret; 334 } 335 336 int ivpu_ipc_send_receive(struct ivpu_device *vdev, struct vpu_jsm_msg *req, 337 enum vpu_ipc_msg_type expected_resp, struct vpu_jsm_msg *resp, 338 u32 channel, unsigned long timeout_ms) 339 { 340 struct vpu_jsm_msg hb_req = { .type = VPU_JSM_MSG_QUERY_ENGINE_HB }; 341 struct vpu_jsm_msg hb_resp; 342 int ret, hb_ret; 343 344 ret = ivpu_rpm_get(vdev); 345 if (ret < 0) 346 return ret; 347 348 ret = ivpu_ipc_send_receive_internal(vdev, req, expected_resp, resp, channel, timeout_ms); 349 if (ret != -ETIMEDOUT) 350 goto rpm_put; 351 352 hb_ret = ivpu_ipc_send_receive_internal(vdev, &hb_req, VPU_JSM_MSG_QUERY_ENGINE_HB_DONE, 353 &hb_resp, VPU_IPC_CHAN_ASYNC_CMD, 354 vdev->timeout.jsm); 355 if (hb_ret == -ETIMEDOUT) 356 ivpu_pm_trigger_recovery(vdev, "IPC timeout"); 357 358 rpm_put: 359 ivpu_rpm_put(vdev); 360 return ret; 361 } 362 363 int ivpu_ipc_send_and_wait(struct ivpu_device *vdev, struct vpu_jsm_msg *req, 364 u32 channel, unsigned long timeout_ms) 365 { 366 struct ivpu_ipc_consumer cons; 367 int ret; 368 369 ret = ivpu_rpm_get(vdev); 370 if (ret < 0) 371 return ret; 372 373 ivpu_ipc_consumer_add(vdev, &cons, channel, NULL); 374 375 ret = ivpu_ipc_send(vdev, &cons, req); 376 if (ret) { 377 ivpu_warn_ratelimited(vdev, "IPC send failed: %d\n", ret); 378 goto consumer_del; 379 } 380 381 msleep(timeout_ms); 382 383 consumer_del: 384 ivpu_ipc_consumer_del(vdev, &cons); 385 ivpu_rpm_put(vdev); 386 return ret; 387 } 388 389 static bool 390 ivpu_ipc_match_consumer(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, 391 struct ivpu_ipc_hdr *ipc_hdr, struct vpu_jsm_msg *jsm_msg) 392 { 393 if (cons->channel != ipc_hdr->channel) 394 return false; 395 396 if (!jsm_msg || jsm_msg->request_id == cons->request_id) 397 return true; 398 399 return false; 400 } 401 402 void ivpu_ipc_irq_handler(struct ivpu_device *vdev) 403 { 404 struct ivpu_ipc_info *ipc = vdev->ipc; 405 struct ivpu_ipc_consumer *cons; 406 struct ivpu_ipc_hdr *ipc_hdr; 407 struct vpu_jsm_msg *jsm_msg; 408 unsigned long flags; 409 bool dispatched; 410 u32 vpu_addr; 411 412 /* 413 * Driver needs to purge all messages from IPC FIFO to clear IPC interrupt. 414 * Without purge IPC FIFO to 0 next IPC interrupts won't be generated. 415 */ 416 while (ivpu_hw_ipc_rx_count_get(vdev)) { 417 vpu_addr = ivpu_hw_ipc_rx_addr_get(vdev); 418 if (vpu_addr == REG_IO_ERROR) { 419 ivpu_err_ratelimited(vdev, "Failed to read IPC rx addr register\n"); 420 return; 421 } 422 423 ipc_hdr = ivpu_to_cpu_addr(ipc->mem_rx, vpu_addr); 424 if (!ipc_hdr) { 425 ivpu_warn_ratelimited(vdev, "IPC msg 0x%x out of range\n", vpu_addr); 426 continue; 427 } 428 ivpu_ipc_msg_dump(vdev, "RX", ipc_hdr, vpu_addr); 429 430 jsm_msg = NULL; 431 if (ipc_hdr->channel != IVPU_IPC_CHAN_BOOT_MSG) { 432 jsm_msg = ivpu_to_cpu_addr(ipc->mem_rx, ipc_hdr->data_addr); 433 if (!jsm_msg) { 434 ivpu_warn_ratelimited(vdev, "JSM msg 0x%x out of range\n", 435 ipc_hdr->data_addr); 436 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, NULL); 437 continue; 438 } 439 ivpu_jsm_msg_dump(vdev, "RX", jsm_msg, ipc_hdr->data_addr); 440 } 441 442 if (atomic_read(&ipc->rx_msg_count) > IPC_MAX_RX_MSG) { 443 ivpu_warn_ratelimited(vdev, "IPC RX msg dropped, msg count %d\n", 444 IPC_MAX_RX_MSG); 445 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg); 446 continue; 447 } 448 449 dispatched = false; 450 spin_lock_irqsave(&ipc->cons_lock, flags); 451 list_for_each_entry(cons, &ipc->cons_list, link) { 452 if (ivpu_ipc_match_consumer(vdev, cons, ipc_hdr, jsm_msg)) { 453 ivpu_ipc_rx_msg_add(vdev, cons, ipc_hdr, jsm_msg); 454 dispatched = true; 455 break; 456 } 457 } 458 spin_unlock_irqrestore(&ipc->cons_lock, flags); 459 460 if (!dispatched) { 461 ivpu_dbg(vdev, IPC, "IPC RX msg 0x%x dropped (no consumer)\n", vpu_addr); 462 ivpu_ipc_rx_mark_free(vdev, ipc_hdr, jsm_msg); 463 } 464 } 465 466 queue_work(system_percpu_wq, &vdev->irq_ipc_work); 467 } 468 469 void ivpu_ipc_irq_work_fn(struct work_struct *work) 470 { 471 struct ivpu_device *vdev = container_of(work, struct ivpu_device, irq_ipc_work); 472 struct ivpu_ipc_info *ipc = vdev->ipc; 473 struct ivpu_ipc_rx_msg *rx_msg, *r; 474 struct list_head cb_msg_list; 475 476 INIT_LIST_HEAD(&cb_msg_list); 477 478 spin_lock_irq(&ipc->cons_lock); 479 list_splice_tail_init(&ipc->cb_msg_list, &cb_msg_list); 480 spin_unlock_irq(&ipc->cons_lock); 481 482 list_for_each_entry_safe(rx_msg, r, &cb_msg_list, link) { 483 rx_msg->callback(vdev, rx_msg->ipc_hdr, rx_msg->jsm_msg); 484 ivpu_ipc_rx_msg_del(vdev, rx_msg); 485 } 486 } 487 488 int ivpu_ipc_init(struct ivpu_device *vdev) 489 { 490 struct ivpu_ipc_info *ipc = vdev->ipc; 491 int ret; 492 493 ipc->mem_tx = ivpu_bo_create_global(vdev, SZ_16K, DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE); 494 if (!ipc->mem_tx) { 495 ivpu_err(vdev, "Failed to allocate mem_tx\n"); 496 return -ENOMEM; 497 } 498 499 ipc->mem_rx = ivpu_bo_create_global(vdev, SZ_16K, DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE); 500 if (!ipc->mem_rx) { 501 ivpu_err(vdev, "Failed to allocate mem_rx\n"); 502 ret = -ENOMEM; 503 goto err_free_tx; 504 } 505 506 ipc->mm_tx = devm_gen_pool_create(vdev->drm.dev, __ffs(IVPU_IPC_ALIGNMENT), 507 -1, "TX_IPC_JSM"); 508 if (IS_ERR(ipc->mm_tx)) { 509 ret = PTR_ERR(ipc->mm_tx); 510 ivpu_err(vdev, "Failed to create gen pool, %pe\n", ipc->mm_tx); 511 goto err_free_rx; 512 } 513 514 ret = gen_pool_add(ipc->mm_tx, ipc->mem_tx->vpu_addr, ivpu_bo_size(ipc->mem_tx), -1); 515 if (ret) { 516 ivpu_err(vdev, "gen_pool_add failed, ret %d\n", ret); 517 goto err_free_rx; 518 } 519 520 spin_lock_init(&ipc->cons_lock); 521 INIT_LIST_HEAD(&ipc->cons_list); 522 INIT_LIST_HEAD(&ipc->cb_msg_list); 523 ret = drmm_mutex_init(&vdev->drm, &ipc->lock); 524 if (ret) { 525 ivpu_err(vdev, "Failed to initialize ipc->lock, ret %d\n", ret); 526 goto err_free_rx; 527 } 528 ivpu_ipc_reset(vdev); 529 return 0; 530 531 err_free_rx: 532 ivpu_bo_free(ipc->mem_rx); 533 err_free_tx: 534 ivpu_bo_free(ipc->mem_tx); 535 return ret; 536 } 537 538 void ivpu_ipc_fini(struct ivpu_device *vdev) 539 { 540 struct ivpu_ipc_info *ipc = vdev->ipc; 541 542 drm_WARN_ON(&vdev->drm, !list_empty(&ipc->cons_list)); 543 drm_WARN_ON(&vdev->drm, !list_empty(&ipc->cb_msg_list)); 544 drm_WARN_ON(&vdev->drm, atomic_read(&ipc->rx_msg_count) > 0); 545 546 ivpu_ipc_mem_fini(vdev); 547 } 548 549 void ivpu_ipc_enable(struct ivpu_device *vdev) 550 { 551 struct ivpu_ipc_info *ipc = vdev->ipc; 552 553 mutex_lock(&ipc->lock); 554 ipc->on = true; 555 mutex_unlock(&ipc->lock); 556 } 557 558 void ivpu_ipc_disable(struct ivpu_device *vdev) 559 { 560 struct ivpu_ipc_info *ipc = vdev->ipc; 561 struct ivpu_ipc_consumer *cons, *c; 562 struct ivpu_ipc_rx_msg *rx_msg, *r; 563 564 drm_WARN_ON(&vdev->drm, !list_empty(&ipc->cb_msg_list)); 565 566 mutex_lock(&ipc->lock); 567 ipc->on = false; 568 mutex_unlock(&ipc->lock); 569 570 spin_lock_irq(&ipc->cons_lock); 571 list_for_each_entry_safe(cons, c, &ipc->cons_list, link) { 572 spin_lock(&cons->rx_lock); 573 if (!cons->rx_callback) 574 cons->aborted = true; 575 list_for_each_entry_safe(rx_msg, r, &cons->rx_msg_list, link) 576 ivpu_ipc_rx_msg_del(vdev, rx_msg); 577 spin_unlock(&cons->rx_lock); 578 wake_up(&cons->rx_msg_wq); 579 } 580 spin_unlock_irq(&ipc->cons_lock); 581 582 drm_WARN_ON(&vdev->drm, atomic_read(&ipc->rx_msg_count) > 0); 583 } 584 585 void ivpu_ipc_reset(struct ivpu_device *vdev) 586 { 587 struct ivpu_ipc_info *ipc = vdev->ipc; 588 589 mutex_lock(&ipc->lock); 590 drm_WARN_ON(&vdev->drm, ipc->on); 591 592 memset(ivpu_bo_vaddr(ipc->mem_tx), 0, ivpu_bo_size(ipc->mem_tx)); 593 memset(ivpu_bo_vaddr(ipc->mem_rx), 0, ivpu_bo_size(ipc->mem_rx)); 594 wmb(); /* Flush WC buffers for TX and RX rings */ 595 596 mutex_unlock(&ipc->lock); 597 } 598