1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022-2023 Intel Corporation 4 */ 5 6 #ifndef _XE_DEVICE_TYPES_H_ 7 #define _XE_DEVICE_TYPES_H_ 8 9 #include <linux/pci.h> 10 11 #include <drm/drm_device.h> 12 #include <drm/drm_file.h> 13 #include <drm/ttm/ttm_device.h> 14 15 #include "xe_devcoredump_types.h" 16 #include "xe_heci_gsc.h" 17 #include "xe_lmtt_types.h" 18 #include "xe_memirq_types.h" 19 #include "xe_oa.h" 20 #include "xe_platform_types.h" 21 #include "xe_pt_types.h" 22 #include "xe_sriov_types.h" 23 #include "xe_step_types.h" 24 25 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) 26 #define TEST_VM_OPS_ERROR 27 #endif 28 29 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) 30 #include "soc/intel_pch.h" 31 #include "intel_display_core.h" 32 #include "intel_display_device.h" 33 #endif 34 35 struct xe_ggtt; 36 struct xe_pat_ops; 37 38 #define XE_BO_INVALID_OFFSET LONG_MAX 39 40 #define GRAPHICS_VER(xe) ((xe)->info.graphics_verx100 / 100) 41 #define MEDIA_VER(xe) ((xe)->info.media_verx100 / 100) 42 #define GRAPHICS_VERx100(xe) ((xe)->info.graphics_verx100) 43 #define MEDIA_VERx100(xe) ((xe)->info.media_verx100) 44 #define IS_DGFX(xe) ((xe)->info.is_dgfx) 45 #define HAS_HECI_GSCFI(xe) ((xe)->info.has_heci_gscfi) 46 #define HAS_HECI_CSCFI(xe) ((xe)->info.has_heci_cscfi) 47 48 #define XE_VRAM_FLAGS_NEED64K BIT(0) 49 50 #define XE_GT0 0 51 #define XE_GT1 1 52 #define XE_MAX_TILES_PER_DEVICE (XE_GT1 + 1) 53 54 #define XE_MAX_ASID (BIT(20)) 55 56 #define IS_PLATFORM_STEP(_xe, _platform, min_step, max_step) \ 57 ((_xe)->info.platform == (_platform) && \ 58 (_xe)->info.step.graphics >= (min_step) && \ 59 (_xe)->info.step.graphics < (max_step)) 60 #define IS_SUBPLATFORM_STEP(_xe, _platform, sub, min_step, max_step) \ 61 ((_xe)->info.platform == (_platform) && \ 62 (_xe)->info.subplatform == (sub) && \ 63 (_xe)->info.step.graphics >= (min_step) && \ 64 (_xe)->info.step.graphics < (max_step)) 65 66 #define tile_to_xe(tile__) \ 67 _Generic(tile__, \ 68 const struct xe_tile * : (const struct xe_device *)((tile__)->xe), \ 69 struct xe_tile * : (tile__)->xe) 70 71 /** 72 * struct xe_mem_region - memory region structure 73 * This is used to describe a memory region in xe 74 * device, such as HBM memory or CXL extension memory. 75 */ 76 struct xe_mem_region { 77 /** @io_start: IO start address of this VRAM instance */ 78 resource_size_t io_start; 79 /** 80 * @io_size: IO size of this VRAM instance 81 * 82 * This represents how much of this VRAM we can access 83 * via the CPU through the VRAM BAR. This can be smaller 84 * than @usable_size, in which case only part of VRAM is CPU 85 * accessible (typically the first 256M). This 86 * configuration is known as small-bar. 87 */ 88 resource_size_t io_size; 89 /** @dpa_base: This memory regions's DPA (device physical address) base */ 90 resource_size_t dpa_base; 91 /** 92 * @usable_size: usable size of VRAM 93 * 94 * Usable size of VRAM excluding reserved portions 95 * (e.g stolen mem) 96 */ 97 resource_size_t usable_size; 98 /** 99 * @actual_physical_size: Actual VRAM size 100 * 101 * Actual VRAM size including reserved portions 102 * (e.g stolen mem) 103 */ 104 resource_size_t actual_physical_size; 105 /** @mapping: pointer to VRAM mappable space */ 106 void __iomem *mapping; 107 }; 108 109 /** 110 * struct xe_mmio - register mmio structure 111 * 112 * Represents an MMIO region that the CPU may use to access registers. A 113 * region may share its IO map with other regions (e.g., all GTs within a 114 * tile share the same map with their parent tile, but represent different 115 * subregions of the overall IO space). 116 */ 117 struct xe_mmio { 118 /** @tile: Backpointer to tile, used for tracing */ 119 struct xe_tile *tile; 120 121 /** @regs: Map used to access registers. */ 122 void __iomem *regs; 123 124 /** 125 * @sriov_vf_gt: Backpointer to GT. 126 * 127 * This pointer is only set for GT MMIO regions and only when running 128 * as an SRIOV VF structure 129 */ 130 struct xe_gt *sriov_vf_gt; 131 132 /** 133 * @regs_size: Length of the register region within the map. 134 * 135 * The size of the iomap set in *regs is generally larger than the 136 * register mmio space since it includes unused regions and/or 137 * non-register regions such as the GGTT PTEs. 138 */ 139 size_t regs_size; 140 141 /** @adj_limit: adjust MMIO address if address is below this value */ 142 u32 adj_limit; 143 144 /** @adj_offset: offset to add to MMIO address when adjusting */ 145 u32 adj_offset; 146 }; 147 148 /** 149 * struct xe_tile - hardware tile structure 150 * 151 * From a driver perspective, a "tile" is effectively a complete GPU, containing 152 * an SGunit, 1-2 GTs, and (for discrete platforms) VRAM. 153 * 154 * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI 155 * device and designate one "root" tile as being responsible for external PCI 156 * communication. PCI BAR0 exposes the GGTT and MMIO register space for each 157 * tile in a stacked layout, and PCI BAR2 exposes the local memory associated 158 * with each tile similarly. Device-wide interrupts can be enabled/disabled 159 * at the root tile, and the MSTR_TILE_INTR register will report which tiles 160 * have interrupts that need servicing. 161 */ 162 struct xe_tile { 163 /** @xe: Backpointer to tile's PCI device */ 164 struct xe_device *xe; 165 166 /** @id: ID of the tile */ 167 u8 id; 168 169 /** 170 * @primary_gt: Primary GT 171 */ 172 struct xe_gt *primary_gt; 173 174 /** 175 * @media_gt: Media GT 176 * 177 * Only present on devices with media version >= 13. 178 */ 179 struct xe_gt *media_gt; 180 181 /** 182 * @mmio: MMIO info for a tile. 183 * 184 * Each tile has its own 16MB space in BAR0, laid out as: 185 * * 0-4MB: registers 186 * * 4MB-8MB: reserved 187 * * 8MB-16MB: global GTT 188 */ 189 struct xe_mmio mmio; 190 191 /** 192 * @mmio_ext: MMIO-extension info for a tile. 193 * 194 * Each tile has its own additional 256MB (28-bit) MMIO-extension space. 195 */ 196 struct xe_mmio mmio_ext; 197 198 /** @mem: memory management info for tile */ 199 struct { 200 /** 201 * @mem.vram: VRAM info for tile. 202 * 203 * Although VRAM is associated with a specific tile, it can 204 * still be accessed by all tiles' GTs. 205 */ 206 struct xe_mem_region vram; 207 208 /** @mem.vram_mgr: VRAM TTM manager */ 209 struct xe_ttm_vram_mgr *vram_mgr; 210 211 /** @mem.ggtt: Global graphics translation table */ 212 struct xe_ggtt *ggtt; 213 214 /** 215 * @mem.kernel_bb_pool: Pool from which batchbuffers are allocated. 216 * 217 * Media GT shares a pool with its primary GT. 218 */ 219 struct xe_sa_manager *kernel_bb_pool; 220 } mem; 221 222 /** @sriov: tile level virtualization data */ 223 union { 224 struct { 225 /** @sriov.pf.lmtt: Local Memory Translation Table. */ 226 struct xe_lmtt lmtt; 227 } pf; 228 struct { 229 /** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */ 230 struct xe_ggtt_node *ggtt_balloon[2]; 231 } vf; 232 } sriov; 233 234 /** @memirq: Memory Based Interrupts. */ 235 struct xe_memirq memirq; 236 237 /** @pcode: tile's PCODE */ 238 struct { 239 /** @pcode.lock: protecting tile's PCODE mailbox data */ 240 struct mutex lock; 241 } pcode; 242 243 /** @migrate: Migration helper for vram blits and clearing */ 244 struct xe_migrate *migrate; 245 246 /** @sysfs: sysfs' kobj used by xe_tile_sysfs */ 247 struct kobject *sysfs; 248 }; 249 250 /** 251 * struct xe_device - Top level struct of XE device 252 */ 253 struct xe_device { 254 /** @drm: drm device */ 255 struct drm_device drm; 256 257 /** @devcoredump: device coredump */ 258 struct xe_devcoredump devcoredump; 259 260 /** @info: device info */ 261 struct intel_device_info { 262 /** @info.platform_name: platform name */ 263 const char *platform_name; 264 /** @info.graphics_name: graphics IP name */ 265 const char *graphics_name; 266 /** @info.media_name: media IP name */ 267 const char *media_name; 268 /** @info.tile_mmio_ext_size: size of MMIO extension space, per-tile */ 269 u32 tile_mmio_ext_size; 270 /** @info.graphics_verx100: graphics IP version */ 271 u32 graphics_verx100; 272 /** @info.media_verx100: media IP version */ 273 u32 media_verx100; 274 /** @info.mem_region_mask: mask of valid memory regions */ 275 u32 mem_region_mask; 276 /** @info.platform: XE platform enum */ 277 enum xe_platform platform; 278 /** @info.subplatform: XE subplatform enum */ 279 enum xe_subplatform subplatform; 280 /** @info.devid: device ID */ 281 u16 devid; 282 /** @info.revid: device revision */ 283 u8 revid; 284 /** @info.step: stepping information for each IP */ 285 struct xe_step_info step; 286 /** @info.dma_mask_size: DMA address bits */ 287 u8 dma_mask_size; 288 /** @info.vram_flags: Vram flags */ 289 u8 vram_flags; 290 /** @info.tile_count: Number of tiles */ 291 u8 tile_count; 292 /** @info.gt_count: Total number of GTs for entire device */ 293 u8 gt_count; 294 /** @info.vm_max_level: Max VM level */ 295 u8 vm_max_level; 296 /** @info.va_bits: Maximum bits of a virtual address */ 297 u8 va_bits; 298 299 /** @info.is_dgfx: is discrete device */ 300 u8 is_dgfx:1; 301 /** @info.has_asid: Has address space ID */ 302 u8 has_asid:1; 303 /** @info.force_execlist: Forced execlist submission */ 304 u8 force_execlist:1; 305 /** @info.has_flat_ccs: Whether flat CCS metadata is used */ 306 u8 has_flat_ccs:1; 307 /** @info.has_llc: Device has a shared CPU+GPU last level cache */ 308 u8 has_llc:1; 309 /** @info.has_mmio_ext: Device has extra MMIO address range */ 310 u8 has_mmio_ext:1; 311 /** @info.has_range_tlb_invalidation: Has range based TLB invalidations */ 312 u8 has_range_tlb_invalidation:1; 313 /** @info.has_sriov: Supports SR-IOV */ 314 u8 has_sriov:1; 315 /** @info.has_usm: Device has unified shared memory support */ 316 u8 has_usm:1; 317 /** 318 * @info.probe_display: Probe display hardware. If set to 319 * false, the driver will behave as if there is no display 320 * hardware present and will not try to read/write to it in any 321 * way. The display hardware, if it exists, will not be 322 * exposed to userspace and will be left untouched in whatever 323 * state the firmware or bootloader left it in. 324 */ 325 u8 probe_display:1; 326 /** @info.skip_mtcfg: skip Multi-Tile configuration from MTCFG register */ 327 u8 skip_mtcfg:1; 328 /** @info.skip_pcode: skip access to PCODE uC */ 329 u8 skip_pcode:1; 330 /** @info.has_heci_gscfi: device has heci gscfi */ 331 u8 has_heci_gscfi:1; 332 /** @info.has_heci_cscfi: device has heci cscfi */ 333 u8 has_heci_cscfi:1; 334 /** @info.skip_guc_pc: Skip GuC based PM feature init */ 335 u8 skip_guc_pc:1; 336 /** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */ 337 u8 has_atomic_enable_pte_bit:1; 338 /** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */ 339 u8 has_device_atomics_on_smem:1; 340 } info; 341 342 /** @irq: device interrupt state */ 343 struct { 344 /** @irq.lock: lock for processing irq's on this device */ 345 spinlock_t lock; 346 347 /** @irq.enabled: interrupts enabled on this device */ 348 bool enabled; 349 } irq; 350 351 /** @ttm: ttm device */ 352 struct ttm_device ttm; 353 354 /** @mmio: mmio info for device */ 355 struct { 356 /** @mmio.size: size of MMIO space for device */ 357 size_t size; 358 /** @mmio.regs: pointer to MMIO space for device */ 359 void __iomem *regs; 360 } mmio; 361 362 /** @mem: memory info for device */ 363 struct { 364 /** @mem.vram: VRAM info for device */ 365 struct xe_mem_region vram; 366 /** @mem.sys_mgr: system TTM manager */ 367 struct ttm_resource_manager sys_mgr; 368 } mem; 369 370 /** @sriov: device level virtualization data */ 371 struct { 372 /** @sriov.__mode: SR-IOV mode (Don't access directly!) */ 373 enum xe_sriov_mode __mode; 374 375 /** @sriov.pf: PF specific data */ 376 struct xe_device_pf pf; 377 378 /** @sriov.wq: workqueue used by the virtualization workers */ 379 struct workqueue_struct *wq; 380 } sriov; 381 382 /** @usm: unified memory state */ 383 struct { 384 /** @usm.asid: convert a ASID to VM */ 385 struct xarray asid_to_vm; 386 /** @usm.next_asid: next ASID, used to cyclical alloc asids */ 387 u32 next_asid; 388 /** @usm.lock: protects UM state */ 389 struct rw_semaphore lock; 390 } usm; 391 392 /** @pinned: pinned BO state */ 393 struct { 394 /** @pinned.lock: protected pinned BO list state */ 395 spinlock_t lock; 396 /** @pinned.kernel_bo_present: pinned kernel BO that are present */ 397 struct list_head kernel_bo_present; 398 /** @pinned.evicted: pinned BO that have been evicted */ 399 struct list_head evicted; 400 /** @pinned.external_vram: pinned external BO in vram*/ 401 struct list_head external_vram; 402 } pinned; 403 404 /** @ufence_wq: user fence wait queue */ 405 wait_queue_head_t ufence_wq; 406 407 /** @preempt_fence_wq: used to serialize preempt fences */ 408 struct workqueue_struct *preempt_fence_wq; 409 410 /** @ordered_wq: used to serialize compute mode resume */ 411 struct workqueue_struct *ordered_wq; 412 413 /** @unordered_wq: used to serialize unordered work, mostly display */ 414 struct workqueue_struct *unordered_wq; 415 416 /** @destroy_wq: used to serialize user destroy work, like queue */ 417 struct workqueue_struct *destroy_wq; 418 419 /** @tiles: device tiles */ 420 struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE]; 421 422 /** 423 * @mem_access: keep track of memory access in the device, possibly 424 * triggering additional actions when they occur. 425 */ 426 struct { 427 /** 428 * @mem_access.vram_userfault: Encapsulate vram_userfault 429 * related stuff 430 */ 431 struct { 432 /** 433 * @mem_access.vram_userfault.lock: Protects access to 434 * @vram_usefault.list Using mutex instead of spinlock 435 * as lock is applied to entire list operation which 436 * may sleep 437 */ 438 struct mutex lock; 439 440 /** 441 * @mem_access.vram_userfault.list: Keep list of userfaulted 442 * vram bo, which require to release their mmap mappings 443 * at runtime suspend path 444 */ 445 struct list_head list; 446 } vram_userfault; 447 } mem_access; 448 449 /** 450 * @pat: Encapsulate PAT related stuff 451 */ 452 struct { 453 /** @pat.ops: Internal operations to abstract platforms */ 454 const struct xe_pat_ops *ops; 455 /** @pat.table: PAT table to program in the HW */ 456 const struct xe_pat_table_entry *table; 457 /** @pat.n_entries: Number of PAT entries */ 458 int n_entries; 459 u32 idx[__XE_CACHE_LEVEL_COUNT]; 460 } pat; 461 462 /** @d3cold: Encapsulate d3cold related stuff */ 463 struct { 464 /** @d3cold.capable: Indicates if root port is d3cold capable */ 465 bool capable; 466 467 /** @d3cold.allowed: Indicates if d3cold is a valid device state */ 468 bool allowed; 469 470 /** 471 * @d3cold.vram_threshold: 472 * 473 * This represents the permissible threshold(in megabytes) 474 * for vram save/restore. d3cold will be disallowed, 475 * when vram_usages is above or equals the threshold value 476 * to avoid the vram save/restore latency. 477 * Default threshold value is 300mb. 478 */ 479 u32 vram_threshold; 480 /** @d3cold.lock: protect vram_threshold */ 481 struct mutex lock; 482 } d3cold; 483 484 /** 485 * @pm_callback_task: Track the active task that is running in either 486 * the runtime_suspend or runtime_resume callbacks. 487 */ 488 struct task_struct *pm_callback_task; 489 490 /** @hwmon: hwmon subsystem integration */ 491 struct xe_hwmon *hwmon; 492 493 /** @heci_gsc: graphics security controller */ 494 struct xe_heci_gsc heci_gsc; 495 496 /** @oa: oa observation subsystem */ 497 struct xe_oa oa; 498 499 /** @needs_flr_on_fini: requests function-reset on fini */ 500 bool needs_flr_on_fini; 501 502 /** @wedged: Struct to control Wedged States and mode */ 503 struct { 504 /** @wedged.flag: Xe device faced a critical error and is now blocked. */ 505 atomic_t flag; 506 /** @wedged.mode: Mode controlled by kernel parameter and debugfs */ 507 int mode; 508 } wedged; 509 510 #ifdef TEST_VM_OPS_ERROR 511 /** 512 * @vm_inject_error_position: inject errors at different places in VM 513 * bind IOCTL based on this value 514 */ 515 u8 vm_inject_error_position; 516 #endif 517 518 /* private: */ 519 520 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) 521 /* 522 * Any fields below this point are the ones used by display. 523 * They are temporarily added here so xe_device can be desguised as 524 * drm_i915_private during build. After cleanup these should go away, 525 * migrating to the right sub-structs 526 */ 527 struct intel_display display; 528 enum intel_pch pch_type; 529 u16 pch_id; 530 531 struct dram_info { 532 bool wm_lv_0_adjust_needed; 533 u8 num_channels; 534 bool symmetric_memory; 535 enum intel_dram_type { 536 INTEL_DRAM_UNKNOWN, 537 INTEL_DRAM_DDR3, 538 INTEL_DRAM_DDR4, 539 INTEL_DRAM_LPDDR3, 540 INTEL_DRAM_LPDDR4, 541 INTEL_DRAM_DDR5, 542 INTEL_DRAM_LPDDR5, 543 INTEL_DRAM_GDDR, 544 } type; 545 u8 num_qgv_points; 546 u8 num_psf_gv_points; 547 } dram_info; 548 549 /* 550 * edram size in MB. 551 * Cannot be determined by PCIID. You must always read a register. 552 */ 553 u32 edram_size_mb; 554 555 /* To shut up runtime pm macros.. */ 556 struct xe_runtime_pm {} runtime_pm; 557 558 /* only to allow build, not used functionally */ 559 u32 irq_mask; 560 561 struct intel_uncore { 562 spinlock_t lock; 563 } uncore; 564 565 /* only to allow build, not used functionally */ 566 struct { 567 unsigned int hpll_freq; 568 unsigned int czclk_freq; 569 unsigned int fsb_freq, mem_freq, is_ddr3; 570 }; 571 572 void *pxp; 573 #endif 574 }; 575 576 /** 577 * struct xe_file - file handle for XE driver 578 */ 579 struct xe_file { 580 /** @xe: xe DEVICE **/ 581 struct xe_device *xe; 582 583 /** @drm: base DRM file */ 584 struct drm_file *drm; 585 586 /** @vm: VM state for file */ 587 struct { 588 /** @vm.xe: xarray to store VMs */ 589 struct xarray xa; 590 /** 591 * @vm.lock: Protects VM lookup + reference and removal a from 592 * file xarray. Not an intended to be an outer lock which does 593 * thing while being held. 594 */ 595 struct mutex lock; 596 } vm; 597 598 /** @exec_queue: Submission exec queue state for file */ 599 struct { 600 /** @exec_queue.xa: xarray to store exece queues */ 601 struct xarray xa; 602 /** 603 * @exec_queue.lock: Protects exec queue lookup + reference and 604 * removal a frommfile xarray. Not an intended to be an outer 605 * lock which does thing while being held. 606 */ 607 struct mutex lock; 608 } exec_queue; 609 610 /** @run_ticks: hw engine class run time in ticks for this drm client */ 611 u64 run_ticks[XE_ENGINE_CLASS_MAX]; 612 613 /** @client: drm client */ 614 struct xe_drm_client *client; 615 616 /** 617 * @process_name: process name for file handle, used to safely output 618 * during error situations where xe file can outlive process 619 */ 620 char *process_name; 621 622 /** 623 * @pid: pid for file handle, used to safely output uring error 624 * situations where xe file can outlive process 625 */ 626 pid_t pid; 627 628 /** @refcount: ref count of this xe file */ 629 struct kref refcount; 630 }; 631 632 #endif 633