1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dwc3-pci.c - PCI Specific glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/dmi.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/slab.h>
15 #include <linux/pci.h>
16 #include <linux/workqueue.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/platform_device.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/gpio/machine.h>
21 #include <linux/acpi.h>
22 #include <linux/delay.h>
23
24 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
25 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
26 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
27 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
28 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
29 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
30 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
31 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
32 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
33 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
34 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
35 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
36 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
37 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
38 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
39 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
40 #define PCI_DEVICE_ID_INTEL_EHL 0x4b7e
41 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
42 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
43 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee
44 #define PCI_DEVICE_ID_INTEL_WCL 0x4d7e
45 #define PCI_DEVICE_ID_INTEL_ADL 0x460e
46 #define PCI_DEVICE_ID_INTEL_ADL_PCH 0x51ee
47 #define PCI_DEVICE_ID_INTEL_ADLN 0x465e
48 #define PCI_DEVICE_ID_INTEL_ADLN_PCH 0x54ee
49 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1
50 #define PCI_DEVICE_ID_INTEL_RPL 0xa70e
51 #define PCI_DEVICE_ID_INTEL_RPLS 0x7a61
52 #define PCI_DEVICE_ID_INTEL_MTLM 0x7eb1
53 #define PCI_DEVICE_ID_INTEL_MTLP 0x7ec1
54 #define PCI_DEVICE_ID_INTEL_MTLS 0x7f6f
55 #define PCI_DEVICE_ID_INTEL_MTL 0x7e7e
56 #define PCI_DEVICE_ID_INTEL_ARLH_PCH 0x777e
57 #define PCI_DEVICE_ID_INTEL_TGL 0x9a15
58 #define PCI_DEVICE_ID_INTEL_PTLH 0xe332
59 #define PCI_DEVICE_ID_INTEL_PTLH_PCH 0xe37e
60 #define PCI_DEVICE_ID_INTEL_PTLU 0xe432
61 #define PCI_DEVICE_ID_INTEL_PTLU_PCH 0xe47e
62 #define PCI_DEVICE_ID_AMD_MR 0x163a
63
64 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
65 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
66 #define PCI_INTEL_BXT_STATE_D0 0
67 #define PCI_INTEL_BXT_STATE_D3 3
68
69 #define GP_RWBAR 1
70 #define GP_RWREG1 0xa0
71 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
72
73 /**
74 * struct dwc3_pci - Driver private structure
75 * @dwc3: child dwc3 platform_device
76 * @pci: our link to PCI bus
77 * @guid: _DSM GUID
78 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
79 * @wakeup_work: work for asynchronous resume
80 */
81 struct dwc3_pci {
82 struct platform_device *dwc3;
83 struct pci_dev *pci;
84
85 guid_t guid;
86
87 unsigned int has_dsm_for_pm:1;
88 struct work_struct wakeup_work;
89 };
90
91 static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
92 static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
93
94 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
95 { "reset-gpios", &reset_gpios, 1 },
96 { "cs-gpios", &cs_gpios, 1 },
97 { },
98 };
99
100 static struct gpiod_lookup_table platform_bytcr_gpios = {
101 .dev_id = "0000:00:16.0",
102 .table = {
103 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
104 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
105 {}
106 },
107 };
108
dwc3_byt_enable_ulpi_refclock(struct pci_dev * pci)109 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
110 {
111 void __iomem *reg;
112 u32 value;
113
114 reg = pcim_iomap(pci, GP_RWBAR, 0);
115 if (!reg)
116 return -ENOMEM;
117
118 value = readl(reg + GP_RWREG1);
119 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
120 goto unmap; /* ULPI refclk already enabled */
121
122 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
123 writel(value, reg + GP_RWREG1);
124 /* This comes from the Intel Android x86 tree w/o any explanation */
125 msleep(100);
126 unmap:
127 pcim_iounmap(pci, reg);
128 return 0;
129 }
130
131 static const struct property_entry dwc3_pci_intel_properties[] = {
132 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
133 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
134 {}
135 };
136
137 static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = {
138 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
139 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
140 PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"),
141 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
142 {}
143 };
144
145 static const struct property_entry dwc3_pci_intel_byt_properties[] = {
146 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
147 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
148 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
149 {}
150 };
151
152 /*
153 * Intel Merrifield SoC uses these endpoints for tracing and they cannot
154 * be re-allocated if being used because the side band flow control signals
155 * are hard wired to certain endpoints:
156 * - 1 High BW Bulk IN (IN#1) (RTIT)
157 * - 1 1KB BW Bulk IN (IN#8) + 1 1KB BW Bulk OUT (Run Control) (OUT#8)
158 */
159 static const u8 dwc3_pci_mrfld_reserved_endpoints[] = { 3, 16, 17 };
160
161 static const struct property_entry dwc3_pci_mrfld_properties[] = {
162 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
163 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
164 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
165 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
166 PROPERTY_ENTRY_U8_ARRAY("snps,reserved-endpoints", dwc3_pci_mrfld_reserved_endpoints),
167 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
168 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
169 {}
170 };
171
172 static const struct property_entry dwc3_pci_amd_properties[] = {
173 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
174 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
175 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
176 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
177 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
178 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
179 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
180 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
181 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
182 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
183 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
184 /* FIXME these quirks should be removed when AMD NL tapes out */
185 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
186 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
187 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
188 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
189 {}
190 };
191
192 static const struct property_entry dwc3_pci_mr_properties[] = {
193 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
194 PROPERTY_ENTRY_BOOL("usb-role-switch"),
195 PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"),
196 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
197 {}
198 };
199
200 static const struct software_node dwc3_pci_intel_swnode = {
201 .properties = dwc3_pci_intel_properties,
202 };
203
204 static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = {
205 .properties = dwc3_pci_intel_phy_charger_detect_properties,
206 };
207
208 static const struct software_node dwc3_pci_intel_byt_swnode = {
209 .properties = dwc3_pci_intel_byt_properties,
210 };
211
212 static const struct software_node dwc3_pci_intel_mrfld_swnode = {
213 .properties = dwc3_pci_mrfld_properties,
214 };
215
216 static const struct software_node dwc3_pci_amd_swnode = {
217 .properties = dwc3_pci_amd_properties,
218 };
219
220 static const struct software_node dwc3_pci_amd_mr_swnode = {
221 .properties = dwc3_pci_mr_properties,
222 };
223
dwc3_pci_quirks(struct dwc3_pci * dwc,const struct software_node * swnode)224 static int dwc3_pci_quirks(struct dwc3_pci *dwc,
225 const struct software_node *swnode)
226 {
227 struct pci_dev *pdev = dwc->pci;
228
229 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
230 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
231 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
232 pdev->device == PCI_DEVICE_ID_INTEL_EHL) {
233 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
234 dwc->has_dsm_for_pm = true;
235 }
236
237 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
238 struct gpio_desc *gpio;
239 const char *bios_ver;
240 int ret;
241
242 /* On BYT the FW does not always enable the refclock */
243 ret = dwc3_byt_enable_ulpi_refclock(pdev);
244 if (ret)
245 return ret;
246
247 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
248 acpi_dwc3_byt_gpios);
249 if (ret)
250 dev_dbg(&pdev->dev, "failed to add mapping table\n");
251
252 /*
253 * A lot of BYT devices lack ACPI resource entries for
254 * the GPIOs. If the ACPI entry for the GPIO controller
255 * is present add a fallback mapping to the reference
256 * design GPIOs which all boards seem to use.
257 */
258 if (acpi_dev_present("INT33FC", NULL, -1))
259 gpiod_add_lookup_table(&platform_bytcr_gpios);
260
261 /*
262 * These GPIOs will turn on the USB2 PHY. Note that we have to
263 * put the gpio descriptors again here because the phy driver
264 * might want to grab them, too.
265 */
266 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
267 if (IS_ERR(gpio))
268 return PTR_ERR(gpio);
269
270 gpiod_set_value_cansleep(gpio, 1);
271 gpiod_put(gpio);
272
273 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
274 if (IS_ERR(gpio))
275 return PTR_ERR(gpio);
276
277 if (gpio) {
278 gpiod_set_value_cansleep(gpio, 1);
279 gpiod_put(gpio);
280 usleep_range(10000, 11000);
281 }
282
283 /*
284 * Make the pdev name predictable (only 1 DWC3 on BYT)
285 * and patch the phy dev-name into the lookup table so
286 * that the phy-driver can get the GPIOs.
287 */
288 dwc->dwc3->id = PLATFORM_DEVID_NONE;
289 platform_bytcr_gpios.dev_id = "dwc3.ulpi";
290
291 /*
292 * Some Android tablets with a Crystal Cove PMIC
293 * (INT33FD), rely on the TUSB1211 phy for charger
294 * detection. These can be identified by them _not_
295 * using the standard ACPI battery and ac drivers.
296 */
297 bios_ver = dmi_get_system_info(DMI_BIOS_VERSION);
298 if (acpi_dev_present("INT33FD", "1", 2) &&
299 acpi_quirk_skip_acpi_ac_and_battery() &&
300 /* Lenovo Yoga Tablet 2 Pro 1380 uses LC824206XA instead */
301 !(bios_ver &&
302 strstarts(bios_ver, "BLADE_21.X64.0005.R00.1504101516"))) {
303 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n");
304 swnode = &dwc3_pci_intel_phy_charger_detect_swnode;
305 }
306 }
307 }
308
309 return device_add_software_node(&dwc->dwc3->dev, swnode);
310 }
311
312 #ifdef CONFIG_PM
dwc3_pci_resume_work(struct work_struct * work)313 static void dwc3_pci_resume_work(struct work_struct *work)
314 {
315 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
316 struct platform_device *dwc3 = dwc->dwc3;
317 int ret;
318
319 ret = pm_runtime_get_sync(&dwc3->dev);
320 if (ret < 0) {
321 pm_runtime_put_sync_autosuspend(&dwc3->dev);
322 return;
323 }
324
325 pm_runtime_mark_last_busy(&dwc3->dev);
326 pm_runtime_put_sync_autosuspend(&dwc3->dev);
327 }
328 #endif
329
dwc3_pci_probe(struct pci_dev * pci,const struct pci_device_id * id)330 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
331 {
332 struct dwc3_pci *dwc;
333 struct resource res[2];
334 int ret;
335 struct device *dev = &pci->dev;
336
337 ret = pcim_enable_device(pci);
338 if (ret) {
339 dev_err(dev, "failed to enable pci device\n");
340 return -ENODEV;
341 }
342
343 pci_set_master(pci);
344
345 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
346 if (!dwc)
347 return -ENOMEM;
348
349 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
350 if (!dwc->dwc3)
351 return -ENOMEM;
352
353 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
354
355 res[0].start = pci_resource_start(pci, 0);
356 res[0].end = pci_resource_end(pci, 0);
357 res[0].name = "dwc_usb3";
358 res[0].flags = IORESOURCE_MEM;
359
360 res[1].start = pci->irq;
361 res[1].name = "dwc_usb3";
362 res[1].flags = IORESOURCE_IRQ;
363
364 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
365 if (ret) {
366 dev_err(dev, "couldn't add resources to dwc3 device\n");
367 goto err;
368 }
369
370 dwc->pci = pci;
371 dwc->dwc3->dev.parent = dev;
372 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
373
374 ret = dwc3_pci_quirks(dwc, (void *)id->driver_data);
375 if (ret)
376 goto err;
377
378 ret = platform_device_add(dwc->dwc3);
379 if (ret) {
380 dev_err(dev, "failed to register dwc3 device\n");
381 goto err;
382 }
383
384 device_init_wakeup(dev, true);
385 pci_set_drvdata(pci, dwc);
386 pm_runtime_put(dev);
387 #ifdef CONFIG_PM
388 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
389 #endif
390
391 return 0;
392 err:
393 device_remove_software_node(&dwc->dwc3->dev);
394 platform_device_put(dwc->dwc3);
395 return ret;
396 }
397
dwc3_pci_remove(struct pci_dev * pci)398 static void dwc3_pci_remove(struct pci_dev *pci)
399 {
400 struct dwc3_pci *dwc = pci_get_drvdata(pci);
401 struct pci_dev *pdev = dwc->pci;
402
403 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
404 gpiod_remove_lookup_table(&platform_bytcr_gpios);
405 #ifdef CONFIG_PM
406 cancel_work_sync(&dwc->wakeup_work);
407 #endif
408 device_init_wakeup(&pci->dev, false);
409 pm_runtime_get(&pci->dev);
410 device_remove_software_node(&dwc->dwc3->dev);
411 platform_device_unregister(dwc->dwc3);
412 }
413
414 static const struct pci_device_id dwc3_pci_id_table[] = {
415 { PCI_DEVICE_DATA(INTEL, BSW, &dwc3_pci_intel_swnode) },
416 { PCI_DEVICE_DATA(INTEL, BYT, &dwc3_pci_intel_byt_swnode) },
417 { PCI_DEVICE_DATA(INTEL, MRFLD, &dwc3_pci_intel_mrfld_swnode) },
418 { PCI_DEVICE_DATA(INTEL, CMLLP, &dwc3_pci_intel_swnode) },
419 { PCI_DEVICE_DATA(INTEL, CMLH, &dwc3_pci_intel_swnode) },
420 { PCI_DEVICE_DATA(INTEL, SPTLP, &dwc3_pci_intel_swnode) },
421 { PCI_DEVICE_DATA(INTEL, SPTH, &dwc3_pci_intel_swnode) },
422 { PCI_DEVICE_DATA(INTEL, BXT, &dwc3_pci_intel_swnode) },
423 { PCI_DEVICE_DATA(INTEL, BXT_M, &dwc3_pci_intel_swnode) },
424 { PCI_DEVICE_DATA(INTEL, APL, &dwc3_pci_intel_swnode) },
425 { PCI_DEVICE_DATA(INTEL, KBP, &dwc3_pci_intel_swnode) },
426 { PCI_DEVICE_DATA(INTEL, GLK, &dwc3_pci_intel_swnode) },
427 { PCI_DEVICE_DATA(INTEL, CNPLP, &dwc3_pci_intel_swnode) },
428 { PCI_DEVICE_DATA(INTEL, CNPH, &dwc3_pci_intel_swnode) },
429 { PCI_DEVICE_DATA(INTEL, CNPV, &dwc3_pci_intel_swnode) },
430 { PCI_DEVICE_DATA(INTEL, ICLLP, &dwc3_pci_intel_swnode) },
431 { PCI_DEVICE_DATA(INTEL, EHL, &dwc3_pci_intel_swnode) },
432 { PCI_DEVICE_DATA(INTEL, TGPLP, &dwc3_pci_intel_swnode) },
433 { PCI_DEVICE_DATA(INTEL, TGPH, &dwc3_pci_intel_swnode) },
434 { PCI_DEVICE_DATA(INTEL, JSP, &dwc3_pci_intel_swnode) },
435 { PCI_DEVICE_DATA(INTEL, WCL, &dwc3_pci_intel_swnode) },
436 { PCI_DEVICE_DATA(INTEL, ADL, &dwc3_pci_intel_swnode) },
437 { PCI_DEVICE_DATA(INTEL, ADL_PCH, &dwc3_pci_intel_swnode) },
438 { PCI_DEVICE_DATA(INTEL, ADLN, &dwc3_pci_intel_swnode) },
439 { PCI_DEVICE_DATA(INTEL, ADLN_PCH, &dwc3_pci_intel_swnode) },
440 { PCI_DEVICE_DATA(INTEL, ADLS, &dwc3_pci_intel_swnode) },
441 { PCI_DEVICE_DATA(INTEL, RPL, &dwc3_pci_intel_swnode) },
442 { PCI_DEVICE_DATA(INTEL, RPLS, &dwc3_pci_intel_swnode) },
443 { PCI_DEVICE_DATA(INTEL, MTLM, &dwc3_pci_intel_swnode) },
444 { PCI_DEVICE_DATA(INTEL, MTLP, &dwc3_pci_intel_swnode) },
445 { PCI_DEVICE_DATA(INTEL, MTL, &dwc3_pci_intel_swnode) },
446 { PCI_DEVICE_DATA(INTEL, MTLS, &dwc3_pci_intel_swnode) },
447 { PCI_DEVICE_DATA(INTEL, ARLH_PCH, &dwc3_pci_intel_swnode) },
448 { PCI_DEVICE_DATA(INTEL, TGL, &dwc3_pci_intel_swnode) },
449 { PCI_DEVICE_DATA(INTEL, PTLH, &dwc3_pci_intel_swnode) },
450 { PCI_DEVICE_DATA(INTEL, PTLH_PCH, &dwc3_pci_intel_swnode) },
451 { PCI_DEVICE_DATA(INTEL, PTLU, &dwc3_pci_intel_swnode) },
452 { PCI_DEVICE_DATA(INTEL, PTLU_PCH, &dwc3_pci_intel_swnode) },
453
454 { PCI_DEVICE_DATA(AMD, NL_USB, &dwc3_pci_amd_swnode) },
455 { PCI_DEVICE_DATA(AMD, MR, &dwc3_pci_amd_mr_swnode) },
456
457 { } /* Terminating Entry */
458 };
459 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
460
461 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
dwc3_pci_dsm(struct dwc3_pci * dwc,int param)462 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
463 {
464 union acpi_object *obj;
465 union acpi_object tmp;
466 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
467
468 if (!dwc->has_dsm_for_pm)
469 return 0;
470
471 tmp.type = ACPI_TYPE_INTEGER;
472 tmp.integer.value = param;
473
474 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
475 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
476 if (!obj) {
477 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
478 return -EIO;
479 }
480
481 ACPI_FREE(obj);
482
483 return 0;
484 }
485 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
486
487 #ifdef CONFIG_PM
dwc3_pci_runtime_suspend(struct device * dev)488 static int dwc3_pci_runtime_suspend(struct device *dev)
489 {
490 struct dwc3_pci *dwc = dev_get_drvdata(dev);
491
492 if (device_can_wakeup(dev))
493 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
494
495 return -EBUSY;
496 }
497
dwc3_pci_runtime_resume(struct device * dev)498 static int dwc3_pci_runtime_resume(struct device *dev)
499 {
500 struct dwc3_pci *dwc = dev_get_drvdata(dev);
501 int ret;
502
503 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
504 if (ret)
505 return ret;
506
507 queue_work(pm_wq, &dwc->wakeup_work);
508
509 return 0;
510 }
511 #endif /* CONFIG_PM */
512
513 #ifdef CONFIG_PM_SLEEP
dwc3_pci_suspend(struct device * dev)514 static int dwc3_pci_suspend(struct device *dev)
515 {
516 struct dwc3_pci *dwc = dev_get_drvdata(dev);
517
518 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
519 }
520
dwc3_pci_resume(struct device * dev)521 static int dwc3_pci_resume(struct device *dev)
522 {
523 struct dwc3_pci *dwc = dev_get_drvdata(dev);
524
525 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
526 }
527 #endif /* CONFIG_PM_SLEEP */
528
529 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
530 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
531 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
532 NULL)
533 };
534
535 static struct pci_driver dwc3_pci_driver = {
536 .name = "dwc3-pci",
537 .id_table = dwc3_pci_id_table,
538 .probe = dwc3_pci_probe,
539 .remove = dwc3_pci_remove,
540 .driver = {
541 .pm = &dwc3_pci_dev_pm_ops,
542 }
543 };
544
545 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
546 MODULE_LICENSE("GPL v2");
547 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
548
549 module_pci_driver(dwc3_pci_driver);
550