1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
4 * using the CPU's debug registers.
5 *
6 * Copyright (C) 2012 ARM Limited
7 * Author: Will Deacon <will.deacon@arm.com>
8 */
9
10 #define pr_fmt(fmt) "hw-breakpoint: " fmt
11
12 #include <linux/compat.h>
13 #include <linux/cpu_pm.h>
14 #include <linux/errno.h>
15 #include <linux/hw_breakpoint.h>
16 #include <linux/kprobes.h>
17 #include <linux/perf_event.h>
18 #include <linux/ptrace.h>
19 #include <linux/smp.h>
20 #include <linux/uaccess.h>
21
22 #include <asm/current.h>
23 #include <asm/daifflags.h>
24 #include <asm/debug-monitors.h>
25 #include <asm/esr.h>
26 #include <asm/exception.h>
27 #include <asm/hw_breakpoint.h>
28 #include <asm/traps.h>
29 #include <asm/cputype.h>
30 #include <asm/system_misc.h>
31
32 /* Breakpoint currently in use for each BRP. */
33 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
34
35 /* Watchpoint currently in use for each WRP. */
36 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
37
38 /* Currently stepping a per-CPU kernel breakpoint. */
39 static DEFINE_PER_CPU(int, stepping_kernel_bp);
40
41 /* Number of BRP/WRP registers on this CPU. */
42 static int core_num_brps;
43 static int core_num_wrps;
44
hw_breakpoint_slots(int type)45 int hw_breakpoint_slots(int type)
46 {
47 /*
48 * We can be called early, so don't rely on
49 * our static variables being initialised.
50 */
51 switch (type) {
52 case TYPE_INST:
53 return get_num_brps();
54 case TYPE_DATA:
55 return get_num_wrps();
56 default:
57 pr_warn("unknown slot type: %d\n", type);
58 return 0;
59 }
60 }
61
62 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \
63 case (OFF + N): \
64 AARCH64_DBG_READ(N, REG, VAL); \
65 break
66
67 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \
68 case (OFF + N): \
69 AARCH64_DBG_WRITE(N, REG, VAL); \
70 break
71
72 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \
73 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
74 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
75 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
76 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
77 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
78 READ_WB_REG_CASE(OFF, 5, REG, VAL); \
79 READ_WB_REG_CASE(OFF, 6, REG, VAL); \
80 READ_WB_REG_CASE(OFF, 7, REG, VAL); \
81 READ_WB_REG_CASE(OFF, 8, REG, VAL); \
82 READ_WB_REG_CASE(OFF, 9, REG, VAL); \
83 READ_WB_REG_CASE(OFF, 10, REG, VAL); \
84 READ_WB_REG_CASE(OFF, 11, REG, VAL); \
85 READ_WB_REG_CASE(OFF, 12, REG, VAL); \
86 READ_WB_REG_CASE(OFF, 13, REG, VAL); \
87 READ_WB_REG_CASE(OFF, 14, REG, VAL); \
88 READ_WB_REG_CASE(OFF, 15, REG, VAL)
89
90 #define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \
91 WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \
92 WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \
93 WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \
94 WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \
95 WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \
96 WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \
97 WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \
98 WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \
99 WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \
100 WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \
101 WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \
102 WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \
103 WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \
104 WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \
105 WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \
106 WRITE_WB_REG_CASE(OFF, 15, REG, VAL)
107
read_wb_reg(int reg,int n)108 static u64 read_wb_reg(int reg, int n)
109 {
110 u64 val = 0;
111
112 switch (reg + n) {
113 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
114 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
115 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
116 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
117 default:
118 pr_warn("attempt to read from unknown breakpoint register %d\n", n);
119 }
120
121 return val;
122 }
123 NOKPROBE_SYMBOL(read_wb_reg);
124
write_wb_reg(int reg,int n,u64 val)125 static void write_wb_reg(int reg, int n, u64 val)
126 {
127 switch (reg + n) {
128 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
129 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
130 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
131 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
132 default:
133 pr_warn("attempt to write to unknown breakpoint register %d\n", n);
134 }
135 isb();
136 }
137 NOKPROBE_SYMBOL(write_wb_reg);
138
139 /*
140 * Convert a breakpoint privilege level to the corresponding exception
141 * level.
142 */
debug_exception_level(int privilege)143 static enum dbg_active_el debug_exception_level(int privilege)
144 {
145 switch (privilege) {
146 case AARCH64_BREAKPOINT_EL0:
147 return DBG_ACTIVE_EL0;
148 case AARCH64_BREAKPOINT_EL1:
149 return DBG_ACTIVE_EL1;
150 default:
151 pr_warn("invalid breakpoint privilege level %d\n", privilege);
152 return -EINVAL;
153 }
154 }
155 NOKPROBE_SYMBOL(debug_exception_level);
156
157 enum hw_breakpoint_ops {
158 HW_BREAKPOINT_INSTALL,
159 HW_BREAKPOINT_UNINSTALL,
160 HW_BREAKPOINT_RESTORE
161 };
162
is_compat_bp(struct perf_event * bp)163 static int is_compat_bp(struct perf_event *bp)
164 {
165 struct task_struct *tsk = bp->hw.target;
166
167 /*
168 * tsk can be NULL for per-cpu (non-ptrace) breakpoints.
169 * In this case, use the native interface, since we don't have
170 * the notion of a "compat CPU" and could end up relying on
171 * deprecated behaviour if we use unaligned watchpoints in
172 * AArch64 state.
173 */
174 return tsk && is_compat_thread(task_thread_info(tsk));
175 }
176
177 /**
178 * hw_breakpoint_slot_setup - Find and setup a perf slot according to
179 * operations
180 *
181 * @slots: pointer to array of slots
182 * @max_slots: max number of slots
183 * @bp: perf_event to setup
184 * @ops: operation to be carried out on the slot
185 *
186 * Return:
187 * slot index on success
188 * -ENOSPC if no slot is available/matches
189 * -EINVAL on wrong operations parameter
190 */
hw_breakpoint_slot_setup(struct perf_event ** slots,int max_slots,struct perf_event * bp,enum hw_breakpoint_ops ops)191 static int hw_breakpoint_slot_setup(struct perf_event **slots, int max_slots,
192 struct perf_event *bp,
193 enum hw_breakpoint_ops ops)
194 {
195 int i;
196 struct perf_event **slot;
197
198 for (i = 0; i < max_slots; ++i) {
199 slot = &slots[i];
200 switch (ops) {
201 case HW_BREAKPOINT_INSTALL:
202 if (!*slot) {
203 *slot = bp;
204 return i;
205 }
206 break;
207 case HW_BREAKPOINT_UNINSTALL:
208 if (*slot == bp) {
209 *slot = NULL;
210 return i;
211 }
212 break;
213 case HW_BREAKPOINT_RESTORE:
214 if (*slot == bp)
215 return i;
216 break;
217 default:
218 pr_warn_once("Unhandled hw breakpoint ops %d\n", ops);
219 return -EINVAL;
220 }
221 }
222 return -ENOSPC;
223 }
224
225 /*
226 * Configure hardware breakpoint registers from a perf event,
227 * according to operation.
228 *
229 * Must be called with debug exceptions masked.
230 */
hw_breakpoint_control(struct perf_event * bp,enum hw_breakpoint_ops ops)231 static int hw_breakpoint_control(struct perf_event *bp,
232 enum hw_breakpoint_ops ops)
233 {
234 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
235 struct perf_event **slots;
236 struct debug_info *debug_info = ¤t->thread.debug;
237 int i, max_slots, ctrl_reg, val_reg, reg_enable;
238 enum dbg_active_el dbg_el = debug_exception_level(info->ctrl.privilege);
239 u32 ctrl;
240
241 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
242 /* Breakpoint */
243 ctrl_reg = AARCH64_DBG_REG_BCR;
244 val_reg = AARCH64_DBG_REG_BVR;
245 slots = this_cpu_ptr(bp_on_reg);
246 max_slots = core_num_brps;
247 reg_enable = !debug_info->bps_disabled;
248 } else {
249 /* Watchpoint */
250 ctrl_reg = AARCH64_DBG_REG_WCR;
251 val_reg = AARCH64_DBG_REG_WVR;
252 slots = this_cpu_ptr(wp_on_reg);
253 max_slots = core_num_wrps;
254 reg_enable = !debug_info->wps_disabled;
255 }
256
257 i = hw_breakpoint_slot_setup(slots, max_slots, bp, ops);
258
259 if (WARN_ONCE(i < 0, "Can't find any breakpoint slot"))
260 return i;
261
262 switch (ops) {
263 case HW_BREAKPOINT_INSTALL:
264 /*
265 * Ensure debug monitors are enabled at the correct exception
266 * level.
267 */
268 enable_debug_monitors(dbg_el);
269 fallthrough;
270 case HW_BREAKPOINT_RESTORE:
271 /* Setup the address register. */
272 write_wb_reg(val_reg, i, info->address);
273
274 /* Setup the control register. */
275 ctrl = encode_ctrl_reg(info->ctrl);
276 write_wb_reg(ctrl_reg, i,
277 reg_enable ? ctrl | 0x1 : ctrl & ~0x1);
278 break;
279 case HW_BREAKPOINT_UNINSTALL:
280 /* Reset the control register. */
281 write_wb_reg(ctrl_reg, i, 0);
282
283 /*
284 * Release the debug monitors for the correct exception
285 * level.
286 */
287 disable_debug_monitors(dbg_el);
288 break;
289 }
290
291 return 0;
292 }
293
294 /*
295 * Install a perf counter breakpoint.
296 *
297 * Perf can and will call this with debug exceptions unmasked.
298 * Mask them to avoid triggering one while manipulating their registers.
299 */
arch_install_hw_breakpoint(struct perf_event * bp)300 int arch_install_hw_breakpoint(struct perf_event *bp)
301 {
302 unsigned long daif = local_daif_save();
303 int ret = hw_breakpoint_control(bp, HW_BREAKPOINT_INSTALL);
304
305 local_daif_restore(daif);
306 return ret;
307 }
308
arch_uninstall_hw_breakpoint(struct perf_event * bp)309 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
310 {
311 unsigned long daif = local_daif_save();
312 hw_breakpoint_control(bp, HW_BREAKPOINT_UNINSTALL);
313 local_daif_restore(daif);
314 }
315
get_hbp_len(u8 hbp_len)316 static int get_hbp_len(u8 hbp_len)
317 {
318 unsigned int len_in_bytes = 0;
319
320 switch (hbp_len) {
321 case ARM_BREAKPOINT_LEN_1:
322 len_in_bytes = 1;
323 break;
324 case ARM_BREAKPOINT_LEN_2:
325 len_in_bytes = 2;
326 break;
327 case ARM_BREAKPOINT_LEN_3:
328 len_in_bytes = 3;
329 break;
330 case ARM_BREAKPOINT_LEN_4:
331 len_in_bytes = 4;
332 break;
333 case ARM_BREAKPOINT_LEN_5:
334 len_in_bytes = 5;
335 break;
336 case ARM_BREAKPOINT_LEN_6:
337 len_in_bytes = 6;
338 break;
339 case ARM_BREAKPOINT_LEN_7:
340 len_in_bytes = 7;
341 break;
342 case ARM_BREAKPOINT_LEN_8:
343 len_in_bytes = 8;
344 break;
345 }
346
347 return len_in_bytes;
348 }
349
350 /*
351 * Check whether bp virtual address is in kernel space.
352 */
arch_check_bp_in_kernelspace(struct arch_hw_breakpoint * hw)353 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
354 {
355 unsigned int len;
356 unsigned long va;
357
358 va = hw->address;
359 len = get_hbp_len(hw->ctrl.len);
360
361 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
362 }
363
364 /*
365 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
366 * Hopefully this will disappear when ptrace can bypass the conversion
367 * to generic breakpoint descriptions.
368 */
arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,int * gen_len,int * gen_type,int * offset)369 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
370 int *gen_len, int *gen_type, int *offset)
371 {
372 /* Type */
373 switch (ctrl.type) {
374 case ARM_BREAKPOINT_EXECUTE:
375 *gen_type = HW_BREAKPOINT_X;
376 break;
377 case ARM_BREAKPOINT_LOAD:
378 *gen_type = HW_BREAKPOINT_R;
379 break;
380 case ARM_BREAKPOINT_STORE:
381 *gen_type = HW_BREAKPOINT_W;
382 break;
383 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
384 *gen_type = HW_BREAKPOINT_RW;
385 break;
386 default:
387 return -EINVAL;
388 }
389
390 if (!ctrl.len)
391 return -EINVAL;
392 *offset = __ffs(ctrl.len);
393
394 /* Len */
395 switch (ctrl.len >> *offset) {
396 case ARM_BREAKPOINT_LEN_1:
397 *gen_len = HW_BREAKPOINT_LEN_1;
398 break;
399 case ARM_BREAKPOINT_LEN_2:
400 *gen_len = HW_BREAKPOINT_LEN_2;
401 break;
402 case ARM_BREAKPOINT_LEN_3:
403 *gen_len = HW_BREAKPOINT_LEN_3;
404 break;
405 case ARM_BREAKPOINT_LEN_4:
406 *gen_len = HW_BREAKPOINT_LEN_4;
407 break;
408 case ARM_BREAKPOINT_LEN_5:
409 *gen_len = HW_BREAKPOINT_LEN_5;
410 break;
411 case ARM_BREAKPOINT_LEN_6:
412 *gen_len = HW_BREAKPOINT_LEN_6;
413 break;
414 case ARM_BREAKPOINT_LEN_7:
415 *gen_len = HW_BREAKPOINT_LEN_7;
416 break;
417 case ARM_BREAKPOINT_LEN_8:
418 *gen_len = HW_BREAKPOINT_LEN_8;
419 break;
420 default:
421 return -EINVAL;
422 }
423
424 return 0;
425 }
426
427 /*
428 * Construct an arch_hw_breakpoint from a perf_event.
429 */
arch_build_bp_info(struct perf_event * bp,const struct perf_event_attr * attr,struct arch_hw_breakpoint * hw)430 static int arch_build_bp_info(struct perf_event *bp,
431 const struct perf_event_attr *attr,
432 struct arch_hw_breakpoint *hw)
433 {
434 /* Type */
435 switch (attr->bp_type) {
436 case HW_BREAKPOINT_X:
437 hw->ctrl.type = ARM_BREAKPOINT_EXECUTE;
438 break;
439 case HW_BREAKPOINT_R:
440 hw->ctrl.type = ARM_BREAKPOINT_LOAD;
441 break;
442 case HW_BREAKPOINT_W:
443 hw->ctrl.type = ARM_BREAKPOINT_STORE;
444 break;
445 case HW_BREAKPOINT_RW:
446 hw->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
447 break;
448 default:
449 return -EINVAL;
450 }
451
452 /* Len */
453 switch (attr->bp_len) {
454 case HW_BREAKPOINT_LEN_1:
455 hw->ctrl.len = ARM_BREAKPOINT_LEN_1;
456 break;
457 case HW_BREAKPOINT_LEN_2:
458 hw->ctrl.len = ARM_BREAKPOINT_LEN_2;
459 break;
460 case HW_BREAKPOINT_LEN_3:
461 hw->ctrl.len = ARM_BREAKPOINT_LEN_3;
462 break;
463 case HW_BREAKPOINT_LEN_4:
464 hw->ctrl.len = ARM_BREAKPOINT_LEN_4;
465 break;
466 case HW_BREAKPOINT_LEN_5:
467 hw->ctrl.len = ARM_BREAKPOINT_LEN_5;
468 break;
469 case HW_BREAKPOINT_LEN_6:
470 hw->ctrl.len = ARM_BREAKPOINT_LEN_6;
471 break;
472 case HW_BREAKPOINT_LEN_7:
473 hw->ctrl.len = ARM_BREAKPOINT_LEN_7;
474 break;
475 case HW_BREAKPOINT_LEN_8:
476 hw->ctrl.len = ARM_BREAKPOINT_LEN_8;
477 break;
478 default:
479 return -EINVAL;
480 }
481
482 /*
483 * On AArch64, we only permit breakpoints of length 4, whereas
484 * AArch32 also requires breakpoints of length 2 for Thumb.
485 * Watchpoints can be of length 1, 2, 4 or 8 bytes.
486 */
487 if (hw->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
488 if (is_compat_bp(bp)) {
489 if (hw->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
490 hw->ctrl.len != ARM_BREAKPOINT_LEN_4)
491 return -EINVAL;
492 } else if (hw->ctrl.len != ARM_BREAKPOINT_LEN_4) {
493 /*
494 * FIXME: Some tools (I'm looking at you perf) assume
495 * that breakpoints should be sizeof(long). This
496 * is nonsense. For now, we fix up the parameter
497 * but we should probably return -EINVAL instead.
498 */
499 hw->ctrl.len = ARM_BREAKPOINT_LEN_4;
500 }
501 }
502
503 /* Address */
504 hw->address = attr->bp_addr;
505
506 /*
507 * Privilege
508 * Note that we disallow combined EL0/EL1 breakpoints because
509 * that would complicate the stepping code.
510 */
511 if (arch_check_bp_in_kernelspace(hw))
512 hw->ctrl.privilege = AARCH64_BREAKPOINT_EL1;
513 else
514 hw->ctrl.privilege = AARCH64_BREAKPOINT_EL0;
515
516 /* Enabled? */
517 hw->ctrl.enabled = !attr->disabled;
518
519 return 0;
520 }
521
522 /*
523 * Validate the arch-specific HW Breakpoint register settings.
524 */
hw_breakpoint_arch_parse(struct perf_event * bp,const struct perf_event_attr * attr,struct arch_hw_breakpoint * hw)525 int hw_breakpoint_arch_parse(struct perf_event *bp,
526 const struct perf_event_attr *attr,
527 struct arch_hw_breakpoint *hw)
528 {
529 int ret;
530 u64 alignment_mask, offset;
531
532 /* Build the arch_hw_breakpoint. */
533 ret = arch_build_bp_info(bp, attr, hw);
534 if (ret)
535 return ret;
536
537 /*
538 * Check address alignment.
539 * We don't do any clever alignment correction for watchpoints
540 * because using 64-bit unaligned addresses is deprecated for
541 * AArch64.
542 *
543 * AArch32 tasks expect some simple alignment fixups, so emulate
544 * that here.
545 */
546 if (is_compat_bp(bp)) {
547 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_8)
548 alignment_mask = 0x7;
549 else
550 alignment_mask = 0x3;
551 offset = hw->address & alignment_mask;
552 switch (offset) {
553 case 0:
554 /* Aligned */
555 break;
556 case 1:
557 case 2:
558 /* Allow halfword watchpoints and breakpoints. */
559 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
560 break;
561
562 fallthrough;
563 case 3:
564 /* Allow single byte watchpoint. */
565 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
566 break;
567
568 fallthrough;
569 default:
570 return -EINVAL;
571 }
572 } else {
573 if (hw->ctrl.type == ARM_BREAKPOINT_EXECUTE)
574 alignment_mask = 0x3;
575 else
576 alignment_mask = 0x7;
577 offset = hw->address & alignment_mask;
578
579 /*
580 * BAS is an 8-bit field in WCR/BCR; the shift below would
581 * silently drop the high bits of ctrl.len when offset + len
582 * exceeds 8, programming hardware to watch fewer bytes than
583 * the user requested.
584 */
585 if (((u32)hw->ctrl.len << offset) > ARM_BREAKPOINT_LEN_8)
586 return -EINVAL;
587 }
588
589 hw->address &= ~alignment_mask;
590 hw->ctrl.len <<= offset;
591
592 /*
593 * Disallow per-task kernel breakpoints since these would
594 * complicate the stepping code.
595 */
596 if (hw->ctrl.privilege == AARCH64_BREAKPOINT_EL1 && bp->hw.target)
597 return -EINVAL;
598
599 return 0;
600 }
601
602 /*
603 * Enable/disable all of the breakpoints active at the specified
604 * exception level at the register level.
605 * This is used when single-stepping after a breakpoint exception or switching
606 * threads.
607 *
608 * Must be called with debug exceptions masked.
609 */
toggle_bp_registers(int reg,enum dbg_active_el el,int enable)610 static void toggle_bp_registers(int reg, enum dbg_active_el el, int enable)
611 {
612 int i, max_slots, privilege;
613 u32 ctrl;
614 struct perf_event **slots;
615
616 switch (reg) {
617 case AARCH64_DBG_REG_BCR:
618 slots = this_cpu_ptr(bp_on_reg);
619 max_slots = core_num_brps;
620 break;
621 case AARCH64_DBG_REG_WCR:
622 slots = this_cpu_ptr(wp_on_reg);
623 max_slots = core_num_wrps;
624 break;
625 default:
626 return;
627 }
628
629 for (i = 0; i < max_slots; ++i) {
630 if (!slots[i])
631 continue;
632
633 privilege = counter_arch_bp(slots[i])->ctrl.privilege;
634 if (debug_exception_level(privilege) != el)
635 continue;
636
637 ctrl = read_wb_reg(reg, i);
638 if (enable)
639 ctrl |= 0x1;
640 else
641 ctrl &= ~0x1;
642 write_wb_reg(reg, i, ctrl);
643 }
644 }
645 NOKPROBE_SYMBOL(toggle_bp_registers);
646
647 /*
648 * Debug exception handlers.
649 */
do_breakpoint(unsigned long esr,struct pt_regs * regs)650 void do_breakpoint(unsigned long esr, struct pt_regs *regs)
651 {
652 int i, step = 0, *kernel_step;
653 u32 ctrl_reg;
654 u64 addr, val;
655 struct perf_event *bp, **slots;
656 struct debug_info *debug_info;
657 struct arch_hw_breakpoint_ctrl ctrl;
658
659 slots = this_cpu_ptr(bp_on_reg);
660 addr = instruction_pointer(regs);
661 debug_info = ¤t->thread.debug;
662
663 for (i = 0; i < core_num_brps; ++i) {
664 rcu_read_lock();
665
666 bp = slots[i];
667
668 if (bp == NULL)
669 goto unlock;
670
671 /* Check if the breakpoint value matches. */
672 val = read_wb_reg(AARCH64_DBG_REG_BVR, i);
673 if (val != (addr & ~0x3))
674 goto unlock;
675
676 /* Possible match, check the byte address select to confirm. */
677 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i);
678 decode_ctrl_reg(ctrl_reg, &ctrl);
679 if (!((1 << (addr & 0x3)) & ctrl.len))
680 goto unlock;
681
682 counter_arch_bp(bp)->trigger = addr;
683 perf_bp_event(bp, regs);
684
685 /* Do we need to handle the stepping? */
686 if (is_default_overflow_handler(bp))
687 step = 1;
688 unlock:
689 rcu_read_unlock();
690 }
691
692 if (!step)
693 return;
694
695 if (user_mode(regs)) {
696 debug_info->bps_disabled = 1;
697 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 0);
698
699 /* If we're already stepping a watchpoint, just return. */
700 if (debug_info->wps_disabled)
701 return;
702
703 if (test_thread_flag(TIF_SINGLESTEP))
704 debug_info->suspended_step = 1;
705 else
706 user_enable_single_step(current);
707 } else {
708 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 0);
709 kernel_step = this_cpu_ptr(&stepping_kernel_bp);
710
711 if (*kernel_step != ARM_KERNEL_STEP_NONE)
712 return;
713
714 if (kernel_active_single_step()) {
715 *kernel_step = ARM_KERNEL_STEP_SUSPEND;
716 } else {
717 *kernel_step = ARM_KERNEL_STEP_ACTIVE;
718 kernel_enable_single_step(regs);
719 }
720 }
721 }
722 NOKPROBE_SYMBOL(do_breakpoint);
723
724 /*
725 * Arm64 hardware does not always report a watchpoint hit address that matches
726 * one of the watchpoints set. It can also report an address "near" the
727 * watchpoint if a single instruction access both watched and unwatched
728 * addresses. There is no straight-forward way, short of disassembling the
729 * offending instruction, to map that address back to the watchpoint. This
730 * function computes the distance of the memory access from the watchpoint as a
731 * heuristic for the likelihood that a given access triggered the watchpoint.
732 *
733 * See Section D2.10.5 "Determining the memory location that caused a Watchpoint
734 * exception" of ARMv8 Architecture Reference Manual for details.
735 *
736 * The function returns the distance of the address from the bytes watched by
737 * the watchpoint. In case of an exact match, it returns 0.
738 */
get_distance_from_watchpoint(unsigned long addr,u64 val,struct arch_hw_breakpoint_ctrl * ctrl)739 static u64 get_distance_from_watchpoint(unsigned long addr, u64 val,
740 struct arch_hw_breakpoint_ctrl *ctrl)
741 {
742 u64 wp_low, wp_high;
743 u32 lens, lene;
744
745 addr = untagged_addr(addr);
746
747 lens = __ffs(ctrl->len);
748 lene = __fls(ctrl->len);
749
750 wp_low = val + lens;
751 wp_high = val + lene;
752 if (addr < wp_low)
753 return wp_low - addr;
754 else if (addr > wp_high)
755 return addr - wp_high;
756 else
757 return 0;
758 }
759
watchpoint_report(struct perf_event * wp,unsigned long addr,struct pt_regs * regs)760 static int watchpoint_report(struct perf_event *wp, unsigned long addr,
761 struct pt_regs *regs)
762 {
763 int step = is_default_overflow_handler(wp);
764 struct arch_hw_breakpoint *info = counter_arch_bp(wp);
765
766 info->trigger = addr;
767
768 /*
769 * If we triggered a user watchpoint from a uaccess routine, then
770 * handle the stepping ourselves since userspace really can't help
771 * us with this.
772 */
773 if (!user_mode(regs) && info->ctrl.privilege == AARCH64_BREAKPOINT_EL0)
774 step = 1;
775 else
776 perf_bp_event(wp, regs);
777
778 return step;
779 }
780
do_watchpoint(unsigned long addr,unsigned long esr,struct pt_regs * regs)781 void do_watchpoint(unsigned long addr, unsigned long esr, struct pt_regs *regs)
782 {
783 int i, step = 0, *kernel_step, access, closest_match = 0;
784 u64 min_dist = -1, dist;
785 u32 ctrl_reg;
786 u64 val;
787 struct perf_event *wp, **slots;
788 struct debug_info *debug_info;
789 struct arch_hw_breakpoint_ctrl ctrl;
790
791 slots = this_cpu_ptr(wp_on_reg);
792 debug_info = ¤t->thread.debug;
793
794 /*
795 * Find all watchpoints that match the reported address. If no exact
796 * match is found. Attribute the hit to the closest watchpoint.
797 */
798 rcu_read_lock();
799 for (i = 0; i < core_num_wrps; ++i) {
800 wp = slots[i];
801 if (wp == NULL)
802 continue;
803
804 /*
805 * Check that the access type matches.
806 * 0 => load, otherwise => store
807 */
808 access = (esr & ESR_ELx_WNR) ? HW_BREAKPOINT_W :
809 HW_BREAKPOINT_R;
810 if (!(access & hw_breakpoint_type(wp)))
811 continue;
812
813 /* Check if the watchpoint value and byte select match. */
814 val = read_wb_reg(AARCH64_DBG_REG_WVR, i);
815 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i);
816 decode_ctrl_reg(ctrl_reg, &ctrl);
817 dist = get_distance_from_watchpoint(addr, val, &ctrl);
818 if (dist < min_dist) {
819 min_dist = dist;
820 closest_match = i;
821 }
822 /* Is this an exact match? */
823 if (dist != 0)
824 continue;
825
826 step = watchpoint_report(wp, addr, regs);
827 }
828
829 /* No exact match found? */
830 if (min_dist > 0 && min_dist != -1)
831 step = watchpoint_report(slots[closest_match], addr, regs);
832
833 rcu_read_unlock();
834
835 if (!step)
836 return;
837
838 /*
839 * We always disable EL0 watchpoints because the kernel can
840 * cause these to fire via an unprivileged access.
841 */
842 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 0);
843
844 if (user_mode(regs)) {
845 debug_info->wps_disabled = 1;
846
847 /* If we're already stepping a breakpoint, just return. */
848 if (debug_info->bps_disabled)
849 return;
850
851 if (test_thread_flag(TIF_SINGLESTEP))
852 debug_info->suspended_step = 1;
853 else
854 user_enable_single_step(current);
855 } else {
856 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 0);
857 kernel_step = this_cpu_ptr(&stepping_kernel_bp);
858
859 if (*kernel_step != ARM_KERNEL_STEP_NONE)
860 return;
861
862 if (kernel_active_single_step()) {
863 *kernel_step = ARM_KERNEL_STEP_SUSPEND;
864 } else {
865 *kernel_step = ARM_KERNEL_STEP_ACTIVE;
866 kernel_enable_single_step(regs);
867 }
868 }
869 }
870 NOKPROBE_SYMBOL(do_watchpoint);
871
872 /*
873 * Handle single-step exception.
874 */
try_step_suspended_breakpoints(struct pt_regs * regs)875 bool try_step_suspended_breakpoints(struct pt_regs *regs)
876 {
877 struct debug_info *debug_info = ¤t->thread.debug;
878 int *kernel_step = this_cpu_ptr(&stepping_kernel_bp);
879 bool handled_exception = false;
880
881 /*
882 * Called from single-step exception entry.
883 * Return true if we stepped a breakpoint and can resume execution,
884 * false if we need to handle a single-step.
885 */
886 if (user_mode(regs)) {
887 if (debug_info->bps_disabled) {
888 debug_info->bps_disabled = 0;
889 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 1);
890 handled_exception = true;
891 }
892
893 if (debug_info->wps_disabled) {
894 debug_info->wps_disabled = 0;
895 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
896 handled_exception = true;
897 }
898
899 if (handled_exception) {
900 if (debug_info->suspended_step) {
901 debug_info->suspended_step = 0;
902 /* Allow exception handling to fall-through. */
903 handled_exception = false;
904 } else {
905 user_disable_single_step(current);
906 }
907 }
908 } else if (*kernel_step != ARM_KERNEL_STEP_NONE) {
909 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 1);
910 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 1);
911
912 if (!debug_info->wps_disabled)
913 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
914
915 if (*kernel_step != ARM_KERNEL_STEP_SUSPEND) {
916 kernel_disable_single_step();
917 handled_exception = true;
918 } else {
919 handled_exception = false;
920 }
921
922 *kernel_step = ARM_KERNEL_STEP_NONE;
923 }
924
925 return handled_exception;
926 }
927 NOKPROBE_SYMBOL(try_step_suspended_breakpoints);
928
929 /*
930 * Context-switcher for restoring suspended CPU-bound breakpoints.
931 *
932 * Breakpoints of the previous task are uninstalled before
933 * this function is called, in perf_event_task_sched_out(), and those
934 * of the next task are installed after, in perf_event_task_sched_in().
935 */
hw_breakpoint_thread_switch(struct task_struct * next)936 void hw_breakpoint_thread_switch(struct task_struct *next)
937 {
938 /*
939 * current next
940 * disabled: 0 0 => The usual case, NOTIFY_DONE
941 * 0 1 => Disable the registers
942 * 1 0 => Enable the registers
943 * 1 1 => NOTIFY_DONE. per-task bps will
944 * get taken care of by perf.
945 */
946
947 struct debug_info *current_debug_info, *next_debug_info;
948 unsigned long daif = local_daif_save();
949
950 current_debug_info = ¤t->thread.debug;
951 next_debug_info = &next->thread.debug;
952
953 /* Update breakpoints. */
954 if (current_debug_info->bps_disabled != next_debug_info->bps_disabled)
955 toggle_bp_registers(AARCH64_DBG_REG_BCR,
956 DBG_ACTIVE_EL0,
957 !next_debug_info->bps_disabled);
958
959 /* Update watchpoints. */
960 if (current_debug_info->wps_disabled != next_debug_info->wps_disabled)
961 toggle_bp_registers(AARCH64_DBG_REG_WCR,
962 DBG_ACTIVE_EL0,
963 !next_debug_info->wps_disabled);
964
965 local_daif_restore(daif);
966 }
967
968 /*
969 * CPU initialisation.
970 */
hw_breakpoint_reset(unsigned int cpu)971 static int hw_breakpoint_reset(unsigned int cpu)
972 {
973 int i;
974 struct perf_event **slots;
975 /*
976 * When a CPU goes through cold-boot, it does not have any installed
977 * slot, so it is safe to share the same function for restoring and
978 * resetting breakpoints; when a CPU is hotplugged in, it goes
979 * through the slots, which are all empty, hence it just resets control
980 * and value for debug registers.
981 * When this function is triggered on warm-boot through a CPU PM
982 * notifier some slots might be initialized; if so they are
983 * reprogrammed according to the debug slots content.
984 */
985 for (slots = this_cpu_ptr(bp_on_reg), i = 0; i < core_num_brps; ++i) {
986 if (slots[i]) {
987 hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
988 } else {
989 write_wb_reg(AARCH64_DBG_REG_BCR, i, 0UL);
990 write_wb_reg(AARCH64_DBG_REG_BVR, i, 0UL);
991 }
992 }
993
994 for (slots = this_cpu_ptr(wp_on_reg), i = 0; i < core_num_wrps; ++i) {
995 if (slots[i]) {
996 hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
997 } else {
998 write_wb_reg(AARCH64_DBG_REG_WCR, i, 0UL);
999 write_wb_reg(AARCH64_DBG_REG_WVR, i, 0UL);
1000 }
1001 }
1002
1003 return 0;
1004 }
1005
1006 /*
1007 * One-time initialisation.
1008 */
arch_hw_breakpoint_init(void)1009 static int __init arch_hw_breakpoint_init(void)
1010 {
1011 int ret;
1012
1013 core_num_brps = get_num_brps();
1014 core_num_wrps = get_num_wrps();
1015
1016 pr_info("found %d breakpoint and %d watchpoint registers.\n",
1017 core_num_brps, core_num_wrps);
1018
1019 /*
1020 * Reset the breakpoint resources. We assume that a halting
1021 * debugger will leave the world in a nice state for us.
1022 */
1023 ret = cpuhp_setup_state(CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING,
1024 "perf/arm64/hw_breakpoint:starting",
1025 hw_breakpoint_reset, NULL);
1026 if (ret)
1027 pr_err("failed to register CPU hotplug notifier: %d\n", ret);
1028
1029 /* Register cpu_suspend hw breakpoint restore hook */
1030 cpu_suspend_set_dbg_restorer(hw_breakpoint_reset);
1031
1032 return ret;
1033 }
1034 arch_initcall(arch_hw_breakpoint_init);
1035
hw_breakpoint_pmu_read(struct perf_event * bp)1036 void hw_breakpoint_pmu_read(struct perf_event *bp)
1037 {
1038 }
1039
1040 /*
1041 * Dummy function to register with die_notifier.
1042 */
hw_breakpoint_exceptions_notify(struct notifier_block * unused,unsigned long val,void * data)1043 int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
1044 unsigned long val, void *data)
1045 {
1046 return NOTIFY_DONE;
1047 }
1048