1 /* SPDX-License-Identifier: MIT */ 2 3 /* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ 4 5 #ifndef __NVRM_FBSR_H__ 6 #define __NVRM_FBSR_H__ 7 #include <nvrm/nvtypes.h> 8 9 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/570.144 */ 10 11 #define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */ 12 typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS { 13 NvHandle hClient; 14 NvHandle hSysMem; 15 NvBool bEnteringGcoffState; 16 NV_DECLARE_ALIGNED(NvU64 sysmemAddrOfSuspendResumeData, 8); 17 } NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS; 18 19 #define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO (0x801306) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID" */ 20 21 typedef struct NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS { 22 NV_DECLARE_ALIGNED(NvU64 Size, 8); 23 NV_DECLARE_ALIGNED(NvU64 Address, 8); 24 NvU32 AddressSpace; 25 NvU32 MaxCompbitLine; 26 NvU32 comptagsPerCacheLine; 27 NvU32 cacheLineSize; 28 NvU32 cacheLineSizePerSlice; 29 NvU32 cacheLineFetchAlignment; 30 NV_DECLARE_ALIGNED(NvU64 backingStoreBase, 8); 31 NvU32 gobsPerComptagPerSlice; 32 NvU32 backingStoreCbcBase; 33 NvU32 comptaglineAllocationPolicy; 34 NV_DECLARE_ALIGNED(NvU64 privRegionStartOffset, 8); 35 NvU32 cbcCoveragePerSlice; 36 } NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS; 37 38 #define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN 0 // ADDR_UNKNOWN 39 #define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM 1 // ADDR_SYSMEM 40 #define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM 2 // ADDR_FBMEM 41 42 #define NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE (0x20800a6f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID" */ 43 44 typedef struct NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS { 45 NvBool bRawMode; 46 } NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS; 47 48 #endif 49