1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016 AmLogic, Inc. 4 * Michael Turquette <mturquette@baylibre.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/init.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/platform_device.h> 11 #include <linux/module.h> 12 13 #include "clk-regmap.h" 14 #include "clk-pll.h" 15 #include "clk-mpll.h" 16 #include "meson-clkc-utils.h" 17 #include "vid-pll-div.h" 18 19 #include <dt-bindings/clock/gxbb-clkc.h> 20 21 #define SCR 0x2c 22 #define TIMEOUT_VALUE 0x3c 23 24 #define HHI_GP0_PLL_CNTL 0x40 25 #define HHI_GP0_PLL_CNTL2 0x44 26 #define HHI_GP0_PLL_CNTL3 0x48 27 #define HHI_GP0_PLL_CNTL4 0x4c 28 #define HHI_GP0_PLL_CNTL5 0x50 29 #define HHI_GP0_PLL_CNTL1 0x58 30 31 #define HHI_XTAL_DIVN_CNTL 0xbc 32 #define HHI_TIMER90K 0xec 33 34 #define HHI_MEM_PD_REG0 0x100 35 #define HHI_MEM_PD_REG1 0x104 36 #define HHI_VPU_MEM_PD_REG1 0x108 37 #define HHI_VIID_CLK_DIV 0x128 38 #define HHI_VIID_CLK_CNTL 0x12c 39 40 #define HHI_GCLK_MPEG0 0x140 41 #define HHI_GCLK_MPEG1 0x144 42 #define HHI_GCLK_MPEG2 0x148 43 #define HHI_GCLK_OTHER 0x150 44 #define HHI_GCLK_AO 0x154 45 #define HHI_SYS_OSCIN_CNTL 0x158 46 #define HHI_SYS_CPU_CLK_CNTL1 0x15c 47 #define HHI_SYS_CPU_RESET_CNTL 0x160 48 #define HHI_VID_CLK_DIV 0x164 49 50 #define HHI_MPEG_CLK_CNTL 0x174 51 #define HHI_AUD_CLK_CNTL 0x178 52 #define HHI_VID_CLK_CNTL 0x17c 53 #define HHI_AUD_CLK_CNTL2 0x190 54 #define HHI_VID_CLK_CNTL2 0x194 55 #define HHI_SYS_CPU_CLK_CNTL0 0x19c 56 #define HHI_VID_PLL_CLK_DIV 0x1a0 57 #define HHI_AUD_CLK_CNTL3 0x1a4 58 #define HHI_MALI_CLK_CNTL 0x1b0 59 #define HHI_VPU_CLK_CNTL 0x1bc 60 61 #define HHI_HDMI_CLK_CNTL 0x1cc 62 #define HHI_VDEC_CLK_CNTL 0x1e0 63 #define HHI_VDEC2_CLK_CNTL 0x1e4 64 #define HHI_VDEC3_CLK_CNTL 0x1e8 65 #define HHI_VDEC4_CLK_CNTL 0x1ec 66 #define HHI_HDCP22_CLK_CNTL 0x1f0 67 #define HHI_VAPBCLK_CNTL 0x1f4 68 69 #define HHI_VPU_CLKB_CNTL 0x20c 70 #define HHI_USB_CLK_CNTL 0x220 71 #define HHI_32K_CLK_CNTL 0x224 72 #define HHI_GEN_CLK_CNTL 0x228 73 74 #define HHI_PCM_CLK_CNTL 0x258 75 #define HHI_NAND_CLK_CNTL 0x25c 76 #define HHI_SD_EMMC_CLK_CNTL 0x264 77 78 #define HHI_MPLL_CNTL 0x280 79 #define HHI_MPLL_CNTL2 0x284 80 #define HHI_MPLL_CNTL3 0x288 81 #define HHI_MPLL_CNTL4 0x28c 82 #define HHI_MPLL_CNTL5 0x290 83 #define HHI_MPLL_CNTL6 0x294 84 #define HHI_MPLL_CNTL7 0x298 85 #define HHI_MPLL_CNTL8 0x29c 86 #define HHI_MPLL_CNTL9 0x2a0 87 #define HHI_MPLL_CNTL10 0x2a4 88 89 #define HHI_MPLL3_CNTL0 0x2e0 90 #define HHI_MPLL3_CNTL1 0x2e4 91 #define HHI_VDAC_CNTL0 0x2f4 92 #define HHI_VDAC_CNTL1 0x2f8 93 94 #define HHI_SYS_PLL_CNTL 0x300 95 #define HHI_SYS_PLL_CNTL2 0x304 96 #define HHI_SYS_PLL_CNTL3 0x308 97 #define HHI_SYS_PLL_CNTL4 0x30c 98 #define HHI_SYS_PLL_CNTL5 0x310 99 #define HHI_DPLL_TOP_I 0x318 100 #define HHI_DPLL_TOP2_I 0x31c 101 #define HHI_HDMI_PLL_CNTL 0x320 102 #define HHI_HDMI_PLL_CNTL2 0x324 103 #define HHI_HDMI_PLL_CNTL3 0x328 104 #define HHI_HDMI_PLL_CNTL4 0x32c 105 #define HHI_HDMI_PLL_CNTL5 0x330 106 #define HHI_HDMI_PLL_CNTL6 0x334 107 #define HHI_HDMI_PLL_CNTL_I 0x338 108 #define HHI_HDMI_PLL_CNTL7 0x33c 109 110 #define HHI_HDMI_PHY_CNTL0 0x3a0 111 #define HHI_HDMI_PHY_CNTL1 0x3a4 112 #define HHI_HDMI_PHY_CNTL2 0x3a8 113 #define HHI_HDMI_PHY_CNTL3 0x3ac 114 115 #define HHI_VID_LOCK_CLK_CNTL 0x3c8 116 #define HHI_BT656_CLK_CNTL 0x3d4 117 #define HHI_SAR_CLK_CNTL 0x3d8 118 119 static struct clk_regmap gxbb_fixed_pll_dco = { 120 .data = &(struct meson_clk_pll_data){ 121 .en = { 122 .reg_off = HHI_MPLL_CNTL, 123 .shift = 30, 124 .width = 1, 125 }, 126 .m = { 127 .reg_off = HHI_MPLL_CNTL, 128 .shift = 0, 129 .width = 9, 130 }, 131 .n = { 132 .reg_off = HHI_MPLL_CNTL, 133 .shift = 9, 134 .width = 5, 135 }, 136 .frac = { 137 .reg_off = HHI_MPLL_CNTL2, 138 .shift = 0, 139 .width = 12, 140 }, 141 .l = { 142 .reg_off = HHI_MPLL_CNTL, 143 .shift = 31, 144 .width = 1, 145 }, 146 .rst = { 147 .reg_off = HHI_MPLL_CNTL, 148 .shift = 29, 149 .width = 1, 150 }, 151 }, 152 .hw.init = &(struct clk_init_data){ 153 .name = "fixed_pll_dco", 154 .ops = &meson_clk_pll_ro_ops, 155 .parent_data = &(const struct clk_parent_data) { 156 .fw_name = "xtal", 157 }, 158 .num_parents = 1, 159 }, 160 }; 161 162 static struct clk_regmap gxbb_fixed_pll = { 163 .data = &(struct clk_regmap_div_data){ 164 .offset = HHI_MPLL_CNTL, 165 .shift = 16, 166 .width = 2, 167 .flags = CLK_DIVIDER_POWER_OF_TWO, 168 }, 169 .hw.init = &(struct clk_init_data){ 170 .name = "fixed_pll", 171 .ops = &clk_regmap_divider_ro_ops, 172 .parent_hws = (const struct clk_hw *[]) { 173 &gxbb_fixed_pll_dco.hw 174 }, 175 .num_parents = 1, 176 /* 177 * This clock won't ever change at runtime so 178 * CLK_SET_RATE_PARENT is not required 179 */ 180 }, 181 }; 182 183 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { 184 .mult = 2, 185 .div = 1, 186 .hw.init = &(struct clk_init_data){ 187 .name = "hdmi_pll_pre_mult", 188 .ops = &clk_fixed_factor_ops, 189 .parent_data = &(const struct clk_parent_data) { 190 .fw_name = "xtal", 191 }, 192 .num_parents = 1, 193 }, 194 }; 195 196 static struct clk_regmap gxbb_hdmi_pll_dco = { 197 .data = &(struct meson_clk_pll_data){ 198 .en = { 199 .reg_off = HHI_HDMI_PLL_CNTL, 200 .shift = 30, 201 .width = 1, 202 }, 203 .m = { 204 .reg_off = HHI_HDMI_PLL_CNTL, 205 .shift = 0, 206 .width = 9, 207 }, 208 .n = { 209 .reg_off = HHI_HDMI_PLL_CNTL, 210 .shift = 9, 211 .width = 5, 212 }, 213 .frac = { 214 .reg_off = HHI_HDMI_PLL_CNTL2, 215 .shift = 0, 216 .width = 12, 217 }, 218 .l = { 219 .reg_off = HHI_HDMI_PLL_CNTL, 220 .shift = 31, 221 .width = 1, 222 }, 223 .rst = { 224 .reg_off = HHI_HDMI_PLL_CNTL, 225 .shift = 28, 226 .width = 1, 227 }, 228 }, 229 .hw.init = &(struct clk_init_data){ 230 .name = "hdmi_pll_dco", 231 .ops = &meson_clk_pll_ro_ops, 232 .parent_hws = (const struct clk_hw *[]) { 233 &gxbb_hdmi_pll_pre_mult.hw 234 }, 235 .num_parents = 1, 236 /* 237 * Display directly handle hdmi pll registers ATM, we need 238 * NOCACHE to keep our view of the clock as accurate as possible 239 */ 240 .flags = CLK_GET_RATE_NOCACHE, 241 }, 242 }; 243 244 static struct clk_regmap gxl_hdmi_pll_dco = { 245 .data = &(struct meson_clk_pll_data){ 246 .en = { 247 .reg_off = HHI_HDMI_PLL_CNTL, 248 .shift = 30, 249 .width = 1, 250 }, 251 .m = { 252 .reg_off = HHI_HDMI_PLL_CNTL, 253 .shift = 0, 254 .width = 9, 255 }, 256 .n = { 257 .reg_off = HHI_HDMI_PLL_CNTL, 258 .shift = 9, 259 .width = 5, 260 }, 261 /* 262 * On gxl, there is a register shift due to 263 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb, 264 * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB 265 * instead which is defined at the same offset. 266 */ 267 .frac = { 268 .reg_off = HHI_HDMI_PLL_CNTL2, 269 .shift = 0, 270 .width = 10, 271 }, 272 .l = { 273 .reg_off = HHI_HDMI_PLL_CNTL, 274 .shift = 31, 275 .width = 1, 276 }, 277 .rst = { 278 .reg_off = HHI_HDMI_PLL_CNTL, 279 .shift = 28, 280 .width = 1, 281 }, 282 }, 283 .hw.init = &(struct clk_init_data){ 284 .name = "hdmi_pll_dco", 285 .ops = &meson_clk_pll_ro_ops, 286 .parent_data = &(const struct clk_parent_data) { 287 .fw_name = "xtal", 288 }, 289 .num_parents = 1, 290 /* 291 * Display directly handle hdmi pll registers ATM, we need 292 * NOCACHE to keep our view of the clock as accurate as possible 293 */ 294 .flags = CLK_GET_RATE_NOCACHE, 295 }, 296 }; 297 298 static struct clk_regmap gxbb_hdmi_pll_od = { 299 .data = &(struct clk_regmap_div_data){ 300 .offset = HHI_HDMI_PLL_CNTL2, 301 .shift = 16, 302 .width = 2, 303 .flags = CLK_DIVIDER_POWER_OF_TWO, 304 }, 305 .hw.init = &(struct clk_init_data){ 306 .name = "hdmi_pll_od", 307 .ops = &clk_regmap_divider_ro_ops, 308 .parent_hws = (const struct clk_hw *[]) { 309 &gxbb_hdmi_pll_dco.hw 310 }, 311 .num_parents = 1, 312 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 313 }, 314 }; 315 316 static struct clk_regmap gxbb_hdmi_pll_od2 = { 317 .data = &(struct clk_regmap_div_data){ 318 .offset = HHI_HDMI_PLL_CNTL2, 319 .shift = 22, 320 .width = 2, 321 .flags = CLK_DIVIDER_POWER_OF_TWO, 322 }, 323 .hw.init = &(struct clk_init_data){ 324 .name = "hdmi_pll_od2", 325 .ops = &clk_regmap_divider_ro_ops, 326 .parent_hws = (const struct clk_hw *[]) { 327 &gxbb_hdmi_pll_od.hw 328 }, 329 .num_parents = 1, 330 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 331 }, 332 }; 333 334 static struct clk_regmap gxbb_hdmi_pll = { 335 .data = &(struct clk_regmap_div_data){ 336 .offset = HHI_HDMI_PLL_CNTL2, 337 .shift = 18, 338 .width = 2, 339 .flags = CLK_DIVIDER_POWER_OF_TWO, 340 }, 341 .hw.init = &(struct clk_init_data){ 342 .name = "hdmi_pll", 343 .ops = &clk_regmap_divider_ro_ops, 344 .parent_hws = (const struct clk_hw *[]) { 345 &gxbb_hdmi_pll_od2.hw 346 }, 347 .num_parents = 1, 348 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 349 }, 350 }; 351 352 static struct clk_regmap gxl_hdmi_pll_od = { 353 .data = &(struct clk_regmap_div_data){ 354 .offset = HHI_HDMI_PLL_CNTL + 8, 355 .shift = 21, 356 .width = 2, 357 .flags = CLK_DIVIDER_POWER_OF_TWO, 358 }, 359 .hw.init = &(struct clk_init_data){ 360 .name = "hdmi_pll_od", 361 .ops = &clk_regmap_divider_ro_ops, 362 .parent_hws = (const struct clk_hw *[]) { 363 &gxl_hdmi_pll_dco.hw 364 }, 365 .num_parents = 1, 366 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 367 }, 368 }; 369 370 static struct clk_regmap gxl_hdmi_pll_od2 = { 371 .data = &(struct clk_regmap_div_data){ 372 .offset = HHI_HDMI_PLL_CNTL + 8, 373 .shift = 23, 374 .width = 2, 375 .flags = CLK_DIVIDER_POWER_OF_TWO, 376 }, 377 .hw.init = &(struct clk_init_data){ 378 .name = "hdmi_pll_od2", 379 .ops = &clk_regmap_divider_ro_ops, 380 .parent_hws = (const struct clk_hw *[]) { 381 &gxl_hdmi_pll_od.hw 382 }, 383 .num_parents = 1, 384 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 385 }, 386 }; 387 388 static struct clk_regmap gxl_hdmi_pll = { 389 .data = &(struct clk_regmap_div_data){ 390 .offset = HHI_HDMI_PLL_CNTL + 8, 391 .shift = 19, 392 .width = 2, 393 .flags = CLK_DIVIDER_POWER_OF_TWO, 394 }, 395 .hw.init = &(struct clk_init_data){ 396 .name = "hdmi_pll", 397 .ops = &clk_regmap_divider_ro_ops, 398 .parent_hws = (const struct clk_hw *[]) { 399 &gxl_hdmi_pll_od2.hw 400 }, 401 .num_parents = 1, 402 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 403 }, 404 }; 405 406 static struct clk_regmap gxbb_sys_pll_dco = { 407 .data = &(struct meson_clk_pll_data){ 408 .en = { 409 .reg_off = HHI_SYS_PLL_CNTL, 410 .shift = 30, 411 .width = 1, 412 }, 413 .m = { 414 .reg_off = HHI_SYS_PLL_CNTL, 415 .shift = 0, 416 .width = 9, 417 }, 418 .n = { 419 .reg_off = HHI_SYS_PLL_CNTL, 420 .shift = 9, 421 .width = 5, 422 }, 423 .l = { 424 .reg_off = HHI_SYS_PLL_CNTL, 425 .shift = 31, 426 .width = 1, 427 }, 428 .rst = { 429 .reg_off = HHI_SYS_PLL_CNTL, 430 .shift = 29, 431 .width = 1, 432 }, 433 }, 434 .hw.init = &(struct clk_init_data){ 435 .name = "sys_pll_dco", 436 .ops = &meson_clk_pll_ro_ops, 437 .parent_data = &(const struct clk_parent_data) { 438 .fw_name = "xtal", 439 }, 440 .num_parents = 1, 441 }, 442 }; 443 444 static struct clk_regmap gxbb_sys_pll = { 445 .data = &(struct clk_regmap_div_data){ 446 .offset = HHI_SYS_PLL_CNTL, 447 .shift = 10, 448 .width = 2, 449 .flags = CLK_DIVIDER_POWER_OF_TWO, 450 }, 451 .hw.init = &(struct clk_init_data){ 452 .name = "sys_pll", 453 .ops = &clk_regmap_divider_ro_ops, 454 .parent_hws = (const struct clk_hw *[]) { 455 &gxbb_sys_pll_dco.hw 456 }, 457 .num_parents = 1, 458 .flags = CLK_SET_RATE_PARENT, 459 }, 460 }; 461 462 static const struct pll_params_table gxbb_gp0_pll_params_table[] = { 463 PLL_PARAMS(32, 1), 464 PLL_PARAMS(33, 1), 465 PLL_PARAMS(34, 1), 466 PLL_PARAMS(35, 1), 467 PLL_PARAMS(36, 1), 468 PLL_PARAMS(37, 1), 469 PLL_PARAMS(38, 1), 470 PLL_PARAMS(39, 1), 471 PLL_PARAMS(40, 1), 472 PLL_PARAMS(41, 1), 473 PLL_PARAMS(42, 1), 474 PLL_PARAMS(43, 1), 475 PLL_PARAMS(44, 1), 476 PLL_PARAMS(45, 1), 477 PLL_PARAMS(46, 1), 478 PLL_PARAMS(47, 1), 479 PLL_PARAMS(48, 1), 480 PLL_PARAMS(49, 1), 481 PLL_PARAMS(50, 1), 482 PLL_PARAMS(51, 1), 483 PLL_PARAMS(52, 1), 484 PLL_PARAMS(53, 1), 485 PLL_PARAMS(54, 1), 486 PLL_PARAMS(55, 1), 487 PLL_PARAMS(56, 1), 488 PLL_PARAMS(57, 1), 489 PLL_PARAMS(58, 1), 490 PLL_PARAMS(59, 1), 491 PLL_PARAMS(60, 1), 492 PLL_PARAMS(61, 1), 493 PLL_PARAMS(62, 1), 494 { /* sentinel */ }, 495 }; 496 497 static const struct reg_sequence gxbb_gp0_pll_init_regs[] = { 498 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, 499 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, 500 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, 501 }; 502 503 static struct clk_regmap gxbb_gp0_pll_dco = { 504 .data = &(struct meson_clk_pll_data){ 505 .en = { 506 .reg_off = HHI_GP0_PLL_CNTL, 507 .shift = 30, 508 .width = 1, 509 }, 510 .m = { 511 .reg_off = HHI_GP0_PLL_CNTL, 512 .shift = 0, 513 .width = 9, 514 }, 515 .n = { 516 .reg_off = HHI_GP0_PLL_CNTL, 517 .shift = 9, 518 .width = 5, 519 }, 520 .l = { 521 .reg_off = HHI_GP0_PLL_CNTL, 522 .shift = 31, 523 .width = 1, 524 }, 525 .rst = { 526 .reg_off = HHI_GP0_PLL_CNTL, 527 .shift = 29, 528 .width = 1, 529 }, 530 .table = gxbb_gp0_pll_params_table, 531 .init_regs = gxbb_gp0_pll_init_regs, 532 .init_count = ARRAY_SIZE(gxbb_gp0_pll_init_regs), 533 }, 534 .hw.init = &(struct clk_init_data){ 535 .name = "gp0_pll_dco", 536 .ops = &meson_clk_pll_ops, 537 .parent_data = &(const struct clk_parent_data) { 538 .fw_name = "xtal", 539 }, 540 .num_parents = 1, 541 }, 542 }; 543 544 static const struct pll_params_table gxl_gp0_pll_params_table[] = { 545 PLL_PARAMS(42, 1), 546 PLL_PARAMS(43, 1), 547 PLL_PARAMS(44, 1), 548 PLL_PARAMS(45, 1), 549 PLL_PARAMS(46, 1), 550 PLL_PARAMS(47, 1), 551 PLL_PARAMS(48, 1), 552 PLL_PARAMS(49, 1), 553 PLL_PARAMS(50, 1), 554 PLL_PARAMS(51, 1), 555 PLL_PARAMS(52, 1), 556 PLL_PARAMS(53, 1), 557 PLL_PARAMS(54, 1), 558 PLL_PARAMS(55, 1), 559 PLL_PARAMS(56, 1), 560 PLL_PARAMS(57, 1), 561 PLL_PARAMS(58, 1), 562 PLL_PARAMS(59, 1), 563 PLL_PARAMS(60, 1), 564 PLL_PARAMS(61, 1), 565 PLL_PARAMS(62, 1), 566 PLL_PARAMS(63, 1), 567 PLL_PARAMS(64, 1), 568 PLL_PARAMS(65, 1), 569 PLL_PARAMS(66, 1), 570 { /* sentinel */ }, 571 }; 572 573 static const struct reg_sequence gxl_gp0_pll_init_regs[] = { 574 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 575 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 576 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 577 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 578 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 579 }; 580 581 static struct clk_regmap gxl_gp0_pll_dco = { 582 .data = &(struct meson_clk_pll_data){ 583 .en = { 584 .reg_off = HHI_GP0_PLL_CNTL, 585 .shift = 30, 586 .width = 1, 587 }, 588 .m = { 589 .reg_off = HHI_GP0_PLL_CNTL, 590 .shift = 0, 591 .width = 9, 592 }, 593 .n = { 594 .reg_off = HHI_GP0_PLL_CNTL, 595 .shift = 9, 596 .width = 5, 597 }, 598 .frac = { 599 .reg_off = HHI_GP0_PLL_CNTL1, 600 .shift = 0, 601 .width = 10, 602 }, 603 .l = { 604 .reg_off = HHI_GP0_PLL_CNTL, 605 .shift = 31, 606 .width = 1, 607 }, 608 .rst = { 609 .reg_off = HHI_GP0_PLL_CNTL, 610 .shift = 29, 611 .width = 1, 612 }, 613 .table = gxl_gp0_pll_params_table, 614 .init_regs = gxl_gp0_pll_init_regs, 615 .init_count = ARRAY_SIZE(gxl_gp0_pll_init_regs), 616 }, 617 .hw.init = &(struct clk_init_data){ 618 .name = "gp0_pll_dco", 619 .ops = &meson_clk_pll_ops, 620 .parent_data = &(const struct clk_parent_data) { 621 .fw_name = "xtal", 622 }, 623 .num_parents = 1, 624 }, 625 }; 626 627 static struct clk_regmap gxbb_gp0_pll = { 628 .data = &(struct clk_regmap_div_data){ 629 .offset = HHI_GP0_PLL_CNTL, 630 .shift = 16, 631 .width = 2, 632 .flags = CLK_DIVIDER_POWER_OF_TWO, 633 }, 634 .hw.init = &(struct clk_init_data){ 635 .name = "gp0_pll", 636 .ops = &clk_regmap_divider_ops, 637 .parent_data = &(const struct clk_parent_data) { 638 /* 639 * Note: 640 * GXL and GXBB have different gp0_pll_dco (with 641 * different struct clk_hw). We fallback to the global 642 * naming string mechanism so gp0_pll picks up the 643 * appropriate one. 644 */ 645 .name = "gp0_pll_dco", 646 .index = -1, 647 }, 648 .num_parents = 1, 649 .flags = CLK_SET_RATE_PARENT, 650 }, 651 }; 652 653 static struct clk_fixed_factor gxbb_fclk_div2_div = { 654 .mult = 1, 655 .div = 2, 656 .hw.init = &(struct clk_init_data){ 657 .name = "fclk_div2_div", 658 .ops = &clk_fixed_factor_ops, 659 .parent_hws = (const struct clk_hw *[]) { 660 &gxbb_fixed_pll.hw 661 }, 662 .num_parents = 1, 663 }, 664 }; 665 666 static struct clk_regmap gxbb_fclk_div2 = { 667 .data = &(struct clk_regmap_gate_data){ 668 .offset = HHI_MPLL_CNTL6, 669 .bit_idx = 27, 670 }, 671 .hw.init = &(struct clk_init_data){ 672 .name = "fclk_div2", 673 .ops = &clk_regmap_gate_ops, 674 .parent_hws = (const struct clk_hw *[]) { 675 &gxbb_fclk_div2_div.hw 676 }, 677 .num_parents = 1, 678 .flags = CLK_IS_CRITICAL, 679 }, 680 }; 681 682 static struct clk_fixed_factor gxbb_fclk_div3_div = { 683 .mult = 1, 684 .div = 3, 685 .hw.init = &(struct clk_init_data){ 686 .name = "fclk_div3_div", 687 .ops = &clk_fixed_factor_ops, 688 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 689 .num_parents = 1, 690 }, 691 }; 692 693 static struct clk_regmap gxbb_fclk_div3 = { 694 .data = &(struct clk_regmap_gate_data){ 695 .offset = HHI_MPLL_CNTL6, 696 .bit_idx = 28, 697 }, 698 .hw.init = &(struct clk_init_data){ 699 .name = "fclk_div3", 700 .ops = &clk_regmap_gate_ops, 701 .parent_hws = (const struct clk_hw *[]) { 702 &gxbb_fclk_div3_div.hw 703 }, 704 .num_parents = 1, 705 /* 706 * FIXME: 707 * This clock, as fdiv2, is used by the SCPI FW and is required 708 * by the platform to operate correctly. 709 * Until the following condition are met, we need this clock to 710 * be marked as critical: 711 * a) The SCPI generic driver claims and enable all the clocks 712 * it needs 713 * b) CCF has a clock hand-off mechanism to make the sure the 714 * clock stays on until the proper driver comes along 715 */ 716 .flags = CLK_IS_CRITICAL, 717 }, 718 }; 719 720 static struct clk_fixed_factor gxbb_fclk_div4_div = { 721 .mult = 1, 722 .div = 4, 723 .hw.init = &(struct clk_init_data){ 724 .name = "fclk_div4_div", 725 .ops = &clk_fixed_factor_ops, 726 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 727 .num_parents = 1, 728 }, 729 }; 730 731 static struct clk_regmap gxbb_fclk_div4 = { 732 .data = &(struct clk_regmap_gate_data){ 733 .offset = HHI_MPLL_CNTL6, 734 .bit_idx = 29, 735 }, 736 .hw.init = &(struct clk_init_data){ 737 .name = "fclk_div4", 738 .ops = &clk_regmap_gate_ops, 739 .parent_hws = (const struct clk_hw *[]) { 740 &gxbb_fclk_div4_div.hw 741 }, 742 .num_parents = 1, 743 }, 744 }; 745 746 static struct clk_fixed_factor gxbb_fclk_div5_div = { 747 .mult = 1, 748 .div = 5, 749 .hw.init = &(struct clk_init_data){ 750 .name = "fclk_div5_div", 751 .ops = &clk_fixed_factor_ops, 752 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 753 .num_parents = 1, 754 }, 755 }; 756 757 static struct clk_regmap gxbb_fclk_div5 = { 758 .data = &(struct clk_regmap_gate_data){ 759 .offset = HHI_MPLL_CNTL6, 760 .bit_idx = 30, 761 }, 762 .hw.init = &(struct clk_init_data){ 763 .name = "fclk_div5", 764 .ops = &clk_regmap_gate_ops, 765 .parent_hws = (const struct clk_hw *[]) { 766 &gxbb_fclk_div5_div.hw 767 }, 768 .num_parents = 1, 769 }, 770 }; 771 772 static struct clk_fixed_factor gxbb_fclk_div7_div = { 773 .mult = 1, 774 .div = 7, 775 .hw.init = &(struct clk_init_data){ 776 .name = "fclk_div7_div", 777 .ops = &clk_fixed_factor_ops, 778 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 779 .num_parents = 1, 780 }, 781 }; 782 783 static struct clk_regmap gxbb_fclk_div7 = { 784 .data = &(struct clk_regmap_gate_data){ 785 .offset = HHI_MPLL_CNTL6, 786 .bit_idx = 31, 787 }, 788 .hw.init = &(struct clk_init_data){ 789 .name = "fclk_div7", 790 .ops = &clk_regmap_gate_ops, 791 .parent_hws = (const struct clk_hw *[]) { 792 &gxbb_fclk_div7_div.hw 793 }, 794 .num_parents = 1, 795 }, 796 }; 797 798 static struct clk_regmap gxbb_mpll_prediv = { 799 .data = &(struct clk_regmap_div_data){ 800 .offset = HHI_MPLL_CNTL5, 801 .shift = 12, 802 .width = 1, 803 }, 804 .hw.init = &(struct clk_init_data){ 805 .name = "mpll_prediv", 806 .ops = &clk_regmap_divider_ro_ops, 807 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 808 .num_parents = 1, 809 }, 810 }; 811 812 static struct clk_regmap gxbb_mpll0_div = { 813 .data = &(struct meson_clk_mpll_data){ 814 .sdm = { 815 .reg_off = HHI_MPLL_CNTL7, 816 .shift = 0, 817 .width = 14, 818 }, 819 .sdm_en = { 820 .reg_off = HHI_MPLL_CNTL, 821 .shift = 25, 822 .width = 1, 823 }, 824 .n2 = { 825 .reg_off = HHI_MPLL_CNTL7, 826 .shift = 16, 827 .width = 9, 828 }, 829 }, 830 .hw.init = &(struct clk_init_data){ 831 .name = "mpll0_div", 832 .ops = &meson_clk_mpll_ops, 833 .parent_hws = (const struct clk_hw *[]) { 834 &gxbb_mpll_prediv.hw 835 }, 836 .num_parents = 1, 837 }, 838 }; 839 840 static struct clk_regmap gxl_mpll0_div = { 841 .data = &(struct meson_clk_mpll_data){ 842 .sdm = { 843 .reg_off = HHI_MPLL_CNTL7, 844 .shift = 0, 845 .width = 14, 846 }, 847 .sdm_en = { 848 .reg_off = HHI_MPLL_CNTL7, 849 .shift = 15, 850 .width = 1, 851 }, 852 .n2 = { 853 .reg_off = HHI_MPLL_CNTL7, 854 .shift = 16, 855 .width = 9, 856 }, 857 }, 858 .hw.init = &(struct clk_init_data){ 859 .name = "mpll0_div", 860 .ops = &meson_clk_mpll_ops, 861 .parent_hws = (const struct clk_hw *[]) { 862 &gxbb_mpll_prediv.hw 863 }, 864 .num_parents = 1, 865 }, 866 }; 867 868 static struct clk_regmap gxbb_mpll0 = { 869 .data = &(struct clk_regmap_gate_data){ 870 .offset = HHI_MPLL_CNTL7, 871 .bit_idx = 14, 872 }, 873 .hw.init = &(struct clk_init_data){ 874 .name = "mpll0", 875 .ops = &clk_regmap_gate_ops, 876 .parent_data = &(const struct clk_parent_data) { 877 /* 878 * Note: 879 * GXL and GXBB have different SDM_EN registers. We 880 * fallback to the global naming string mechanism so 881 * mpll0_div picks up the appropriate one. 882 */ 883 .name = "mpll0_div", 884 .index = -1, 885 }, 886 .num_parents = 1, 887 .flags = CLK_SET_RATE_PARENT, 888 }, 889 }; 890 891 static struct clk_regmap gxbb_mpll1_div = { 892 .data = &(struct meson_clk_mpll_data){ 893 .sdm = { 894 .reg_off = HHI_MPLL_CNTL8, 895 .shift = 0, 896 .width = 14, 897 }, 898 .sdm_en = { 899 .reg_off = HHI_MPLL_CNTL8, 900 .shift = 15, 901 .width = 1, 902 }, 903 .n2 = { 904 .reg_off = HHI_MPLL_CNTL8, 905 .shift = 16, 906 .width = 9, 907 }, 908 }, 909 .hw.init = &(struct clk_init_data){ 910 .name = "mpll1_div", 911 .ops = &meson_clk_mpll_ops, 912 .parent_hws = (const struct clk_hw *[]) { 913 &gxbb_mpll_prediv.hw 914 }, 915 .num_parents = 1, 916 }, 917 }; 918 919 static struct clk_regmap gxbb_mpll1 = { 920 .data = &(struct clk_regmap_gate_data){ 921 .offset = HHI_MPLL_CNTL8, 922 .bit_idx = 14, 923 }, 924 .hw.init = &(struct clk_init_data){ 925 .name = "mpll1", 926 .ops = &clk_regmap_gate_ops, 927 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw }, 928 .num_parents = 1, 929 .flags = CLK_SET_RATE_PARENT, 930 }, 931 }; 932 933 static struct clk_regmap gxbb_mpll2_div = { 934 .data = &(struct meson_clk_mpll_data){ 935 .sdm = { 936 .reg_off = HHI_MPLL_CNTL9, 937 .shift = 0, 938 .width = 14, 939 }, 940 .sdm_en = { 941 .reg_off = HHI_MPLL_CNTL9, 942 .shift = 15, 943 .width = 1, 944 }, 945 .n2 = { 946 .reg_off = HHI_MPLL_CNTL9, 947 .shift = 16, 948 .width = 9, 949 }, 950 }, 951 .hw.init = &(struct clk_init_data){ 952 .name = "mpll2_div", 953 .ops = &meson_clk_mpll_ops, 954 .parent_hws = (const struct clk_hw *[]) { 955 &gxbb_mpll_prediv.hw 956 }, 957 .num_parents = 1, 958 }, 959 }; 960 961 static struct clk_regmap gxbb_mpll2 = { 962 .data = &(struct clk_regmap_gate_data){ 963 .offset = HHI_MPLL_CNTL9, 964 .bit_idx = 14, 965 }, 966 .hw.init = &(struct clk_init_data){ 967 .name = "mpll2", 968 .ops = &clk_regmap_gate_ops, 969 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw }, 970 .num_parents = 1, 971 .flags = CLK_SET_RATE_PARENT, 972 }, 973 }; 974 975 /* clk81 is often referred as "mpeg_clk" */ 976 static u32 clk81_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 }; 977 static const struct clk_parent_data clk81_parents[] = { 978 { .fw_name = "xtal", }, 979 { .hw = &gxbb_fclk_div7.hw }, 980 { .hw = &gxbb_mpll1.hw }, 981 { .hw = &gxbb_mpll2.hw }, 982 { .hw = &gxbb_fclk_div4.hw }, 983 { .hw = &gxbb_fclk_div3.hw }, 984 { .hw = &gxbb_fclk_div5.hw }, 985 }; 986 987 static struct clk_regmap gxbb_clk81_sel = { 988 .data = &(struct clk_regmap_mux_data){ 989 .offset = HHI_MPEG_CLK_CNTL, 990 .mask = 0x7, 991 .shift = 12, 992 .table = clk81_parents_val_table, 993 }, 994 .hw.init = &(struct clk_init_data){ 995 .name = "clk81_sel", 996 .ops = &clk_regmap_mux_ro_ops, 997 /* 998 * bits 14:12 selects from 8 possible parents: 999 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 1000 * fclk_div4, fclk_div3, fclk_div5 1001 */ 1002 .parent_data = clk81_parents, 1003 .num_parents = ARRAY_SIZE(clk81_parents), 1004 }, 1005 }; 1006 1007 static struct clk_regmap gxbb_clk81_div = { 1008 .data = &(struct clk_regmap_div_data){ 1009 .offset = HHI_MPEG_CLK_CNTL, 1010 .shift = 0, 1011 .width = 7, 1012 }, 1013 .hw.init = &(struct clk_init_data){ 1014 .name = "clk81_div", 1015 .ops = &clk_regmap_divider_ro_ops, 1016 .parent_hws = (const struct clk_hw *[]) { 1017 &gxbb_clk81_sel.hw 1018 }, 1019 .num_parents = 1, 1020 }, 1021 }; 1022 1023 /* the mother of dragons gates */ 1024 static struct clk_regmap gxbb_clk81 = { 1025 .data = &(struct clk_regmap_gate_data){ 1026 .offset = HHI_MPEG_CLK_CNTL, 1027 .bit_idx = 7, 1028 }, 1029 .hw.init = &(struct clk_init_data){ 1030 .name = "clk81", 1031 .ops = &clk_regmap_gate_ops, 1032 .parent_hws = (const struct clk_hw *[]) { 1033 &gxbb_clk81_div.hw 1034 }, 1035 .num_parents = 1, 1036 .flags = CLK_IS_CRITICAL, 1037 }, 1038 }; 1039 1040 static struct clk_regmap gxbb_sar_adc_clk_sel = { 1041 .data = &(struct clk_regmap_mux_data){ 1042 .offset = HHI_SAR_CLK_CNTL, 1043 .mask = 0x3, 1044 .shift = 9, 1045 }, 1046 .hw.init = &(struct clk_init_data){ 1047 .name = "sar_adc_clk_sel", 1048 .ops = &clk_regmap_mux_ops, 1049 /* NOTE: The datasheet doesn't list the parents for bit 10 */ 1050 .parent_data = (const struct clk_parent_data []) { 1051 { .fw_name = "xtal", }, 1052 { .hw = &gxbb_clk81.hw }, 1053 }, 1054 .num_parents = 2, 1055 }, 1056 }; 1057 1058 static struct clk_regmap gxbb_sar_adc_clk_div = { 1059 .data = &(struct clk_regmap_div_data){ 1060 .offset = HHI_SAR_CLK_CNTL, 1061 .shift = 0, 1062 .width = 8, 1063 }, 1064 .hw.init = &(struct clk_init_data){ 1065 .name = "sar_adc_clk_div", 1066 .ops = &clk_regmap_divider_ops, 1067 .parent_hws = (const struct clk_hw *[]) { 1068 &gxbb_sar_adc_clk_sel.hw 1069 }, 1070 .num_parents = 1, 1071 .flags = CLK_SET_RATE_PARENT, 1072 }, 1073 }; 1074 1075 static struct clk_regmap gxbb_sar_adc_clk = { 1076 .data = &(struct clk_regmap_gate_data){ 1077 .offset = HHI_SAR_CLK_CNTL, 1078 .bit_idx = 8, 1079 }, 1080 .hw.init = &(struct clk_init_data){ 1081 .name = "sar_adc_clk", 1082 .ops = &clk_regmap_gate_ops, 1083 .parent_hws = (const struct clk_hw *[]) { 1084 &gxbb_sar_adc_clk_div.hw 1085 }, 1086 .num_parents = 1, 1087 .flags = CLK_SET_RATE_PARENT, 1088 }, 1089 }; 1090 1091 /* 1092 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 1093 * muxed by a glitch-free switch. The CCF can manage this glitch-free 1094 * mux because it does top-to-bottom updates the each clock tree and 1095 * switches to the "inactive" one when CLK_SET_RATE_GATE is set. 1096 */ 1097 1098 static const struct clk_parent_data gxbb_mali_parents[] = { 1099 { .fw_name = "xtal", }, 1100 { .hw = &gxbb_gp0_pll.hw }, 1101 { .hw = &gxbb_mpll2.hw }, 1102 { .hw = &gxbb_mpll1.hw }, 1103 { .hw = &gxbb_fclk_div7.hw }, 1104 { .hw = &gxbb_fclk_div4.hw }, 1105 { .hw = &gxbb_fclk_div3.hw }, 1106 { .hw = &gxbb_fclk_div5.hw }, 1107 }; 1108 1109 static struct clk_regmap gxbb_mali_0_sel = { 1110 .data = &(struct clk_regmap_mux_data){ 1111 .offset = HHI_MALI_CLK_CNTL, 1112 .mask = 0x7, 1113 .shift = 9, 1114 }, 1115 .hw.init = &(struct clk_init_data){ 1116 .name = "mali_0_sel", 1117 .ops = &clk_regmap_mux_ops, 1118 .parent_data = gxbb_mali_parents, 1119 .num_parents = ARRAY_SIZE(gxbb_mali_parents), 1120 /* 1121 * Don't request the parent to change the rate because 1122 * all GPU frequencies can be derived from the fclk_* 1123 * clocks and one special GP0_PLL setting. This is 1124 * important because we need the MPLL clocks for audio. 1125 */ 1126 .flags = 0, 1127 }, 1128 }; 1129 1130 static struct clk_regmap gxbb_mali_0_div = { 1131 .data = &(struct clk_regmap_div_data){ 1132 .offset = HHI_MALI_CLK_CNTL, 1133 .shift = 0, 1134 .width = 7, 1135 }, 1136 .hw.init = &(struct clk_init_data){ 1137 .name = "mali_0_div", 1138 .ops = &clk_regmap_divider_ops, 1139 .parent_hws = (const struct clk_hw *[]) { 1140 &gxbb_mali_0_sel.hw 1141 }, 1142 .num_parents = 1, 1143 .flags = CLK_SET_RATE_PARENT, 1144 }, 1145 }; 1146 1147 static struct clk_regmap gxbb_mali_0 = { 1148 .data = &(struct clk_regmap_gate_data){ 1149 .offset = HHI_MALI_CLK_CNTL, 1150 .bit_idx = 8, 1151 }, 1152 .hw.init = &(struct clk_init_data){ 1153 .name = "mali_0", 1154 .ops = &clk_regmap_gate_ops, 1155 .parent_hws = (const struct clk_hw *[]) { 1156 &gxbb_mali_0_div.hw 1157 }, 1158 .num_parents = 1, 1159 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1160 }, 1161 }; 1162 1163 static struct clk_regmap gxbb_mali_1_sel = { 1164 .data = &(struct clk_regmap_mux_data){ 1165 .offset = HHI_MALI_CLK_CNTL, 1166 .mask = 0x7, 1167 .shift = 25, 1168 }, 1169 .hw.init = &(struct clk_init_data){ 1170 .name = "mali_1_sel", 1171 .ops = &clk_regmap_mux_ops, 1172 .parent_data = gxbb_mali_parents, 1173 .num_parents = ARRAY_SIZE(gxbb_mali_parents), 1174 /* 1175 * Don't request the parent to change the rate because 1176 * all GPU frequencies can be derived from the fclk_* 1177 * clocks and one special GP0_PLL setting. This is 1178 * important because we need the MPLL clocks for audio. 1179 */ 1180 .flags = 0, 1181 }, 1182 }; 1183 1184 static struct clk_regmap gxbb_mali_1_div = { 1185 .data = &(struct clk_regmap_div_data){ 1186 .offset = HHI_MALI_CLK_CNTL, 1187 .shift = 16, 1188 .width = 7, 1189 }, 1190 .hw.init = &(struct clk_init_data){ 1191 .name = "mali_1_div", 1192 .ops = &clk_regmap_divider_ops, 1193 .parent_hws = (const struct clk_hw *[]) { 1194 &gxbb_mali_1_sel.hw 1195 }, 1196 .num_parents = 1, 1197 .flags = CLK_SET_RATE_PARENT, 1198 }, 1199 }; 1200 1201 static struct clk_regmap gxbb_mali_1 = { 1202 .data = &(struct clk_regmap_gate_data){ 1203 .offset = HHI_MALI_CLK_CNTL, 1204 .bit_idx = 24, 1205 }, 1206 .hw.init = &(struct clk_init_data){ 1207 .name = "mali_1", 1208 .ops = &clk_regmap_gate_ops, 1209 .parent_hws = (const struct clk_hw *[]) { 1210 &gxbb_mali_1_div.hw 1211 }, 1212 .num_parents = 1, 1213 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1214 }, 1215 }; 1216 1217 static struct clk_regmap gxbb_mali = { 1218 .data = &(struct clk_regmap_mux_data){ 1219 .offset = HHI_MALI_CLK_CNTL, 1220 .mask = 1, 1221 .shift = 31, 1222 }, 1223 .hw.init = &(struct clk_init_data){ 1224 .name = "mali", 1225 .ops = &clk_regmap_mux_ops, 1226 .parent_hws = (const struct clk_hw *[]) { 1227 &gxbb_mali_0.hw, 1228 &gxbb_mali_1.hw, 1229 }, 1230 .num_parents = 2, 1231 .flags = CLK_SET_RATE_PARENT, 1232 }, 1233 }; 1234 1235 static u32 gxbb_cts_mclk_parents_val_table[] = { 1, 2, 3 }; 1236 static const struct clk_hw *gxbb_cts_mclk_parents[] = { 1237 &gxbb_mpll0.hw, 1238 &gxbb_mpll1.hw, 1239 &gxbb_mpll2.hw, 1240 }; 1241 1242 static struct clk_regmap gxbb_cts_amclk_sel = { 1243 .data = &(struct clk_regmap_mux_data){ 1244 .offset = HHI_AUD_CLK_CNTL, 1245 .mask = 0x3, 1246 .shift = 9, 1247 .table = gxbb_cts_mclk_parents_val_table, 1248 .flags = CLK_MUX_ROUND_CLOSEST, 1249 }, 1250 .hw.init = &(struct clk_init_data){ 1251 .name = "cts_amclk_sel", 1252 .ops = &clk_regmap_mux_ops, 1253 .parent_hws = gxbb_cts_mclk_parents, 1254 .num_parents = ARRAY_SIZE(gxbb_cts_mclk_parents), 1255 }, 1256 }; 1257 1258 static struct clk_regmap gxbb_cts_amclk_div = { 1259 .data = &(struct clk_regmap_div_data) { 1260 .offset = HHI_AUD_CLK_CNTL, 1261 .shift = 0, 1262 .width = 8, 1263 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1264 }, 1265 .hw.init = &(struct clk_init_data){ 1266 .name = "cts_amclk_div", 1267 .ops = &clk_regmap_divider_ops, 1268 .parent_hws = (const struct clk_hw *[]) { 1269 &gxbb_cts_amclk_sel.hw 1270 }, 1271 .num_parents = 1, 1272 .flags = CLK_SET_RATE_PARENT, 1273 }, 1274 }; 1275 1276 static struct clk_regmap gxbb_cts_amclk = { 1277 .data = &(struct clk_regmap_gate_data){ 1278 .offset = HHI_AUD_CLK_CNTL, 1279 .bit_idx = 8, 1280 }, 1281 .hw.init = &(struct clk_init_data){ 1282 .name = "cts_amclk", 1283 .ops = &clk_regmap_gate_ops, 1284 .parent_hws = (const struct clk_hw *[]) { 1285 &gxbb_cts_amclk_div.hw 1286 }, 1287 .num_parents = 1, 1288 .flags = CLK_SET_RATE_PARENT, 1289 }, 1290 }; 1291 1292 static struct clk_regmap gxbb_cts_mclk_i958_sel = { 1293 .data = &(struct clk_regmap_mux_data){ 1294 .offset = HHI_AUD_CLK_CNTL2, 1295 .mask = 0x3, 1296 .shift = 25, 1297 .table = gxbb_cts_mclk_parents_val_table, 1298 .flags = CLK_MUX_ROUND_CLOSEST, 1299 }, 1300 .hw.init = &(struct clk_init_data) { 1301 .name = "cts_mclk_i958_sel", 1302 .ops = &clk_regmap_mux_ops, 1303 .parent_hws = gxbb_cts_mclk_parents, 1304 .num_parents = ARRAY_SIZE(gxbb_cts_mclk_parents), 1305 }, 1306 }; 1307 1308 static struct clk_regmap gxbb_cts_mclk_i958_div = { 1309 .data = &(struct clk_regmap_div_data){ 1310 .offset = HHI_AUD_CLK_CNTL2, 1311 .shift = 16, 1312 .width = 8, 1313 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1314 }, 1315 .hw.init = &(struct clk_init_data) { 1316 .name = "cts_mclk_i958_div", 1317 .ops = &clk_regmap_divider_ops, 1318 .parent_hws = (const struct clk_hw *[]) { 1319 &gxbb_cts_mclk_i958_sel.hw 1320 }, 1321 .num_parents = 1, 1322 .flags = CLK_SET_RATE_PARENT, 1323 }, 1324 }; 1325 1326 static struct clk_regmap gxbb_cts_mclk_i958 = { 1327 .data = &(struct clk_regmap_gate_data){ 1328 .offset = HHI_AUD_CLK_CNTL2, 1329 .bit_idx = 24, 1330 }, 1331 .hw.init = &(struct clk_init_data){ 1332 .name = "cts_mclk_i958", 1333 .ops = &clk_regmap_gate_ops, 1334 .parent_hws = (const struct clk_hw *[]) { 1335 &gxbb_cts_mclk_i958_div.hw 1336 }, 1337 .num_parents = 1, 1338 .flags = CLK_SET_RATE_PARENT, 1339 }, 1340 }; 1341 1342 static struct clk_regmap gxbb_cts_i958 = { 1343 .data = &(struct clk_regmap_mux_data){ 1344 .offset = HHI_AUD_CLK_CNTL2, 1345 .mask = 0x1, 1346 .shift = 27, 1347 }, 1348 .hw.init = &(struct clk_init_data){ 1349 .name = "cts_i958", 1350 .ops = &clk_regmap_mux_ops, 1351 .parent_hws = (const struct clk_hw *[]) { 1352 &gxbb_cts_amclk.hw, 1353 &gxbb_cts_mclk_i958.hw 1354 }, 1355 .num_parents = 2, 1356 /* 1357 *The parent is specific to origin of the audio data. Let the 1358 * consumer choose the appropriate parent 1359 */ 1360 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 1361 }, 1362 }; 1363 1364 /* 1365 * This table skips a clock named 'cts_slow_oscin' in the documentation 1366 * This clock does not exist yet in this controller or the AO one 1367 */ 1368 static u32 gxbb_32k_clk_parents_val_table[] = { 0, 2, 3 }; 1369 static const struct clk_parent_data gxbb_32k_clk_parents[] = { 1370 { .fw_name = "xtal", }, 1371 { .hw = &gxbb_fclk_div3.hw }, 1372 { .hw = &gxbb_fclk_div5.hw }, 1373 }; 1374 1375 static struct clk_regmap gxbb_32k_clk_sel = { 1376 .data = &(struct clk_regmap_mux_data){ 1377 .offset = HHI_32K_CLK_CNTL, 1378 .mask = 0x3, 1379 .shift = 16, 1380 .table = gxbb_32k_clk_parents_val_table, 1381 }, 1382 .hw.init = &(struct clk_init_data){ 1383 .name = "32k_clk_sel", 1384 .ops = &clk_regmap_mux_ops, 1385 .parent_data = gxbb_32k_clk_parents, 1386 .num_parents = 4, 1387 .flags = CLK_SET_RATE_PARENT, 1388 }, 1389 }; 1390 1391 static struct clk_regmap gxbb_32k_clk_div = { 1392 .data = &(struct clk_regmap_div_data){ 1393 .offset = HHI_32K_CLK_CNTL, 1394 .shift = 0, 1395 .width = 14, 1396 }, 1397 .hw.init = &(struct clk_init_data){ 1398 .name = "32k_clk_div", 1399 .ops = &clk_regmap_divider_ops, 1400 .parent_hws = (const struct clk_hw *[]) { 1401 &gxbb_32k_clk_sel.hw 1402 }, 1403 .num_parents = 1, 1404 .flags = CLK_SET_RATE_PARENT, 1405 }, 1406 }; 1407 1408 static struct clk_regmap gxbb_32k_clk = { 1409 .data = &(struct clk_regmap_gate_data){ 1410 .offset = HHI_32K_CLK_CNTL, 1411 .bit_idx = 15, 1412 }, 1413 .hw.init = &(struct clk_init_data){ 1414 .name = "32k_clk", 1415 .ops = &clk_regmap_gate_ops, 1416 .parent_hws = (const struct clk_hw *[]) { 1417 &gxbb_32k_clk_div.hw 1418 }, 1419 .num_parents = 1, 1420 .flags = CLK_SET_RATE_PARENT, 1421 }, 1422 }; 1423 1424 static const struct clk_parent_data gxbb_sd_emmc_clk0_parents[] = { 1425 { .fw_name = "xtal", }, 1426 { .hw = &gxbb_fclk_div2.hw }, 1427 { .hw = &gxbb_fclk_div3.hw }, 1428 { .hw = &gxbb_fclk_div5.hw }, 1429 { .hw = &gxbb_fclk_div7.hw }, 1430 /* 1431 * Following these parent clocks, we should also have had mpll2, mpll3 1432 * and gp0_pll but these clocks are too precious to be used here. All 1433 * the necessary rates for MMC and NAND operation can be achieved using 1434 * xtal or fclk_div clocks 1435 */ 1436 }; 1437 1438 /* SDIO clock */ 1439 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { 1440 .data = &(struct clk_regmap_mux_data){ 1441 .offset = HHI_SD_EMMC_CLK_CNTL, 1442 .mask = 0x7, 1443 .shift = 9, 1444 }, 1445 .hw.init = &(struct clk_init_data) { 1446 .name = "sd_emmc_a_clk0_sel", 1447 .ops = &clk_regmap_mux_ops, 1448 .parent_data = gxbb_sd_emmc_clk0_parents, 1449 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents), 1450 .flags = CLK_SET_RATE_PARENT, 1451 }, 1452 }; 1453 1454 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { 1455 .data = &(struct clk_regmap_div_data){ 1456 .offset = HHI_SD_EMMC_CLK_CNTL, 1457 .shift = 0, 1458 .width = 7, 1459 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1460 }, 1461 .hw.init = &(struct clk_init_data) { 1462 .name = "sd_emmc_a_clk0_div", 1463 .ops = &clk_regmap_divider_ops, 1464 .parent_hws = (const struct clk_hw *[]) { 1465 &gxbb_sd_emmc_a_clk0_sel.hw 1466 }, 1467 .num_parents = 1, 1468 .flags = CLK_SET_RATE_PARENT, 1469 }, 1470 }; 1471 1472 static struct clk_regmap gxbb_sd_emmc_a_clk0 = { 1473 .data = &(struct clk_regmap_gate_data){ 1474 .offset = HHI_SD_EMMC_CLK_CNTL, 1475 .bit_idx = 7, 1476 }, 1477 .hw.init = &(struct clk_init_data){ 1478 .name = "sd_emmc_a_clk0", 1479 .ops = &clk_regmap_gate_ops, 1480 .parent_hws = (const struct clk_hw *[]) { 1481 &gxbb_sd_emmc_a_clk0_div.hw 1482 }, 1483 .num_parents = 1, 1484 .flags = CLK_SET_RATE_PARENT, 1485 }, 1486 }; 1487 1488 /* SDcard clock */ 1489 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { 1490 .data = &(struct clk_regmap_mux_data){ 1491 .offset = HHI_SD_EMMC_CLK_CNTL, 1492 .mask = 0x7, 1493 .shift = 25, 1494 }, 1495 .hw.init = &(struct clk_init_data) { 1496 .name = "sd_emmc_b_clk0_sel", 1497 .ops = &clk_regmap_mux_ops, 1498 .parent_data = gxbb_sd_emmc_clk0_parents, 1499 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents), 1500 .flags = CLK_SET_RATE_PARENT, 1501 }, 1502 }; 1503 1504 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { 1505 .data = &(struct clk_regmap_div_data){ 1506 .offset = HHI_SD_EMMC_CLK_CNTL, 1507 .shift = 16, 1508 .width = 7, 1509 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1510 }, 1511 .hw.init = &(struct clk_init_data) { 1512 .name = "sd_emmc_b_clk0_div", 1513 .ops = &clk_regmap_divider_ops, 1514 .parent_hws = (const struct clk_hw *[]) { 1515 &gxbb_sd_emmc_b_clk0_sel.hw 1516 }, 1517 .num_parents = 1, 1518 .flags = CLK_SET_RATE_PARENT, 1519 }, 1520 }; 1521 1522 static struct clk_regmap gxbb_sd_emmc_b_clk0 = { 1523 .data = &(struct clk_regmap_gate_data){ 1524 .offset = HHI_SD_EMMC_CLK_CNTL, 1525 .bit_idx = 23, 1526 }, 1527 .hw.init = &(struct clk_init_data){ 1528 .name = "sd_emmc_b_clk0", 1529 .ops = &clk_regmap_gate_ops, 1530 .parent_hws = (const struct clk_hw *[]) { 1531 &gxbb_sd_emmc_b_clk0_div.hw 1532 }, 1533 .num_parents = 1, 1534 .flags = CLK_SET_RATE_PARENT, 1535 }, 1536 }; 1537 1538 /* EMMC/NAND clock */ 1539 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { 1540 .data = &(struct clk_regmap_mux_data){ 1541 .offset = HHI_NAND_CLK_CNTL, 1542 .mask = 0x7, 1543 .shift = 9, 1544 }, 1545 .hw.init = &(struct clk_init_data) { 1546 .name = "sd_emmc_c_clk0_sel", 1547 .ops = &clk_regmap_mux_ops, 1548 .parent_data = gxbb_sd_emmc_clk0_parents, 1549 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents), 1550 .flags = CLK_SET_RATE_PARENT, 1551 }, 1552 }; 1553 1554 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { 1555 .data = &(struct clk_regmap_div_data){ 1556 .offset = HHI_NAND_CLK_CNTL, 1557 .shift = 0, 1558 .width = 7, 1559 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1560 }, 1561 .hw.init = &(struct clk_init_data) { 1562 .name = "sd_emmc_c_clk0_div", 1563 .ops = &clk_regmap_divider_ops, 1564 .parent_hws = (const struct clk_hw *[]) { 1565 &gxbb_sd_emmc_c_clk0_sel.hw 1566 }, 1567 .num_parents = 1, 1568 .flags = CLK_SET_RATE_PARENT, 1569 }, 1570 }; 1571 1572 static struct clk_regmap gxbb_sd_emmc_c_clk0 = { 1573 .data = &(struct clk_regmap_gate_data){ 1574 .offset = HHI_NAND_CLK_CNTL, 1575 .bit_idx = 7, 1576 }, 1577 .hw.init = &(struct clk_init_data){ 1578 .name = "sd_emmc_c_clk0", 1579 .ops = &clk_regmap_gate_ops, 1580 .parent_hws = (const struct clk_hw *[]) { 1581 &gxbb_sd_emmc_c_clk0_div.hw 1582 }, 1583 .num_parents = 1, 1584 .flags = CLK_SET_RATE_PARENT, 1585 }, 1586 }; 1587 1588 /* VPU Clock */ 1589 1590 static const struct clk_hw *gxbb_vpu_parents[] = { 1591 &gxbb_fclk_div4.hw, 1592 &gxbb_fclk_div3.hw, 1593 &gxbb_fclk_div5.hw, 1594 &gxbb_fclk_div7.hw, 1595 }; 1596 1597 static struct clk_regmap gxbb_vpu_0_sel = { 1598 .data = &(struct clk_regmap_mux_data){ 1599 .offset = HHI_VPU_CLK_CNTL, 1600 .mask = 0x3, 1601 .shift = 9, 1602 }, 1603 .hw.init = &(struct clk_init_data){ 1604 .name = "vpu_0_sel", 1605 .ops = &clk_regmap_mux_ops, 1606 /* 1607 * bits 9:10 selects from 4 possible parents: 1608 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1609 */ 1610 .parent_hws = gxbb_vpu_parents, 1611 .num_parents = ARRAY_SIZE(gxbb_vpu_parents), 1612 .flags = CLK_SET_RATE_NO_REPARENT, 1613 }, 1614 }; 1615 1616 static struct clk_regmap gxbb_vpu_0_div = { 1617 .data = &(struct clk_regmap_div_data){ 1618 .offset = HHI_VPU_CLK_CNTL, 1619 .shift = 0, 1620 .width = 7, 1621 }, 1622 .hw.init = &(struct clk_init_data){ 1623 .name = "vpu_0_div", 1624 .ops = &clk_regmap_divider_ops, 1625 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw }, 1626 .num_parents = 1, 1627 .flags = CLK_SET_RATE_PARENT, 1628 }, 1629 }; 1630 1631 static struct clk_regmap gxbb_vpu_0 = { 1632 .data = &(struct clk_regmap_gate_data){ 1633 .offset = HHI_VPU_CLK_CNTL, 1634 .bit_idx = 8, 1635 }, 1636 .hw.init = &(struct clk_init_data) { 1637 .name = "vpu_0", 1638 .ops = &clk_regmap_gate_ops, 1639 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw }, 1640 .num_parents = 1, 1641 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1642 }, 1643 }; 1644 1645 static struct clk_regmap gxbb_vpu_1_sel = { 1646 .data = &(struct clk_regmap_mux_data){ 1647 .offset = HHI_VPU_CLK_CNTL, 1648 .mask = 0x3, 1649 .shift = 25, 1650 }, 1651 .hw.init = &(struct clk_init_data){ 1652 .name = "vpu_1_sel", 1653 .ops = &clk_regmap_mux_ops, 1654 /* 1655 * bits 25:26 selects from 4 possible parents: 1656 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1657 */ 1658 .parent_hws = gxbb_vpu_parents, 1659 .num_parents = ARRAY_SIZE(gxbb_vpu_parents), 1660 .flags = CLK_SET_RATE_NO_REPARENT, 1661 }, 1662 }; 1663 1664 static struct clk_regmap gxbb_vpu_1_div = { 1665 .data = &(struct clk_regmap_div_data){ 1666 .offset = HHI_VPU_CLK_CNTL, 1667 .shift = 16, 1668 .width = 7, 1669 }, 1670 .hw.init = &(struct clk_init_data){ 1671 .name = "vpu_1_div", 1672 .ops = &clk_regmap_divider_ops, 1673 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw }, 1674 .num_parents = 1, 1675 .flags = CLK_SET_RATE_PARENT, 1676 }, 1677 }; 1678 1679 static struct clk_regmap gxbb_vpu_1 = { 1680 .data = &(struct clk_regmap_gate_data){ 1681 .offset = HHI_VPU_CLK_CNTL, 1682 .bit_idx = 24, 1683 }, 1684 .hw.init = &(struct clk_init_data) { 1685 .name = "vpu_1", 1686 .ops = &clk_regmap_gate_ops, 1687 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw }, 1688 .num_parents = 1, 1689 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1690 }, 1691 }; 1692 1693 static struct clk_regmap gxbb_vpu = { 1694 .data = &(struct clk_regmap_mux_data){ 1695 .offset = HHI_VPU_CLK_CNTL, 1696 .mask = 1, 1697 .shift = 31, 1698 }, 1699 .hw.init = &(struct clk_init_data){ 1700 .name = "vpu", 1701 .ops = &clk_regmap_mux_ops, 1702 /* 1703 * bit 31 selects from 2 possible parents: 1704 * vpu_0 or vpu_1 1705 */ 1706 .parent_hws = (const struct clk_hw *[]) { 1707 &gxbb_vpu_0.hw, 1708 &gxbb_vpu_1.hw 1709 }, 1710 .num_parents = 2, 1711 .flags = CLK_SET_RATE_NO_REPARENT, 1712 }, 1713 }; 1714 1715 /* VAPB Clock */ 1716 1717 static const struct clk_hw *gxbb_vapb_parents[] = { 1718 &gxbb_fclk_div4.hw, 1719 &gxbb_fclk_div3.hw, 1720 &gxbb_fclk_div5.hw, 1721 &gxbb_fclk_div7.hw, 1722 }; 1723 1724 static struct clk_regmap gxbb_vapb_0_sel = { 1725 .data = &(struct clk_regmap_mux_data){ 1726 .offset = HHI_VAPBCLK_CNTL, 1727 .mask = 0x3, 1728 .shift = 9, 1729 }, 1730 .hw.init = &(struct clk_init_data){ 1731 .name = "vapb_0_sel", 1732 .ops = &clk_regmap_mux_ops, 1733 /* 1734 * bits 9:10 selects from 4 possible parents: 1735 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1736 */ 1737 .parent_hws = gxbb_vapb_parents, 1738 .num_parents = ARRAY_SIZE(gxbb_vapb_parents), 1739 .flags = CLK_SET_RATE_NO_REPARENT, 1740 }, 1741 }; 1742 1743 static struct clk_regmap gxbb_vapb_0_div = { 1744 .data = &(struct clk_regmap_div_data){ 1745 .offset = HHI_VAPBCLK_CNTL, 1746 .shift = 0, 1747 .width = 7, 1748 }, 1749 .hw.init = &(struct clk_init_data){ 1750 .name = "vapb_0_div", 1751 .ops = &clk_regmap_divider_ops, 1752 .parent_hws = (const struct clk_hw *[]) { 1753 &gxbb_vapb_0_sel.hw 1754 }, 1755 .num_parents = 1, 1756 .flags = CLK_SET_RATE_PARENT, 1757 }, 1758 }; 1759 1760 static struct clk_regmap gxbb_vapb_0 = { 1761 .data = &(struct clk_regmap_gate_data){ 1762 .offset = HHI_VAPBCLK_CNTL, 1763 .bit_idx = 8, 1764 }, 1765 .hw.init = &(struct clk_init_data) { 1766 .name = "vapb_0", 1767 .ops = &clk_regmap_gate_ops, 1768 .parent_hws = (const struct clk_hw *[]) { 1769 &gxbb_vapb_0_div.hw 1770 }, 1771 .num_parents = 1, 1772 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1773 }, 1774 }; 1775 1776 static struct clk_regmap gxbb_vapb_1_sel = { 1777 .data = &(struct clk_regmap_mux_data){ 1778 .offset = HHI_VAPBCLK_CNTL, 1779 .mask = 0x3, 1780 .shift = 25, 1781 }, 1782 .hw.init = &(struct clk_init_data){ 1783 .name = "vapb_1_sel", 1784 .ops = &clk_regmap_mux_ops, 1785 /* 1786 * bits 25:26 selects from 4 possible parents: 1787 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1788 */ 1789 .parent_hws = gxbb_vapb_parents, 1790 .num_parents = ARRAY_SIZE(gxbb_vapb_parents), 1791 .flags = CLK_SET_RATE_NO_REPARENT, 1792 }, 1793 }; 1794 1795 static struct clk_regmap gxbb_vapb_1_div = { 1796 .data = &(struct clk_regmap_div_data){ 1797 .offset = HHI_VAPBCLK_CNTL, 1798 .shift = 16, 1799 .width = 7, 1800 }, 1801 .hw.init = &(struct clk_init_data){ 1802 .name = "vapb_1_div", 1803 .ops = &clk_regmap_divider_ops, 1804 .parent_hws = (const struct clk_hw *[]) { 1805 &gxbb_vapb_1_sel.hw 1806 }, 1807 .num_parents = 1, 1808 .flags = CLK_SET_RATE_PARENT, 1809 }, 1810 }; 1811 1812 static struct clk_regmap gxbb_vapb_1 = { 1813 .data = &(struct clk_regmap_gate_data){ 1814 .offset = HHI_VAPBCLK_CNTL, 1815 .bit_idx = 24, 1816 }, 1817 .hw.init = &(struct clk_init_data) { 1818 .name = "vapb_1", 1819 .ops = &clk_regmap_gate_ops, 1820 .parent_hws = (const struct clk_hw *[]) { 1821 &gxbb_vapb_1_div.hw 1822 }, 1823 .num_parents = 1, 1824 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1825 }, 1826 }; 1827 1828 static struct clk_regmap gxbb_vapb_sel = { 1829 .data = &(struct clk_regmap_mux_data){ 1830 .offset = HHI_VAPBCLK_CNTL, 1831 .mask = 1, 1832 .shift = 31, 1833 }, 1834 .hw.init = &(struct clk_init_data){ 1835 .name = "vapb_sel", 1836 .ops = &clk_regmap_mux_ops, 1837 /* 1838 * bit 31 selects from 2 possible parents: 1839 * vapb_0 or vapb_1 1840 */ 1841 .parent_hws = (const struct clk_hw *[]) { 1842 &gxbb_vapb_0.hw, 1843 &gxbb_vapb_1.hw 1844 }, 1845 .num_parents = 2, 1846 .flags = CLK_SET_RATE_NO_REPARENT, 1847 }, 1848 }; 1849 1850 static struct clk_regmap gxbb_vapb = { 1851 .data = &(struct clk_regmap_gate_data){ 1852 .offset = HHI_VAPBCLK_CNTL, 1853 .bit_idx = 30, 1854 }, 1855 .hw.init = &(struct clk_init_data) { 1856 .name = "vapb", 1857 .ops = &clk_regmap_gate_ops, 1858 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw }, 1859 .num_parents = 1, 1860 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1861 }, 1862 }; 1863 1864 /* Video Clocks */ 1865 1866 static struct clk_regmap gxbb_vid_pll_div = { 1867 .data = &(struct meson_vid_pll_div_data){ 1868 .val = { 1869 .reg_off = HHI_VID_PLL_CLK_DIV, 1870 .shift = 0, 1871 .width = 15, 1872 }, 1873 .sel = { 1874 .reg_off = HHI_VID_PLL_CLK_DIV, 1875 .shift = 16, 1876 .width = 2, 1877 }, 1878 }, 1879 .hw.init = &(struct clk_init_data) { 1880 .name = "vid_pll_div", 1881 .ops = &meson_vid_pll_div_ro_ops, 1882 .parent_data = &(const struct clk_parent_data) { 1883 /* 1884 * Note: 1885 * GXL and GXBB have different hdmi_plls (with 1886 * different struct clk_hw). We fallback to the global 1887 * naming string mechanism so vid_pll_div picks up the 1888 * appropriate one. 1889 */ 1890 .name = "hdmi_pll", 1891 .index = -1, 1892 }, 1893 .num_parents = 1, 1894 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 1895 }, 1896 }; 1897 1898 static const struct clk_parent_data gxbb_vid_pll_parents[] = { 1899 { .hw = &gxbb_vid_pll_div.hw }, 1900 /* 1901 * Note: 1902 * GXL and GXBB have different hdmi_plls (with 1903 * different struct clk_hw). We fallback to the global 1904 * naming string mechanism so vid_pll_div picks up the 1905 * appropriate one. 1906 */ 1907 { .name = "hdmi_pll", .index = -1 }, 1908 }; 1909 1910 static struct clk_regmap gxbb_vid_pll_sel = { 1911 .data = &(struct clk_regmap_mux_data){ 1912 .offset = HHI_VID_PLL_CLK_DIV, 1913 .mask = 0x1, 1914 .shift = 18, 1915 }, 1916 .hw.init = &(struct clk_init_data){ 1917 .name = "vid_pll_sel", 1918 .ops = &clk_regmap_mux_ops, 1919 /* 1920 * bit 18 selects from 2 possible parents: 1921 * vid_pll_div or hdmi_pll 1922 */ 1923 .parent_data = gxbb_vid_pll_parents, 1924 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parents), 1925 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1926 }, 1927 }; 1928 1929 static struct clk_regmap gxbb_vid_pll = { 1930 .data = &(struct clk_regmap_gate_data){ 1931 .offset = HHI_VID_PLL_CLK_DIV, 1932 .bit_idx = 19, 1933 }, 1934 .hw.init = &(struct clk_init_data) { 1935 .name = "vid_pll", 1936 .ops = &clk_regmap_gate_ops, 1937 .parent_hws = (const struct clk_hw *[]) { 1938 &gxbb_vid_pll_sel.hw 1939 }, 1940 .num_parents = 1, 1941 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1942 }, 1943 }; 1944 1945 static const struct clk_hw *gxbb_vclk_parents[] = { 1946 &gxbb_vid_pll.hw, 1947 &gxbb_fclk_div4.hw, 1948 &gxbb_fclk_div3.hw, 1949 &gxbb_fclk_div5.hw, 1950 &gxbb_vid_pll.hw, 1951 &gxbb_fclk_div7.hw, 1952 &gxbb_mpll1.hw, 1953 }; 1954 1955 static struct clk_regmap gxbb_vclk_sel = { 1956 .data = &(struct clk_regmap_mux_data){ 1957 .offset = HHI_VID_CLK_CNTL, 1958 .mask = 0x7, 1959 .shift = 16, 1960 }, 1961 .hw.init = &(struct clk_init_data){ 1962 .name = "vclk_sel", 1963 .ops = &clk_regmap_mux_ops, 1964 /* 1965 * bits 16:18 selects from 8 possible parents: 1966 * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1967 * vid_pll, fclk_div7, mp1 1968 */ 1969 .parent_hws = gxbb_vclk_parents, 1970 .num_parents = ARRAY_SIZE(gxbb_vclk_parents), 1971 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1972 }, 1973 }; 1974 1975 static struct clk_regmap gxbb_vclk2_sel = { 1976 .data = &(struct clk_regmap_mux_data){ 1977 .offset = HHI_VIID_CLK_CNTL, 1978 .mask = 0x7, 1979 .shift = 16, 1980 }, 1981 .hw.init = &(struct clk_init_data){ 1982 .name = "vclk2_sel", 1983 .ops = &clk_regmap_mux_ops, 1984 /* 1985 * bits 16:18 selects from 8 possible parents: 1986 * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1987 * vid_pll, fclk_div7, mp1 1988 */ 1989 .parent_hws = gxbb_vclk_parents, 1990 .num_parents = ARRAY_SIZE(gxbb_vclk_parents), 1991 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1992 }, 1993 }; 1994 1995 static struct clk_regmap gxbb_vclk_input = { 1996 .data = &(struct clk_regmap_gate_data){ 1997 .offset = HHI_VID_CLK_DIV, 1998 .bit_idx = 16, 1999 }, 2000 .hw.init = &(struct clk_init_data) { 2001 .name = "vclk_input", 2002 .ops = &clk_regmap_gate_ops, 2003 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw }, 2004 .num_parents = 1, 2005 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2006 }, 2007 }; 2008 2009 static struct clk_regmap gxbb_vclk2_input = { 2010 .data = &(struct clk_regmap_gate_data){ 2011 .offset = HHI_VIID_CLK_DIV, 2012 .bit_idx = 16, 2013 }, 2014 .hw.init = &(struct clk_init_data) { 2015 .name = "vclk2_input", 2016 .ops = &clk_regmap_gate_ops, 2017 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw }, 2018 .num_parents = 1, 2019 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2020 }, 2021 }; 2022 2023 static struct clk_regmap gxbb_vclk_div = { 2024 .data = &(struct clk_regmap_div_data){ 2025 .offset = HHI_VID_CLK_DIV, 2026 .shift = 0, 2027 .width = 8, 2028 }, 2029 .hw.init = &(struct clk_init_data){ 2030 .name = "vclk_div", 2031 .ops = &clk_regmap_divider_ops, 2032 .parent_hws = (const struct clk_hw *[]) { 2033 &gxbb_vclk_input.hw 2034 }, 2035 .num_parents = 1, 2036 .flags = CLK_GET_RATE_NOCACHE, 2037 }, 2038 }; 2039 2040 static struct clk_regmap gxbb_vclk2_div = { 2041 .data = &(struct clk_regmap_div_data){ 2042 .offset = HHI_VIID_CLK_DIV, 2043 .shift = 0, 2044 .width = 8, 2045 }, 2046 .hw.init = &(struct clk_init_data){ 2047 .name = "vclk2_div", 2048 .ops = &clk_regmap_divider_ops, 2049 .parent_hws = (const struct clk_hw *[]) { 2050 &gxbb_vclk2_input.hw 2051 }, 2052 .num_parents = 1, 2053 .flags = CLK_GET_RATE_NOCACHE, 2054 }, 2055 }; 2056 2057 static struct clk_regmap gxbb_vclk = { 2058 .data = &(struct clk_regmap_gate_data){ 2059 .offset = HHI_VID_CLK_CNTL, 2060 .bit_idx = 19, 2061 }, 2062 .hw.init = &(struct clk_init_data) { 2063 .name = "vclk", 2064 .ops = &clk_regmap_gate_ops, 2065 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw }, 2066 .num_parents = 1, 2067 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2068 }, 2069 }; 2070 2071 static struct clk_regmap gxbb_vclk2 = { 2072 .data = &(struct clk_regmap_gate_data){ 2073 .offset = HHI_VIID_CLK_CNTL, 2074 .bit_idx = 19, 2075 }, 2076 .hw.init = &(struct clk_init_data) { 2077 .name = "vclk2", 2078 .ops = &clk_regmap_gate_ops, 2079 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw }, 2080 .num_parents = 1, 2081 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2082 }, 2083 }; 2084 2085 static struct clk_regmap gxbb_vclk_div1 = { 2086 .data = &(struct clk_regmap_gate_data){ 2087 .offset = HHI_VID_CLK_CNTL, 2088 .bit_idx = 0, 2089 }, 2090 .hw.init = &(struct clk_init_data) { 2091 .name = "vclk_div1", 2092 .ops = &clk_regmap_gate_ops, 2093 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2094 .num_parents = 1, 2095 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2096 }, 2097 }; 2098 2099 static struct clk_regmap gxbb_vclk_div2_en = { 2100 .data = &(struct clk_regmap_gate_data){ 2101 .offset = HHI_VID_CLK_CNTL, 2102 .bit_idx = 1, 2103 }, 2104 .hw.init = &(struct clk_init_data) { 2105 .name = "vclk_div2_en", 2106 .ops = &clk_regmap_gate_ops, 2107 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2108 .num_parents = 1, 2109 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2110 }, 2111 }; 2112 2113 static struct clk_regmap gxbb_vclk_div4_en = { 2114 .data = &(struct clk_regmap_gate_data){ 2115 .offset = HHI_VID_CLK_CNTL, 2116 .bit_idx = 2, 2117 }, 2118 .hw.init = &(struct clk_init_data) { 2119 .name = "vclk_div4_en", 2120 .ops = &clk_regmap_gate_ops, 2121 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2122 .num_parents = 1, 2123 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2124 }, 2125 }; 2126 2127 static struct clk_regmap gxbb_vclk_div6_en = { 2128 .data = &(struct clk_regmap_gate_data){ 2129 .offset = HHI_VID_CLK_CNTL, 2130 .bit_idx = 3, 2131 }, 2132 .hw.init = &(struct clk_init_data) { 2133 .name = "vclk_div6_en", 2134 .ops = &clk_regmap_gate_ops, 2135 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2136 .num_parents = 1, 2137 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2138 }, 2139 }; 2140 2141 static struct clk_regmap gxbb_vclk_div12_en = { 2142 .data = &(struct clk_regmap_gate_data){ 2143 .offset = HHI_VID_CLK_CNTL, 2144 .bit_idx = 4, 2145 }, 2146 .hw.init = &(struct clk_init_data) { 2147 .name = "vclk_div12_en", 2148 .ops = &clk_regmap_gate_ops, 2149 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2150 .num_parents = 1, 2151 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2152 }, 2153 }; 2154 2155 static struct clk_regmap gxbb_vclk2_div1 = { 2156 .data = &(struct clk_regmap_gate_data){ 2157 .offset = HHI_VIID_CLK_CNTL, 2158 .bit_idx = 0, 2159 }, 2160 .hw.init = &(struct clk_init_data) { 2161 .name = "vclk2_div1", 2162 .ops = &clk_regmap_gate_ops, 2163 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2164 .num_parents = 1, 2165 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2166 }, 2167 }; 2168 2169 static struct clk_regmap gxbb_vclk2_div2_en = { 2170 .data = &(struct clk_regmap_gate_data){ 2171 .offset = HHI_VIID_CLK_CNTL, 2172 .bit_idx = 1, 2173 }, 2174 .hw.init = &(struct clk_init_data) { 2175 .name = "vclk2_div2_en", 2176 .ops = &clk_regmap_gate_ops, 2177 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2178 .num_parents = 1, 2179 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2180 }, 2181 }; 2182 2183 static struct clk_regmap gxbb_vclk2_div4_en = { 2184 .data = &(struct clk_regmap_gate_data){ 2185 .offset = HHI_VIID_CLK_CNTL, 2186 .bit_idx = 2, 2187 }, 2188 .hw.init = &(struct clk_init_data) { 2189 .name = "vclk2_div4_en", 2190 .ops = &clk_regmap_gate_ops, 2191 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2192 .num_parents = 1, 2193 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2194 }, 2195 }; 2196 2197 static struct clk_regmap gxbb_vclk2_div6_en = { 2198 .data = &(struct clk_regmap_gate_data){ 2199 .offset = HHI_VIID_CLK_CNTL, 2200 .bit_idx = 3, 2201 }, 2202 .hw.init = &(struct clk_init_data) { 2203 .name = "vclk2_div6_en", 2204 .ops = &clk_regmap_gate_ops, 2205 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2206 .num_parents = 1, 2207 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2208 }, 2209 }; 2210 2211 static struct clk_regmap gxbb_vclk2_div12_en = { 2212 .data = &(struct clk_regmap_gate_data){ 2213 .offset = HHI_VIID_CLK_CNTL, 2214 .bit_idx = 4, 2215 }, 2216 .hw.init = &(struct clk_init_data) { 2217 .name = "vclk2_div12_en", 2218 .ops = &clk_regmap_gate_ops, 2219 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2220 .num_parents = 1, 2221 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2222 }, 2223 }; 2224 2225 static struct clk_fixed_factor gxbb_vclk_div2 = { 2226 .mult = 1, 2227 .div = 2, 2228 .hw.init = &(struct clk_init_data){ 2229 .name = "vclk_div2", 2230 .ops = &clk_fixed_factor_ops, 2231 .parent_hws = (const struct clk_hw *[]) { 2232 &gxbb_vclk_div2_en.hw 2233 }, 2234 .num_parents = 1, 2235 }, 2236 }; 2237 2238 static struct clk_fixed_factor gxbb_vclk_div4 = { 2239 .mult = 1, 2240 .div = 4, 2241 .hw.init = &(struct clk_init_data){ 2242 .name = "vclk_div4", 2243 .ops = &clk_fixed_factor_ops, 2244 .parent_hws = (const struct clk_hw *[]) { 2245 &gxbb_vclk_div4_en.hw 2246 }, 2247 .num_parents = 1, 2248 }, 2249 }; 2250 2251 static struct clk_fixed_factor gxbb_vclk_div6 = { 2252 .mult = 1, 2253 .div = 6, 2254 .hw.init = &(struct clk_init_data){ 2255 .name = "vclk_div6", 2256 .ops = &clk_fixed_factor_ops, 2257 .parent_hws = (const struct clk_hw *[]) { 2258 &gxbb_vclk_div6_en.hw 2259 }, 2260 .num_parents = 1, 2261 }, 2262 }; 2263 2264 static struct clk_fixed_factor gxbb_vclk_div12 = { 2265 .mult = 1, 2266 .div = 12, 2267 .hw.init = &(struct clk_init_data){ 2268 .name = "vclk_div12", 2269 .ops = &clk_fixed_factor_ops, 2270 .parent_hws = (const struct clk_hw *[]) { 2271 &gxbb_vclk_div12_en.hw 2272 }, 2273 .num_parents = 1, 2274 }, 2275 }; 2276 2277 static struct clk_fixed_factor gxbb_vclk2_div2 = { 2278 .mult = 1, 2279 .div = 2, 2280 .hw.init = &(struct clk_init_data){ 2281 .name = "vclk2_div2", 2282 .ops = &clk_fixed_factor_ops, 2283 .parent_hws = (const struct clk_hw *[]) { 2284 &gxbb_vclk2_div2_en.hw 2285 }, 2286 .num_parents = 1, 2287 }, 2288 }; 2289 2290 static struct clk_fixed_factor gxbb_vclk2_div4 = { 2291 .mult = 1, 2292 .div = 4, 2293 .hw.init = &(struct clk_init_data){ 2294 .name = "vclk2_div4", 2295 .ops = &clk_fixed_factor_ops, 2296 .parent_hws = (const struct clk_hw *[]) { 2297 &gxbb_vclk2_div4_en.hw 2298 }, 2299 .num_parents = 1, 2300 }, 2301 }; 2302 2303 static struct clk_fixed_factor gxbb_vclk2_div6 = { 2304 .mult = 1, 2305 .div = 6, 2306 .hw.init = &(struct clk_init_data){ 2307 .name = "vclk2_div6", 2308 .ops = &clk_fixed_factor_ops, 2309 .parent_hws = (const struct clk_hw *[]) { 2310 &gxbb_vclk2_div6_en.hw 2311 }, 2312 .num_parents = 1, 2313 }, 2314 }; 2315 2316 static struct clk_fixed_factor gxbb_vclk2_div12 = { 2317 .mult = 1, 2318 .div = 12, 2319 .hw.init = &(struct clk_init_data){ 2320 .name = "vclk2_div12", 2321 .ops = &clk_fixed_factor_ops, 2322 .parent_hws = (const struct clk_hw *[]) { 2323 &gxbb_vclk2_div12_en.hw 2324 }, 2325 .num_parents = 1, 2326 }, 2327 }; 2328 2329 static u32 gxbb_cts_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 2330 static const struct clk_hw *gxbb_cts_parents[] = { 2331 &gxbb_vclk_div1.hw, 2332 &gxbb_vclk_div2.hw, 2333 &gxbb_vclk_div4.hw, 2334 &gxbb_vclk_div6.hw, 2335 &gxbb_vclk_div12.hw, 2336 &gxbb_vclk2_div1.hw, 2337 &gxbb_vclk2_div2.hw, 2338 &gxbb_vclk2_div4.hw, 2339 &gxbb_vclk2_div6.hw, 2340 &gxbb_vclk2_div12.hw, 2341 }; 2342 2343 static struct clk_regmap gxbb_cts_enci_sel = { 2344 .data = &(struct clk_regmap_mux_data){ 2345 .offset = HHI_VID_CLK_DIV, 2346 .mask = 0xf, 2347 .shift = 28, 2348 .table = gxbb_cts_parents_val_table, 2349 }, 2350 .hw.init = &(struct clk_init_data){ 2351 .name = "cts_enci_sel", 2352 .ops = &clk_regmap_mux_ops, 2353 .parent_hws = gxbb_cts_parents, 2354 .num_parents = ARRAY_SIZE(gxbb_cts_parents), 2355 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2356 }, 2357 }; 2358 2359 static struct clk_regmap gxbb_cts_encp_sel = { 2360 .data = &(struct clk_regmap_mux_data){ 2361 .offset = HHI_VID_CLK_DIV, 2362 .mask = 0xf, 2363 .shift = 20, 2364 .table = gxbb_cts_parents_val_table, 2365 }, 2366 .hw.init = &(struct clk_init_data){ 2367 .name = "cts_encp_sel", 2368 .ops = &clk_regmap_mux_ops, 2369 .parent_hws = gxbb_cts_parents, 2370 .num_parents = ARRAY_SIZE(gxbb_cts_parents), 2371 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2372 }, 2373 }; 2374 2375 static struct clk_regmap gxbb_cts_vdac_sel = { 2376 .data = &(struct clk_regmap_mux_data){ 2377 .offset = HHI_VIID_CLK_DIV, 2378 .mask = 0xf, 2379 .shift = 28, 2380 .table = gxbb_cts_parents_val_table, 2381 }, 2382 .hw.init = &(struct clk_init_data){ 2383 .name = "cts_vdac_sel", 2384 .ops = &clk_regmap_mux_ops, 2385 .parent_hws = gxbb_cts_parents, 2386 .num_parents = ARRAY_SIZE(gxbb_cts_parents), 2387 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2388 }, 2389 }; 2390 2391 static struct clk_regmap gxbb_cts_enci = { 2392 .data = &(struct clk_regmap_gate_data){ 2393 .offset = HHI_VID_CLK_CNTL2, 2394 .bit_idx = 0, 2395 }, 2396 .hw.init = &(struct clk_init_data) { 2397 .name = "cts_enci", 2398 .ops = &clk_regmap_gate_ops, 2399 .parent_hws = (const struct clk_hw *[]) { 2400 &gxbb_cts_enci_sel.hw 2401 }, 2402 .num_parents = 1, 2403 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2404 }, 2405 }; 2406 2407 static struct clk_regmap gxbb_cts_encp = { 2408 .data = &(struct clk_regmap_gate_data){ 2409 .offset = HHI_VID_CLK_CNTL2, 2410 .bit_idx = 2, 2411 }, 2412 .hw.init = &(struct clk_init_data) { 2413 .name = "cts_encp", 2414 .ops = &clk_regmap_gate_ops, 2415 .parent_hws = (const struct clk_hw *[]) { 2416 &gxbb_cts_encp_sel.hw 2417 }, 2418 .num_parents = 1, 2419 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2420 }, 2421 }; 2422 2423 static struct clk_regmap gxbb_cts_vdac = { 2424 .data = &(struct clk_regmap_gate_data){ 2425 .offset = HHI_VID_CLK_CNTL2, 2426 .bit_idx = 4, 2427 }, 2428 .hw.init = &(struct clk_init_data) { 2429 .name = "cts_vdac", 2430 .ops = &clk_regmap_gate_ops, 2431 .parent_hws = (const struct clk_hw *[]) { 2432 &gxbb_cts_vdac_sel.hw 2433 }, 2434 .num_parents = 1, 2435 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2436 }, 2437 }; 2438 2439 /* TOFIX: add support for cts_tcon */ 2440 static u32 gxbb_hdmi_tx_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 2441 static const struct clk_hw *gxbb_hdmi_tx_parents[] = { 2442 &gxbb_vclk_div1.hw, 2443 &gxbb_vclk_div2.hw, 2444 &gxbb_vclk_div4.hw, 2445 &gxbb_vclk_div6.hw, 2446 &gxbb_vclk_div12.hw, 2447 &gxbb_vclk2_div1.hw, 2448 &gxbb_vclk2_div2.hw, 2449 &gxbb_vclk2_div4.hw, 2450 &gxbb_vclk2_div6.hw, 2451 &gxbb_vclk2_div12.hw, 2452 }; 2453 2454 static struct clk_regmap gxbb_hdmi_tx_sel = { 2455 .data = &(struct clk_regmap_mux_data){ 2456 .offset = HHI_HDMI_CLK_CNTL, 2457 .mask = 0xf, 2458 .shift = 16, 2459 .table = gxbb_hdmi_tx_parents_val_table, 2460 }, 2461 .hw.init = &(struct clk_init_data){ 2462 .name = "hdmi_tx_sel", 2463 .ops = &clk_regmap_mux_ops, 2464 /* 2465 * bits 31:28 selects from 12 possible parents: 2466 * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12 2467 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12, 2468 * cts_tcon 2469 */ 2470 .parent_hws = gxbb_hdmi_tx_parents, 2471 .num_parents = ARRAY_SIZE(gxbb_hdmi_tx_parents), 2472 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2473 }, 2474 }; 2475 2476 static struct clk_regmap gxbb_hdmi_tx = { 2477 .data = &(struct clk_regmap_gate_data){ 2478 .offset = HHI_VID_CLK_CNTL2, 2479 .bit_idx = 5, 2480 }, 2481 .hw.init = &(struct clk_init_data) { 2482 .name = "hdmi_tx", 2483 .ops = &clk_regmap_gate_ops, 2484 .parent_hws = (const struct clk_hw *[]) { 2485 &gxbb_hdmi_tx_sel.hw 2486 }, 2487 .num_parents = 1, 2488 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2489 }, 2490 }; 2491 2492 /* HDMI Clocks */ 2493 2494 static const struct clk_parent_data gxbb_hdmi_parents[] = { 2495 { .fw_name = "xtal", }, 2496 { .hw = &gxbb_fclk_div4.hw }, 2497 { .hw = &gxbb_fclk_div3.hw }, 2498 { .hw = &gxbb_fclk_div5.hw }, 2499 }; 2500 2501 static struct clk_regmap gxbb_hdmi_sel = { 2502 .data = &(struct clk_regmap_mux_data){ 2503 .offset = HHI_HDMI_CLK_CNTL, 2504 .mask = 0x3, 2505 .shift = 9, 2506 .flags = CLK_MUX_ROUND_CLOSEST, 2507 }, 2508 .hw.init = &(struct clk_init_data){ 2509 .name = "hdmi_sel", 2510 .ops = &clk_regmap_mux_ops, 2511 .parent_data = gxbb_hdmi_parents, 2512 .num_parents = ARRAY_SIZE(gxbb_hdmi_parents), 2513 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2514 }, 2515 }; 2516 2517 static struct clk_regmap gxbb_hdmi_div = { 2518 .data = &(struct clk_regmap_div_data){ 2519 .offset = HHI_HDMI_CLK_CNTL, 2520 .shift = 0, 2521 .width = 7, 2522 }, 2523 .hw.init = &(struct clk_init_data){ 2524 .name = "hdmi_div", 2525 .ops = &clk_regmap_divider_ops, 2526 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw }, 2527 .num_parents = 1, 2528 .flags = CLK_GET_RATE_NOCACHE, 2529 }, 2530 }; 2531 2532 static struct clk_regmap gxbb_hdmi = { 2533 .data = &(struct clk_regmap_gate_data){ 2534 .offset = HHI_HDMI_CLK_CNTL, 2535 .bit_idx = 8, 2536 }, 2537 .hw.init = &(struct clk_init_data) { 2538 .name = "hdmi", 2539 .ops = &clk_regmap_gate_ops, 2540 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw }, 2541 .num_parents = 1, 2542 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2543 }, 2544 }; 2545 2546 /* VDEC clocks */ 2547 2548 static const struct clk_hw *gxbb_vdec_parents[] = { 2549 &gxbb_fclk_div4.hw, 2550 &gxbb_fclk_div3.hw, 2551 &gxbb_fclk_div5.hw, 2552 &gxbb_fclk_div7.hw, 2553 }; 2554 2555 static struct clk_regmap gxbb_vdec_1_sel = { 2556 .data = &(struct clk_regmap_mux_data){ 2557 .offset = HHI_VDEC_CLK_CNTL, 2558 .mask = 0x3, 2559 .shift = 9, 2560 .flags = CLK_MUX_ROUND_CLOSEST, 2561 }, 2562 .hw.init = &(struct clk_init_data){ 2563 .name = "vdec_1_sel", 2564 .ops = &clk_regmap_mux_ops, 2565 .parent_hws = gxbb_vdec_parents, 2566 .num_parents = ARRAY_SIZE(gxbb_vdec_parents), 2567 .flags = CLK_SET_RATE_PARENT, 2568 }, 2569 }; 2570 2571 static struct clk_regmap gxbb_vdec_1_div = { 2572 .data = &(struct clk_regmap_div_data){ 2573 .offset = HHI_VDEC_CLK_CNTL, 2574 .shift = 0, 2575 .width = 7, 2576 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2577 }, 2578 .hw.init = &(struct clk_init_data){ 2579 .name = "vdec_1_div", 2580 .ops = &clk_regmap_divider_ops, 2581 .parent_hws = (const struct clk_hw *[]) { 2582 &gxbb_vdec_1_sel.hw 2583 }, 2584 .num_parents = 1, 2585 .flags = CLK_SET_RATE_PARENT, 2586 }, 2587 }; 2588 2589 static struct clk_regmap gxbb_vdec_1 = { 2590 .data = &(struct clk_regmap_gate_data){ 2591 .offset = HHI_VDEC_CLK_CNTL, 2592 .bit_idx = 8, 2593 }, 2594 .hw.init = &(struct clk_init_data) { 2595 .name = "vdec_1", 2596 .ops = &clk_regmap_gate_ops, 2597 .parent_hws = (const struct clk_hw *[]) { 2598 &gxbb_vdec_1_div.hw 2599 }, 2600 .num_parents = 1, 2601 .flags = CLK_SET_RATE_PARENT, 2602 }, 2603 }; 2604 2605 static struct clk_regmap gxbb_vdec_hevc_sel = { 2606 .data = &(struct clk_regmap_mux_data){ 2607 .offset = HHI_VDEC2_CLK_CNTL, 2608 .mask = 0x3, 2609 .shift = 25, 2610 .flags = CLK_MUX_ROUND_CLOSEST, 2611 }, 2612 .hw.init = &(struct clk_init_data){ 2613 .name = "vdec_hevc_sel", 2614 .ops = &clk_regmap_mux_ops, 2615 .parent_hws = gxbb_vdec_parents, 2616 .num_parents = ARRAY_SIZE(gxbb_vdec_parents), 2617 .flags = CLK_SET_RATE_PARENT, 2618 }, 2619 }; 2620 2621 static struct clk_regmap gxbb_vdec_hevc_div = { 2622 .data = &(struct clk_regmap_div_data){ 2623 .offset = HHI_VDEC2_CLK_CNTL, 2624 .shift = 16, 2625 .width = 7, 2626 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2627 }, 2628 .hw.init = &(struct clk_init_data){ 2629 .name = "vdec_hevc_div", 2630 .ops = &clk_regmap_divider_ops, 2631 .parent_hws = (const struct clk_hw *[]) { 2632 &gxbb_vdec_hevc_sel.hw 2633 }, 2634 .num_parents = 1, 2635 .flags = CLK_SET_RATE_PARENT, 2636 }, 2637 }; 2638 2639 static struct clk_regmap gxbb_vdec_hevc = { 2640 .data = &(struct clk_regmap_gate_data){ 2641 .offset = HHI_VDEC2_CLK_CNTL, 2642 .bit_idx = 24, 2643 }, 2644 .hw.init = &(struct clk_init_data) { 2645 .name = "vdec_hevc", 2646 .ops = &clk_regmap_gate_ops, 2647 .parent_hws = (const struct clk_hw *[]) { 2648 &gxbb_vdec_hevc_div.hw 2649 }, 2650 .num_parents = 1, 2651 .flags = CLK_SET_RATE_PARENT, 2652 }, 2653 }; 2654 2655 static u32 gxbb_gen_clk_parents_val_table[] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, }; 2656 static const struct clk_parent_data gxbb_gen_clk_parents[] = { 2657 { .fw_name = "xtal", }, 2658 { .hw = &gxbb_vdec_1.hw }, 2659 { .hw = &gxbb_vdec_hevc.hw }, 2660 { .hw = &gxbb_mpll0.hw }, 2661 { .hw = &gxbb_mpll1.hw }, 2662 { .hw = &gxbb_mpll2.hw }, 2663 { .hw = &gxbb_fclk_div4.hw }, 2664 { .hw = &gxbb_fclk_div3.hw }, 2665 { .hw = &gxbb_fclk_div5.hw }, 2666 { .hw = &gxbb_fclk_div7.hw }, 2667 { .hw = &gxbb_gp0_pll.hw }, 2668 }; 2669 2670 static struct clk_regmap gxbb_gen_clk_sel = { 2671 .data = &(struct clk_regmap_mux_data){ 2672 .offset = HHI_GEN_CLK_CNTL, 2673 .mask = 0xf, 2674 .shift = 12, 2675 .table = gxbb_gen_clk_parents_val_table, 2676 }, 2677 .hw.init = &(struct clk_init_data){ 2678 .name = "gen_clk_sel", 2679 .ops = &clk_regmap_mux_ops, 2680 /* 2681 * bits 15:12 selects from 14 possible parents: 2682 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 2683 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4, 2684 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 2685 */ 2686 .parent_data = gxbb_gen_clk_parents, 2687 .num_parents = ARRAY_SIZE(gxbb_gen_clk_parents), 2688 }, 2689 }; 2690 2691 static struct clk_regmap gxbb_gen_clk_div = { 2692 .data = &(struct clk_regmap_div_data){ 2693 .offset = HHI_GEN_CLK_CNTL, 2694 .shift = 0, 2695 .width = 11, 2696 }, 2697 .hw.init = &(struct clk_init_data){ 2698 .name = "gen_clk_div", 2699 .ops = &clk_regmap_divider_ops, 2700 .parent_hws = (const struct clk_hw *[]) { 2701 &gxbb_gen_clk_sel.hw 2702 }, 2703 .num_parents = 1, 2704 .flags = CLK_SET_RATE_PARENT, 2705 }, 2706 }; 2707 2708 static struct clk_regmap gxbb_gen_clk = { 2709 .data = &(struct clk_regmap_gate_data){ 2710 .offset = HHI_GEN_CLK_CNTL, 2711 .bit_idx = 7, 2712 }, 2713 .hw.init = &(struct clk_init_data){ 2714 .name = "gen_clk", 2715 .ops = &clk_regmap_gate_ops, 2716 .parent_hws = (const struct clk_hw *[]) { 2717 &gxbb_gen_clk_div.hw 2718 }, 2719 .num_parents = 1, 2720 .flags = CLK_SET_RATE_PARENT, 2721 }, 2722 }; 2723 2724 static const struct clk_parent_data gxbb_pclk_parents = { .hw = &gxbb_clk81.hw }; 2725 2726 #define GXBB_PCLK(_name, _reg, _bit, _flags) \ 2727 MESON_PCLK(_name, _reg, _bit, &gxbb_pclk_parents, _flags) 2728 2729 /* 2730 * Everything Else (EE) domain gates 2731 * 2732 * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons 2733 * Users are encouraged to test without it and submit changes to: 2734 * - remove the flag if not necessary 2735 * - replace the flag with something more adequate, such as CLK_IS_CRITICAL, 2736 * if appropriate. 2737 * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable 2738 * for a particular clock. 2739 */ 2740 static GXBB_PCLK(gxbb_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); 2741 static GXBB_PCLK(gxbb_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED); 2742 static GXBB_PCLK(gxbb_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); 2743 static GXBB_PCLK(gxbb_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); 2744 static GXBB_PCLK(gxbb_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED); 2745 static GXBB_PCLK(gxbb_spicc, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); 2746 static GXBB_PCLK(gxbb_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); 2747 static GXBB_PCLK(gxbb_sana, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSED); 2748 static GXBB_PCLK(gxbb_smart_card, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UNUSED); 2749 static GXBB_PCLK(gxbb_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); 2750 static GXBB_PCLK(gxbb_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); 2751 static GXBB_PCLK(gxbb_sdhc, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); 2752 static GXBB_PCLK(gxbb_stream, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED); 2753 static GXBB_PCLK(gxbb_async_fifo, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED); 2754 static GXBB_PCLK(gxbb_sdio, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED); 2755 static GXBB_PCLK(gxbb_abuf, HHI_GCLK_MPEG0, 18, CLK_IGNORE_UNUSED); 2756 static GXBB_PCLK(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED); 2757 static GXBB_PCLK(gxbb_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED); 2758 static GXBB_PCLK(gxbb_emmc_a, HHI_GCLK_MPEG0, 24, CLK_IGNORE_UNUSED); 2759 static GXBB_PCLK(gxbb_emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED); 2760 static GXBB_PCLK(gxbb_emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED); 2761 static GXBB_PCLK(gxl_acodec, HHI_GCLK_MPEG0, 28, CLK_IGNORE_UNUSED); 2762 static GXBB_PCLK(gxbb_spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED); 2763 2764 static GXBB_PCLK(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2, CLK_IGNORE_UNUSED); 2765 static GXBB_PCLK(gxbb_eth, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); 2766 static GXBB_PCLK(gxbb_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED); 2767 static GXBB_PCLK(gxbb_blkmv, HHI_GCLK_MPEG1, 14, CLK_IGNORE_UNUSED); 2768 static GXBB_PCLK(gxbb_aiu, HHI_GCLK_MPEG1, 15, CLK_IGNORE_UNUSED); 2769 static GXBB_PCLK(gxbb_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); 2770 static GXBB_PCLK(gxbb_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); 2771 static GXBB_PCLK(gxbb_usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED); 2772 static GXBB_PCLK(gxbb_usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED); 2773 static GXBB_PCLK(gxbb_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); 2774 static GXBB_PCLK(gxbb_nand, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED); 2775 static GXBB_PCLK(gxbb_dos_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UNUSED); 2776 static GXBB_PCLK(gxbb_usb, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); 2777 static GXBB_PCLK(gxbb_vdin1, HHI_GCLK_MPEG1, 28, CLK_IGNORE_UNUSED); 2778 static GXBB_PCLK(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED); 2779 static GXBB_PCLK(gxbb_efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED); 2780 static GXBB_PCLK(gxbb_boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED); 2781 2782 static GXBB_PCLK(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED); 2783 static GXBB_PCLK(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED); 2784 static GXBB_PCLK(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3, CLK_IGNORE_UNUSED); 2785 static GXBB_PCLK(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNUSED); 2786 static GXBB_PCLK(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED); 2787 static GXBB_PCLK(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9, CLK_IGNORE_UNUSED); 2788 static GXBB_PCLK(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED); 2789 static GXBB_PCLK(gxbb_dvin, HHI_GCLK_MPEG2, 12, CLK_IGNORE_UNUSED); 2790 static GXBB_PCLK(gxbb_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED); 2791 static GXBB_PCLK(gxbb_sar_adc, HHI_GCLK_MPEG2, 22, CLK_IGNORE_UNUSED); 2792 static GXBB_PCLK(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED); 2793 static GXBB_PCLK(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_IGNORE_UNUSED); 2794 static GXBB_PCLK(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUSED); 2795 2796 static GXBB_PCLK(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_UNUSED); 2797 static GXBB_PCLK(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_UNUSED); 2798 static GXBB_PCLK(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_UNUSED); 2799 static GXBB_PCLK(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_UNUSED); 2800 static GXBB_PCLK(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8, CLK_IGNORE_UNUSED); 2801 static GXBB_PCLK(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9, CLK_IGNORE_UNUSED); 2802 static GXBB_PCLK(gxbb_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSED); 2803 static GXBB_PCLK(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UNUSED); 2804 static GXBB_PCLK(gxbb_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UNUSED); 2805 static GXBB_PCLK(gxbb_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSED); 2806 static GXBB_PCLK(gxbb_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED); 2807 static GXBB_PCLK(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22, CLK_IGNORE_UNUSED); 2808 static GXBB_PCLK(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24, CLK_IGNORE_UNUSED); 2809 static GXBB_PCLK(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UNUSED); 2810 static GXBB_PCLK(gxbb_vclk_other, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED); 2811 static GXBB_PCLK(gxbb_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED); 2812 2813 /* Always On (AO) domain gates */ 2814 2815 static GXBB_PCLK(gxbb_ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED); 2816 static GXBB_PCLK(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED); 2817 static GXBB_PCLK(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED); 2818 static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED); 2819 static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED); 2820 2821 /* AIU gates */ 2822 static const struct clk_parent_data gxbb_aiu_glue_parents = { .hw = &gxbb_aiu.hw }; 2823 static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu_glue_parents, CLK_IGNORE_UNUSED); 2824 2825 static const struct clk_parent_data gxbb_aiu_pclk_parents = { .hw = &gxbb_aiu_glue.hw }; 2826 #define GXBB_AIU_PCLK(_name, _bit, _flags) \ 2827 MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &gxbb_aiu_pclk_parents, _flags) 2828 2829 static GXBB_AIU_PCLK(gxbb_iec958, 7, CLK_IGNORE_UNUSED); 2830 static GXBB_AIU_PCLK(gxbb_i2s_out, 8, CLK_IGNORE_UNUSED); 2831 static GXBB_AIU_PCLK(gxbb_amclk, 9, CLK_IGNORE_UNUSED); 2832 static GXBB_AIU_PCLK(gxbb_aififo2, 10, CLK_IGNORE_UNUSED); 2833 static GXBB_AIU_PCLK(gxbb_mixer, 11, CLK_IGNORE_UNUSED); 2834 static GXBB_AIU_PCLK(gxbb_mixer_iface, 12, CLK_IGNORE_UNUSED); 2835 static GXBB_AIU_PCLK(gxbb_adc, 13, CLK_IGNORE_UNUSED); 2836 2837 /* Array of all clocks provided by this provider */ 2838 2839 static struct clk_hw *gxbb_hw_clks[] = { 2840 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 2841 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 2842 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 2843 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 2844 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 2845 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 2846 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 2847 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 2848 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 2849 [CLKID_MPEG_SEL] = &gxbb_clk81_sel.hw, 2850 [CLKID_MPEG_DIV] = &gxbb_clk81_div.hw, 2851 [CLKID_CLK81] = &gxbb_clk81.hw, 2852 [CLKID_MPLL0] = &gxbb_mpll0.hw, 2853 [CLKID_MPLL1] = &gxbb_mpll1.hw, 2854 [CLKID_MPLL2] = &gxbb_mpll2.hw, 2855 [CLKID_DDR] = &gxbb_ddr.hw, 2856 [CLKID_DOS] = &gxbb_dos.hw, 2857 [CLKID_ISA] = &gxbb_isa.hw, 2858 [CLKID_PL301] = &gxbb_pl301.hw, 2859 [CLKID_PERIPHS] = &gxbb_periphs.hw, 2860 [CLKID_SPICC] = &gxbb_spicc.hw, 2861 [CLKID_I2C] = &gxbb_i2c.hw, 2862 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 2863 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 2864 [CLKID_RNG0] = &gxbb_rng0.hw, 2865 [CLKID_UART0] = &gxbb_uart0.hw, 2866 [CLKID_SDHC] = &gxbb_sdhc.hw, 2867 [CLKID_STREAM] = &gxbb_stream.hw, 2868 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 2869 [CLKID_SDIO] = &gxbb_sdio.hw, 2870 [CLKID_ABUF] = &gxbb_abuf.hw, 2871 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 2872 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 2873 [CLKID_SPI] = &gxbb_spi.hw, 2874 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 2875 [CLKID_ETH] = &gxbb_eth.hw, 2876 [CLKID_DEMUX] = &gxbb_demux.hw, 2877 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 2878 [CLKID_IEC958] = &gxbb_iec958.hw, 2879 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 2880 [CLKID_AMCLK] = &gxbb_amclk.hw, 2881 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 2882 [CLKID_MIXER] = &gxbb_mixer.hw, 2883 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 2884 [CLKID_ADC] = &gxbb_adc.hw, 2885 [CLKID_BLKMV] = &gxbb_blkmv.hw, 2886 [CLKID_AIU] = &gxbb_aiu.hw, 2887 [CLKID_UART1] = &gxbb_uart1.hw, 2888 [CLKID_G2D] = &gxbb_g2d.hw, 2889 [CLKID_USB0] = &gxbb_usb0.hw, 2890 [CLKID_USB1] = &gxbb_usb1.hw, 2891 [CLKID_RESET] = &gxbb_reset.hw, 2892 [CLKID_NAND] = &gxbb_nand.hw, 2893 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 2894 [CLKID_USB] = &gxbb_usb.hw, 2895 [CLKID_VDIN1] = &gxbb_vdin1.hw, 2896 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2897 [CLKID_EFUSE] = &gxbb_efuse.hw, 2898 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2899 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 2900 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 2901 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 2902 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 2903 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 2904 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 2905 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 2906 [CLKID_DVIN] = &gxbb_dvin.hw, 2907 [CLKID_UART2] = &gxbb_uart2.hw, 2908 [CLKID_SANA] = &gxbb_sana.hw, 2909 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 2910 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 2911 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 2912 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 2913 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 2914 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 2915 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 2916 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 2917 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 2918 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 2919 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 2920 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 2921 [CLKID_ENC480P] = &gxbb_enc480p.hw, 2922 [CLKID_RNG1] = &gxbb_rng1.hw, 2923 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 2924 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 2925 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 2926 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 2927 [CLKID_EDP] = &gxbb_edp.hw, 2928 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 2929 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 2930 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 2931 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 2932 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 2933 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 2934 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 2935 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 2936 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 2937 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 2938 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 2939 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 2940 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 2941 [CLKID_MALI_0] = &gxbb_mali_0.hw, 2942 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 2943 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 2944 [CLKID_MALI_1] = &gxbb_mali_1.hw, 2945 [CLKID_MALI] = &gxbb_mali.hw, 2946 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 2947 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 2948 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 2949 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 2950 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 2951 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 2952 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 2953 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 2954 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 2955 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2956 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2957 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2958 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2959 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2960 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2961 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2962 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2963 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2964 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2965 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2966 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2967 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2968 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2969 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2970 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2971 [CLKID_VPU] = &gxbb_vpu.hw, 2972 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2973 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2974 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2975 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2976 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2977 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2978 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2979 [CLKID_VAPB] = &gxbb_vapb.hw, 2980 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, 2981 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2982 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2983 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2984 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 2985 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 2986 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 2987 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 2988 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 2989 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2990 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 2991 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 2992 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 2993 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 2994 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 2995 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 2996 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 2997 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 2998 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 2999 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 3000 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw, 3001 [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw, 3002 [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw, 3003 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 3004 [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw, 3005 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 3006 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 3007 [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 3008 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 3009 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 3010 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 3011 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 3012 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 3013 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 3014 [CLKID_VCLK] = &gxbb_vclk.hw, 3015 [CLKID_VCLK2] = &gxbb_vclk2.hw, 3016 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 3017 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 3018 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 3019 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 3020 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 3021 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 3022 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 3023 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 3024 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 3025 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 3026 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 3027 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 3028 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 3029 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 3030 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 3031 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 3032 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 3033 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 3034 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 3035 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 3036 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 3037 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 3038 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 3039 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 3040 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 3041 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 3042 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 3043 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 3044 [CLKID_HDMI] = &gxbb_hdmi.hw, 3045 }; 3046 3047 static struct clk_hw *gxl_hw_clks[] = { 3048 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 3049 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, 3050 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 3051 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 3052 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 3053 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 3054 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 3055 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 3056 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 3057 [CLKID_MPEG_SEL] = &gxbb_clk81_sel.hw, 3058 [CLKID_MPEG_DIV] = &gxbb_clk81_div.hw, 3059 [CLKID_CLK81] = &gxbb_clk81.hw, 3060 [CLKID_MPLL0] = &gxbb_mpll0.hw, 3061 [CLKID_MPLL1] = &gxbb_mpll1.hw, 3062 [CLKID_MPLL2] = &gxbb_mpll2.hw, 3063 [CLKID_DDR] = &gxbb_ddr.hw, 3064 [CLKID_DOS] = &gxbb_dos.hw, 3065 [CLKID_ISA] = &gxbb_isa.hw, 3066 [CLKID_PL301] = &gxbb_pl301.hw, 3067 [CLKID_PERIPHS] = &gxbb_periphs.hw, 3068 [CLKID_SPICC] = &gxbb_spicc.hw, 3069 [CLKID_I2C] = &gxbb_i2c.hw, 3070 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 3071 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 3072 [CLKID_RNG0] = &gxbb_rng0.hw, 3073 [CLKID_UART0] = &gxbb_uart0.hw, 3074 [CLKID_SDHC] = &gxbb_sdhc.hw, 3075 [CLKID_STREAM] = &gxbb_stream.hw, 3076 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 3077 [CLKID_SDIO] = &gxbb_sdio.hw, 3078 [CLKID_ABUF] = &gxbb_abuf.hw, 3079 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 3080 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 3081 [CLKID_SPI] = &gxbb_spi.hw, 3082 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 3083 [CLKID_ETH] = &gxbb_eth.hw, 3084 [CLKID_DEMUX] = &gxbb_demux.hw, 3085 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 3086 [CLKID_IEC958] = &gxbb_iec958.hw, 3087 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 3088 [CLKID_AMCLK] = &gxbb_amclk.hw, 3089 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 3090 [CLKID_MIXER] = &gxbb_mixer.hw, 3091 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 3092 [CLKID_ADC] = &gxbb_adc.hw, 3093 [CLKID_BLKMV] = &gxbb_blkmv.hw, 3094 [CLKID_AIU] = &gxbb_aiu.hw, 3095 [CLKID_UART1] = &gxbb_uart1.hw, 3096 [CLKID_G2D] = &gxbb_g2d.hw, 3097 [CLKID_USB0] = &gxbb_usb0.hw, 3098 [CLKID_USB1] = &gxbb_usb1.hw, 3099 [CLKID_RESET] = &gxbb_reset.hw, 3100 [CLKID_NAND] = &gxbb_nand.hw, 3101 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 3102 [CLKID_USB] = &gxbb_usb.hw, 3103 [CLKID_VDIN1] = &gxbb_vdin1.hw, 3104 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 3105 [CLKID_EFUSE] = &gxbb_efuse.hw, 3106 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 3107 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 3108 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 3109 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 3110 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 3111 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 3112 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 3113 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 3114 [CLKID_DVIN] = &gxbb_dvin.hw, 3115 [CLKID_UART2] = &gxbb_uart2.hw, 3116 [CLKID_SANA] = &gxbb_sana.hw, 3117 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 3118 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 3119 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 3120 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 3121 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 3122 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 3123 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 3124 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 3125 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 3126 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 3127 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 3128 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 3129 [CLKID_ENC480P] = &gxbb_enc480p.hw, 3130 [CLKID_RNG1] = &gxbb_rng1.hw, 3131 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 3132 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 3133 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 3134 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 3135 [CLKID_EDP] = &gxbb_edp.hw, 3136 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 3137 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 3138 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 3139 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 3140 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 3141 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 3142 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 3143 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 3144 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 3145 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 3146 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 3147 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 3148 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 3149 [CLKID_MALI_0] = &gxbb_mali_0.hw, 3150 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 3151 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 3152 [CLKID_MALI_1] = &gxbb_mali_1.hw, 3153 [CLKID_MALI] = &gxbb_mali.hw, 3154 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 3155 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 3156 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 3157 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 3158 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 3159 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 3160 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 3161 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 3162 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 3163 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 3164 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 3165 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 3166 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 3167 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 3168 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 3169 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 3170 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 3171 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 3172 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 3173 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 3174 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 3175 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 3176 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 3177 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 3178 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 3179 [CLKID_VPU] = &gxbb_vpu.hw, 3180 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 3181 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 3182 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 3183 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 3184 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 3185 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 3186 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 3187 [CLKID_VAPB] = &gxbb_vapb.hw, 3188 [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw, 3189 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 3190 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 3191 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 3192 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 3193 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 3194 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 3195 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 3196 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 3197 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 3198 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 3199 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 3200 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 3201 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 3202 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 3203 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 3204 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 3205 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 3206 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 3207 [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw, 3208 [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw, 3209 [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw, 3210 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 3211 [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw, 3212 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 3213 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 3214 [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 3215 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 3216 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 3217 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 3218 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 3219 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 3220 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 3221 [CLKID_VCLK] = &gxbb_vclk.hw, 3222 [CLKID_VCLK2] = &gxbb_vclk2.hw, 3223 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 3224 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 3225 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 3226 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 3227 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 3228 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 3229 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 3230 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 3231 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 3232 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 3233 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 3234 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 3235 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 3236 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 3237 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 3238 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 3239 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 3240 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 3241 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 3242 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 3243 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 3244 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 3245 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 3246 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 3247 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 3248 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 3249 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 3250 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 3251 [CLKID_HDMI] = &gxbb_hdmi.hw, 3252 [CLKID_ACODEC] = &gxl_acodec.hw, 3253 }; 3254 3255 static const struct meson_clkc_data gxbb_clkc_data = { 3256 .hw_clks = { 3257 .hws = gxbb_hw_clks, 3258 .num = ARRAY_SIZE(gxbb_hw_clks), 3259 }, 3260 }; 3261 3262 static const struct meson_clkc_data gxl_clkc_data = { 3263 .hw_clks = { 3264 .hws = gxl_hw_clks, 3265 .num = ARRAY_SIZE(gxl_hw_clks), 3266 }, 3267 }; 3268 3269 static const struct of_device_id gxbb_clkc_match_table[] = { 3270 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 3271 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 3272 {}, 3273 }; 3274 MODULE_DEVICE_TABLE(of, gxbb_clkc_match_table); 3275 3276 static struct platform_driver gxbb_clkc_driver = { 3277 .probe = meson_clkc_syscon_probe, 3278 .driver = { 3279 .name = "gxbb-clkc", 3280 .of_match_table = gxbb_clkc_match_table, 3281 }, 3282 }; 3283 module_platform_driver(gxbb_clkc_driver); 3284 3285 MODULE_DESCRIPTION("Amlogic GXBB Main Clock Controller driver"); 3286 MODULE_LICENSE("GPL"); 3287 MODULE_IMPORT_NS("CLK_MESON"); 3288