1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include "xe_wa.h"
7
8 #include <drm/drm_managed.h>
9 #include <kunit/visibility.h>
10 #include <linux/compiler_types.h>
11 #include <linux/fault-inject.h>
12
13 #include <generated/xe_device_wa_oob.h>
14 #include <generated/xe_wa_oob.h>
15
16 #include "regs/xe_engine_regs.h"
17 #include "regs/xe_gt_regs.h"
18 #include "regs/xe_guc_regs.h"
19 #include "regs/xe_regs.h"
20 #include "xe_device_types.h"
21 #include "xe_force_wake.h"
22 #include "xe_gt_types.h"
23 #include "xe_hw_engine_types.h"
24 #include "xe_mmio.h"
25 #include "xe_platform_types.h"
26 #include "xe_rtp.h"
27 #include "xe_sriov.h"
28 #include "xe_step.h"
29
30 /**
31 * DOC: Hardware workarounds
32 *
33 * Hardware workarounds are register programming documented to be executed in
34 * the driver that fall outside of the normal programming sequences for a
35 * platform. There are some basic categories of workarounds, depending on
36 * how/when they are applied:
37 *
38 * - LRC workarounds: workarounds that touch registers that are
39 * saved/restored to/from the HW context image. The list is emitted (via Load
40 * Register Immediate commands) once when initializing the device and saved in
41 * the default context. That default context is then used on every context
42 * creation to have a "primed golden context", i.e. a context image that
43 * already contains the changes needed to all the registers. See
44 * drivers/gpu/drm/xe/xe_lrc.c for default context handling.
45 *
46 * - Engine workarounds: the list of these WAs is applied whenever the specific
47 * engine is reset. It's also possible that a set of engine classes share a
48 * common power domain and they are reset together. This happens on some
49 * platforms with render and compute engines. In this case (at least) one of
50 * them need to keeep the workaround programming: the approach taken in the
51 * driver is to tie those workarounds to the first compute/render engine that
52 * is registered. When executing with GuC submission, engine resets are
53 * outside of kernel driver control, hence the list of registers involved is
54 * written once, on engine initialization, and then passed to GuC, that
55 * saves/restores their values before/after the reset takes place. See
56 * drivers/gpu/drm/xe/xe_guc_ads.c for reference.
57 *
58 * - GT workarounds: the list of these WAs is applied whenever these registers
59 * revert to their default values: on GPU reset, suspend/resume [1]_, etc.
60 *
61 * - Register whitelist: some workarounds need to be implemented in userspace,
62 * but need to touch privileged registers. The whitelist in the kernel
63 * instructs the hardware to allow the access to happen. From the kernel side,
64 * this is just a special case of a MMIO workaround (as we write the list of
65 * these to/be-whitelisted registers to some special HW registers).
66 *
67 * - Workaround batchbuffers: buffers that get executed automatically by the
68 * hardware on every HW context restore. These buffers are created and
69 * programmed in the default context so the hardware always go through those
70 * programming sequences when switching contexts. The support for workaround
71 * batchbuffers is enabled via these hardware mechanisms:
72 *
73 * #. INDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer
74 * and an offset are provided in the default context, pointing the hardware
75 * to jump to that location when that offset is reached in the context
76 * restore. When a context is being restored, this is executed after the
77 * ring context, in the middle (or beginning) of the engine context image.
78 *
79 * #. BB_PER_CTX_PTR (also known as **post context restore bb**): A
80 * batchbuffer is provided in the default context, pointing the hardware to
81 * a buffer to continue executing after the engine registers are restored
82 * in a context restore sequence.
83 *
84 * Below is the timeline for a context restore sequence:
85 *
86 * .. code::
87 *
88 * INDIRECT_CTX_OFFSET
89 * |----------->|
90 * .------------.------------.-------------.------------.--------------.-----------.
91 * |Ring | Engine | Mid-context | Engine | Post-context | Ring |
92 * |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution |
93 * `------------'------------'-------------'------------'--------------'-----------'
94 *
95 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from
96 * a central place. Those are peppered around the rest of the code, as needed.
97 * There's a central place to control which workarounds are enabled:
98 * drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and
99 * drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds.
100 * These files only record which workarounds are enabled: during early device
101 * initialization those rules are evaluated and recorded by the driver. Then
102 * later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to
103 * implement them.
104 *
105 * .. [1] Technically, some registers are powercontext saved & restored, so they
106 * survive a suspend/resume. In practice, writing them again is not too
107 * costly and simplifies things, so it's the approach taken in the driver.
108 *
109 * .. note::
110 * Hardware workarounds in xe work the same way as in i915, with the
111 * difference of how they are maintained in the code. In xe it uses the
112 * xe_rtp infrastructure so the workarounds can be kept in tables, following
113 * a more declarative approach rather than procedural.
114 *
115 * .. note::
116 * When a workaround applies to every single known IP version in a range,
117 * the preferred handling is to use a single range-based RTP entry rather
118 * than individual entries for each version, even if some of the intermediate
119 * version numbers are currently unused. If a new intermediate IP version
120 * appears in the future and is enabled in the driver, any existing
121 * range-based entries that contain the new version number will need to be
122 * analyzed to determine whether their workarounds should apply to the new
123 * version, or whether any existing range based entries needs to be split
124 * into two entries that do not include the new intermediate version.
125 */
126
127 #undef XE_REG_MCR
128 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
129
130 __diag_push();
131 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
132
133 static const struct xe_rtp_entry_sr gt_was[] = {
134 /* Workarounds applying over a range of IPs */
135
136 { XE_RTP_NAME("14011060649"),
137 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
138 ENGINE_CLASS(VIDEO_DECODE),
139 FUNC(xe_rtp_match_even_instance)),
140 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
141 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
142 },
143 { XE_RTP_NAME("14011059788"),
144 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
145 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
146 },
147 { XE_RTP_NAME("14015795083"),
148 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
149 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
150 },
151 { XE_RTP_NAME("16021867713"),
152 XE_RTP_RULES(MEDIA_VERSION_RANGE(1300, 3002),
153 ENGINE_CLASS(VIDEO_DECODE)),
154 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
155 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
156 },
157 { XE_RTP_NAME("14019449301"),
158 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 2000), ENGINE_CLASS(VIDEO_DECODE)),
159 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
160 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
161 },
162 { XE_RTP_NAME("16028005424"),
163 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), OR,
164 MEDIA_VERSION_RANGE(1301, 3500)),
165 XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
166 },
167 { XE_RTP_NAME("14026578760"),
168 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, 3511), OR,
169 MEDIA_VERSION(3503)),
170 XE_RTP_ACTIONS(SET(GAMSTLB_CTRL, DIS_PEND_GPA_LINK))
171 },
172
173 /* DG1 */
174
175 { XE_RTP_NAME("1409420604"),
176 XE_RTP_RULES(PLATFORM(DG1)),
177 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
178 },
179 { XE_RTP_NAME("1408615072"),
180 XE_RTP_RULES(PLATFORM(DG1)),
181 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
182 },
183
184 /* DG2 */
185
186 { XE_RTP_NAME("22010523718"),
187 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
188 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
189 },
190 { XE_RTP_NAME("14011006942"),
191 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
192 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
193 },
194 { XE_RTP_NAME("14014830051"),
195 XE_RTP_RULES(PLATFORM(DG2)),
196 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
197 },
198 { XE_RTP_NAME("18018781329"),
199 XE_RTP_RULES(PLATFORM(DG2)),
200 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
201 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
202 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
203 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
204 },
205 { XE_RTP_NAME("1509235366"),
206 XE_RTP_RULES(PLATFORM(DG2)),
207 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
208 INVALIDATION_BROADCAST_MODE_DIS |
209 GLOBAL_INVALIDATION_MODE))
210 },
211
212 /* PVC */
213
214 { XE_RTP_NAME("18018781329"),
215 XE_RTP_RULES(PLATFORM(PVC)),
216 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
217 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
218 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
219 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
220 },
221 { XE_RTP_NAME("16016694945"),
222 XE_RTP_RULES(PLATFORM(PVC)),
223 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
224 },
225
226 /* Xe_LPG */
227
228 { XE_RTP_NAME("14018575942"),
229 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
230 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
231 },
232 { XE_RTP_NAME("22016670082"),
233 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
234 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
235 },
236
237 /* Xe_LPM+ */
238
239 { XE_RTP_NAME("22016670082"),
240 XE_RTP_RULES(MEDIA_VERSION(1300)),
241 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
242 },
243
244 /* Xe2_LPM */
245
246 { XE_RTP_NAME("14017421178"),
247 XE_RTP_RULES(MEDIA_VERSION(2000),
248 ENGINE_CLASS(VIDEO_DECODE)),
249 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
250 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
251 },
252
253 /* Xe2_HPG */
254
255 { XE_RTP_NAME("16025250150"),
256 XE_RTP_RULES(GRAPHICS_VERSION(2001)),
257 XE_RTP_ACTIONS(FIELD_SET(LSN_VC_REG2,
258 LSN_LNI_WGT_MASK | LSN_LNE_WGT_MASK |
259 LSN_DIM_X_WGT_MASK | LSN_DIM_Y_WGT_MASK |
260 LSN_DIM_Z_WGT_MASK,
261 LSN_LNI_WGT(1) | LSN_LNE_WGT(1) |
262 LSN_DIM_X_WGT(1) | LSN_DIM_Y_WGT(1) |
263 LSN_DIM_Z_WGT(1)),
264 SET(LSC_CHICKEN_BIT_0_UDW, L3_128B_256B_WRT_DIS))
265 },
266
267 /* Xe3_LPG */
268
269 { XE_RTP_NAME("14021871409"),
270 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
271 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS))
272 },
273
274 /* Xe3_LPM */
275
276 { XE_RTP_NAME("16021865536"),
277 XE_RTP_RULES(MEDIA_VERSION_RANGE(3000, 3002),
278 ENGINE_CLASS(VIDEO_DECODE)),
279 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
280 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
281 },
282 { XE_RTP_NAME("14021486841"),
283 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
284 ENGINE_CLASS(VIDEO_DECODE)),
285 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
286 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
287 },
288
289 /* Xe3P_LPG */
290
291 { XE_RTP_NAME("14025160223"),
292 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
293 XE_RTP_ACTIONS(SET(MMIOATSREQLIMIT_GAM_WALK_3D,
294 DIS_ATS_WRONLY_PG))
295 },
296 { XE_RTP_NAME("14026144927, 16029437861"),
297 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
298 XE_RTP_ACTIONS(SET(L3SQCREG2, L3_SQ_DISABLE_COAMA_2WAY_COH |
299 L3_SQ_DISABLE_COAMA))
300 },
301 { XE_RTP_NAME("14025635424"),
302 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
303 XE_RTP_ACTIONS(SET(GAMSTLB_CTRL2, STLB_SINGLE_BANK_MODE))
304 },
305 { XE_RTP_NAME("16028005424"),
306 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
307 XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
308 },
309 };
310
311 static const struct xe_rtp_entry_sr engine_was[] = {
312 /* Workarounds applying over a range of IPs */
313
314 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
315 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
316 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
317 FF_TESSELATION_DOP_GATE_DISABLE))
318 },
319 { XE_RTP_NAME("1409804808"),
320 XE_RTP_RULES(GRAPHICS_VERSION(1200),
321 ENGINE_CLASS(RENDER),
322 IS_INTEGRATED),
323 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
324 },
325 { XE_RTP_NAME("14010229206, 1409085225"),
326 XE_RTP_RULES(GRAPHICS_VERSION(1200),
327 ENGINE_CLASS(RENDER),
328 IS_INTEGRATED),
329 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
330 },
331 { XE_RTP_NAME("1606931601"),
332 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
333 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
334 },
335 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
336 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
337 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),
338 FF_DOP_CLOCK_GATE_DISABLE))
339 },
340 { XE_RTP_NAME("1406941453"),
341 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
342 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
343 },
344 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
345 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
346 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
347 FFSC_PERCTX_PREEMPT_CTRL))
348 },
349 { XE_RTP_NAME("18032247524"),
350 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
351 FUNC(xe_rtp_match_first_render_or_compute)),
352 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
353 },
354 { XE_RTP_NAME("16018712365"),
355 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
356 FUNC(xe_rtp_match_first_render_or_compute)),
357 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
358 },
359 { XE_RTP_NAME("14020338487"),
360 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
361 FUNC(xe_rtp_match_first_render_or_compute)),
362 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
363 },
364 { XE_RTP_NAME("14018471104"),
365 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
366 FUNC(xe_rtp_match_first_render_or_compute)),
367 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
368 },
369 /*
370 * Although this workaround isn't required for the RCS, disabling these
371 * reports has no impact for our driver or the GuC, so we go ahead and
372 * apply this to all engines for simplicity.
373 */
374 { XE_RTP_NAME("16021639441"),
375 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), OR,
376 MEDIA_VERSION_RANGE(1301, 2000)),
377 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
378 GHWSP_CSB_REPORT_DIS |
379 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
380 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
381 },
382 { XE_RTP_NAME("14021402888"),
383 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005), ENGINE_CLASS(RENDER)),
384 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
385 },
386 { XE_RTP_NAME("13012615864"),
387 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005),
388 FUNC(xe_rtp_match_first_render_or_compute)),
389 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
390 },
391 { XE_RTP_NAME("18041344222"),
392 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3000),
393 FUNC(xe_rtp_match_first_render_or_compute),
394 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
395 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
396 },
397
398 /* TGL */
399
400 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
401 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
402 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
403 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
404 RC_SEMA_IDLE_MSG_DISABLE))
405 },
406
407 /* RKL */
408
409 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
410 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
411 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
412 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
413 RC_SEMA_IDLE_MSG_DISABLE))
414 },
415
416 /* ADL-P */
417
418 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
419 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
420 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
421 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
422 RC_SEMA_IDLE_MSG_DISABLE))
423 },
424
425 /* DG2 */
426
427 { XE_RTP_NAME("22013037850"),
428 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
429 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
430 DISABLE_128B_EVICTION_COMMAND_UDW))
431 },
432 { XE_RTP_NAME("22014226127"),
433 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
434 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
435 },
436 { XE_RTP_NAME("18017747507"),
437 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
438 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
439 POLYGON_TRIFAN_LINELOOP_DISABLE))
440 },
441 { XE_RTP_NAME("22012826095, 22013059131"),
442 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
443 FUNC(xe_rtp_match_first_render_or_compute)),
444 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
445 MAXREQS_PER_BANK,
446 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
447 },
448 { XE_RTP_NAME("22013059131"),
449 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
450 FUNC(xe_rtp_match_first_render_or_compute)),
451 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
452 },
453 { XE_RTP_NAME("14015227452"),
454 XE_RTP_RULES(PLATFORM(DG2),
455 FUNC(xe_rtp_match_first_render_or_compute)),
456 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
457 },
458 { XE_RTP_NAME("18028616096"),
459 XE_RTP_RULES(PLATFORM(DG2),
460 FUNC(xe_rtp_match_first_render_or_compute)),
461 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
462 },
463 { XE_RTP_NAME("22015475538"),
464 XE_RTP_RULES(PLATFORM(DG2),
465 FUNC(xe_rtp_match_first_render_or_compute)),
466 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
467 },
468 { XE_RTP_NAME("22012654132"),
469 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
470 FUNC(xe_rtp_match_first_render_or_compute)),
471 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
472 /*
473 * Register can't be read back for verification on
474 * DG2 due to Wa_14012342262
475 */
476 .read_mask = 0))
477 },
478 { XE_RTP_NAME("1509727124"),
479 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
480 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
481 },
482 { XE_RTP_NAME("22012856258"),
483 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
484 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
485 },
486 { XE_RTP_NAME("22010960976, 14013347512"),
487 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
488 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
489 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
490 },
491 { XE_RTP_NAME("14015150844"),
492 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
493 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
494 XE_RTP_NOCHECK))
495 },
496
497 /* PVC */
498
499 { XE_RTP_NAME("22014226127"),
500 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
501 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
502 },
503 { XE_RTP_NAME("14015227452"),
504 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
505 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
506 },
507 { XE_RTP_NAME("18020744125"),
508 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute),
509 ENGINE_CLASS(COMPUTE)),
510 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
511 },
512
513 /* Xe_LPG */
514
515 { XE_RTP_NAME("14017856879"),
516 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
517 FUNC(xe_rtp_match_first_render_or_compute)),
518 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
519 },
520 { XE_RTP_NAME("14015150844"),
521 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
522 FUNC(xe_rtp_match_first_render_or_compute)),
523 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
524 XE_RTP_NOCHECK))
525 },
526 { XE_RTP_NAME("14020495402"),
527 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
528 FUNC(xe_rtp_match_first_render_or_compute)),
529 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING))
530 },
531
532 /* Xe2_LPG */
533
534 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */
535 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
536 FUNC(xe_rtp_match_first_render_or_compute)),
537 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
538 },
539 { XE_RTP_NAME("16018610683"),
540 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
541 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
542 },
543
544 /* Xe2_HPG */
545
546 { XE_RTP_NAME("16018737384"),
547 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2999),
548 FUNC(xe_rtp_match_first_render_or_compute)),
549 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
550 },
551 { XE_RTP_NAME("14019811474"),
552 XE_RTP_RULES(GRAPHICS_VERSION(2001),
553 FUNC(xe_rtp_match_first_render_or_compute)),
554 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
555 },
556 { XE_RTP_NAME("14021821874, 14022954250"),
557 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
558 FUNC(xe_rtp_match_first_render_or_compute)),
559 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
560 },
561
562 /* Xe3_LPG */
563
564 { XE_RTP_NAME("18034896535"),
565 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
566 FUNC(xe_rtp_match_first_render_or_compute)),
567 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
568 },
569 { XE_RTP_NAME("16024792527"),
570 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
571 FUNC(xe_rtp_match_first_render_or_compute)),
572 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER,
573 SMP_FORCE_128B_OVERFETCH))
574 },
575 { XE_RTP_NAME("14023061436"),
576 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005),
577 FUNC(xe_rtp_match_first_render_or_compute)),
578 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
579 },
580 { XE_RTP_NAME("16023105232"),
581 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR,
582 GRAPHICS_VERSION_RANGE(2001, 3001)),
583 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
584 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
585 },
586
587 /* Xe3p_LPG*/
588
589 { XE_RTP_NAME("22021149932"),
590 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
591 FUNC(xe_rtp_match_first_render_or_compute)),
592 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, SAMPLER_LD_LSC_DISABLE))
593 },
594 { XE_RTP_NAME("14025676848"),
595 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
596 FUNC(xe_rtp_match_first_render_or_compute)),
597 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE))
598 },
599 { XE_RTP_NAME("16028951944"),
600 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
601 FUNC(xe_rtp_match_first_render_or_compute)),
602 XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS))
603 },
604 };
605
606 static const struct xe_rtp_entry_sr lrc_was[] = {
607 { XE_RTP_NAME("16011163337"),
608 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
609 /* read verification is ignored due to 1608008084. */
610 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
611 FF_MODE2_GS_TIMER_MASK,
612 FF_MODE2_GS_TIMER_224))
613 },
614 { XE_RTP_NAME("1604555607"),
615 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
616 /* read verification is ignored due to 1608008084. */
617 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
618 FF_MODE2_TDS_TIMER_MASK,
619 FF_MODE2_TDS_TIMER_128))
620 },
621 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
622 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
623 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
624 DISABLE_CPS_AWARE_COLOR_PIPE))
625 },
626 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
627 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
628 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
629 PREEMPT_GPGPU_LEVEL_MASK,
630 PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
631 },
632 { XE_RTP_NAME("1806527549"),
633 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
634 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
635 },
636 { XE_RTP_NAME("1606376872"),
637 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
638 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
639 },
640 { XE_RTP_NAME("14019877138"),
641 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, 2004), ENGINE_CLASS(RENDER)),
642 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
643 },
644 { XE_RTP_NAME("14019386621"),
645 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
646 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
647 },
648 { XE_RTP_NAME("14019988906"),
649 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
650 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
651 },
652 { XE_RTP_NAME("18033852989"),
653 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
654 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
655 },
656 { XE_RTP_NAME("15016589081"),
657 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
658 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
659 },
660 { XE_RTP_NAME("14026781792"),
661 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3510), ENGINE_CLASS(RENDER)),
662 XE_RTP_ACTIONS(SET(FF_MODE, DIS_TE_PATCH_CTRL))
663 },
664
665 /* DG1 */
666
667 { XE_RTP_NAME("1409044764"),
668 XE_RTP_RULES(PLATFORM(DG1)),
669 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
670 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
671 },
672 { XE_RTP_NAME("22010493298"),
673 XE_RTP_RULES(PLATFORM(DG1)),
674 XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
675 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
676 },
677
678 /* DG2 */
679
680 { XE_RTP_NAME("16013271637"),
681 XE_RTP_RULES(PLATFORM(DG2)),
682 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
683 MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
684 },
685 { XE_RTP_NAME("14014947963"),
686 XE_RTP_RULES(PLATFORM(DG2)),
687 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
688 PREEMPTION_VERTEX_COUNT,
689 0x4000))
690 },
691 { XE_RTP_NAME("18018764978"),
692 XE_RTP_RULES(PLATFORM(DG2)),
693 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
694 SCOREBOARD_STALL_FLUSH_CONTROL))
695 },
696 { XE_RTP_NAME("18019271663"),
697 XE_RTP_RULES(PLATFORM(DG2)),
698 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
699 },
700
701 /* PVC */
702
703 { XE_RTP_NAME("16017236439"),
704 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
705 FUNC(xe_rtp_match_even_instance)),
706 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
707 BCS_SWCTRL_DISABLE_256B,
708 XE_RTP_ACTION_FLAG(ENGINE_BASE))),
709 },
710
711 /* Xe_LPG */
712
713 { XE_RTP_NAME("18019271663"),
714 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
715 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
716 },
717
718 /* Xe2_LPG */
719
720 { XE_RTP_NAME("14021567978"),
721 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
722 ENGINE_CLASS(RENDER)),
723 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
724 },
725 { XE_RTP_NAME("14020756599"),
726 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR,
727 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)),
728 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
729 },
730 { XE_RTP_NAME("14021490052"),
731 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
732 XE_RTP_ACTIONS(SET(FF_MODE,
733 DIS_MESH_PARTIAL_AUTOSTRIP |
734 DIS_MESH_AUTOSTRIP),
735 SET(VFLSKPD,
736 DIS_PARTIAL_AUTOSTRIP |
737 DIS_AUTOSTRIP))
738 },
739
740 /* Xe2_HPG */
741
742 { XE_RTP_NAME("14020756599"),
743 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
744 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
745 },
746 { XE_RTP_NAME("14019988906"),
747 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
748 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
749 },
750 { XE_RTP_NAME("14019877138"),
751 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
752 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
753 },
754 { XE_RTP_NAME("14021490052"),
755 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
756 XE_RTP_ACTIONS(SET(FF_MODE,
757 DIS_MESH_PARTIAL_AUTOSTRIP |
758 DIS_MESH_AUTOSTRIP),
759 SET(VFLSKPD,
760 DIS_PARTIAL_AUTOSTRIP |
761 DIS_AUTOSTRIP))
762 },
763 { XE_RTP_NAME("22021007897"),
764 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
765 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
766 },
767
768 /* Xe3_LPG */
769 { XE_RTP_NAME("14021490052"),
770 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
771 ENGINE_CLASS(RENDER)),
772 XE_RTP_ACTIONS(SET(FF_MODE,
773 DIS_MESH_PARTIAL_AUTOSTRIP |
774 DIS_MESH_AUTOSTRIP),
775 SET(VFLSKPD,
776 DIS_PARTIAL_AUTOSTRIP |
777 DIS_AUTOSTRIP))
778 },
779 { XE_RTP_NAME("22021007897"),
780 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),
781 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
782 },
783 { XE_RTP_NAME("14024681466"),
784 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),
785 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, FAST_CLEAR_VALIGN_FIX))
786 },
787 { XE_RTP_NAME("15016589081"),
788 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
789 ENGINE_CLASS(RENDER)),
790 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
791 },
792 };
793
794 static __maybe_unused const struct xe_rtp_entry oob_was[] = {
795 #include <generated/xe_wa_oob.c>
796 {}
797 };
798
799 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
800
801 static __maybe_unused const struct xe_rtp_entry device_oob_was[] = {
802 #include <generated/xe_device_wa_oob.c>
803 {}
804 };
805
806 static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT);
807
808 __diag_pop();
809
810 /**
811 * xe_wa_process_device_oob - process OOB workaround table
812 * @xe: device instance to process workarounds for
813 *
814 * process OOB workaround table for this device, marking in @xe the
815 * workarounds that are active.
816 */
817
xe_wa_process_device_oob(struct xe_device * xe)818 void xe_wa_process_device_oob(struct xe_device *xe)
819 {
820 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe);
821
822 xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was));
823
824 xe->wa_active.oob_initialized = true;
825 xe_rtp_process(&ctx, device_oob_was);
826 }
827
828 /**
829 * xe_wa_process_gt_oob - process GT OOB workaround table
830 * @gt: GT instance to process workarounds for
831 *
832 * Process OOB workaround table for this platform, marking in @gt the
833 * workarounds that are active.
834 */
xe_wa_process_gt_oob(struct xe_gt * gt)835 void xe_wa_process_gt_oob(struct xe_gt *gt)
836 {
837 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
838
839 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
840 ARRAY_SIZE(oob_was));
841 gt->wa_active.oob_initialized = true;
842 xe_rtp_process(&ctx, oob_was);
843 }
844
845 /**
846 * xe_wa_process_gt - process GT workaround table
847 * @gt: GT instance to process workarounds for
848 *
849 * Process GT workaround table for this platform, saving in @gt all the
850 * workarounds that need to be applied at the GT level.
851 */
xe_wa_process_gt(struct xe_gt * gt)852 void xe_wa_process_gt(struct xe_gt *gt)
853 {
854 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
855
856 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
857 ARRAY_SIZE(gt_was));
858 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was),
859 >->reg_sr, false);
860 }
861 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
862
863 /**
864 * xe_wa_process_engine - process engine workaround table
865 * @hwe: engine instance to process workarounds for
866 *
867 * Process engine workaround table for this platform, saving in @hwe all the
868 * workarounds that need to be applied at the engine level that match this
869 * engine.
870 */
xe_wa_process_engine(struct xe_hw_engine * hwe)871 void xe_wa_process_engine(struct xe_hw_engine *hwe)
872 {
873 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
874
875 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
876 ARRAY_SIZE(engine_was));
877 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was),
878 &hwe->reg_sr, false);
879 }
880
881 /**
882 * xe_wa_process_lrc - process context workaround table
883 * @hwe: engine instance to process workarounds for
884 *
885 * Process context workaround table for this platform, saving in @hwe all the
886 * workarounds that need to be applied on context restore. These are workarounds
887 * touching registers that are part of the HW context image.
888 */
xe_wa_process_lrc(struct xe_hw_engine * hwe)889 void xe_wa_process_lrc(struct xe_hw_engine *hwe)
890 {
891 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
892
893 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
894 ARRAY_SIZE(lrc_was));
895 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was),
896 &hwe->reg_lrc, true);
897 }
898
899 /**
900 * xe_wa_device_init - initialize device with workaround oob bookkeeping
901 * @xe: Xe device instance to initialize
902 *
903 * Returns 0 for success, negative with error code otherwise
904 */
xe_wa_device_init(struct xe_device * xe)905 int xe_wa_device_init(struct xe_device *xe)
906 {
907 unsigned long *p;
908
909 p = drmm_kzalloc(&xe->drm,
910 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)),
911 GFP_KERNEL);
912
913 if (!p)
914 return -ENOMEM;
915
916 xe->wa_active.oob = p;
917
918 return 0;
919 }
920
921 /**
922 * xe_wa_gt_init - initialize gt with workaround bookkeeping
923 * @gt: GT instance to initialize
924 *
925 * Returns 0 for success, negative error code otherwise.
926 */
xe_wa_gt_init(struct xe_gt * gt)927 int xe_wa_gt_init(struct xe_gt *gt)
928 {
929 struct xe_device *xe = gt_to_xe(gt);
930 size_t n_oob, n_lrc, n_engine, n_gt, total;
931 unsigned long *p;
932
933 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
934 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
935 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
936 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
937 total = n_gt + n_engine + n_lrc + n_oob;
938
939 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
940 if (!p)
941 return -ENOMEM;
942
943 gt->wa_active.gt = p;
944 p += n_gt;
945 gt->wa_active.engine = p;
946 p += n_engine;
947 gt->wa_active.lrc = p;
948 p += n_lrc;
949 gt->wa_active.oob = p;
950
951 return 0;
952 }
953 ALLOW_ERROR_INJECTION(xe_wa_gt_init, ERRNO); /* See xe_pci_probe() */
954
xe_wa_device_dump(struct xe_device * xe,struct drm_printer * p)955 void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p)
956 {
957 size_t idx;
958
959 drm_printf(p, "Device OOB Workarounds\n");
960 for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was))
961 if (device_oob_was[idx].name)
962 drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name);
963 }
964
965 /**
966 * xe_wa_gt_dump() - Dump GT workarounds into a drm printer.
967 * @gt: the &xe_gt
968 * @p: the &drm_printer
969 *
970 * Return: always 0.
971 */
xe_wa_gt_dump(struct xe_gt * gt,struct drm_printer * p)972 int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p)
973 {
974 size_t idx;
975
976 drm_printf(p, "GT Workarounds\n");
977 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
978 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
979
980 drm_puts(p, "\n");
981 drm_printf(p, "Engine Workarounds\n");
982 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
983 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
984
985 drm_puts(p, "\n");
986 drm_printf(p, "LRC Workarounds\n");
987 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
988 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
989
990 drm_puts(p, "\n");
991 drm_printf(p, "OOB Workarounds\n");
992 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
993 if (oob_was[idx].name)
994 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
995 return 0;
996 }
997
998 /*
999 * Apply tile (non-GT, non-display) workarounds. Think very carefully before
1000 * adding anything to this function; most workarounds should be implemented
1001 * elsewhere. The programming here is primarily for sgunit/soc workarounds,
1002 * which are relatively rare. Since the registers these workarounds target are
1003 * outside the GT, they should only need to be applied once at device
1004 * probe/resume; they will not lose their values on any kind of GT or engine
1005 * reset.
1006 *
1007 * TODO: We may want to move this over to xe_rtp in the future once we have
1008 * enough workarounds to justify the work.
1009 */
xe_wa_apply_tile_workarounds(struct xe_tile * tile)1010 void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
1011 {
1012 struct xe_mmio *mmio = &tile->mmio;
1013
1014 if (IS_SRIOV_VF(tile->xe))
1015 return;
1016
1017 if (XE_DEVICE_WA(tile->xe, 22010954014))
1018 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
1019 }
1020