1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2015-2018 Etnaviv Project
4 */
5
6 #include <linux/clk.h>
7 #include <linux/component.h>
8 #include <linux/delay.h>
9 #include <linux/dma-fence.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/thermal.h>
17
18 #include "etnaviv_cmdbuf.h"
19 #include "etnaviv_dump.h"
20 #include "etnaviv_gpu.h"
21 #include "etnaviv_gem.h"
22 #include "etnaviv_mmu.h"
23 #include "etnaviv_perfmon.h"
24 #include "etnaviv_sched.h"
25 #include "common.xml.h"
26 #include "state.xml.h"
27 #include "state_hi.xml.h"
28 #include "cmdstream.xml.h"
29
30 static const struct platform_device_id gpu_ids[] = {
31 { .name = "etnaviv-gpu,2d" },
32 { },
33 };
34
35 /*
36 * Driver functions:
37 */
38
etnaviv_gpu_get_param(struct etnaviv_gpu * gpu,u32 param,u64 * value)39 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
40 {
41 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
42
43 switch (param) {
44 case ETNAVIV_PARAM_GPU_MODEL:
45 *value = gpu->identity.model;
46 break;
47
48 case ETNAVIV_PARAM_GPU_REVISION:
49 *value = gpu->identity.revision;
50 break;
51
52 case ETNAVIV_PARAM_GPU_FEATURES_0:
53 *value = gpu->identity.features;
54 break;
55
56 case ETNAVIV_PARAM_GPU_FEATURES_1:
57 *value = gpu->identity.minor_features0;
58 break;
59
60 case ETNAVIV_PARAM_GPU_FEATURES_2:
61 *value = gpu->identity.minor_features1;
62 break;
63
64 case ETNAVIV_PARAM_GPU_FEATURES_3:
65 *value = gpu->identity.minor_features2;
66 break;
67
68 case ETNAVIV_PARAM_GPU_FEATURES_4:
69 *value = gpu->identity.minor_features3;
70 break;
71
72 case ETNAVIV_PARAM_GPU_FEATURES_5:
73 *value = gpu->identity.minor_features4;
74 break;
75
76 case ETNAVIV_PARAM_GPU_FEATURES_6:
77 *value = gpu->identity.minor_features5;
78 break;
79
80 case ETNAVIV_PARAM_GPU_FEATURES_7:
81 *value = gpu->identity.minor_features6;
82 break;
83
84 case ETNAVIV_PARAM_GPU_FEATURES_8:
85 *value = gpu->identity.minor_features7;
86 break;
87
88 case ETNAVIV_PARAM_GPU_FEATURES_9:
89 *value = gpu->identity.minor_features8;
90 break;
91
92 case ETNAVIV_PARAM_GPU_FEATURES_10:
93 *value = gpu->identity.minor_features9;
94 break;
95
96 case ETNAVIV_PARAM_GPU_FEATURES_11:
97 *value = gpu->identity.minor_features10;
98 break;
99
100 case ETNAVIV_PARAM_GPU_FEATURES_12:
101 *value = gpu->identity.minor_features11;
102 break;
103
104 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
105 *value = gpu->identity.stream_count;
106 break;
107
108 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
109 *value = gpu->identity.register_max;
110 break;
111
112 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
113 *value = gpu->identity.thread_count;
114 break;
115
116 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
117 *value = gpu->identity.vertex_cache_size;
118 break;
119
120 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
121 *value = gpu->identity.shader_core_count;
122 break;
123
124 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
125 *value = gpu->identity.pixel_pipes;
126 break;
127
128 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
129 *value = gpu->identity.vertex_output_buffer_size;
130 break;
131
132 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
133 *value = gpu->identity.buffer_size;
134 break;
135
136 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
137 *value = gpu->identity.instruction_count;
138 break;
139
140 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
141 *value = gpu->identity.num_constants;
142 break;
143
144 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
145 *value = gpu->identity.varyings_count;
146 break;
147
148 case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
149 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
150 *value = ETNAVIV_SOFTPIN_START_ADDRESS;
151 else
152 *value = ~0ULL;
153 break;
154
155 case ETNAVIV_PARAM_GPU_PRODUCT_ID:
156 *value = gpu->identity.product_id;
157 break;
158
159 case ETNAVIV_PARAM_GPU_CUSTOMER_ID:
160 *value = gpu->identity.customer_id;
161 break;
162
163 case ETNAVIV_PARAM_GPU_ECO_ID:
164 *value = gpu->identity.eco_id;
165 break;
166
167 default:
168 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
169 return -EINVAL;
170 }
171
172 return 0;
173 }
174
etnaviv_is_model_rev(struct etnaviv_gpu * gpu,u32 model,u32 revision)175 static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision)
176 {
177 return gpu->identity.model == model &&
178 gpu->identity.revision == revision;
179 }
180
181 #define etnaviv_field(val, field) \
182 (((val) & field##__MASK) >> field##__SHIFT)
183
etnaviv_hw_specs(struct etnaviv_gpu * gpu)184 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
185 {
186 if (gpu->identity.minor_features0 &
187 chipMinorFeatures0_MORE_MINOR_FEATURES) {
188 u32 specs[4];
189 unsigned int streams;
190
191 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
192 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
193 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
194 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
195
196 gpu->identity.stream_count = etnaviv_field(specs[0],
197 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
198 gpu->identity.register_max = etnaviv_field(specs[0],
199 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
200 gpu->identity.thread_count = etnaviv_field(specs[0],
201 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
202 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
203 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
204 gpu->identity.shader_core_count = etnaviv_field(specs[0],
205 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
206 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
207 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
208 gpu->identity.vertex_output_buffer_size =
209 etnaviv_field(specs[0],
210 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
211
212 gpu->identity.buffer_size = etnaviv_field(specs[1],
213 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
214 gpu->identity.instruction_count = etnaviv_field(specs[1],
215 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
216 gpu->identity.num_constants = etnaviv_field(specs[1],
217 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
218
219 gpu->identity.varyings_count = etnaviv_field(specs[2],
220 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
221
222 /* This overrides the value from older register if non-zero */
223 streams = etnaviv_field(specs[3],
224 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
225 if (streams)
226 gpu->identity.stream_count = streams;
227 }
228
229 /* Fill in the stream count if not specified */
230 if (gpu->identity.stream_count == 0) {
231 if (gpu->identity.model >= 0x1000)
232 gpu->identity.stream_count = 4;
233 else
234 gpu->identity.stream_count = 1;
235 }
236
237 /* Convert the register max value */
238 if (gpu->identity.register_max)
239 gpu->identity.register_max = 1 << gpu->identity.register_max;
240 else if (gpu->identity.model == chipModel_GC400)
241 gpu->identity.register_max = 32;
242 else
243 gpu->identity.register_max = 64;
244
245 /* Convert thread count */
246 if (gpu->identity.thread_count)
247 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
248 else if (gpu->identity.model == chipModel_GC400)
249 gpu->identity.thread_count = 64;
250 else if (gpu->identity.model == chipModel_GC500 ||
251 gpu->identity.model == chipModel_GC530)
252 gpu->identity.thread_count = 128;
253 else
254 gpu->identity.thread_count = 256;
255
256 if (gpu->identity.vertex_cache_size == 0)
257 gpu->identity.vertex_cache_size = 8;
258
259 if (gpu->identity.shader_core_count == 0) {
260 if (gpu->identity.model >= 0x1000)
261 gpu->identity.shader_core_count = 2;
262 else
263 gpu->identity.shader_core_count = 1;
264 }
265
266 if (gpu->identity.pixel_pipes == 0)
267 gpu->identity.pixel_pipes = 1;
268
269 /* Convert virtex buffer size */
270 if (gpu->identity.vertex_output_buffer_size) {
271 gpu->identity.vertex_output_buffer_size =
272 1 << gpu->identity.vertex_output_buffer_size;
273 } else if (gpu->identity.model == chipModel_GC400) {
274 if (gpu->identity.revision < 0x4000)
275 gpu->identity.vertex_output_buffer_size = 512;
276 else if (gpu->identity.revision < 0x4200)
277 gpu->identity.vertex_output_buffer_size = 256;
278 else
279 gpu->identity.vertex_output_buffer_size = 128;
280 } else {
281 gpu->identity.vertex_output_buffer_size = 512;
282 }
283
284 switch (gpu->identity.instruction_count) {
285 case 0:
286 if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
287 gpu->identity.model == chipModel_GC880)
288 gpu->identity.instruction_count = 512;
289 else
290 gpu->identity.instruction_count = 256;
291 break;
292
293 case 1:
294 gpu->identity.instruction_count = 1024;
295 break;
296
297 case 2:
298 gpu->identity.instruction_count = 2048;
299 break;
300
301 default:
302 gpu->identity.instruction_count = 256;
303 break;
304 }
305
306 if (gpu->identity.num_constants == 0)
307 gpu->identity.num_constants = 168;
308
309 if (gpu->identity.varyings_count == 0) {
310 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
311 gpu->identity.varyings_count = 12;
312 else
313 gpu->identity.varyings_count = 8;
314 }
315
316 /*
317 * For some cores, two varyings are consumed for position, so the
318 * maximum varying count needs to be reduced by one.
319 */
320 if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) ||
321 etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
322 etnaviv_is_model_rev(gpu, 0x4000, 0x5245) ||
323 etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
324 etnaviv_is_model_rev(gpu, 0x3000, 0x5435) ||
325 etnaviv_is_model_rev(gpu, 0x2200, 0x5244) ||
326 etnaviv_is_model_rev(gpu, 0x2100, 0x5108) ||
327 etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
328 etnaviv_is_model_rev(gpu, 0x1500, 0x5246) ||
329 etnaviv_is_model_rev(gpu, 0x880, 0x5107) ||
330 etnaviv_is_model_rev(gpu, 0x880, 0x5106))
331 gpu->identity.varyings_count -= 1;
332 }
333
etnaviv_hw_identify(struct etnaviv_gpu * gpu)334 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
335 {
336 u32 chipIdentity;
337
338 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
339
340 /* Special case for older graphic cores. */
341 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
342 gpu->identity.model = chipModel_GC500;
343 gpu->identity.revision = etnaviv_field(chipIdentity,
344 VIVS_HI_CHIP_IDENTITY_REVISION);
345 } else {
346 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
347
348 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
349 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
350 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
351
352 /*
353 * Reading these two registers on GC600 rev 0x19 result in a
354 * unhandled fault: external abort on non-linefetch
355 */
356 if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) {
357 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
358 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
359 }
360
361 /*
362 * !!!! HACK ALERT !!!!
363 * Because people change device IDs without letting software
364 * know about it - here is the hack to make it all look the
365 * same. Only for GC400 family.
366 */
367 if ((gpu->identity.model & 0xff00) == 0x0400 &&
368 gpu->identity.model != chipModel_GC420) {
369 gpu->identity.model = gpu->identity.model & 0x0400;
370 }
371
372 /* Another special case */
373 if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) {
374 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
375
376 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
377 /*
378 * This IP has an ECO; put the correct
379 * revision in it.
380 */
381 gpu->identity.revision = 0x1051;
382 }
383 }
384
385 /*
386 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
387 * reality it's just a re-branded GC3000. We can identify this
388 * core by the upper half of the revision register being all 1.
389 * Fix model/rev here, so all other places can refer to this
390 * core by its real identity.
391 */
392 if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) {
393 gpu->identity.model = chipModel_GC3000;
394 gpu->identity.revision &= 0xffff;
395 }
396
397 if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617))
398 gpu->identity.eco_id = 1;
399
400 if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511))
401 gpu->identity.eco_id = 1;
402 }
403
404 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
405 gpu->identity.model, gpu->identity.revision);
406
407 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
408 /*
409 * If there is a match in the HWDB, we aren't interested in the
410 * remaining register values, as they might be wrong.
411 */
412 if (etnaviv_fill_identity_from_hwdb(gpu))
413 return;
414
415 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
416
417 /* Disable fast clear on GC700. */
418 if (gpu->identity.model == chipModel_GC700)
419 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
420
421 /* These models/revisions don't have the 2D pipe bit */
422 if ((gpu->identity.model == chipModel_GC500 &&
423 gpu->identity.revision <= 2) ||
424 gpu->identity.model == chipModel_GC300)
425 gpu->identity.features |= chipFeatures_PIPE_2D;
426
427 if ((gpu->identity.model == chipModel_GC500 &&
428 gpu->identity.revision < 2) ||
429 (gpu->identity.model == chipModel_GC300 &&
430 gpu->identity.revision < 0x2000)) {
431
432 /*
433 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
434 * registers.
435 */
436 gpu->identity.minor_features0 = 0;
437 gpu->identity.minor_features1 = 0;
438 gpu->identity.minor_features2 = 0;
439 gpu->identity.minor_features3 = 0;
440 gpu->identity.minor_features4 = 0;
441 gpu->identity.minor_features5 = 0;
442 } else
443 gpu->identity.minor_features0 =
444 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
445
446 if (gpu->identity.minor_features0 &
447 chipMinorFeatures0_MORE_MINOR_FEATURES) {
448 gpu->identity.minor_features1 =
449 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
450 gpu->identity.minor_features2 =
451 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
452 gpu->identity.minor_features3 =
453 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
454 gpu->identity.minor_features4 =
455 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
456 gpu->identity.minor_features5 =
457 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
458 }
459
460 /* GC600/300 idle register reports zero bits where modules aren't present */
461 if (gpu->identity.model == chipModel_GC600 ||
462 gpu->identity.model == chipModel_GC300)
463 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
464 VIVS_HI_IDLE_STATE_RA |
465 VIVS_HI_IDLE_STATE_SE |
466 VIVS_HI_IDLE_STATE_PA |
467 VIVS_HI_IDLE_STATE_SH |
468 VIVS_HI_IDLE_STATE_PE |
469 VIVS_HI_IDLE_STATE_DE |
470 VIVS_HI_IDLE_STATE_FE;
471
472 etnaviv_hw_specs(gpu);
473 }
474
etnaviv_gpu_load_clock(struct etnaviv_gpu * gpu,u32 clock)475 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
476 {
477 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
478 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
479 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
480 }
481
etnaviv_gpu_update_clock(struct etnaviv_gpu * gpu)482 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
483 {
484 if (gpu->identity.minor_features2 &
485 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
486 clk_set_rate(gpu->clk_core,
487 gpu->base_rate_core >> gpu->freq_scale);
488 clk_set_rate(gpu->clk_shader,
489 gpu->base_rate_shader >> gpu->freq_scale);
490 } else {
491 unsigned int fscale = 1 << (6 - gpu->freq_scale);
492 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
493
494 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
495 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
496 etnaviv_gpu_load_clock(gpu, clock);
497 }
498
499 /*
500 * Choose number of wait cycles to target a ~30us (1/32768) max latency
501 * until new work is picked up by the FE when it polls in the idle loop.
502 * If the GPU base frequency is unknown use 200 wait cycles.
503 */
504 gpu->fe_waitcycles = clamp(gpu->base_rate_core >> (15 - gpu->freq_scale),
505 200UL, 0xffffUL);
506 }
507
etnaviv_hw_reset(struct etnaviv_gpu * gpu)508 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
509 {
510 u32 control, idle;
511 unsigned long timeout;
512 bool failed = true;
513
514 /* We hope that the GPU resets in under one second */
515 timeout = jiffies + msecs_to_jiffies(1000);
516
517 while (time_is_after_jiffies(timeout)) {
518 unsigned int fscale = 1 << (6 - gpu->freq_scale);
519 u32 pulse_eater = 0x01590880;
520
521 /* disable clock gating */
522 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, 0x0);
523
524 /* disable pulse eater */
525 pulse_eater |= BIT(17);
526 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
527 pulse_eater |= BIT(0);
528 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
529
530 /* enable clock */
531 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
532 etnaviv_gpu_load_clock(gpu, control);
533
534 /* isolate the GPU. */
535 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
536 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
537
538 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
539 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
540 VIVS_MMUv2_AHB_CONTROL_RESET);
541 } else {
542 /* set soft reset. */
543 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
544 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
545 }
546
547 /* wait for reset. */
548 usleep_range(10, 20);
549
550 /* reset soft reset bit. */
551 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
552 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
553
554 /* reset GPU isolation. */
555 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
556 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
557
558 /* read idle register. */
559 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
560
561 /* try resetting again if FE is not idle */
562 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
563 dev_dbg(gpu->dev, "FE is not idle\n");
564 continue;
565 }
566
567 /* read reset register. */
568 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
569
570 /* is the GPU idle? */
571 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
572 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
573 dev_dbg(gpu->dev, "GPU is not idle\n");
574 continue;
575 }
576
577 /* disable debug registers, as they are not normally needed */
578 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
579 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
580
581 failed = false;
582 break;
583 }
584
585 if (failed) {
586 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
587 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
588
589 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
590 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
591 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
592 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
593
594 return -EBUSY;
595 }
596
597 /* We rely on the GPU running, so program the clock */
598 etnaviv_gpu_update_clock(gpu);
599
600 gpu->state = ETNA_GPU_STATE_RESET;
601 gpu->exec_state = -1;
602 if (gpu->mmu_context)
603 etnaviv_iommu_context_put(gpu->mmu_context);
604 gpu->mmu_context = NULL;
605
606 return 0;
607 }
608
etnaviv_gpu_enable_mlcg(struct etnaviv_gpu * gpu)609 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
610 {
611 u32 pmc, ppc;
612
613 /* enable clock gating */
614 ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
615 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
616
617 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
618 if (gpu->identity.revision == 0x4301 ||
619 gpu->identity.revision == 0x4302)
620 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
621
622 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc);
623
624 pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS);
625
626 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
627 if (gpu->identity.model >= chipModel_GC400 &&
628 gpu->identity.model != chipModel_GC420 &&
629 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
630 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
631
632 /*
633 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
634 * present without a bug fix.
635 */
636 if (gpu->identity.revision < 0x5000 &&
637 gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
638 !(gpu->identity.minor_features1 &
639 chipMinorFeatures1_DISABLE_PE_GATING))
640 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
641
642 if (gpu->identity.revision < 0x5422)
643 pmc |= BIT(15); /* Unknown bit */
644
645 /* Disable TX clock gating on affected core revisions. */
646 if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
647 etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
648 etnaviv_is_model_rev(gpu, 0x7000, 0x6202) ||
649 etnaviv_is_model_rev(gpu, 0x7000, 0x6203))
650 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
651
652 /* Disable SE and RA clock gating on affected core revisions. */
653 if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202))
654 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
655 VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
656
657 /* Disable SH_EU clock gating on affected core revisions. */
658 if (etnaviv_is_model_rev(gpu, 0x8000, 0x7200) ||
659 etnaviv_is_model_rev(gpu, 0x8000, 0x8002) ||
660 etnaviv_is_model_rev(gpu, 0x9200, 0x6304))
661 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU;
662
663 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
664 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
665
666 gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
667 }
668
etnaviv_gpu_start_fe(struct etnaviv_gpu * gpu,u32 address,u16 prefetch)669 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
670 {
671 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
672 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
673 VIVS_FE_COMMAND_CONTROL_ENABLE |
674 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
675
676 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
677 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
678 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
679 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
680 }
681 }
682
etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu * gpu,struct etnaviv_iommu_context * context)683 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu,
684 struct etnaviv_iommu_context *context)
685 {
686 u16 prefetch;
687 u32 address;
688
689 WARN_ON(gpu->state != ETNA_GPU_STATE_INITIALIZED);
690
691 /* setup the MMU */
692 etnaviv_iommu_restore(gpu, context);
693
694 /* Start command processor */
695 prefetch = etnaviv_buffer_init(gpu);
696 address = etnaviv_cmdbuf_get_va(&gpu->buffer,
697 &gpu->mmu_context->cmdbuf_mapping);
698
699 etnaviv_gpu_start_fe(gpu, address, prefetch);
700
701 gpu->state = ETNA_GPU_STATE_RUNNING;
702 }
703
etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu * gpu)704 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
705 {
706 /*
707 * Base value for VIVS_PM_PULSE_EATER register on models where it
708 * cannot be read, extracted from vivante kernel driver.
709 */
710 u32 pulse_eater = 0x01590880;
711
712 if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
713 etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) {
714 pulse_eater |= BIT(23);
715
716 }
717
718 if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) ||
719 etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) {
720 pulse_eater &= ~BIT(16);
721 pulse_eater |= BIT(17);
722 }
723
724 if ((gpu->identity.revision > 0x5420) &&
725 (gpu->identity.features & chipFeatures_PIPE_3D))
726 {
727 /* Performance fix: disable internal DFS */
728 pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER);
729 pulse_eater |= BIT(18);
730 }
731
732 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
733 }
734
etnaviv_gpu_hw_init(struct etnaviv_gpu * gpu)735 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
736 {
737 WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED ||
738 gpu->state == ETNA_GPU_STATE_RESET));
739
740 if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) ||
741 etnaviv_is_model_rev(gpu, 0x320, 0x5220)) &&
742 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
743 u32 mc_memory_debug;
744
745 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
746
747 if (gpu->identity.revision == 0x5007)
748 mc_memory_debug |= 0x0c;
749 else
750 mc_memory_debug |= 0x08;
751
752 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
753 }
754
755 /* enable module-level clock gating */
756 etnaviv_gpu_enable_mlcg(gpu);
757
758 /*
759 * Update GPU AXI cache atttribute to "cacheable, no allocate".
760 * This is necessary to prevent the iMX6 SoC locking up.
761 */
762 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
763 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
764 VIVS_HI_AXI_CONFIG_ARCACHE(2));
765
766 /* GC2000 rev 5108 needs a special bus config */
767 if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) {
768 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
769 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
770 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
771 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
772 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
773 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
774 }
775
776 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
777 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
778 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
779 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
780 }
781
782 /* setup the pulse eater */
783 etnaviv_gpu_setup_pulse_eater(gpu);
784
785 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
786
787 gpu->state = ETNA_GPU_STATE_INITIALIZED;
788 }
789
etnaviv_gpu_init(struct etnaviv_gpu * gpu)790 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
791 {
792 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
793 dma_addr_t cmdbuf_paddr;
794 int ret, i;
795
796 ret = pm_runtime_get_sync(gpu->dev);
797 if (ret < 0) {
798 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
799 goto pm_put;
800 }
801
802 etnaviv_hw_identify(gpu);
803
804 if (gpu->identity.model == 0) {
805 dev_err(gpu->dev, "Unknown GPU model\n");
806 ret = -ENXIO;
807 goto fail;
808 }
809
810 if (gpu->identity.nn_core_count > 0)
811 dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, "
812 "for which the UAPI is still experimental\n");
813
814 /* Exclude VG cores with FE2.0 */
815 if (gpu->identity.features & chipFeatures_PIPE_VG &&
816 gpu->identity.features & chipFeatures_FE20) {
817 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
818 ret = -ENXIO;
819 goto fail;
820 }
821
822 /*
823 * On cores with security features supported, we claim control over the
824 * security states.
825 */
826 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
827 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
828 gpu->sec_mode = ETNA_SEC_KERNEL;
829
830 gpu->state = ETNA_GPU_STATE_IDENTIFIED;
831
832 ret = etnaviv_hw_reset(gpu);
833 if (ret) {
834 dev_err(gpu->dev, "GPU reset failed\n");
835 goto fail;
836 }
837
838 ret = etnaviv_iommu_global_init(gpu);
839 if (ret)
840 goto fail;
841
842 /*
843 * If the GPU is part of a system with DMA addressing limitations,
844 * request pages for our SHM backend buffers from the DMA32 zone to
845 * hopefully avoid performance killing SWIOTLB bounce buffering.
846 */
847 if (dma_addressing_limited(gpu->dev))
848 priv->shm_gfp_mask |= GFP_DMA32;
849
850 /* Create buffer: */
851 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer,
852 PAGE_SIZE);
853 if (ret) {
854 dev_err(gpu->dev, "could not create command buffer\n");
855 goto fail;
856 }
857
858 /*
859 * Set the GPU linear window to cover the cmdbuf region, as the GPU
860 * won't be able to start execution otherwise. The alignment to 128M is
861 * chosen arbitrarily but helps in debugging, as the MMU offset
862 * calculations are much more straight forward this way.
863 *
864 * On MC1.0 cores the linear window offset is ignored by the TS engine,
865 * leading to inconsistent memory views. Avoid using the offset on those
866 * cores if possible, otherwise disable the TS feature. MMUv2 doesn't
867 * expose this issue, as all TS accesses are MMU translated, so the
868 * linear window offset won't be used.
869 */
870 cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);
871
872 if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
873 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20) ||
874 (gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION)) {
875 if (cmdbuf_paddr >= SZ_2G)
876 priv->mmu_global->memory_base = SZ_2G;
877 else
878 priv->mmu_global->memory_base = cmdbuf_paddr;
879 } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) {
880 dev_info(gpu->dev,
881 "Need to move linear window on MC1.0, disabling TS\n");
882 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
883 priv->mmu_global->memory_base = SZ_2G;
884 }
885
886 /* Setup event management */
887 spin_lock_init(&gpu->event_spinlock);
888 init_completion(&gpu->event_free);
889 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
890 for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
891 complete(&gpu->event_free);
892
893 /* Now program the hardware */
894 mutex_lock(&gpu->lock);
895 etnaviv_gpu_hw_init(gpu);
896 mutex_unlock(&gpu->lock);
897
898 pm_runtime_mark_last_busy(gpu->dev);
899 pm_runtime_put_autosuspend(gpu->dev);
900
901 return 0;
902
903 fail:
904 pm_runtime_mark_last_busy(gpu->dev);
905 pm_put:
906 pm_runtime_put_autosuspend(gpu->dev);
907
908 return ret;
909 }
910
911 #ifdef CONFIG_DEBUG_FS
912 struct dma_debug {
913 u32 address[2];
914 u32 state[2];
915 };
916
verify_dma(struct etnaviv_gpu * gpu,struct dma_debug * debug)917 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
918 {
919 u32 i;
920
921 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
922 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
923
924 for (i = 0; i < 500; i++) {
925 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
926 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
927
928 if (debug->address[0] != debug->address[1])
929 break;
930
931 if (debug->state[0] != debug->state[1])
932 break;
933 }
934 }
935
etnaviv_gpu_debugfs(struct etnaviv_gpu * gpu,struct seq_file * m)936 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
937 {
938 struct dma_debug debug;
939 u32 dma_lo, dma_hi, axi, idle;
940 int ret;
941
942 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
943
944 ret = pm_runtime_get_sync(gpu->dev);
945 if (ret < 0)
946 goto pm_put;
947
948 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
949 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
950 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
951 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
952
953 verify_dma(gpu, &debug);
954
955 seq_puts(m, "\tidentity\n");
956 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
957 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
958 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
959 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
960 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
961
962 seq_puts(m, "\tfeatures\n");
963 seq_printf(m, "\t major_features: 0x%08x\n",
964 gpu->identity.features);
965 seq_printf(m, "\t minor_features0: 0x%08x\n",
966 gpu->identity.minor_features0);
967 seq_printf(m, "\t minor_features1: 0x%08x\n",
968 gpu->identity.minor_features1);
969 seq_printf(m, "\t minor_features2: 0x%08x\n",
970 gpu->identity.minor_features2);
971 seq_printf(m, "\t minor_features3: 0x%08x\n",
972 gpu->identity.minor_features3);
973 seq_printf(m, "\t minor_features4: 0x%08x\n",
974 gpu->identity.minor_features4);
975 seq_printf(m, "\t minor_features5: 0x%08x\n",
976 gpu->identity.minor_features5);
977 seq_printf(m, "\t minor_features6: 0x%08x\n",
978 gpu->identity.minor_features6);
979 seq_printf(m, "\t minor_features7: 0x%08x\n",
980 gpu->identity.minor_features7);
981 seq_printf(m, "\t minor_features8: 0x%08x\n",
982 gpu->identity.minor_features8);
983 seq_printf(m, "\t minor_features9: 0x%08x\n",
984 gpu->identity.minor_features9);
985 seq_printf(m, "\t minor_features10: 0x%08x\n",
986 gpu->identity.minor_features10);
987 seq_printf(m, "\t minor_features11: 0x%08x\n",
988 gpu->identity.minor_features11);
989
990 seq_puts(m, "\tspecs\n");
991 seq_printf(m, "\t stream_count: %d\n",
992 gpu->identity.stream_count);
993 seq_printf(m, "\t register_max: %d\n",
994 gpu->identity.register_max);
995 seq_printf(m, "\t thread_count: %d\n",
996 gpu->identity.thread_count);
997 seq_printf(m, "\t vertex_cache_size: %d\n",
998 gpu->identity.vertex_cache_size);
999 seq_printf(m, "\t shader_core_count: %d\n",
1000 gpu->identity.shader_core_count);
1001 seq_printf(m, "\t nn_core_count: %d\n",
1002 gpu->identity.nn_core_count);
1003 seq_printf(m, "\t pixel_pipes: %d\n",
1004 gpu->identity.pixel_pipes);
1005 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
1006 gpu->identity.vertex_output_buffer_size);
1007 seq_printf(m, "\t buffer_size: %d\n",
1008 gpu->identity.buffer_size);
1009 seq_printf(m, "\t instruction_count: %d\n",
1010 gpu->identity.instruction_count);
1011 seq_printf(m, "\t num_constants: %d\n",
1012 gpu->identity.num_constants);
1013 seq_printf(m, "\t varyings_count: %d\n",
1014 gpu->identity.varyings_count);
1015
1016 seq_printf(m, "\taxi: 0x%08x\n", axi);
1017 seq_printf(m, "\tidle: 0x%08x\n", idle);
1018 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
1019 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
1020 seq_puts(m, "\t FE is not idle\n");
1021 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
1022 seq_puts(m, "\t DE is not idle\n");
1023 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
1024 seq_puts(m, "\t PE is not idle\n");
1025 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
1026 seq_puts(m, "\t SH is not idle\n");
1027 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
1028 seq_puts(m, "\t PA is not idle\n");
1029 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
1030 seq_puts(m, "\t SE is not idle\n");
1031 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
1032 seq_puts(m, "\t RA is not idle\n");
1033 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
1034 seq_puts(m, "\t TX is not idle\n");
1035 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
1036 seq_puts(m, "\t VG is not idle\n");
1037 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
1038 seq_puts(m, "\t IM is not idle\n");
1039 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
1040 seq_puts(m, "\t FP is not idle\n");
1041 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
1042 seq_puts(m, "\t TS is not idle\n");
1043 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
1044 seq_puts(m, "\t BL is not idle\n");
1045 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
1046 seq_puts(m, "\t ASYNCFE is not idle\n");
1047 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
1048 seq_puts(m, "\t MC is not idle\n");
1049 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
1050 seq_puts(m, "\t PPA is not idle\n");
1051 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
1052 seq_puts(m, "\t WD is not idle\n");
1053 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
1054 seq_puts(m, "\t NN is not idle\n");
1055 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
1056 seq_puts(m, "\t TP is not idle\n");
1057 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
1058 seq_puts(m, "\t AXI low power mode\n");
1059
1060 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
1061 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
1062 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
1063 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
1064
1065 seq_puts(m, "\tMC\n");
1066 seq_printf(m, "\t read0: 0x%08x\n", read0);
1067 seq_printf(m, "\t read1: 0x%08x\n", read1);
1068 seq_printf(m, "\t write: 0x%08x\n", write);
1069 }
1070
1071 seq_puts(m, "\tDMA ");
1072
1073 if (debug.address[0] == debug.address[1] &&
1074 debug.state[0] == debug.state[1]) {
1075 seq_puts(m, "seems to be stuck\n");
1076 } else if (debug.address[0] == debug.address[1]) {
1077 seq_puts(m, "address is constant\n");
1078 } else {
1079 seq_puts(m, "is running\n");
1080 }
1081
1082 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
1083 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
1084 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
1085 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
1086 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
1087 dma_lo, dma_hi);
1088
1089 ret = 0;
1090
1091 pm_runtime_mark_last_busy(gpu->dev);
1092 pm_put:
1093 pm_runtime_put_autosuspend(gpu->dev);
1094
1095 return ret;
1096 }
1097 #endif
1098
1099 /* fence object management */
1100 struct etnaviv_fence {
1101 struct etnaviv_gpu *gpu;
1102 struct dma_fence base;
1103 };
1104
to_etnaviv_fence(struct dma_fence * fence)1105 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1106 {
1107 return container_of(fence, struct etnaviv_fence, base);
1108 }
1109
etnaviv_fence_get_driver_name(struct dma_fence * fence)1110 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1111 {
1112 return "etnaviv";
1113 }
1114
etnaviv_fence_get_timeline_name(struct dma_fence * fence)1115 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1116 {
1117 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1118
1119 return dev_name(f->gpu->dev);
1120 }
1121
etnaviv_fence_signaled(struct dma_fence * fence)1122 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1123 {
1124 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1125
1126 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1127 }
1128
etnaviv_fence_release(struct dma_fence * fence)1129 static void etnaviv_fence_release(struct dma_fence *fence)
1130 {
1131 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1132
1133 kfree_rcu(f, base.rcu);
1134 }
1135
1136 static const struct dma_fence_ops etnaviv_fence_ops = {
1137 .get_driver_name = etnaviv_fence_get_driver_name,
1138 .get_timeline_name = etnaviv_fence_get_timeline_name,
1139 .signaled = etnaviv_fence_signaled,
1140 .release = etnaviv_fence_release,
1141 };
1142
etnaviv_gpu_fence_alloc(struct etnaviv_gpu * gpu)1143 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1144 {
1145 struct etnaviv_fence *f;
1146
1147 /*
1148 * GPU lock must already be held, otherwise fence completion order might
1149 * not match the seqno order assigned here.
1150 */
1151 lockdep_assert_held(&gpu->lock);
1152
1153 f = kzalloc(sizeof(*f), GFP_KERNEL);
1154 if (!f)
1155 return NULL;
1156
1157 f->gpu = gpu;
1158
1159 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1160 gpu->fence_context, ++gpu->next_fence);
1161
1162 return &f->base;
1163 }
1164
1165 /* returns true if fence a comes after fence b */
fence_after(u32 a,u32 b)1166 static inline bool fence_after(u32 a, u32 b)
1167 {
1168 return (s32)(a - b) > 0;
1169 }
1170
1171 /*
1172 * event management:
1173 */
1174
event_alloc(struct etnaviv_gpu * gpu,unsigned nr_events,unsigned int * events)1175 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1176 unsigned int *events)
1177 {
1178 unsigned long timeout = msecs_to_jiffies(10 * 10000);
1179 unsigned i, acquired = 0, rpm_count = 0;
1180 int ret;
1181
1182 for (i = 0; i < nr_events; i++) {
1183 unsigned long remaining;
1184
1185 remaining = wait_for_completion_timeout(&gpu->event_free, timeout);
1186
1187 if (!remaining) {
1188 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1189 ret = -EBUSY;
1190 goto out;
1191 }
1192
1193 acquired++;
1194 timeout = remaining;
1195 }
1196
1197 spin_lock(&gpu->event_spinlock);
1198
1199 for (i = 0; i < nr_events; i++) {
1200 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1201
1202 events[i] = event;
1203 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1204 set_bit(event, gpu->event_bitmap);
1205 }
1206
1207 spin_unlock(&gpu->event_spinlock);
1208
1209 for (i = 0; i < nr_events; i++) {
1210 ret = pm_runtime_resume_and_get(gpu->dev);
1211 if (ret)
1212 goto out_rpm;
1213 rpm_count++;
1214 }
1215
1216 return 0;
1217
1218 out_rpm:
1219 for (i = 0; i < rpm_count; i++)
1220 pm_runtime_put_autosuspend(gpu->dev);
1221 out:
1222 for (i = 0; i < acquired; i++)
1223 complete(&gpu->event_free);
1224
1225 return ret;
1226 }
1227
event_free(struct etnaviv_gpu * gpu,unsigned int event)1228 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1229 {
1230 if (!test_bit(event, gpu->event_bitmap)) {
1231 dev_warn(gpu->dev, "event %u is already marked as free",
1232 event);
1233 } else {
1234 clear_bit(event, gpu->event_bitmap);
1235 complete(&gpu->event_free);
1236 }
1237
1238 pm_runtime_put_autosuspend(gpu->dev);
1239 }
1240
1241 /*
1242 * Cmdstream submission/retirement:
1243 */
etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu * gpu,u32 id,struct drm_etnaviv_timespec * timeout)1244 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1245 u32 id, struct drm_etnaviv_timespec *timeout)
1246 {
1247 struct dma_fence *fence;
1248 int ret;
1249
1250 /*
1251 * Look up the fence and take a reference. We might still find a fence
1252 * whose refcount has already dropped to zero. dma_fence_get_rcu
1253 * pretends we didn't find a fence in that case.
1254 */
1255 rcu_read_lock();
1256 fence = xa_load(&gpu->user_fences, id);
1257 if (fence)
1258 fence = dma_fence_get_rcu(fence);
1259 rcu_read_unlock();
1260
1261 if (!fence)
1262 return 0;
1263
1264 if (!timeout) {
1265 /* No timeout was requested: just test for completion */
1266 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1267 } else {
1268 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1269
1270 ret = dma_fence_wait_timeout(fence, true, remaining);
1271 if (ret == 0)
1272 ret = -ETIMEDOUT;
1273 else if (ret != -ERESTARTSYS)
1274 ret = 0;
1275
1276 }
1277
1278 dma_fence_put(fence);
1279 return ret;
1280 }
1281
1282 /*
1283 * Wait for an object to become inactive. This, on it's own, is not race
1284 * free: the object is moved by the scheduler off the active list, and
1285 * then the iova is put. Moreover, the object could be re-submitted just
1286 * after we notice that it's become inactive.
1287 *
1288 * Although the retirement happens under the gpu lock, we don't want to hold
1289 * that lock in this function while waiting.
1290 */
etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu * gpu,struct etnaviv_gem_object * etnaviv_obj,struct drm_etnaviv_timespec * timeout)1291 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1292 struct etnaviv_gem_object *etnaviv_obj,
1293 struct drm_etnaviv_timespec *timeout)
1294 {
1295 unsigned long remaining;
1296 long ret;
1297
1298 if (!timeout)
1299 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1300
1301 remaining = etnaviv_timeout_to_jiffies(timeout);
1302
1303 ret = wait_event_interruptible_timeout(gpu->fence_event,
1304 !is_active(etnaviv_obj),
1305 remaining);
1306 if (ret > 0)
1307 return 0;
1308 else if (ret == -ERESTARTSYS)
1309 return -ERESTARTSYS;
1310 else
1311 return -ETIMEDOUT;
1312 }
1313
sync_point_perfmon_sample(struct etnaviv_gpu * gpu,struct etnaviv_event * event,unsigned int flags)1314 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1315 struct etnaviv_event *event, unsigned int flags)
1316 {
1317 const struct etnaviv_gem_submit *submit = event->submit;
1318 unsigned int i;
1319
1320 for (i = 0; i < submit->nr_pmrs; i++) {
1321 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1322
1323 if (pmr->flags == flags)
1324 etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1325 }
1326 }
1327
sync_point_perfmon_sample_pre(struct etnaviv_gpu * gpu,struct etnaviv_event * event)1328 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1329 struct etnaviv_event *event)
1330 {
1331 u32 val;
1332
1333 /* disable clock gating */
1334 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1335 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1336 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
1337
1338 /* enable debug register */
1339 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1340 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1341 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1342
1343 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1344 }
1345
sync_point_perfmon_sample_post(struct etnaviv_gpu * gpu,struct etnaviv_event * event)1346 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1347 struct etnaviv_event *event)
1348 {
1349 const struct etnaviv_gem_submit *submit = event->submit;
1350 unsigned int i;
1351 u32 val;
1352
1353 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1354
1355 for (i = 0; i < submit->nr_pmrs; i++) {
1356 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1357
1358 *pmr->bo_vma = pmr->sequence;
1359 }
1360
1361 /* disable debug register */
1362 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1363 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1364 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1365
1366 /* enable clock gating */
1367 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1368 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1369 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
1370 }
1371
1372
1373 /* add bo's to gpu's ring, and kick gpu: */
etnaviv_gpu_submit(struct etnaviv_gem_submit * submit)1374 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1375 {
1376 struct etnaviv_gpu *gpu = submit->gpu;
1377 struct dma_fence *gpu_fence;
1378 unsigned int i, nr_events = 1, event[3];
1379 int ret;
1380
1381 /*
1382 * if there are performance monitor requests we need to have
1383 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1384 * requests.
1385 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1386 * and update the sequence number for userspace.
1387 */
1388 if (submit->nr_pmrs)
1389 nr_events = 3;
1390
1391 ret = event_alloc(gpu, nr_events, event);
1392 if (ret) {
1393 DRM_ERROR("no free events\n");
1394 pm_runtime_put_noidle(gpu->dev);
1395 return NULL;
1396 }
1397
1398 mutex_lock(&gpu->lock);
1399
1400 gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1401 if (!gpu_fence) {
1402 for (i = 0; i < nr_events; i++)
1403 event_free(gpu, event[i]);
1404
1405 goto out_unlock;
1406 }
1407
1408 if (gpu->state == ETNA_GPU_STATE_INITIALIZED)
1409 etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context);
1410
1411 if (submit->prev_mmu_context)
1412 etnaviv_iommu_context_put(submit->prev_mmu_context);
1413 submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context);
1414
1415 if (submit->nr_pmrs) {
1416 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1417 kref_get(&submit->refcount);
1418 gpu->event[event[1]].submit = submit;
1419 etnaviv_sync_point_queue(gpu, event[1]);
1420 }
1421
1422 gpu->event[event[0]].fence = gpu_fence;
1423 submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1424 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1425 event[0], &submit->cmdbuf);
1426
1427 if (submit->nr_pmrs) {
1428 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1429 kref_get(&submit->refcount);
1430 gpu->event[event[2]].submit = submit;
1431 etnaviv_sync_point_queue(gpu, event[2]);
1432 }
1433
1434 out_unlock:
1435 mutex_unlock(&gpu->lock);
1436
1437 return gpu_fence;
1438 }
1439
sync_point_worker(struct work_struct * work)1440 static void sync_point_worker(struct work_struct *work)
1441 {
1442 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1443 sync_point_work);
1444 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1445 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1446
1447 event->sync_point(gpu, event);
1448 etnaviv_submit_put(event->submit);
1449 event_free(gpu, gpu->sync_point_event);
1450
1451 /* restart FE last to avoid GPU and IRQ racing against this worker */
1452 etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1453 }
1454
etnaviv_gpu_recover_hang(struct etnaviv_gem_submit * submit)1455 void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit)
1456 {
1457 struct etnaviv_gpu *gpu = submit->gpu;
1458 char *comm = NULL, *cmd = NULL;
1459 struct task_struct *task;
1460 unsigned int i;
1461
1462 dev_err(gpu->dev, "recover hung GPU!\n");
1463
1464 task = get_pid_task(submit->pid, PIDTYPE_PID);
1465 if (task) {
1466 comm = kstrdup(task->comm, GFP_KERNEL);
1467 cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
1468 put_task_struct(task);
1469 }
1470
1471 if (comm && cmd)
1472 dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd);
1473
1474 kfree(cmd);
1475 kfree(comm);
1476
1477 if (pm_runtime_get_sync(gpu->dev) < 0)
1478 goto pm_put;
1479
1480 mutex_lock(&gpu->lock);
1481
1482 etnaviv_hw_reset(gpu);
1483
1484 /* complete all events, the GPU won't do it after the reset */
1485 spin_lock(&gpu->event_spinlock);
1486 for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS)
1487 event_free(gpu, i);
1488 spin_unlock(&gpu->event_spinlock);
1489
1490 etnaviv_gpu_hw_init(gpu);
1491
1492 mutex_unlock(&gpu->lock);
1493 pm_runtime_mark_last_busy(gpu->dev);
1494 pm_put:
1495 pm_runtime_put_autosuspend(gpu->dev);
1496 }
1497
dump_mmu_fault(struct etnaviv_gpu * gpu)1498 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1499 {
1500 static const char *fault_reasons[] = {
1501 "slave not present",
1502 "page not present",
1503 "write violation",
1504 "out of bounds",
1505 "read security violation",
1506 "write security violation",
1507 };
1508
1509 u32 status_reg, status;
1510 int i;
1511
1512 if (gpu->sec_mode == ETNA_SEC_NONE)
1513 status_reg = VIVS_MMUv2_STATUS;
1514 else
1515 status_reg = VIVS_MMUv2_SEC_STATUS;
1516
1517 status = gpu_read(gpu, status_reg);
1518 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1519
1520 for (i = 0; i < 4; i++) {
1521 const char *reason = "unknown";
1522 u32 address_reg;
1523 u32 mmu_status;
1524
1525 mmu_status = (status >> (i * 4)) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK;
1526 if (!mmu_status)
1527 continue;
1528
1529 if ((mmu_status - 1) < ARRAY_SIZE(fault_reasons))
1530 reason = fault_reasons[mmu_status - 1];
1531
1532 if (gpu->sec_mode == ETNA_SEC_NONE)
1533 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1534 else
1535 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1536
1537 dev_err_ratelimited(gpu->dev,
1538 "MMU %d fault (%s) addr 0x%08x\n",
1539 i, reason, gpu_read(gpu, address_reg));
1540 }
1541 }
1542
irq_handler(int irq,void * data)1543 static irqreturn_t irq_handler(int irq, void *data)
1544 {
1545 struct etnaviv_gpu *gpu = data;
1546 irqreturn_t ret = IRQ_NONE;
1547
1548 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1549
1550 if (intr != 0) {
1551 ktime_t now = ktime_get();
1552 int event;
1553
1554 pm_runtime_mark_last_busy(gpu->dev);
1555
1556 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1557
1558 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1559 dev_err(gpu->dev, "AXI bus error\n");
1560 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1561 }
1562
1563 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1564 dump_mmu_fault(gpu);
1565 gpu->state = ETNA_GPU_STATE_FAULT;
1566 drm_sched_fault(&gpu->sched);
1567 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1568 }
1569
1570 while ((event = ffs(intr)) != 0) {
1571 struct dma_fence *fence;
1572
1573 event -= 1;
1574
1575 intr &= ~(1 << event);
1576
1577 dev_dbg(gpu->dev, "event %u\n", event);
1578
1579 if (gpu->event[event].sync_point) {
1580 gpu->sync_point_event = event;
1581 queue_work(gpu->wq, &gpu->sync_point_work);
1582 }
1583
1584 fence = gpu->event[event].fence;
1585 if (!fence)
1586 continue;
1587
1588 gpu->event[event].fence = NULL;
1589
1590 /*
1591 * Events can be processed out of order. Eg,
1592 * - allocate and queue event 0
1593 * - allocate event 1
1594 * - event 0 completes, we process it
1595 * - allocate and queue event 0
1596 * - event 1 and event 0 complete
1597 * we can end up processing event 0 first, then 1.
1598 */
1599 if (fence_after(fence->seqno, gpu->completed_fence))
1600 gpu->completed_fence = fence->seqno;
1601 dma_fence_signal_timestamp(fence, now);
1602
1603 event_free(gpu, event);
1604 }
1605
1606 ret = IRQ_HANDLED;
1607 }
1608
1609 return ret;
1610 }
1611
etnaviv_gpu_clk_enable(struct etnaviv_gpu * gpu)1612 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1613 {
1614 int ret;
1615
1616 ret = clk_prepare_enable(gpu->clk_reg);
1617 if (ret)
1618 return ret;
1619
1620 ret = clk_prepare_enable(gpu->clk_bus);
1621 if (ret)
1622 goto disable_clk_reg;
1623
1624 ret = clk_prepare_enable(gpu->clk_core);
1625 if (ret)
1626 goto disable_clk_bus;
1627
1628 ret = clk_prepare_enable(gpu->clk_shader);
1629 if (ret)
1630 goto disable_clk_core;
1631
1632 return 0;
1633
1634 disable_clk_core:
1635 clk_disable_unprepare(gpu->clk_core);
1636 disable_clk_bus:
1637 clk_disable_unprepare(gpu->clk_bus);
1638 disable_clk_reg:
1639 clk_disable_unprepare(gpu->clk_reg);
1640
1641 return ret;
1642 }
1643
etnaviv_gpu_clk_disable(struct etnaviv_gpu * gpu)1644 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1645 {
1646 clk_disable_unprepare(gpu->clk_shader);
1647 clk_disable_unprepare(gpu->clk_core);
1648 clk_disable_unprepare(gpu->clk_bus);
1649 clk_disable_unprepare(gpu->clk_reg);
1650
1651 return 0;
1652 }
1653
etnaviv_gpu_wait_idle(struct etnaviv_gpu * gpu,unsigned int timeout_ms)1654 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1655 {
1656 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1657
1658 do {
1659 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1660
1661 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1662 return 0;
1663
1664 if (time_is_before_jiffies(timeout)) {
1665 dev_warn(gpu->dev,
1666 "timed out waiting for idle: idle=0x%x\n",
1667 idle);
1668 return -ETIMEDOUT;
1669 }
1670
1671 udelay(5);
1672 } while (1);
1673 }
1674
etnaviv_gpu_hw_suspend(struct etnaviv_gpu * gpu)1675 static void etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1676 {
1677 if (gpu->state == ETNA_GPU_STATE_RUNNING) {
1678 /* Replace the last WAIT with END */
1679 mutex_lock(&gpu->lock);
1680 etnaviv_buffer_end(gpu);
1681 mutex_unlock(&gpu->lock);
1682
1683 /*
1684 * We know that only the FE is busy here, this should
1685 * happen quickly (as the WAIT is only 200 cycles). If
1686 * we fail, just warn and continue.
1687 */
1688 etnaviv_gpu_wait_idle(gpu, 100);
1689
1690 gpu->state = ETNA_GPU_STATE_INITIALIZED;
1691 }
1692
1693 gpu->exec_state = -1;
1694 }
1695
etnaviv_gpu_hw_resume(struct etnaviv_gpu * gpu)1696 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1697 {
1698 int ret;
1699
1700 ret = mutex_lock_killable(&gpu->lock);
1701 if (ret)
1702 return ret;
1703
1704 etnaviv_gpu_update_clock(gpu);
1705 etnaviv_gpu_hw_init(gpu);
1706
1707 mutex_unlock(&gpu->lock);
1708
1709 return 0;
1710 }
1711
1712 static int
etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device * cdev,unsigned long * state)1713 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1714 unsigned long *state)
1715 {
1716 *state = 6;
1717
1718 return 0;
1719 }
1720
1721 static int
etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device * cdev,unsigned long * state)1722 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1723 unsigned long *state)
1724 {
1725 struct etnaviv_gpu *gpu = cdev->devdata;
1726
1727 *state = gpu->freq_scale;
1728
1729 return 0;
1730 }
1731
1732 static int
etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device * cdev,unsigned long state)1733 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1734 unsigned long state)
1735 {
1736 struct etnaviv_gpu *gpu = cdev->devdata;
1737
1738 mutex_lock(&gpu->lock);
1739 gpu->freq_scale = state;
1740 if (!pm_runtime_suspended(gpu->dev))
1741 etnaviv_gpu_update_clock(gpu);
1742 mutex_unlock(&gpu->lock);
1743
1744 return 0;
1745 }
1746
1747 static const struct thermal_cooling_device_ops cooling_ops = {
1748 .get_max_state = etnaviv_gpu_cooling_get_max_state,
1749 .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1750 .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1751 };
1752
etnaviv_gpu_bind(struct device * dev,struct device * master,void * data)1753 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1754 void *data)
1755 {
1756 struct drm_device *drm = data;
1757 struct etnaviv_drm_private *priv = drm->dev_private;
1758 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1759 int ret;
1760
1761 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1762 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1763 (char *)dev_name(dev), gpu, &cooling_ops);
1764 if (IS_ERR(gpu->cooling))
1765 return PTR_ERR(gpu->cooling);
1766 }
1767
1768 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1769 if (!gpu->wq) {
1770 ret = -ENOMEM;
1771 goto out_thermal;
1772 }
1773
1774 ret = etnaviv_sched_init(gpu);
1775 if (ret)
1776 goto out_workqueue;
1777
1778 if (!IS_ENABLED(CONFIG_PM)) {
1779 ret = etnaviv_gpu_clk_enable(gpu);
1780 if (ret < 0)
1781 goto out_sched;
1782 }
1783
1784 gpu->drm = drm;
1785 gpu->fence_context = dma_fence_context_alloc(1);
1786 xa_init_flags(&gpu->user_fences, XA_FLAGS_ALLOC);
1787 spin_lock_init(&gpu->fence_spinlock);
1788
1789 INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1790 init_waitqueue_head(&gpu->fence_event);
1791
1792 priv->gpu[priv->num_gpus++] = gpu;
1793
1794 return 0;
1795
1796 out_sched:
1797 etnaviv_sched_fini(gpu);
1798
1799 out_workqueue:
1800 destroy_workqueue(gpu->wq);
1801
1802 out_thermal:
1803 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1804 thermal_cooling_device_unregister(gpu->cooling);
1805
1806 return ret;
1807 }
1808
etnaviv_gpu_unbind(struct device * dev,struct device * master,void * data)1809 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1810 void *data)
1811 {
1812 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1813
1814 DBG("%s", dev_name(gpu->dev));
1815
1816 destroy_workqueue(gpu->wq);
1817
1818 etnaviv_sched_fini(gpu);
1819
1820 if (IS_ENABLED(CONFIG_PM)) {
1821 pm_runtime_get_sync(gpu->dev);
1822 pm_runtime_put_sync_suspend(gpu->dev);
1823 } else {
1824 etnaviv_gpu_hw_suspend(gpu);
1825 etnaviv_gpu_clk_disable(gpu);
1826 }
1827
1828 if (gpu->mmu_context)
1829 etnaviv_iommu_context_put(gpu->mmu_context);
1830
1831 etnaviv_cmdbuf_free(&gpu->buffer);
1832 etnaviv_iommu_global_fini(gpu);
1833
1834 gpu->drm = NULL;
1835 xa_destroy(&gpu->user_fences);
1836
1837 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1838 thermal_cooling_device_unregister(gpu->cooling);
1839 gpu->cooling = NULL;
1840 }
1841
1842 static const struct component_ops gpu_ops = {
1843 .bind = etnaviv_gpu_bind,
1844 .unbind = etnaviv_gpu_unbind,
1845 };
1846
1847 static const struct of_device_id etnaviv_gpu_match[] = {
1848 {
1849 .compatible = "vivante,gc"
1850 },
1851 { /* sentinel */ }
1852 };
1853 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1854
etnaviv_gpu_platform_probe(struct platform_device * pdev)1855 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1856 {
1857 struct device *dev = &pdev->dev;
1858 struct etnaviv_gpu *gpu;
1859 int err;
1860
1861 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1862 if (!gpu)
1863 return -ENOMEM;
1864
1865 gpu->dev = &pdev->dev;
1866 mutex_init(&gpu->lock);
1867 mutex_init(&gpu->sched_lock);
1868
1869 /* Map registers: */
1870 gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1871 if (IS_ERR(gpu->mmio))
1872 return PTR_ERR(gpu->mmio);
1873
1874 /* Get Interrupt: */
1875 gpu->irq = platform_get_irq(pdev, 0);
1876 if (gpu->irq < 0)
1877 return gpu->irq;
1878
1879 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1880 dev_name(gpu->dev), gpu);
1881 if (err) {
1882 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1883 return err;
1884 }
1885
1886 /* Get Clocks: */
1887 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg");
1888 DBG("clk_reg: %p", gpu->clk_reg);
1889 if (IS_ERR(gpu->clk_reg))
1890 return PTR_ERR(gpu->clk_reg);
1891
1892 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus");
1893 DBG("clk_bus: %p", gpu->clk_bus);
1894 if (IS_ERR(gpu->clk_bus))
1895 return PTR_ERR(gpu->clk_bus);
1896
1897 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1898 DBG("clk_core: %p", gpu->clk_core);
1899 if (IS_ERR(gpu->clk_core))
1900 return PTR_ERR(gpu->clk_core);
1901 gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1902
1903 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader");
1904 DBG("clk_shader: %p", gpu->clk_shader);
1905 if (IS_ERR(gpu->clk_shader))
1906 return PTR_ERR(gpu->clk_shader);
1907 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1908
1909 /* TODO: figure out max mapped size */
1910 dev_set_drvdata(dev, gpu);
1911
1912 /*
1913 * We treat the device as initially suspended. The runtime PM
1914 * autosuspend delay is rather arbitary: no measurements have
1915 * yet been performed to determine an appropriate value.
1916 */
1917 pm_runtime_use_autosuspend(gpu->dev);
1918 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1919 pm_runtime_enable(gpu->dev);
1920
1921 err = component_add(&pdev->dev, &gpu_ops);
1922 if (err < 0) {
1923 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1924 return err;
1925 }
1926
1927 return 0;
1928 }
1929
etnaviv_gpu_platform_remove(struct platform_device * pdev)1930 static void etnaviv_gpu_platform_remove(struct platform_device *pdev)
1931 {
1932 component_del(&pdev->dev, &gpu_ops);
1933 pm_runtime_disable(&pdev->dev);
1934 }
1935
etnaviv_gpu_rpm_suspend(struct device * dev)1936 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1937 {
1938 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1939 u32 idle, mask;
1940
1941 /* If there are any jobs in the HW queue, we're not idle */
1942 if (atomic_read(&gpu->sched.credit_count))
1943 return -EBUSY;
1944
1945 /* Check whether the hardware (except FE and MC) is idle */
1946 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1947 VIVS_HI_IDLE_STATE_MC);
1948 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1949 if (idle != mask) {
1950 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",
1951 idle);
1952 return -EBUSY;
1953 }
1954
1955 etnaviv_gpu_hw_suspend(gpu);
1956
1957 gpu->state = ETNA_GPU_STATE_IDENTIFIED;
1958
1959 return etnaviv_gpu_clk_disable(gpu);
1960 }
1961
etnaviv_gpu_rpm_resume(struct device * dev)1962 static int etnaviv_gpu_rpm_resume(struct device *dev)
1963 {
1964 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1965 int ret;
1966
1967 ret = etnaviv_gpu_clk_enable(gpu);
1968 if (ret)
1969 return ret;
1970
1971 /* Re-initialise the basic hardware state */
1972 if (gpu->state == ETNA_GPU_STATE_IDENTIFIED) {
1973 ret = etnaviv_gpu_hw_resume(gpu);
1974 if (ret) {
1975 etnaviv_gpu_clk_disable(gpu);
1976 return ret;
1977 }
1978 }
1979
1980 return 0;
1981 }
1982
1983 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1984 RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, NULL)
1985 };
1986
1987 struct platform_driver etnaviv_gpu_driver = {
1988 .driver = {
1989 .name = "etnaviv-gpu",
1990 .pm = pm_ptr(&etnaviv_gpu_pm_ops),
1991 .of_match_table = etnaviv_gpu_match,
1992 },
1993 .probe = etnaviv_gpu_platform_probe,
1994 .remove_new = etnaviv_gpu_platform_remove,
1995 .id_table = gpu_ids,
1996 };
1997