1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10
11 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
12
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
15 #include "clk-rcg.h"
16 #include "clk-regmap.h"
17 #include "clk-regmap-divider.h"
18 #include "common.h"
19 #include "gdsc.h"
20 #include "reset.h"
21
22 enum {
23 DT_BI_TCXO,
24 DT_GPLL0_OUT_MAIN,
25 DT_GPLL0_OUT_MAIN_DIV,
26 };
27
28 enum {
29 P_BI_TCXO,
30 P_GPLL0_OUT_MAIN,
31 P_GPLL0_OUT_MAIN_DIV,
32 P_GPU_CC_PLL0_OUT_MAIN,
33 P_GPU_CC_PLL1_OUT_MAIN,
34 };
35
36 static const struct pll_vco lucid_ole_vco[] = {
37 { 249600000, 2000000000, 0 },
38 };
39
40 static const struct alpha_pll_config gpu_cc_pll0_config = {
41 .l = 0x1e,
42 .alpha = 0xbaaa,
43 .config_ctl_val = 0x20485699,
44 .config_ctl_hi_val = 0x00182261,
45 .config_ctl_hi1_val = 0x82aa299c,
46 .test_ctl_val = 0x00000000,
47 .test_ctl_hi_val = 0x00000003,
48 .test_ctl_hi1_val = 0x00009000,
49 .test_ctl_hi2_val = 0x00000034,
50 .user_ctl_val = 0x00000000,
51 .user_ctl_hi_val = 0x00000005,
52 };
53
54 static struct clk_alpha_pll gpu_cc_pll0 = {
55 .offset = 0x0,
56 .vco_table = lucid_ole_vco,
57 .num_vco = ARRAY_SIZE(lucid_ole_vco),
58 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
59 .clkr = {
60 .hw.init = &(const struct clk_init_data) {
61 .name = "gpu_cc_pll0",
62 .parent_data = &(const struct clk_parent_data) {
63 .index = DT_BI_TCXO,
64 },
65 .num_parents = 1,
66 .ops = &clk_alpha_pll_lucid_evo_ops,
67 },
68 },
69 };
70
71 static const struct alpha_pll_config gpu_cc_pll1_config = {
72 .l = 0x16,
73 .alpha = 0xeaaa,
74 .config_ctl_val = 0x20485699,
75 .config_ctl_hi_val = 0x00182261,
76 .config_ctl_hi1_val = 0x82aa299c,
77 .test_ctl_val = 0x00000000,
78 .test_ctl_hi_val = 0x00000003,
79 .test_ctl_hi1_val = 0x00009000,
80 .test_ctl_hi2_val = 0x00000034,
81 .user_ctl_val = 0x00000000,
82 .user_ctl_hi_val = 0x00000005,
83 };
84
85 static struct clk_alpha_pll gpu_cc_pll1 = {
86 .offset = 0x1000,
87 .vco_table = lucid_ole_vco,
88 .num_vco = ARRAY_SIZE(lucid_ole_vco),
89 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
90 .clkr = {
91 .hw.init = &(const struct clk_init_data) {
92 .name = "gpu_cc_pll1",
93 .parent_data = &(const struct clk_parent_data) {
94 .index = DT_BI_TCXO,
95 },
96 .num_parents = 1,
97 .ops = &clk_alpha_pll_lucid_evo_ops,
98 },
99 },
100 };
101
102 static const struct parent_map gpu_cc_parent_map_0[] = {
103 { P_BI_TCXO, 0 },
104 { P_GPLL0_OUT_MAIN, 5 },
105 { P_GPLL0_OUT_MAIN_DIV, 6 },
106 };
107
108 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
109 { .index = DT_BI_TCXO },
110 { .index = DT_GPLL0_OUT_MAIN },
111 { .index = DT_GPLL0_OUT_MAIN_DIV },
112 };
113
114 static const struct parent_map gpu_cc_parent_map_1[] = {
115 { P_BI_TCXO, 0 },
116 { P_GPU_CC_PLL0_OUT_MAIN, 1 },
117 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
118 { P_GPLL0_OUT_MAIN, 5 },
119 { P_GPLL0_OUT_MAIN_DIV, 6 },
120 };
121
122 static const struct clk_parent_data gpu_cc_parent_data_1[] = {
123 { .index = DT_BI_TCXO },
124 { .hw = &gpu_cc_pll0.clkr.hw },
125 { .hw = &gpu_cc_pll1.clkr.hw },
126 { .index = DT_GPLL0_OUT_MAIN },
127 { .index = DT_GPLL0_OUT_MAIN_DIV },
128 };
129
130 static const struct parent_map gpu_cc_parent_map_2[] = {
131 { P_BI_TCXO, 0 },
132 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
133 { P_GPLL0_OUT_MAIN, 5 },
134 { P_GPLL0_OUT_MAIN_DIV, 6 },
135 };
136
137 static const struct clk_parent_data gpu_cc_parent_data_2[] = {
138 { .index = DT_BI_TCXO },
139 { .hw = &gpu_cc_pll1.clkr.hw },
140 { .index = DT_GPLL0_OUT_MAIN },
141 { .index = DT_GPLL0_OUT_MAIN_DIV },
142 };
143
144 static const struct parent_map gpu_cc_parent_map_3[] = {
145 { P_BI_TCXO, 0 },
146 };
147
148 static const struct clk_parent_data gpu_cc_parent_data_3[] = {
149 { .index = DT_BI_TCXO },
150 };
151
152 static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
153 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
154 { }
155 };
156
157 static struct clk_rcg2 gpu_cc_ff_clk_src = {
158 .cmd_rcgr = 0x9474,
159 .mnd_width = 0,
160 .hid_width = 5,
161 .parent_map = gpu_cc_parent_map_0,
162 .freq_tbl = ftbl_gpu_cc_ff_clk_src,
163 .clkr.hw.init = &(const struct clk_init_data) {
164 .name = "gpu_cc_ff_clk_src",
165 .parent_data = gpu_cc_parent_data_0,
166 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
167 .flags = CLK_SET_RATE_PARENT,
168 .ops = &clk_rcg2_shared_ops,
169 },
170 };
171
172 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
173 F(19200000, P_BI_TCXO, 1, 0, 0),
174 F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
175 F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
176 { }
177 };
178
179 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
180 .cmd_rcgr = 0x9318,
181 .mnd_width = 0,
182 .hid_width = 5,
183 .parent_map = gpu_cc_parent_map_1,
184 .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
185 .clkr.hw.init = &(const struct clk_init_data) {
186 .name = "gpu_cc_gmu_clk_src",
187 .parent_data = gpu_cc_parent_data_1,
188 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
189 .flags = CLK_SET_RATE_PARENT,
190 .ops = &clk_rcg2_shared_ops,
191 },
192 };
193
194 static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
195 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
196 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
197 F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
198 { }
199 };
200
201 static struct clk_rcg2 gpu_cc_hub_clk_src = {
202 .cmd_rcgr = 0x93ec,
203 .mnd_width = 0,
204 .hid_width = 5,
205 .parent_map = gpu_cc_parent_map_2,
206 .freq_tbl = ftbl_gpu_cc_hub_clk_src,
207 .clkr.hw.init = &(const struct clk_init_data) {
208 .name = "gpu_cc_hub_clk_src",
209 .parent_data = gpu_cc_parent_data_2,
210 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
211 .flags = CLK_SET_RATE_PARENT,
212 .ops = &clk_rcg2_shared_ops,
213 },
214 };
215
216 static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
217 F(19200000, P_BI_TCXO, 1, 0, 0),
218 { }
219 };
220
221 static struct clk_rcg2 gpu_cc_xo_clk_src = {
222 .cmd_rcgr = 0x9010,
223 .mnd_width = 0,
224 .hid_width = 5,
225 .parent_map = gpu_cc_parent_map_3,
226 .freq_tbl = ftbl_gpu_cc_xo_clk_src,
227 .clkr.hw.init = &(const struct clk_init_data) {
228 .name = "gpu_cc_xo_clk_src",
229 .parent_data = gpu_cc_parent_data_3,
230 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
231 .flags = CLK_SET_RATE_PARENT,
232 .ops = &clk_rcg2_shared_ops,
233 },
234 };
235
236 static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
237 .reg = 0x9054,
238 .shift = 0,
239 .width = 4,
240 .clkr.hw.init = &(const struct clk_init_data) {
241 .name = "gpu_cc_demet_div_clk_src",
242 .parent_hws = (const struct clk_hw*[]) {
243 &gpu_cc_xo_clk_src.clkr.hw,
244 },
245 .num_parents = 1,
246 .flags = CLK_SET_RATE_PARENT,
247 .ops = &clk_regmap_div_ro_ops,
248 },
249 };
250
251 static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
252 .reg = 0x9050,
253 .shift = 0,
254 .width = 4,
255 .clkr.hw.init = &(const struct clk_init_data) {
256 .name = "gpu_cc_xo_div_clk_src",
257 .parent_hws = (const struct clk_hw*[]) {
258 &gpu_cc_xo_clk_src.clkr.hw,
259 },
260 .num_parents = 1,
261 .flags = CLK_SET_RATE_PARENT,
262 .ops = &clk_regmap_div_ro_ops,
263 },
264 };
265
266 static struct clk_branch gpu_cc_ahb_clk = {
267 .halt_reg = 0x911c,
268 .halt_check = BRANCH_HALT_DELAY,
269 .clkr = {
270 .enable_reg = 0x911c,
271 .enable_mask = BIT(0),
272 .hw.init = &(const struct clk_init_data) {
273 .name = "gpu_cc_ahb_clk",
274 .parent_hws = (const struct clk_hw*[]) {
275 &gpu_cc_hub_clk_src.clkr.hw,
276 },
277 .num_parents = 1,
278 .flags = CLK_SET_RATE_PARENT,
279 .ops = &clk_branch2_ops,
280 },
281 },
282 };
283
284 static struct clk_branch gpu_cc_crc_ahb_clk = {
285 .halt_reg = 0x9120,
286 .halt_check = BRANCH_HALT_VOTED,
287 .clkr = {
288 .enable_reg = 0x9120,
289 .enable_mask = BIT(0),
290 .hw.init = &(const struct clk_init_data) {
291 .name = "gpu_cc_crc_ahb_clk",
292 .parent_hws = (const struct clk_hw*[]) {
293 &gpu_cc_hub_clk_src.clkr.hw,
294 },
295 .num_parents = 1,
296 .flags = CLK_SET_RATE_PARENT,
297 .ops = &clk_branch2_ops,
298 },
299 },
300 };
301
302 static struct clk_branch gpu_cc_cx_ff_clk = {
303 .halt_reg = 0x914c,
304 .halt_check = BRANCH_HALT,
305 .clkr = {
306 .enable_reg = 0x914c,
307 .enable_mask = BIT(0),
308 .hw.init = &(const struct clk_init_data) {
309 .name = "gpu_cc_cx_ff_clk",
310 .parent_hws = (const struct clk_hw*[]) {
311 &gpu_cc_ff_clk_src.clkr.hw,
312 },
313 .num_parents = 1,
314 .flags = CLK_SET_RATE_PARENT,
315 .ops = &clk_branch2_ops,
316 },
317 },
318 };
319
320 static struct clk_branch gpu_cc_cx_gmu_clk = {
321 .halt_reg = 0x913c,
322 .halt_check = BRANCH_HALT_VOTED,
323 .clkr = {
324 .enable_reg = 0x913c,
325 .enable_mask = BIT(0),
326 .hw.init = &(const struct clk_init_data) {
327 .name = "gpu_cc_cx_gmu_clk",
328 .parent_hws = (const struct clk_hw*[]) {
329 &gpu_cc_gmu_clk_src.clkr.hw,
330 },
331 .num_parents = 1,
332 .flags = CLK_SET_RATE_PARENT,
333 .ops = &clk_branch2_aon_ops,
334 },
335 },
336 };
337
338 static struct clk_branch gpu_cc_cxo_clk = {
339 .halt_reg = 0x9144,
340 .halt_check = BRANCH_HALT,
341 .clkr = {
342 .enable_reg = 0x9144,
343 .enable_mask = BIT(0),
344 .hw.init = &(const struct clk_init_data) {
345 .name = "gpu_cc_cxo_clk",
346 .parent_hws = (const struct clk_hw*[]) {
347 &gpu_cc_xo_clk_src.clkr.hw,
348 },
349 .num_parents = 1,
350 .flags = CLK_SET_RATE_PARENT,
351 .ops = &clk_branch2_ops,
352 },
353 },
354 };
355
356 static struct clk_branch gpu_cc_freq_measure_clk = {
357 .halt_reg = 0x9008,
358 .halt_check = BRANCH_HALT,
359 .clkr = {
360 .enable_reg = 0x9008,
361 .enable_mask = BIT(0),
362 .hw.init = &(const struct clk_init_data) {
363 .name = "gpu_cc_freq_measure_clk",
364 .parent_hws = (const struct clk_hw*[]) {
365 &gpu_cc_xo_div_clk_src.clkr.hw,
366 },
367 .num_parents = 1,
368 .flags = CLK_SET_RATE_PARENT,
369 .ops = &clk_branch2_ops,
370 },
371 },
372 };
373
374 static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
375 .halt_reg = 0x7000,
376 .halt_check = BRANCH_HALT_VOTED,
377 .clkr = {
378 .enable_reg = 0x7000,
379 .enable_mask = BIT(0),
380 .hw.init = &(const struct clk_init_data) {
381 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
382 .ops = &clk_branch2_ops,
383 },
384 },
385 };
386
387 static struct clk_branch gpu_cc_hub_aon_clk = {
388 .halt_reg = 0x93e8,
389 .halt_check = BRANCH_HALT,
390 .clkr = {
391 .enable_reg = 0x93e8,
392 .enable_mask = BIT(0),
393 .hw.init = &(const struct clk_init_data) {
394 .name = "gpu_cc_hub_aon_clk",
395 .parent_hws = (const struct clk_hw*[]) {
396 &gpu_cc_hub_clk_src.clkr.hw,
397 },
398 .num_parents = 1,
399 .flags = CLK_SET_RATE_PARENT,
400 .ops = &clk_branch2_aon_ops,
401 },
402 },
403 };
404
405 static struct clk_branch gpu_cc_hub_cx_int_clk = {
406 .halt_reg = 0x9148,
407 .halt_check = BRANCH_HALT_VOTED,
408 .clkr = {
409 .enable_reg = 0x9148,
410 .enable_mask = BIT(0),
411 .hw.init = &(const struct clk_init_data) {
412 .name = "gpu_cc_hub_cx_int_clk",
413 .parent_hws = (const struct clk_hw*[]) {
414 &gpu_cc_hub_clk_src.clkr.hw,
415 },
416 .num_parents = 1,
417 .flags = CLK_SET_RATE_PARENT,
418 .ops = &clk_branch2_aon_ops,
419 },
420 },
421 };
422
423 static struct clk_branch gpu_cc_memnoc_gfx_clk = {
424 .halt_reg = 0x9150,
425 .halt_check = BRANCH_HALT_VOTED,
426 .clkr = {
427 .enable_reg = 0x9150,
428 .enable_mask = BIT(0),
429 .hw.init = &(const struct clk_init_data) {
430 .name = "gpu_cc_memnoc_gfx_clk",
431 .ops = &clk_branch2_ops,
432 },
433 },
434 };
435
436 static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
437 .halt_reg = 0x9288,
438 .halt_check = BRANCH_HALT,
439 .clkr = {
440 .enable_reg = 0x9288,
441 .enable_mask = BIT(0),
442 .hw.init = &(const struct clk_init_data) {
443 .name = "gpu_cc_mnd1x_0_gfx3d_clk",
444 .ops = &clk_branch2_ops,
445 },
446 },
447 };
448
449 static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
450 .halt_reg = 0x928c,
451 .halt_check = BRANCH_HALT,
452 .clkr = {
453 .enable_reg = 0x928c,
454 .enable_mask = BIT(0),
455 .hw.init = &(const struct clk_init_data) {
456 .name = "gpu_cc_mnd1x_1_gfx3d_clk",
457 .ops = &clk_branch2_ops,
458 },
459 },
460 };
461
462 static struct clk_branch gpu_cc_sleep_clk = {
463 .halt_reg = 0x9134,
464 .halt_check = BRANCH_HALT_VOTED,
465 .clkr = {
466 .enable_reg = 0x9134,
467 .enable_mask = BIT(0),
468 .hw.init = &(const struct clk_init_data) {
469 .name = "gpu_cc_sleep_clk",
470 .ops = &clk_branch2_ops,
471 },
472 },
473 };
474
475 static struct gdsc gpu_cc_cx_gdsc = {
476 .gdscr = 0x9108,
477 .gds_hw_ctrl = 0x953c,
478 .en_rest_wait_val = 0x2,
479 .en_few_wait_val = 0x2,
480 .clk_dis_wait_val = 0xf,
481 .pd = {
482 .name = "gpu_cc_cx_gdsc",
483 },
484 .pwrsts = PWRSTS_OFF_ON,
485 .flags = RETAIN_FF_ENABLE | VOTABLE,
486 };
487
488 static struct gdsc gpu_cc_gx_gdsc = {
489 .gdscr = 0x905c,
490 .clamp_io_ctrl = 0x9504,
491 .en_rest_wait_val = 0x2,
492 .en_few_wait_val = 0x2,
493 .clk_dis_wait_val = 0xf,
494 .pd = {
495 .name = "gpu_cc_gx_gdsc",
496 .power_on = gdsc_gx_do_nothing_enable,
497 },
498 .pwrsts = PWRSTS_OFF_ON,
499 .flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
500 };
501
502 static struct clk_regmap *gpu_cc_sm8550_clocks[] = {
503 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
504 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
505 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
506 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
507 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
508 [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
509 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
510 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
511 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
512 [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
513 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
514 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
515 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
516 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
517 [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
518 [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
519 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
520 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
521 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
522 [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
523 [GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
524 };
525
526 static struct gdsc *gpu_cc_sm8550_gdscs[] = {
527 [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
528 [GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc,
529 };
530
531 static const struct qcom_reset_map gpu_cc_sm8550_resets[] = {
532 [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
533 [GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
534 [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
535 [GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
536 [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
537 [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
538 [GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
539 [GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
540 };
541
542 static const struct regmap_config gpu_cc_sm8550_regmap_config = {
543 .reg_bits = 32,
544 .reg_stride = 4,
545 .val_bits = 32,
546 .max_register = 0x9988,
547 .fast_io = true,
548 };
549
550 static const struct qcom_cc_desc gpu_cc_sm8550_desc = {
551 .config = &gpu_cc_sm8550_regmap_config,
552 .clks = gpu_cc_sm8550_clocks,
553 .num_clks = ARRAY_SIZE(gpu_cc_sm8550_clocks),
554 .resets = gpu_cc_sm8550_resets,
555 .num_resets = ARRAY_SIZE(gpu_cc_sm8550_resets),
556 .gdscs = gpu_cc_sm8550_gdscs,
557 .num_gdscs = ARRAY_SIZE(gpu_cc_sm8550_gdscs),
558 };
559
560 static const struct of_device_id gpu_cc_sm8550_match_table[] = {
561 { .compatible = "qcom,sm8550-gpucc" },
562 { }
563 };
564 MODULE_DEVICE_TABLE(of, gpu_cc_sm8550_match_table);
565
gpu_cc_sm8550_probe(struct platform_device * pdev)566 static int gpu_cc_sm8550_probe(struct platform_device *pdev)
567 {
568 struct regmap *regmap;
569
570 regmap = qcom_cc_map(pdev, &gpu_cc_sm8550_desc);
571 if (IS_ERR(regmap))
572 return PTR_ERR(regmap);
573
574 clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
575 clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
576
577 /* Keep some clocks always-on */
578 qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */
579 qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */
580
581 return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8550_desc, regmap);
582 }
583
584 static struct platform_driver gpu_cc_sm8550_driver = {
585 .probe = gpu_cc_sm8550_probe,
586 .driver = {
587 .name = "gpu_cc-sm8550",
588 .of_match_table = gpu_cc_sm8550_match_table,
589 },
590 };
591
592 module_platform_driver(gpu_cc_sm8550_driver);
593
594 MODULE_DESCRIPTION("QTI GPUCC SM8550 Driver");
595 MODULE_LICENSE("GPL");
596