1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/mod_devicetable.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11
12 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
13 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
14
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
17 #include "clk-rcg.h"
18 #include "clk-regmap.h"
19 #include "clk-regmap-divider.h"
20 #include "clk-regmap-mux.h"
21 #include "clk-regmap-phy-mux.h"
22 #include "gdsc.h"
23 #include "reset.h"
24
25 enum {
26 DT_BI_TCXO,
27 DT_GPLL0_OUT_MAIN,
28 DT_GPLL0_OUT_MAIN_DIV,
29 };
30
31 enum {
32 P_BI_TCXO,
33 P_GPLL0_OUT_MAIN,
34 P_GPLL0_OUT_MAIN_DIV,
35 P_GPU_CC_PLL0_OUT_MAIN,
36 P_GPU_CC_PLL1_OUT_MAIN,
37 };
38
39 static const struct pll_vco lucid_evo_vco[] = {
40 { 249600000, 2000000000, 0 },
41 };
42
43 static const struct alpha_pll_config gpu_cc_pll0_config = {
44 .l = 0x1d,
45 .alpha = 0xb000,
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00182261,
48 .config_ctl_hi1_val = 0x32aa299c,
49 .user_ctl_val = 0x00000000,
50 .user_ctl_hi_val = 0x00000805,
51 };
52
53 static const struct alpha_pll_config sm8475_gpu_cc_pll0_config = {
54 .l = 0x1d,
55 .alpha = 0xb000,
56 .config_ctl_val = 0x20485699,
57 .config_ctl_hi_val = 0x00182261,
58 .config_ctl_hi1_val = 0x82aa299c,
59 .test_ctl_val = 0x00000000,
60 .test_ctl_hi_val = 0x00000003,
61 .test_ctl_hi1_val = 0x00009000,
62 .test_ctl_hi2_val = 0x00000034,
63 .user_ctl_val = 0x00000000,
64 .user_ctl_hi_val = 0x00000005,
65 };
66
67 static struct clk_alpha_pll gpu_cc_pll0 = {
68 .offset = 0x0,
69 .vco_table = lucid_evo_vco,
70 .num_vco = ARRAY_SIZE(lucid_evo_vco),
71 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
72 .clkr = {
73 .hw.init = &(struct clk_init_data){
74 .name = "gpu_cc_pll0",
75 .parent_data = &(const struct clk_parent_data){
76 .index = DT_BI_TCXO,
77 },
78 .num_parents = 1,
79 .ops = &clk_alpha_pll_lucid_evo_ops,
80 },
81 },
82 };
83
84 static const struct alpha_pll_config gpu_cc_pll1_config = {
85 .l = 0x34,
86 .alpha = 0x1555,
87 .config_ctl_val = 0x20485699,
88 .config_ctl_hi_val = 0x00182261,
89 .config_ctl_hi1_val = 0x32aa299c,
90 .user_ctl_val = 0x00000000,
91 .user_ctl_hi_val = 0x00000805,
92 };
93
94 static const struct alpha_pll_config sm8475_gpu_cc_pll1_config = {
95 .l = 0x34,
96 .alpha = 0x1555,
97 .config_ctl_val = 0x20485699,
98 .config_ctl_hi_val = 0x00182261,
99 .config_ctl_hi1_val = 0x82aa299c,
100 .test_ctl_val = 0x00000000,
101 .test_ctl_hi_val = 0x00000003,
102 .test_ctl_hi1_val = 0x00009000,
103 .test_ctl_hi2_val = 0x00000034,
104 .user_ctl_val = 0x00000000,
105 .user_ctl_hi_val = 0x00000005,
106 };
107
108 static struct clk_alpha_pll gpu_cc_pll1 = {
109 .offset = 0x1000,
110 .vco_table = lucid_evo_vco,
111 .num_vco = ARRAY_SIZE(lucid_evo_vco),
112 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
113 .clkr = {
114 .hw.init = &(struct clk_init_data){
115 .name = "gpu_cc_pll1",
116 .parent_data = &(const struct clk_parent_data){
117 .index = DT_BI_TCXO,
118 },
119 .num_parents = 1,
120 .ops = &clk_alpha_pll_lucid_evo_ops,
121 },
122 },
123 };
124
125 static const struct parent_map gpu_cc_parent_map_0[] = {
126 { P_BI_TCXO, 0 },
127 { P_GPLL0_OUT_MAIN, 5 },
128 { P_GPLL0_OUT_MAIN_DIV, 6 },
129 };
130
131 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
132 { .index = DT_BI_TCXO },
133 { .index = DT_GPLL0_OUT_MAIN },
134 { .index = DT_GPLL0_OUT_MAIN_DIV },
135 };
136
137 static const struct parent_map gpu_cc_parent_map_1[] = {
138 { P_BI_TCXO, 0 },
139 { P_GPU_CC_PLL0_OUT_MAIN, 1 },
140 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
141 { P_GPLL0_OUT_MAIN, 5 },
142 { P_GPLL0_OUT_MAIN_DIV, 6 },
143 };
144
145 static const struct clk_parent_data gpu_cc_parent_data_1[] = {
146 { .index = DT_BI_TCXO },
147 { .hw = &gpu_cc_pll0.clkr.hw },
148 { .hw = &gpu_cc_pll1.clkr.hw },
149 { .index = DT_GPLL0_OUT_MAIN },
150 { .index = DT_GPLL0_OUT_MAIN_DIV },
151 };
152
153 static const struct parent_map gpu_cc_parent_map_2[] = {
154 { P_BI_TCXO, 0 },
155 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
156 { P_GPLL0_OUT_MAIN, 5 },
157 { P_GPLL0_OUT_MAIN_DIV, 6 },
158 };
159
160 static const struct clk_parent_data gpu_cc_parent_data_2[] = {
161 { .index = DT_BI_TCXO },
162 { .hw = &gpu_cc_pll1.clkr.hw },
163 { .index = DT_GPLL0_OUT_MAIN },
164 { .index = DT_GPLL0_OUT_MAIN_DIV },
165 };
166
167 static const struct parent_map gpu_cc_parent_map_3[] = {
168 { P_BI_TCXO, 0 },
169 };
170
171 static const struct clk_parent_data gpu_cc_parent_data_3[] = {
172 { .index = DT_BI_TCXO },
173 };
174
175 static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
176 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
177 { }
178 };
179
180 static struct clk_rcg2 gpu_cc_ff_clk_src = {
181 .cmd_rcgr = 0x9474,
182 .mnd_width = 0,
183 .hid_width = 5,
184 .parent_map = gpu_cc_parent_map_0,
185 .freq_tbl = ftbl_gpu_cc_ff_clk_src,
186 .hw_clk_ctrl = true,
187 .clkr.hw.init = &(struct clk_init_data){
188 .name = "gpu_cc_ff_clk_src",
189 .parent_data = gpu_cc_parent_data_0,
190 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
191 .flags = CLK_SET_RATE_PARENT,
192 .ops = &clk_rcg2_shared_ops,
193 },
194 };
195
196 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
197 F(19200000, P_BI_TCXO, 1, 0, 0),
198 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
199 F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
200 { }
201 };
202
203 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
204 .cmd_rcgr = 0x9318,
205 .mnd_width = 0,
206 .hid_width = 5,
207 .parent_map = gpu_cc_parent_map_1,
208 .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
209 .hw_clk_ctrl = true,
210 .clkr.hw.init = &(struct clk_init_data){
211 .name = "gpu_cc_gmu_clk_src",
212 .parent_data = gpu_cc_parent_data_1,
213 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
214 .flags = CLK_SET_RATE_PARENT,
215 .ops = &clk_rcg2_shared_ops,
216 },
217 };
218
219 static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
220 F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
221 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
222 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
223 { }
224 };
225
226 static struct clk_rcg2 gpu_cc_hub_clk_src = {
227 .cmd_rcgr = 0x93ec,
228 .mnd_width = 0,
229 .hid_width = 5,
230 .parent_map = gpu_cc_parent_map_2,
231 .freq_tbl = ftbl_gpu_cc_hub_clk_src,
232 .hw_clk_ctrl = true,
233 .clkr.hw.init = &(struct clk_init_data){
234 .name = "gpu_cc_hub_clk_src",
235 .parent_data = gpu_cc_parent_data_2,
236 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
237 .flags = CLK_SET_RATE_PARENT,
238 .ops = &clk_rcg2_shared_ops,
239 },
240 };
241
242 static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
243 F(19200000, P_BI_TCXO, 1, 0, 0),
244 { }
245 };
246
247 static struct clk_rcg2 gpu_cc_xo_clk_src = {
248 .cmd_rcgr = 0x9010,
249 .mnd_width = 0,
250 .hid_width = 5,
251 .parent_map = gpu_cc_parent_map_3,
252 .freq_tbl = ftbl_gpu_cc_xo_clk_src,
253 .hw_clk_ctrl = true,
254 .clkr.hw.init = &(struct clk_init_data){
255 .name = "gpu_cc_xo_clk_src",
256 .parent_data = gpu_cc_parent_data_3,
257 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
258 .flags = CLK_SET_RATE_PARENT,
259 .ops = &clk_rcg2_shared_ops,
260 },
261 };
262
263 static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
264 .reg = 0x9054,
265 .shift = 0,
266 .width = 4,
267 .clkr.hw.init = &(struct clk_init_data) {
268 .name = "gpu_cc_demet_div_clk_src",
269 .parent_hws = (const struct clk_hw*[]){
270 &gpu_cc_xo_clk_src.clkr.hw,
271 },
272 .num_parents = 1,
273 .flags = CLK_SET_RATE_PARENT,
274 .ops = &clk_regmap_div_ro_ops,
275 },
276 };
277
278 static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
279 .reg = 0x9430,
280 .shift = 0,
281 .width = 4,
282 .clkr.hw.init = &(struct clk_init_data) {
283 .name = "gpu_cc_hub_ahb_div_clk_src",
284 .parent_hws = (const struct clk_hw*[]){
285 &gpu_cc_hub_clk_src.clkr.hw,
286 },
287 .num_parents = 1,
288 .flags = CLK_SET_RATE_PARENT,
289 .ops = &clk_regmap_div_ro_ops,
290 },
291 };
292
293 static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
294 .reg = 0x942c,
295 .shift = 0,
296 .width = 4,
297 .clkr.hw.init = &(struct clk_init_data) {
298 .name = "gpu_cc_hub_cx_int_div_clk_src",
299 .parent_hws = (const struct clk_hw*[]){
300 &gpu_cc_hub_clk_src.clkr.hw,
301 },
302 .num_parents = 1,
303 .flags = CLK_SET_RATE_PARENT,
304 .ops = &clk_regmap_div_ro_ops,
305 },
306 };
307
308 static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
309 .reg = 0x9050,
310 .shift = 0,
311 .width = 4,
312 .clkr.hw.init = &(struct clk_init_data) {
313 .name = "gpu_cc_xo_div_clk_src",
314 .parent_hws = (const struct clk_hw*[]){
315 &gpu_cc_xo_clk_src.clkr.hw,
316 },
317 .num_parents = 1,
318 .flags = CLK_SET_RATE_PARENT,
319 .ops = &clk_regmap_div_ro_ops,
320 },
321 };
322
323 static struct clk_branch gpu_cc_ahb_clk = {
324 .halt_reg = 0x911c,
325 .halt_check = BRANCH_HALT_DELAY,
326 .clkr = {
327 .enable_reg = 0x911c,
328 .enable_mask = BIT(0),
329 .hw.init = &(struct clk_init_data){
330 .name = "gpu_cc_ahb_clk",
331 .parent_hws = (const struct clk_hw*[]) {
332 &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
333 },
334 .num_parents = 1,
335 .flags = CLK_SET_RATE_PARENT,
336 .ops = &clk_branch2_ops,
337 },
338 },
339 };
340
341 static struct clk_branch gpu_cc_crc_ahb_clk = {
342 .halt_reg = 0x9120,
343 .halt_check = BRANCH_HALT_VOTED,
344 .clkr = {
345 .enable_reg = 0x9120,
346 .enable_mask = BIT(0),
347 .hw.init = &(struct clk_init_data){
348 .name = "gpu_cc_crc_ahb_clk",
349 .parent_hws = (const struct clk_hw*[]) {
350 &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
351 },
352 .num_parents = 1,
353 .flags = CLK_SET_RATE_PARENT,
354 .ops = &clk_branch2_ops,
355 },
356 },
357 };
358
359 static struct clk_branch gpu_cc_cx_apb_clk = {
360 .halt_reg = 0x912c,
361 .halt_check = BRANCH_HALT_VOTED,
362 .clkr = {
363 .enable_reg = 0x912c,
364 .enable_mask = BIT(0),
365 .hw.init = &(struct clk_init_data){
366 .name = "gpu_cc_cx_apb_clk",
367 .ops = &clk_branch2_ops,
368 },
369 },
370 };
371
372 static struct clk_branch gpu_cc_cx_ff_clk = {
373 .halt_reg = 0x914c,
374 .halt_check = BRANCH_HALT,
375 .clkr = {
376 .enable_reg = 0x914c,
377 .enable_mask = BIT(0),
378 .hw.init = &(struct clk_init_data){
379 .name = "gpu_cc_cx_ff_clk",
380 .parent_hws = (const struct clk_hw*[]) {
381 &gpu_cc_ff_clk_src.clkr.hw,
382 },
383 .num_parents = 1,
384 .flags = CLK_SET_RATE_PARENT,
385 .ops = &clk_branch2_ops,
386 },
387 },
388 };
389
390 static struct clk_branch gpu_cc_cx_gmu_clk = {
391 .halt_reg = 0x913c,
392 .halt_check = BRANCH_HALT,
393 .clkr = {
394 .enable_reg = 0x913c,
395 .enable_mask = BIT(0),
396 .hw.init = &(struct clk_init_data){
397 .name = "gpu_cc_cx_gmu_clk",
398 .parent_hws = (const struct clk_hw*[]) {
399 &gpu_cc_gmu_clk_src.clkr.hw,
400 },
401 .num_parents = 1,
402 .flags = CLK_SET_RATE_PARENT,
403 .ops = &clk_branch2_aon_ops,
404 },
405 },
406 };
407
408 static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
409 .halt_reg = 0x9130,
410 .halt_check = BRANCH_HALT_VOTED,
411 .clkr = {
412 .enable_reg = 0x9130,
413 .enable_mask = BIT(0),
414 .hw.init = &(struct clk_init_data){
415 .name = "gpu_cc_cx_snoc_dvm_clk",
416 .ops = &clk_branch2_ops,
417 },
418 },
419 };
420
421 static struct clk_branch gpu_cc_cxo_aon_clk = {
422 .halt_reg = 0x9004,
423 .halt_check = BRANCH_HALT_VOTED,
424 .clkr = {
425 .enable_reg = 0x9004,
426 .enable_mask = BIT(0),
427 .hw.init = &(struct clk_init_data){
428 .name = "gpu_cc_cxo_aon_clk",
429 .parent_hws = (const struct clk_hw*[]) {
430 &gpu_cc_xo_clk_src.clkr.hw,
431 },
432 .num_parents = 1,
433 .flags = CLK_SET_RATE_PARENT,
434 .ops = &clk_branch2_ops,
435 },
436 },
437 };
438
439 static struct clk_branch gpu_cc_cxo_clk = {
440 .halt_reg = 0x9144,
441 .halt_check = BRANCH_HALT,
442 .clkr = {
443 .enable_reg = 0x9144,
444 .enable_mask = BIT(0),
445 .hw.init = &(struct clk_init_data){
446 .name = "gpu_cc_cxo_clk",
447 .parent_hws = (const struct clk_hw*[]) {
448 &gpu_cc_xo_clk_src.clkr.hw,
449 },
450 .num_parents = 1,
451 .flags = CLK_SET_RATE_PARENT,
452 .ops = &clk_branch2_ops,
453 },
454 },
455 };
456
457 static struct clk_branch gpu_cc_demet_clk = {
458 .halt_reg = 0x900c,
459 .halt_check = BRANCH_HALT,
460 .clkr = {
461 .enable_reg = 0x900c,
462 .enable_mask = BIT(0),
463 .hw.init = &(struct clk_init_data){
464 .name = "gpu_cc_demet_clk",
465 .parent_hws = (const struct clk_hw*[]) {
466 &gpu_cc_demet_div_clk_src.clkr.hw,
467 },
468 .num_parents = 1,
469 .flags = CLK_SET_RATE_PARENT,
470 .ops = &clk_branch2_aon_ops,
471 },
472 },
473 };
474
475 static struct clk_branch gpu_cc_freq_measure_clk = {
476 .halt_reg = 0x9008,
477 .halt_check = BRANCH_HALT,
478 .clkr = {
479 .enable_reg = 0x9008,
480 .enable_mask = BIT(0),
481 .hw.init = &(struct clk_init_data){
482 .name = "gpu_cc_freq_measure_clk",
483 .parent_hws = (const struct clk_hw*[]) {
484 &gpu_cc_xo_div_clk_src.clkr.hw,
485 },
486 .num_parents = 1,
487 .flags = CLK_SET_RATE_PARENT,
488 .ops = &clk_branch2_ops,
489 },
490 },
491 };
492
493 static struct clk_branch gpu_cc_gx_ff_clk = {
494 .halt_reg = 0x90c0,
495 .halt_check = BRANCH_HALT,
496 .clkr = {
497 .enable_reg = 0x90c0,
498 .enable_mask = BIT(0),
499 .hw.init = &(struct clk_init_data){
500 .name = "gpu_cc_gx_ff_clk",
501 .parent_hws = (const struct clk_hw*[]) {
502 &gpu_cc_ff_clk_src.clkr.hw,
503 },
504 .num_parents = 1,
505 .flags = CLK_SET_RATE_PARENT,
506 .ops = &clk_branch2_ops,
507 },
508 },
509 };
510
511 static struct clk_branch gpu_cc_gx_gfx3d_clk = {
512 .halt_reg = 0x90a8,
513 .halt_check = BRANCH_HALT,
514 .clkr = {
515 .enable_reg = 0x90a8,
516 .enable_mask = BIT(0),
517 .hw.init = &(struct clk_init_data){
518 .name = "gpu_cc_gx_gfx3d_clk",
519 .ops = &clk_branch2_ops,
520 },
521 },
522 };
523
524 static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = {
525 .halt_reg = 0x90c8,
526 .halt_check = BRANCH_HALT,
527 .clkr = {
528 .enable_reg = 0x90c8,
529 .enable_mask = BIT(0),
530 .hw.init = &(struct clk_init_data){
531 .name = "gpu_cc_gx_gfx3d_rdvm_clk",
532 .ops = &clk_branch2_ops,
533 },
534 },
535 };
536
537 static struct clk_branch gpu_cc_gx_gmu_clk = {
538 .halt_reg = 0x90bc,
539 .halt_check = BRANCH_HALT,
540 .clkr = {
541 .enable_reg = 0x90bc,
542 .enable_mask = BIT(0),
543 .hw.init = &(struct clk_init_data){
544 .name = "gpu_cc_gx_gmu_clk",
545 .parent_hws = (const struct clk_hw*[]) {
546 &gpu_cc_gmu_clk_src.clkr.hw,
547 },
548 .num_parents = 1,
549 .flags = CLK_SET_RATE_PARENT,
550 .ops = &clk_branch2_ops,
551 },
552 },
553 };
554
555 static struct clk_branch gpu_cc_gx_vsense_clk = {
556 .halt_reg = 0x90b0,
557 .halt_check = BRANCH_HALT_VOTED,
558 .clkr = {
559 .enable_reg = 0x90b0,
560 .enable_mask = BIT(0),
561 .hw.init = &(struct clk_init_data){
562 .name = "gpu_cc_gx_vsense_clk",
563 .ops = &clk_branch2_ops,
564 },
565 },
566 };
567
568 static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
569 .halt_reg = 0x7000,
570 .halt_check = BRANCH_HALT_VOTED,
571 .clkr = {
572 .enable_reg = 0x7000,
573 .enable_mask = BIT(0),
574 .hw.init = &(struct clk_init_data){
575 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
576 .ops = &clk_branch2_ops,
577 },
578 },
579 };
580
581 static struct clk_branch gpu_cc_hub_aon_clk = {
582 .halt_reg = 0x93e8,
583 .halt_check = BRANCH_HALT,
584 .clkr = {
585 .enable_reg = 0x93e8,
586 .enable_mask = BIT(0),
587 .hw.init = &(struct clk_init_data){
588 .name = "gpu_cc_hub_aon_clk",
589 .parent_hws = (const struct clk_hw*[]) {
590 &gpu_cc_hub_clk_src.clkr.hw,
591 },
592 .num_parents = 1,
593 .flags = CLK_SET_RATE_PARENT,
594 .ops = &clk_branch2_aon_ops,
595 },
596 },
597 };
598
599 static struct clk_branch gpu_cc_hub_cx_int_clk = {
600 .halt_reg = 0x9148,
601 .halt_check = BRANCH_HALT,
602 .clkr = {
603 .enable_reg = 0x9148,
604 .enable_mask = BIT(0),
605 .hw.init = &(struct clk_init_data){
606 .name = "gpu_cc_hub_cx_int_clk",
607 .parent_hws = (const struct clk_hw*[]) {
608 &gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
609 },
610 .num_parents = 1,
611 .flags = CLK_SET_RATE_PARENT,
612 .ops = &clk_branch2_aon_ops,
613 },
614 },
615 };
616
617 static struct clk_branch gpu_cc_memnoc_gfx_clk = {
618 .halt_reg = 0x9150,
619 .halt_check = BRANCH_HALT,
620 .clkr = {
621 .enable_reg = 0x9150,
622 .enable_mask = BIT(0),
623 .hw.init = &(struct clk_init_data){
624 .name = "gpu_cc_memnoc_gfx_clk",
625 .ops = &clk_branch2_ops,
626 },
627 },
628 };
629
630 static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
631 .halt_reg = 0x9288,
632 .halt_check = BRANCH_HALT,
633 .clkr = {
634 .enable_reg = 0x9288,
635 .enable_mask = BIT(0),
636 .hw.init = &(struct clk_init_data){
637 .name = "gpu_cc_mnd1x_0_gfx3d_clk",
638 .ops = &clk_branch2_ops,
639 },
640 },
641 };
642
643 static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
644 .halt_reg = 0x928c,
645 .halt_check = BRANCH_HALT,
646 .clkr = {
647 .enable_reg = 0x928c,
648 .enable_mask = BIT(0),
649 .hw.init = &(struct clk_init_data){
650 .name = "gpu_cc_mnd1x_1_gfx3d_clk",
651 .ops = &clk_branch2_ops,
652 },
653 },
654 };
655
656 static struct clk_branch gpu_cc_sleep_clk = {
657 .halt_reg = 0x9134,
658 .halt_check = BRANCH_HALT_VOTED,
659 .clkr = {
660 .enable_reg = 0x9134,
661 .enable_mask = BIT(0),
662 .hw.init = &(struct clk_init_data){
663 .name = "gpu_cc_sleep_clk",
664 .ops = &clk_branch2_ops,
665 },
666 },
667 };
668
669 static struct gdsc gpu_cx_gdsc = {
670 .gdscr = 0x9108,
671 .gds_hw_ctrl = 0x953c,
672 .clk_dis_wait_val = 8,
673 .pd = {
674 .name = "gpu_cx_gdsc",
675 },
676 .pwrsts = PWRSTS_OFF_ON,
677 .flags = VOTABLE | RETAIN_FF_ENABLE,
678 };
679
680 static struct gdsc gpu_gx_gdsc = {
681 .gdscr = 0x905c,
682 .clamp_io_ctrl = 0x9504,
683 .resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR,
684 GPUCC_GPU_CC_ACD_BCR,
685 GPUCC_GPU_CC_GX_ACD_IROOT_BCR },
686 .reset_count = 3,
687 .pd = {
688 .name = "gpu_gx_gdsc",
689 .power_on = gdsc_gx_do_nothing_enable,
690 },
691 .pwrsts = PWRSTS_OFF_ON,
692 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
693 };
694
695 static struct clk_regmap *gpu_cc_sm8450_clocks[] = {
696 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
697 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
698 [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
699 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
700 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
701 [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
702 [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
703 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
704 [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
705 [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
706 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
707 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
708 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
709 [GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr,
710 [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
711 [GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr,
712 [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
713 [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
714 [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
715 [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
716 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
717 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
718 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
719 [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
720 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
721 [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
722 [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
723 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
724 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
725 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
726 [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
727 [GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
728 };
729
730 static const struct qcom_reset_map gpu_cc_sm8450_resets[] = {
731 [GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
732 [GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
733 [GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
734 [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
735 [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
736 [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
737 [GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
738 [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
739 [GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c },
740 };
741
742 static struct gdsc *gpu_cc_sm8450_gdscs[] = {
743 [GPU_CX_GDSC] = &gpu_cx_gdsc,
744 [GPU_GX_GDSC] = &gpu_gx_gdsc,
745 };
746
747 static const struct regmap_config gpu_cc_sm8450_regmap_config = {
748 .reg_bits = 32,
749 .reg_stride = 4,
750 .val_bits = 32,
751 .max_register = 0xa000,
752 .fast_io = true,
753 };
754
755 static const struct qcom_cc_desc gpu_cc_sm8450_desc = {
756 .config = &gpu_cc_sm8450_regmap_config,
757 .clks = gpu_cc_sm8450_clocks,
758 .num_clks = ARRAY_SIZE(gpu_cc_sm8450_clocks),
759 .resets = gpu_cc_sm8450_resets,
760 .num_resets = ARRAY_SIZE(gpu_cc_sm8450_resets),
761 .gdscs = gpu_cc_sm8450_gdscs,
762 .num_gdscs = ARRAY_SIZE(gpu_cc_sm8450_gdscs),
763 };
764
765 static const struct of_device_id gpu_cc_sm8450_match_table[] = {
766 { .compatible = "qcom,sm8450-gpucc" },
767 { .compatible = "qcom,sm8475-gpucc" },
768 { }
769 };
770 MODULE_DEVICE_TABLE(of, gpu_cc_sm8450_match_table);
771
gpu_cc_sm8450_probe(struct platform_device * pdev)772 static int gpu_cc_sm8450_probe(struct platform_device *pdev)
773 {
774 struct regmap *regmap;
775
776 regmap = qcom_cc_map(pdev, &gpu_cc_sm8450_desc);
777 if (IS_ERR(regmap))
778 return PTR_ERR(regmap);
779
780 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-gpucc")) {
781 /* Update GPUCC PLL0 */
782 gpu_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
783
784 /* Update GPUCC PLL1 */
785 gpu_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
786
787 clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &sm8475_gpu_cc_pll0_config);
788 clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &sm8475_gpu_cc_pll1_config);
789 } else {
790 clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
791 clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
792 }
793
794 return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8450_desc, regmap);
795 }
796
797 static struct platform_driver gpu_cc_sm8450_driver = {
798 .probe = gpu_cc_sm8450_probe,
799 .driver = {
800 .name = "sm8450-gpucc",
801 .of_match_table = gpu_cc_sm8450_match_table,
802 },
803 };
804 module_platform_driver(gpu_cc_sm8450_driver);
805
806 MODULE_DESCRIPTION("QTI GPU_CC SM8450 / SM8475 Driver");
807 MODULE_LICENSE("GPL");
808