1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10
11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
13
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
20 #include "clk-regmap-phy-mux.h"
21 #include "gdsc.h"
22 #include "reset.h"
23
24 enum {
25 DT_BI_TCXO,
26 DT_GPLL0_OUT_MAIN,
27 DT_GPLL0_OUT_MAIN_DIV,
28 };
29
30 enum {
31 P_BI_TCXO,
32 P_GPLL0_OUT_MAIN,
33 P_GPLL0_OUT_MAIN_DIV,
34 P_GPU_CC_PLL0_OUT_MAIN,
35 P_GPU_CC_PLL1_OUT_MAIN,
36 };
37
38 static const struct pll_vco lucid_evo_vco[] = {
39 { 249600000, 2000000000, 0 },
40 };
41
42 static const struct alpha_pll_config gpu_cc_pll0_config = {
43 .l = 0x1d,
44 .alpha = 0xb000,
45 .config_ctl_val = 0x20485699,
46 .config_ctl_hi_val = 0x00182261,
47 .config_ctl_hi1_val = 0x32aa299c,
48 .user_ctl_val = 0x00000000,
49 .user_ctl_hi_val = 0x00000805,
50 };
51
52 static const struct alpha_pll_config sm8475_gpu_cc_pll0_config = {
53 .l = 0x1d,
54 .alpha = 0xb000,
55 .config_ctl_val = 0x20485699,
56 .config_ctl_hi_val = 0x00182261,
57 .config_ctl_hi1_val = 0x82aa299c,
58 .test_ctl_val = 0x00000000,
59 .test_ctl_hi_val = 0x00000003,
60 .test_ctl_hi1_val = 0x00009000,
61 .test_ctl_hi2_val = 0x00000034,
62 .user_ctl_val = 0x00000000,
63 .user_ctl_hi_val = 0x00000005,
64 };
65
66 static struct clk_alpha_pll gpu_cc_pll0 = {
67 .offset = 0x0,
68 .vco_table = lucid_evo_vco,
69 .num_vco = ARRAY_SIZE(lucid_evo_vco),
70 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
71 .clkr = {
72 .hw.init = &(struct clk_init_data){
73 .name = "gpu_cc_pll0",
74 .parent_data = &(const struct clk_parent_data){
75 .index = DT_BI_TCXO,
76 },
77 .num_parents = 1,
78 .ops = &clk_alpha_pll_lucid_evo_ops,
79 },
80 },
81 };
82
83 static const struct alpha_pll_config gpu_cc_pll1_config = {
84 .l = 0x34,
85 .alpha = 0x1555,
86 .config_ctl_val = 0x20485699,
87 .config_ctl_hi_val = 0x00182261,
88 .config_ctl_hi1_val = 0x32aa299c,
89 .user_ctl_val = 0x00000000,
90 .user_ctl_hi_val = 0x00000805,
91 };
92
93 static const struct alpha_pll_config sm8475_gpu_cc_pll1_config = {
94 .l = 0x34,
95 .alpha = 0x1555,
96 .config_ctl_val = 0x20485699,
97 .config_ctl_hi_val = 0x00182261,
98 .config_ctl_hi1_val = 0x82aa299c,
99 .test_ctl_val = 0x00000000,
100 .test_ctl_hi_val = 0x00000003,
101 .test_ctl_hi1_val = 0x00009000,
102 .test_ctl_hi2_val = 0x00000034,
103 .user_ctl_val = 0x00000000,
104 .user_ctl_hi_val = 0x00000005,
105 };
106
107 static struct clk_alpha_pll gpu_cc_pll1 = {
108 .offset = 0x1000,
109 .vco_table = lucid_evo_vco,
110 .num_vco = ARRAY_SIZE(lucid_evo_vco),
111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
112 .clkr = {
113 .hw.init = &(struct clk_init_data){
114 .name = "gpu_cc_pll1",
115 .parent_data = &(const struct clk_parent_data){
116 .index = DT_BI_TCXO,
117 },
118 .num_parents = 1,
119 .ops = &clk_alpha_pll_lucid_evo_ops,
120 },
121 },
122 };
123
124 static const struct parent_map gpu_cc_parent_map_0[] = {
125 { P_BI_TCXO, 0 },
126 { P_GPLL0_OUT_MAIN, 5 },
127 { P_GPLL0_OUT_MAIN_DIV, 6 },
128 };
129
130 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
131 { .index = DT_BI_TCXO },
132 { .index = DT_GPLL0_OUT_MAIN },
133 { .index = DT_GPLL0_OUT_MAIN_DIV },
134 };
135
136 static const struct parent_map gpu_cc_parent_map_1[] = {
137 { P_BI_TCXO, 0 },
138 { P_GPU_CC_PLL0_OUT_MAIN, 1 },
139 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
140 { P_GPLL0_OUT_MAIN, 5 },
141 { P_GPLL0_OUT_MAIN_DIV, 6 },
142 };
143
144 static const struct clk_parent_data gpu_cc_parent_data_1[] = {
145 { .index = DT_BI_TCXO },
146 { .hw = &gpu_cc_pll0.clkr.hw },
147 { .hw = &gpu_cc_pll1.clkr.hw },
148 { .index = DT_GPLL0_OUT_MAIN },
149 { .index = DT_GPLL0_OUT_MAIN_DIV },
150 };
151
152 static const struct parent_map gpu_cc_parent_map_2[] = {
153 { P_BI_TCXO, 0 },
154 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
155 { P_GPLL0_OUT_MAIN, 5 },
156 { P_GPLL0_OUT_MAIN_DIV, 6 },
157 };
158
159 static const struct clk_parent_data gpu_cc_parent_data_2[] = {
160 { .index = DT_BI_TCXO },
161 { .hw = &gpu_cc_pll1.clkr.hw },
162 { .index = DT_GPLL0_OUT_MAIN },
163 { .index = DT_GPLL0_OUT_MAIN_DIV },
164 };
165
166 static const struct parent_map gpu_cc_parent_map_3[] = {
167 { P_BI_TCXO, 0 },
168 };
169
170 static const struct clk_parent_data gpu_cc_parent_data_3[] = {
171 { .index = DT_BI_TCXO },
172 };
173
174 static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
175 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
176 { }
177 };
178
179 static struct clk_rcg2 gpu_cc_ff_clk_src = {
180 .cmd_rcgr = 0x9474,
181 .mnd_width = 0,
182 .hid_width = 5,
183 .parent_map = gpu_cc_parent_map_0,
184 .freq_tbl = ftbl_gpu_cc_ff_clk_src,
185 .hw_clk_ctrl = true,
186 .clkr.hw.init = &(struct clk_init_data){
187 .name = "gpu_cc_ff_clk_src",
188 .parent_data = gpu_cc_parent_data_0,
189 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
190 .flags = CLK_SET_RATE_PARENT,
191 .ops = &clk_rcg2_shared_ops,
192 },
193 };
194
195 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
196 F(19200000, P_BI_TCXO, 1, 0, 0),
197 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
198 F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
199 { }
200 };
201
202 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
203 .cmd_rcgr = 0x9318,
204 .mnd_width = 0,
205 .hid_width = 5,
206 .parent_map = gpu_cc_parent_map_1,
207 .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
208 .hw_clk_ctrl = true,
209 .clkr.hw.init = &(struct clk_init_data){
210 .name = "gpu_cc_gmu_clk_src",
211 .parent_data = gpu_cc_parent_data_1,
212 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
213 .flags = CLK_SET_RATE_PARENT,
214 .ops = &clk_rcg2_shared_ops,
215 },
216 };
217
218 static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
219 F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
220 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
221 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
222 { }
223 };
224
225 static struct clk_rcg2 gpu_cc_hub_clk_src = {
226 .cmd_rcgr = 0x93ec,
227 .mnd_width = 0,
228 .hid_width = 5,
229 .parent_map = gpu_cc_parent_map_2,
230 .freq_tbl = ftbl_gpu_cc_hub_clk_src,
231 .hw_clk_ctrl = true,
232 .clkr.hw.init = &(struct clk_init_data){
233 .name = "gpu_cc_hub_clk_src",
234 .parent_data = gpu_cc_parent_data_2,
235 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
236 .flags = CLK_SET_RATE_PARENT,
237 .ops = &clk_rcg2_shared_ops,
238 },
239 };
240
241 static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
242 F(19200000, P_BI_TCXO, 1, 0, 0),
243 { }
244 };
245
246 static struct clk_rcg2 gpu_cc_xo_clk_src = {
247 .cmd_rcgr = 0x9010,
248 .mnd_width = 0,
249 .hid_width = 5,
250 .parent_map = gpu_cc_parent_map_3,
251 .freq_tbl = ftbl_gpu_cc_xo_clk_src,
252 .hw_clk_ctrl = true,
253 .clkr.hw.init = &(struct clk_init_data){
254 .name = "gpu_cc_xo_clk_src",
255 .parent_data = gpu_cc_parent_data_3,
256 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
257 .flags = CLK_SET_RATE_PARENT,
258 .ops = &clk_rcg2_shared_ops,
259 },
260 };
261
262 static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
263 .reg = 0x9054,
264 .shift = 0,
265 .width = 4,
266 .clkr.hw.init = &(struct clk_init_data) {
267 .name = "gpu_cc_demet_div_clk_src",
268 .parent_hws = (const struct clk_hw*[]){
269 &gpu_cc_xo_clk_src.clkr.hw,
270 },
271 .num_parents = 1,
272 .flags = CLK_SET_RATE_PARENT,
273 .ops = &clk_regmap_div_ro_ops,
274 },
275 };
276
277 static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
278 .reg = 0x9430,
279 .shift = 0,
280 .width = 4,
281 .clkr.hw.init = &(struct clk_init_data) {
282 .name = "gpu_cc_hub_ahb_div_clk_src",
283 .parent_hws = (const struct clk_hw*[]){
284 &gpu_cc_hub_clk_src.clkr.hw,
285 },
286 .num_parents = 1,
287 .flags = CLK_SET_RATE_PARENT,
288 .ops = &clk_regmap_div_ro_ops,
289 },
290 };
291
292 static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
293 .reg = 0x942c,
294 .shift = 0,
295 .width = 4,
296 .clkr.hw.init = &(struct clk_init_data) {
297 .name = "gpu_cc_hub_cx_int_div_clk_src",
298 .parent_hws = (const struct clk_hw*[]){
299 &gpu_cc_hub_clk_src.clkr.hw,
300 },
301 .num_parents = 1,
302 .flags = CLK_SET_RATE_PARENT,
303 .ops = &clk_regmap_div_ro_ops,
304 },
305 };
306
307 static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
308 .reg = 0x9050,
309 .shift = 0,
310 .width = 4,
311 .clkr.hw.init = &(struct clk_init_data) {
312 .name = "gpu_cc_xo_div_clk_src",
313 .parent_hws = (const struct clk_hw*[]){
314 &gpu_cc_xo_clk_src.clkr.hw,
315 },
316 .num_parents = 1,
317 .flags = CLK_SET_RATE_PARENT,
318 .ops = &clk_regmap_div_ro_ops,
319 },
320 };
321
322 static struct clk_branch gpu_cc_ahb_clk = {
323 .halt_reg = 0x911c,
324 .halt_check = BRANCH_HALT_DELAY,
325 .clkr = {
326 .enable_reg = 0x911c,
327 .enable_mask = BIT(0),
328 .hw.init = &(struct clk_init_data){
329 .name = "gpu_cc_ahb_clk",
330 .parent_hws = (const struct clk_hw*[]) {
331 &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
332 },
333 .num_parents = 1,
334 .flags = CLK_SET_RATE_PARENT,
335 .ops = &clk_branch2_ops,
336 },
337 },
338 };
339
340 static struct clk_branch gpu_cc_crc_ahb_clk = {
341 .halt_reg = 0x9120,
342 .halt_check = BRANCH_HALT_VOTED,
343 .clkr = {
344 .enable_reg = 0x9120,
345 .enable_mask = BIT(0),
346 .hw.init = &(struct clk_init_data){
347 .name = "gpu_cc_crc_ahb_clk",
348 .parent_hws = (const struct clk_hw*[]) {
349 &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
350 },
351 .num_parents = 1,
352 .flags = CLK_SET_RATE_PARENT,
353 .ops = &clk_branch2_ops,
354 },
355 },
356 };
357
358 static struct clk_branch gpu_cc_cx_apb_clk = {
359 .halt_reg = 0x912c,
360 .halt_check = BRANCH_HALT_VOTED,
361 .clkr = {
362 .enable_reg = 0x912c,
363 .enable_mask = BIT(0),
364 .hw.init = &(struct clk_init_data){
365 .name = "gpu_cc_cx_apb_clk",
366 .ops = &clk_branch2_ops,
367 },
368 },
369 };
370
371 static struct clk_branch gpu_cc_cx_ff_clk = {
372 .halt_reg = 0x914c,
373 .halt_check = BRANCH_HALT,
374 .clkr = {
375 .enable_reg = 0x914c,
376 .enable_mask = BIT(0),
377 .hw.init = &(struct clk_init_data){
378 .name = "gpu_cc_cx_ff_clk",
379 .parent_hws = (const struct clk_hw*[]) {
380 &gpu_cc_ff_clk_src.clkr.hw,
381 },
382 .num_parents = 1,
383 .flags = CLK_SET_RATE_PARENT,
384 .ops = &clk_branch2_ops,
385 },
386 },
387 };
388
389 static struct clk_branch gpu_cc_cx_gmu_clk = {
390 .halt_reg = 0x913c,
391 .halt_check = BRANCH_HALT,
392 .clkr = {
393 .enable_reg = 0x913c,
394 .enable_mask = BIT(0),
395 .hw.init = &(struct clk_init_data){
396 .name = "gpu_cc_cx_gmu_clk",
397 .parent_hws = (const struct clk_hw*[]) {
398 &gpu_cc_gmu_clk_src.clkr.hw,
399 },
400 .num_parents = 1,
401 .flags = CLK_SET_RATE_PARENT,
402 .ops = &clk_branch2_aon_ops,
403 },
404 },
405 };
406
407 static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
408 .halt_reg = 0x9130,
409 .halt_check = BRANCH_HALT_VOTED,
410 .clkr = {
411 .enable_reg = 0x9130,
412 .enable_mask = BIT(0),
413 .hw.init = &(struct clk_init_data){
414 .name = "gpu_cc_cx_snoc_dvm_clk",
415 .ops = &clk_branch2_ops,
416 },
417 },
418 };
419
420 static struct clk_branch gpu_cc_cxo_aon_clk = {
421 .halt_reg = 0x9004,
422 .halt_check = BRANCH_HALT_VOTED,
423 .clkr = {
424 .enable_reg = 0x9004,
425 .enable_mask = BIT(0),
426 .hw.init = &(struct clk_init_data){
427 .name = "gpu_cc_cxo_aon_clk",
428 .parent_hws = (const struct clk_hw*[]) {
429 &gpu_cc_xo_clk_src.clkr.hw,
430 },
431 .num_parents = 1,
432 .flags = CLK_SET_RATE_PARENT,
433 .ops = &clk_branch2_ops,
434 },
435 },
436 };
437
438 static struct clk_branch gpu_cc_cxo_clk = {
439 .halt_reg = 0x9144,
440 .halt_check = BRANCH_HALT,
441 .clkr = {
442 .enable_reg = 0x9144,
443 .enable_mask = BIT(0),
444 .hw.init = &(struct clk_init_data){
445 .name = "gpu_cc_cxo_clk",
446 .parent_hws = (const struct clk_hw*[]) {
447 &gpu_cc_xo_clk_src.clkr.hw,
448 },
449 .num_parents = 1,
450 .flags = CLK_SET_RATE_PARENT,
451 .ops = &clk_branch2_ops,
452 },
453 },
454 };
455
456 static struct clk_branch gpu_cc_demet_clk = {
457 .halt_reg = 0x900c,
458 .halt_check = BRANCH_HALT,
459 .clkr = {
460 .enable_reg = 0x900c,
461 .enable_mask = BIT(0),
462 .hw.init = &(struct clk_init_data){
463 .name = "gpu_cc_demet_clk",
464 .parent_hws = (const struct clk_hw*[]) {
465 &gpu_cc_demet_div_clk_src.clkr.hw,
466 },
467 .num_parents = 1,
468 .flags = CLK_SET_RATE_PARENT,
469 .ops = &clk_branch2_aon_ops,
470 },
471 },
472 };
473
474 static struct clk_branch gpu_cc_freq_measure_clk = {
475 .halt_reg = 0x9008,
476 .halt_check = BRANCH_HALT,
477 .clkr = {
478 .enable_reg = 0x9008,
479 .enable_mask = BIT(0),
480 .hw.init = &(struct clk_init_data){
481 .name = "gpu_cc_freq_measure_clk",
482 .parent_hws = (const struct clk_hw*[]) {
483 &gpu_cc_xo_div_clk_src.clkr.hw,
484 },
485 .num_parents = 1,
486 .flags = CLK_SET_RATE_PARENT,
487 .ops = &clk_branch2_ops,
488 },
489 },
490 };
491
492 static struct clk_branch gpu_cc_gx_ff_clk = {
493 .halt_reg = 0x90c0,
494 .halt_check = BRANCH_HALT,
495 .clkr = {
496 .enable_reg = 0x90c0,
497 .enable_mask = BIT(0),
498 .hw.init = &(struct clk_init_data){
499 .name = "gpu_cc_gx_ff_clk",
500 .parent_hws = (const struct clk_hw*[]) {
501 &gpu_cc_ff_clk_src.clkr.hw,
502 },
503 .num_parents = 1,
504 .flags = CLK_SET_RATE_PARENT,
505 .ops = &clk_branch2_ops,
506 },
507 },
508 };
509
510 static struct clk_branch gpu_cc_gx_gfx3d_clk = {
511 .halt_reg = 0x90a8,
512 .halt_check = BRANCH_HALT,
513 .clkr = {
514 .enable_reg = 0x90a8,
515 .enable_mask = BIT(0),
516 .hw.init = &(struct clk_init_data){
517 .name = "gpu_cc_gx_gfx3d_clk",
518 .ops = &clk_branch2_ops,
519 },
520 },
521 };
522
523 static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = {
524 .halt_reg = 0x90c8,
525 .halt_check = BRANCH_HALT,
526 .clkr = {
527 .enable_reg = 0x90c8,
528 .enable_mask = BIT(0),
529 .hw.init = &(struct clk_init_data){
530 .name = "gpu_cc_gx_gfx3d_rdvm_clk",
531 .ops = &clk_branch2_ops,
532 },
533 },
534 };
535
536 static struct clk_branch gpu_cc_gx_gmu_clk = {
537 .halt_reg = 0x90bc,
538 .halt_check = BRANCH_HALT,
539 .clkr = {
540 .enable_reg = 0x90bc,
541 .enable_mask = BIT(0),
542 .hw.init = &(struct clk_init_data){
543 .name = "gpu_cc_gx_gmu_clk",
544 .parent_hws = (const struct clk_hw*[]) {
545 &gpu_cc_gmu_clk_src.clkr.hw,
546 },
547 .num_parents = 1,
548 .flags = CLK_SET_RATE_PARENT,
549 .ops = &clk_branch2_ops,
550 },
551 },
552 };
553
554 static struct clk_branch gpu_cc_gx_vsense_clk = {
555 .halt_reg = 0x90b0,
556 .halt_check = BRANCH_HALT_VOTED,
557 .clkr = {
558 .enable_reg = 0x90b0,
559 .enable_mask = BIT(0),
560 .hw.init = &(struct clk_init_data){
561 .name = "gpu_cc_gx_vsense_clk",
562 .ops = &clk_branch2_ops,
563 },
564 },
565 };
566
567 static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
568 .halt_reg = 0x7000,
569 .halt_check = BRANCH_HALT_VOTED,
570 .clkr = {
571 .enable_reg = 0x7000,
572 .enable_mask = BIT(0),
573 .hw.init = &(struct clk_init_data){
574 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
575 .ops = &clk_branch2_ops,
576 },
577 },
578 };
579
580 static struct clk_branch gpu_cc_hub_aon_clk = {
581 .halt_reg = 0x93e8,
582 .halt_check = BRANCH_HALT,
583 .clkr = {
584 .enable_reg = 0x93e8,
585 .enable_mask = BIT(0),
586 .hw.init = &(struct clk_init_data){
587 .name = "gpu_cc_hub_aon_clk",
588 .parent_hws = (const struct clk_hw*[]) {
589 &gpu_cc_hub_clk_src.clkr.hw,
590 },
591 .num_parents = 1,
592 .flags = CLK_SET_RATE_PARENT,
593 .ops = &clk_branch2_aon_ops,
594 },
595 },
596 };
597
598 static struct clk_branch gpu_cc_hub_cx_int_clk = {
599 .halt_reg = 0x9148,
600 .halt_check = BRANCH_HALT,
601 .clkr = {
602 .enable_reg = 0x9148,
603 .enable_mask = BIT(0),
604 .hw.init = &(struct clk_init_data){
605 .name = "gpu_cc_hub_cx_int_clk",
606 .parent_hws = (const struct clk_hw*[]) {
607 &gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
608 },
609 .num_parents = 1,
610 .flags = CLK_SET_RATE_PARENT,
611 .ops = &clk_branch2_aon_ops,
612 },
613 },
614 };
615
616 static struct clk_branch gpu_cc_memnoc_gfx_clk = {
617 .halt_reg = 0x9150,
618 .halt_check = BRANCH_HALT,
619 .clkr = {
620 .enable_reg = 0x9150,
621 .enable_mask = BIT(0),
622 .hw.init = &(struct clk_init_data){
623 .name = "gpu_cc_memnoc_gfx_clk",
624 .ops = &clk_branch2_ops,
625 },
626 },
627 };
628
629 static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
630 .halt_reg = 0x9288,
631 .halt_check = BRANCH_HALT,
632 .clkr = {
633 .enable_reg = 0x9288,
634 .enable_mask = BIT(0),
635 .hw.init = &(struct clk_init_data){
636 .name = "gpu_cc_mnd1x_0_gfx3d_clk",
637 .ops = &clk_branch2_ops,
638 },
639 },
640 };
641
642 static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
643 .halt_reg = 0x928c,
644 .halt_check = BRANCH_HALT,
645 .clkr = {
646 .enable_reg = 0x928c,
647 .enable_mask = BIT(0),
648 .hw.init = &(struct clk_init_data){
649 .name = "gpu_cc_mnd1x_1_gfx3d_clk",
650 .ops = &clk_branch2_ops,
651 },
652 },
653 };
654
655 static struct clk_branch gpu_cc_sleep_clk = {
656 .halt_reg = 0x9134,
657 .halt_check = BRANCH_HALT_VOTED,
658 .clkr = {
659 .enable_reg = 0x9134,
660 .enable_mask = BIT(0),
661 .hw.init = &(struct clk_init_data){
662 .name = "gpu_cc_sleep_clk",
663 .ops = &clk_branch2_ops,
664 },
665 },
666 };
667
668 static struct gdsc gpu_cx_gdsc = {
669 .gdscr = 0x9108,
670 .gds_hw_ctrl = 0x953c,
671 .clk_dis_wait_val = 8,
672 .pd = {
673 .name = "gpu_cx_gdsc",
674 },
675 .pwrsts = PWRSTS_OFF_ON,
676 .flags = VOTABLE | RETAIN_FF_ENABLE,
677 };
678
679 static struct gdsc gpu_gx_gdsc = {
680 .gdscr = 0x905c,
681 .clamp_io_ctrl = 0x9504,
682 .resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR,
683 GPUCC_GPU_CC_ACD_BCR,
684 GPUCC_GPU_CC_GX_ACD_IROOT_BCR },
685 .reset_count = 3,
686 .pd = {
687 .name = "gpu_gx_gdsc",
688 .power_on = gdsc_gx_do_nothing_enable,
689 },
690 .pwrsts = PWRSTS_OFF_ON,
691 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
692 };
693
694 static struct clk_regmap *gpu_cc_sm8450_clocks[] = {
695 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
696 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
697 [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
698 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
699 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
700 [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
701 [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
702 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
703 [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
704 [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
705 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
706 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
707 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
708 [GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr,
709 [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
710 [GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr,
711 [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
712 [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
713 [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
714 [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
715 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
716 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
717 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
718 [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
719 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
720 [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
721 [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
722 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
723 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
724 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
725 [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
726 [GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
727 };
728
729 static const struct qcom_reset_map gpu_cc_sm8450_resets[] = {
730 [GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
731 [GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
732 [GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
733 [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
734 [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
735 [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
736 [GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
737 [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
738 [GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c },
739 };
740
741 static struct gdsc *gpu_cc_sm8450_gdscs[] = {
742 [GPU_CX_GDSC] = &gpu_cx_gdsc,
743 [GPU_GX_GDSC] = &gpu_gx_gdsc,
744 };
745
746 static const struct regmap_config gpu_cc_sm8450_regmap_config = {
747 .reg_bits = 32,
748 .reg_stride = 4,
749 .val_bits = 32,
750 .max_register = 0xa000,
751 .fast_io = true,
752 };
753
754 static const struct qcom_cc_desc gpu_cc_sm8450_desc = {
755 .config = &gpu_cc_sm8450_regmap_config,
756 .clks = gpu_cc_sm8450_clocks,
757 .num_clks = ARRAY_SIZE(gpu_cc_sm8450_clocks),
758 .resets = gpu_cc_sm8450_resets,
759 .num_resets = ARRAY_SIZE(gpu_cc_sm8450_resets),
760 .gdscs = gpu_cc_sm8450_gdscs,
761 .num_gdscs = ARRAY_SIZE(gpu_cc_sm8450_gdscs),
762 };
763
764 static const struct of_device_id gpu_cc_sm8450_match_table[] = {
765 { .compatible = "qcom,sm8450-gpucc" },
766 { .compatible = "qcom,sm8475-gpucc" },
767 { }
768 };
769 MODULE_DEVICE_TABLE(of, gpu_cc_sm8450_match_table);
770
gpu_cc_sm8450_probe(struct platform_device * pdev)771 static int gpu_cc_sm8450_probe(struct platform_device *pdev)
772 {
773 struct regmap *regmap;
774
775 regmap = qcom_cc_map(pdev, &gpu_cc_sm8450_desc);
776 if (IS_ERR(regmap))
777 return PTR_ERR(regmap);
778
779 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-gpucc")) {
780 /* Update GPUCC PLL0 */
781 gpu_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
782
783 /* Update GPUCC PLL1 */
784 gpu_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
785
786 clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &sm8475_gpu_cc_pll0_config);
787 clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &sm8475_gpu_cc_pll1_config);
788 } else {
789 clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
790 clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
791 }
792
793 return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8450_desc, regmap);
794 }
795
796 static struct platform_driver gpu_cc_sm8450_driver = {
797 .probe = gpu_cc_sm8450_probe,
798 .driver = {
799 .name = "sm8450-gpucc",
800 .of_match_table = gpu_cc_sm8450_match_table,
801 },
802 };
803 module_platform_driver(gpu_cc_sm8450_driver);
804
805 MODULE_DESCRIPTION("QTI GPU_CC SM8450 / SM8475 Driver");
806 MODULE_LICENSE("GPL");
807