1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10
11 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
12
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
15 #include "clk-pll.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "common.h"
20 #include "gdsc.h"
21 #include "reset.h"
22
23 enum {
24 DT_BI_TCXO,
25 DT_GPLL0_OUT_MAIN,
26 DT_GPLL0_OUT_MAIN_DIV,
27 };
28
29 enum {
30 P_BI_TCXO,
31 P_GPLL0_OUT_MAIN,
32 P_GPLL0_OUT_MAIN_DIV,
33 P_GPU_CC_PLL0_OUT_EVEN,
34 P_GPU_CC_PLL0_OUT_MAIN,
35 P_GPU_CC_PLL0_OUT_ODD,
36 P_GPU_CC_PLL1_OUT_EVEN,
37 P_GPU_CC_PLL1_OUT_MAIN,
38 P_GPU_CC_PLL1_OUT_ODD,
39 };
40
41 static const struct pll_vco lucid_evo_vco[] = {
42 { 249600000, 2020000000, 0 },
43 };
44
45 /* 680.0 MHz Configuration */
46 static const struct alpha_pll_config gpu_cc_pll0_config = {
47 .l = 0x23,
48 .alpha = 0x6aaa,
49 .config_ctl_val = 0x20485699,
50 .config_ctl_hi_val = 0x00182261,
51 .config_ctl_hi1_val = 0x32aa299c,
52 .user_ctl_val = 0x00000000,
53 .user_ctl_hi_val = 0x00000805,
54 };
55
56 static struct clk_alpha_pll gpu_cc_pll0 = {
57 .offset = 0x0,
58 .vco_table = lucid_evo_vco,
59 .num_vco = ARRAY_SIZE(lucid_evo_vco),
60 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
61 .clkr = {
62 .hw.init = &(const struct clk_init_data) {
63 .name = "gpu_cc_pll0",
64 .parent_data = &(const struct clk_parent_data) {
65 .index = DT_BI_TCXO,
66 },
67 .num_parents = 1,
68 .ops = &clk_alpha_pll_lucid_evo_ops,
69 },
70 },
71 };
72
73 /* 500.0 MHz Configuration */
74 static const struct alpha_pll_config gpu_cc_pll1_config = {
75 .l = 0x1a,
76 .alpha = 0xaaa,
77 .config_ctl_val = 0x20485699,
78 .config_ctl_hi_val = 0x00182261,
79 .config_ctl_hi1_val = 0x32aa299c,
80 .user_ctl_val = 0x00000000,
81 .user_ctl_hi_val = 0x00000805,
82 };
83
84 static struct clk_alpha_pll gpu_cc_pll1 = {
85 .offset = 0x1000,
86 .vco_table = lucid_evo_vco,
87 .num_vco = ARRAY_SIZE(lucid_evo_vco),
88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
89 .clkr = {
90 .hw.init = &(const struct clk_init_data) {
91 .name = "gpu_cc_pll1",
92 .parent_data = &(const struct clk_parent_data) {
93 .index = DT_BI_TCXO,
94 },
95 .num_parents = 1,
96 .ops = &clk_alpha_pll_lucid_evo_ops,
97 },
98 },
99 };
100
101 static const struct parent_map gpu_cc_parent_map_0[] = {
102 { P_BI_TCXO, 0 },
103 { P_GPLL0_OUT_MAIN, 5 },
104 { P_GPLL0_OUT_MAIN_DIV, 6 },
105 };
106
107 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
108 { .index = DT_BI_TCXO },
109 { .index = DT_GPLL0_OUT_MAIN },
110 { .index = DT_GPLL0_OUT_MAIN_DIV },
111 };
112
113 static const struct parent_map gpu_cc_parent_map_1[] = {
114 { P_BI_TCXO, 0 },
115 { P_GPU_CC_PLL0_OUT_MAIN, 1 },
116 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
117 { P_GPLL0_OUT_MAIN, 5 },
118 { P_GPLL0_OUT_MAIN_DIV, 6 },
119 };
120
121 static const struct clk_parent_data gpu_cc_parent_data_1[] = {
122 { .index = DT_BI_TCXO },
123 { .hw = &gpu_cc_pll0.clkr.hw },
124 { .hw = &gpu_cc_pll1.clkr.hw },
125 { .index = DT_GPLL0_OUT_MAIN },
126 { .index = DT_GPLL0_OUT_MAIN_DIV },
127 };
128
129 static const struct parent_map gpu_cc_parent_map_2[] = {
130 { P_BI_TCXO, 0 },
131 { P_GPU_CC_PLL0_OUT_EVEN, 1 },
132 { P_GPU_CC_PLL0_OUT_ODD, 2 },
133 { P_GPU_CC_PLL1_OUT_EVEN, 3 },
134 { P_GPU_CC_PLL1_OUT_ODD, 4 },
135 { P_GPLL0_OUT_MAIN, 5 },
136 };
137
138 static const struct clk_parent_data gpu_cc_parent_data_2[] = {
139 { .index = DT_BI_TCXO },
140 { .hw = &gpu_cc_pll0.clkr.hw },
141 { .hw = &gpu_cc_pll0.clkr.hw },
142 { .hw = &gpu_cc_pll1.clkr.hw },
143 { .hw = &gpu_cc_pll1.clkr.hw },
144 { .index = DT_GPLL0_OUT_MAIN },
145 };
146
147 static const struct parent_map gpu_cc_parent_map_3[] = {
148 { P_BI_TCXO, 0 },
149 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
150 { P_GPLL0_OUT_MAIN, 5 },
151 { P_GPLL0_OUT_MAIN_DIV, 6 },
152 };
153
154 static const struct clk_parent_data gpu_cc_parent_data_3[] = {
155 { .index = DT_BI_TCXO },
156 { .hw = &gpu_cc_pll1.clkr.hw },
157 { .index = DT_GPLL0_OUT_MAIN },
158 { .index = DT_GPLL0_OUT_MAIN_DIV },
159 };
160
161 static const struct parent_map gpu_cc_parent_map_4[] = {
162 { P_BI_TCXO, 0 },
163 };
164
165 static const struct clk_parent_data gpu_cc_parent_data_4[] = {
166 { .index = DT_BI_TCXO },
167 };
168
169 static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
170 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
171 { }
172 };
173
174 static struct clk_rcg2 gpu_cc_ff_clk_src = {
175 .cmd_rcgr = 0x9474,
176 .mnd_width = 0,
177 .hid_width = 5,
178 .parent_map = gpu_cc_parent_map_0,
179 .freq_tbl = ftbl_gpu_cc_ff_clk_src,
180 .clkr.hw.init = &(const struct clk_init_data) {
181 .name = "gpu_cc_ff_clk_src",
182 .parent_data = gpu_cc_parent_data_0,
183 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
184 .flags = CLK_SET_RATE_PARENT,
185 .ops = &clk_rcg2_shared_ops,
186 },
187 };
188
189 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
190 .cmd_rcgr = 0x9318,
191 .mnd_width = 0,
192 .hid_width = 5,
193 .parent_map = gpu_cc_parent_map_1,
194 .freq_tbl = ftbl_gpu_cc_ff_clk_src,
195 .clkr.hw.init = &(const struct clk_init_data) {
196 .name = "gpu_cc_gmu_clk_src",
197 .parent_data = gpu_cc_parent_data_1,
198 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
199 .flags = CLK_SET_RATE_PARENT,
200 .ops = &clk_rcg2_shared_ops,
201 },
202 };
203
204 static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
205 F(340000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
206 F(500000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
207 F(605000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
208 F(765000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
209 F(850000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
210 F(955000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
211 F(1010000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
212 { }
213 };
214
215 static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
216 .cmd_rcgr = 0x9070,
217 .mnd_width = 0,
218 .hid_width = 5,
219 .parent_map = gpu_cc_parent_map_2,
220 .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
221 .clkr.hw.init = &(const struct clk_init_data) {
222 .name = "gpu_cc_gx_gfx3d_clk_src",
223 .parent_data = gpu_cc_parent_data_2,
224 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
225 .flags = CLK_SET_RATE_PARENT,
226 .ops = &clk_rcg2_shared_ops,
227 },
228 };
229
230 static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
231 F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
232 { }
233 };
234
235 static struct clk_rcg2 gpu_cc_hub_clk_src = {
236 .cmd_rcgr = 0x93ec,
237 .mnd_width = 0,
238 .hid_width = 5,
239 .parent_map = gpu_cc_parent_map_3,
240 .freq_tbl = ftbl_gpu_cc_hub_clk_src,
241 .clkr.hw.init = &(const struct clk_init_data) {
242 .name = "gpu_cc_hub_clk_src",
243 .parent_data = gpu_cc_parent_data_3,
244 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
245 .flags = CLK_SET_RATE_PARENT,
246 .ops = &clk_rcg2_shared_ops,
247 },
248 };
249
250 static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
251 F(19200000, P_BI_TCXO, 1, 0, 0),
252 { }
253 };
254
255 static struct clk_rcg2 gpu_cc_xo_clk_src = {
256 .cmd_rcgr = 0x9010,
257 .mnd_width = 0,
258 .hid_width = 5,
259 .parent_map = gpu_cc_parent_map_4,
260 .freq_tbl = ftbl_gpu_cc_xo_clk_src,
261 .clkr.hw.init = &(const struct clk_init_data) {
262 .name = "gpu_cc_xo_clk_src",
263 .parent_data = gpu_cc_parent_data_4,
264 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_4),
265 .flags = CLK_SET_RATE_PARENT,
266 .ops = &clk_rcg2_shared_ops,
267 },
268 };
269
270 static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
271 .reg = 0x9054,
272 .shift = 0,
273 .width = 4,
274 .clkr.hw.init = &(const struct clk_init_data) {
275 .name = "gpu_cc_demet_div_clk_src",
276 .parent_hws = (const struct clk_hw*[]) {
277 &gpu_cc_xo_clk_src.clkr.hw,
278 },
279 .num_parents = 1,
280 .flags = CLK_SET_RATE_PARENT,
281 .ops = &clk_regmap_div_ro_ops,
282 },
283 };
284
285 static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
286 .reg = 0x9430,
287 .shift = 0,
288 .width = 4,
289 .clkr.hw.init = &(const struct clk_init_data) {
290 .name = "gpu_cc_hub_ahb_div_clk_src",
291 .parent_hws = (const struct clk_hw*[]) {
292 &gpu_cc_hub_clk_src.clkr.hw,
293 },
294 .num_parents = 1,
295 .flags = CLK_SET_RATE_PARENT,
296 .ops = &clk_regmap_div_ro_ops,
297 },
298 };
299
300 static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
301 .reg = 0x942c,
302 .shift = 0,
303 .width = 4,
304 .clkr.hw.init = &(const struct clk_init_data) {
305 .name = "gpu_cc_hub_cx_int_div_clk_src",
306 .parent_hws = (const struct clk_hw*[]) {
307 &gpu_cc_hub_clk_src.clkr.hw,
308 },
309 .num_parents = 1,
310 .flags = CLK_SET_RATE_PARENT,
311 .ops = &clk_regmap_div_ro_ops,
312 },
313 };
314
315 static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
316 .reg = 0x9050,
317 .shift = 0,
318 .width = 4,
319 .clkr.hw.init = &(const struct clk_init_data) {
320 .name = "gpu_cc_xo_div_clk_src",
321 .parent_hws = (const struct clk_hw*[]) {
322 &gpu_cc_xo_clk_src.clkr.hw,
323 },
324 .num_parents = 1,
325 .flags = CLK_SET_RATE_PARENT,
326 .ops = &clk_regmap_div_ro_ops,
327 },
328 };
329
330 static struct clk_branch gpu_cc_ahb_clk = {
331 .halt_reg = 0x911c,
332 .halt_check = BRANCH_HALT_DELAY,
333 .clkr = {
334 .enable_reg = 0x911c,
335 .enable_mask = BIT(0),
336 .hw.init = &(const struct clk_init_data) {
337 .name = "gpu_cc_ahb_clk",
338 .parent_hws = (const struct clk_hw*[]) {
339 &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
340 },
341 .num_parents = 1,
342 .flags = CLK_SET_RATE_PARENT,
343 .ops = &clk_branch2_ops,
344 },
345 },
346 };
347
348 static struct clk_branch gpu_cc_crc_ahb_clk = {
349 .halt_reg = 0x9120,
350 .halt_check = BRANCH_HALT,
351 .clkr = {
352 .enable_reg = 0x9120,
353 .enable_mask = BIT(0),
354 .hw.init = &(const struct clk_init_data) {
355 .name = "gpu_cc_crc_ahb_clk",
356 .parent_hws = (const struct clk_hw*[]) {
357 &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
358 },
359 .num_parents = 1,
360 .flags = CLK_SET_RATE_PARENT,
361 .ops = &clk_branch2_ops,
362 },
363 },
364 };
365
366 static struct clk_branch gpu_cc_cx_ff_clk = {
367 .halt_reg = 0x914c,
368 .halt_check = BRANCH_HALT,
369 .clkr = {
370 .enable_reg = 0x914c,
371 .enable_mask = BIT(0),
372 .hw.init = &(const struct clk_init_data) {
373 .name = "gpu_cc_cx_ff_clk",
374 .parent_hws = (const struct clk_hw*[]) {
375 &gpu_cc_ff_clk_src.clkr.hw,
376 },
377 .num_parents = 1,
378 .flags = CLK_SET_RATE_PARENT,
379 .ops = &clk_branch2_ops,
380 },
381 },
382 };
383
384 static struct clk_branch gpu_cc_cx_gfx3d_clk = {
385 .halt_reg = 0x919c,
386 .halt_check = BRANCH_HALT,
387 .clkr = {
388 .enable_reg = 0x919c,
389 .enable_mask = BIT(0),
390 .hw.init = &(const struct clk_init_data) {
391 .name = "gpu_cc_cx_gfx3d_clk",
392 .parent_hws = (const struct clk_hw*[]) {
393 &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
394 },
395 .num_parents = 1,
396 .flags = CLK_SET_RATE_PARENT,
397 .ops = &clk_branch2_ops,
398 },
399 },
400 };
401
402 static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {
403 .halt_reg = 0x91a0,
404 .halt_check = BRANCH_HALT,
405 .clkr = {
406 .enable_reg = 0x91a0,
407 .enable_mask = BIT(0),
408 .hw.init = &(const struct clk_init_data) {
409 .name = "gpu_cc_cx_gfx3d_slv_clk",
410 .parent_hws = (const struct clk_hw*[]) {
411 &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
412 },
413 .num_parents = 1,
414 .flags = CLK_SET_RATE_PARENT,
415 .ops = &clk_branch2_ops,
416 },
417 },
418 };
419
420 static struct clk_branch gpu_cc_cx_gmu_clk = {
421 .halt_reg = 0x913c,
422 .halt_check = BRANCH_HALT,
423 .clkr = {
424 .enable_reg = 0x913c,
425 .enable_mask = BIT(0),
426 .hw.init = &(const struct clk_init_data) {
427 .name = "gpu_cc_cx_gmu_clk",
428 .parent_hws = (const struct clk_hw*[]) {
429 &gpu_cc_gmu_clk_src.clkr.hw,
430 },
431 .num_parents = 1,
432 .flags = CLK_SET_RATE_PARENT,
433 .ops = &clk_branch2_aon_ops,
434 },
435 },
436 };
437
438 static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
439 .halt_reg = 0x9130,
440 .halt_check = BRANCH_HALT,
441 .clkr = {
442 .enable_reg = 0x9130,
443 .enable_mask = BIT(0),
444 .hw.init = &(const struct clk_init_data) {
445 .name = "gpu_cc_cx_snoc_dvm_clk",
446 .ops = &clk_branch2_ops,
447 },
448 },
449 };
450
451 static struct clk_branch gpu_cc_cxo_clk = {
452 .halt_reg = 0x9144,
453 .halt_check = BRANCH_HALT,
454 .clkr = {
455 .enable_reg = 0x9144,
456 .enable_mask = BIT(0),
457 .hw.init = &(const struct clk_init_data) {
458 .name = "gpu_cc_cxo_clk",
459 .parent_hws = (const struct clk_hw*[]) {
460 &gpu_cc_xo_clk_src.clkr.hw,
461 },
462 .num_parents = 1,
463 .flags = CLK_SET_RATE_PARENT,
464 .ops = &clk_branch2_ops,
465 },
466 },
467 };
468
469 static struct clk_branch gpu_cc_freq_measure_clk = {
470 .halt_reg = 0x9008,
471 .halt_check = BRANCH_HALT,
472 .clkr = {
473 .enable_reg = 0x9008,
474 .enable_mask = BIT(0),
475 .hw.init = &(const struct clk_init_data) {
476 .name = "gpu_cc_freq_measure_clk",
477 .parent_hws = (const struct clk_hw*[]) {
478 &gpu_cc_xo_div_clk_src.clkr.hw,
479 },
480 .num_parents = 1,
481 .flags = CLK_SET_RATE_PARENT,
482 .ops = &clk_branch2_ops,
483 },
484 },
485 };
486
487 static struct clk_branch gpu_cc_gx_cxo_clk = {
488 .halt_reg = 0x90b8,
489 .halt_check = BRANCH_HALT,
490 .clkr = {
491 .enable_reg = 0x90b8,
492 .enable_mask = BIT(0),
493 .hw.init = &(const struct clk_init_data) {
494 .name = "gpu_cc_gx_cxo_clk",
495 .parent_hws = (const struct clk_hw*[]) {
496 &gpu_cc_xo_clk_src.clkr.hw,
497 },
498 .num_parents = 1,
499 .flags = CLK_SET_RATE_PARENT,
500 .ops = &clk_branch2_ops,
501 },
502 },
503 };
504
505 static struct clk_branch gpu_cc_gx_ff_clk = {
506 .halt_reg = 0x90c0,
507 .halt_check = BRANCH_HALT,
508 .clkr = {
509 .enable_reg = 0x90c0,
510 .enable_mask = BIT(0),
511 .hw.init = &(const struct clk_init_data) {
512 .name = "gpu_cc_gx_ff_clk",
513 .parent_hws = (const struct clk_hw*[]) {
514 &gpu_cc_ff_clk_src.clkr.hw,
515 },
516 .num_parents = 1,
517 .flags = CLK_SET_RATE_PARENT,
518 .ops = &clk_branch2_ops,
519 },
520 },
521 };
522
523 static struct clk_branch gpu_cc_gx_gfx3d_clk = {
524 .halt_reg = 0x90a8,
525 .halt_check = BRANCH_HALT,
526 .clkr = {
527 .enable_reg = 0x90a8,
528 .enable_mask = BIT(0),
529 .hw.init = &(const struct clk_init_data) {
530 .name = "gpu_cc_gx_gfx3d_clk",
531 .parent_hws = (const struct clk_hw*[]) {
532 &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
533 },
534 .num_parents = 1,
535 .flags = CLK_SET_RATE_PARENT,
536 .ops = &clk_branch2_ops,
537 },
538 },
539 };
540
541 static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = {
542 .halt_reg = 0x90c8,
543 .halt_check = BRANCH_HALT,
544 .clkr = {
545 .enable_reg = 0x90c8,
546 .enable_mask = BIT(0),
547 .hw.init = &(const struct clk_init_data) {
548 .name = "gpu_cc_gx_gfx3d_rdvm_clk",
549 .parent_hws = (const struct clk_hw*[]) {
550 &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
551 },
552 .num_parents = 1,
553 .flags = CLK_SET_RATE_PARENT,
554 .ops = &clk_branch2_ops,
555 },
556 },
557 };
558
559 static struct clk_branch gpu_cc_gx_gmu_clk = {
560 .halt_reg = 0x90bc,
561 .halt_check = BRANCH_HALT,
562 .clkr = {
563 .enable_reg = 0x90bc,
564 .enable_mask = BIT(0),
565 .hw.init = &(const struct clk_init_data) {
566 .name = "gpu_cc_gx_gmu_clk",
567 .parent_hws = (const struct clk_hw*[]) {
568 &gpu_cc_gmu_clk_src.clkr.hw,
569 },
570 .num_parents = 1,
571 .flags = CLK_SET_RATE_PARENT,
572 .ops = &clk_branch2_ops,
573 },
574 },
575 };
576
577 static struct clk_branch gpu_cc_gx_vsense_clk = {
578 .halt_reg = 0x90b0,
579 .halt_check = BRANCH_HALT,
580 .clkr = {
581 .enable_reg = 0x90b0,
582 .enable_mask = BIT(0),
583 .hw.init = &(const struct clk_init_data) {
584 .name = "gpu_cc_gx_vsense_clk",
585 .ops = &clk_branch2_ops,
586 },
587 },
588 };
589
590 static struct clk_branch gpu_cc_hub_aon_clk = {
591 .halt_reg = 0x93e8,
592 .halt_check = BRANCH_HALT,
593 .clkr = {
594 .enable_reg = 0x93e8,
595 .enable_mask = BIT(0),
596 .hw.init = &(const struct clk_init_data) {
597 .name = "gpu_cc_hub_aon_clk",
598 .parent_hws = (const struct clk_hw*[]) {
599 &gpu_cc_hub_clk_src.clkr.hw,
600 },
601 .num_parents = 1,
602 .flags = CLK_SET_RATE_PARENT,
603 .ops = &clk_branch2_aon_ops,
604 },
605 },
606 };
607
608 static struct clk_branch gpu_cc_hub_cx_int_clk = {
609 .halt_reg = 0x9148,
610 .halt_check = BRANCH_HALT,
611 .clkr = {
612 .enable_reg = 0x9148,
613 .enable_mask = BIT(0),
614 .hw.init = &(const struct clk_init_data) {
615 .name = "gpu_cc_hub_cx_int_clk",
616 .parent_hws = (const struct clk_hw*[]) {
617 &gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
618 },
619 .num_parents = 1,
620 .flags = CLK_SET_RATE_PARENT,
621 .ops = &clk_branch2_aon_ops,
622 },
623 },
624 };
625
626 static struct clk_branch gpu_cc_memnoc_gfx_clk = {
627 .halt_reg = 0x9150,
628 .halt_check = BRANCH_HALT,
629 .clkr = {
630 .enable_reg = 0x9150,
631 .enable_mask = BIT(0),
632 .hw.init = &(const struct clk_init_data) {
633 .name = "gpu_cc_memnoc_gfx_clk",
634 .ops = &clk_branch2_ops,
635 },
636 },
637 };
638
639 static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
640 .halt_reg = 0x9288,
641 .halt_check = BRANCH_HALT,
642 .clkr = {
643 .enable_reg = 0x9288,
644 .enable_mask = BIT(0),
645 .hw.init = &(const struct clk_init_data) {
646 .name = "gpu_cc_mnd1x_0_gfx3d_clk",
647 .parent_hws = (const struct clk_hw*[]) {
648 &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
649 },
650 .num_parents = 1,
651 .flags = CLK_SET_RATE_PARENT,
652 .ops = &clk_branch2_ops,
653 },
654 },
655 };
656
657 static struct clk_branch gpu_cc_sleep_clk = {
658 .halt_reg = 0x9134,
659 .halt_check = BRANCH_HALT,
660 .clkr = {
661 .enable_reg = 0x9134,
662 .enable_mask = BIT(0),
663 .hw.init = &(const struct clk_init_data) {
664 .name = "gpu_cc_sleep_clk",
665 .ops = &clk_branch2_ops,
666 },
667 },
668 };
669
670 static struct gdsc gpu_cc_cx_gdsc = {
671 .gdscr = 0x9108,
672 .gds_hw_ctrl = 0x953c,
673 .clk_dis_wait_val = 8,
674 .pd = {
675 .name = "gpu_cx_gdsc",
676 },
677 .pwrsts = PWRSTS_OFF_ON,
678 .flags = VOTABLE | RETAIN_FF_ENABLE,
679 };
680
681 static struct gdsc gpu_cc_gx_gdsc = {
682 .gdscr = 0x905c,
683 .clamp_io_ctrl = 0x9504,
684 .resets = (unsigned int []){ GPU_CC_GX_BCR,
685 GPU_CC_ACD_BCR,
686 GPU_CC_GX_ACD_IROOT_BCR },
687 .reset_count = 3,
688 .pd = {
689 .name = "gpu_gx_gdsc",
690 .power_on = gdsc_gx_do_nothing_enable,
691 },
692 .pwrsts = PWRSTS_OFF_ON,
693 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
694 };
695
696 static struct clk_regmap *gpu_cc_sm4450_clocks[] = {
697 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
698 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
699 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
700 [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
701 [GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,
702 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
703 [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
704 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
705 [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
706 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
707 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
708 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
709 [GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
710 [GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr,
711 [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
712 [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
713 [GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr,
714 [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
715 [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
716 [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
717 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
718 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
719 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
720 [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
721 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
722 [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
723 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
724 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
725 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
726 [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
727 [GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
728 };
729
730 static struct gdsc *gpu_cc_sm4450_gdscs[] = {
731 [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
732 [GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc,
733 };
734
735 static const struct qcom_reset_map gpu_cc_sm4450_resets[] = {
736 [GPU_CC_CB_BCR] = { 0x93a0 },
737 [GPU_CC_CX_BCR] = { 0x9104 },
738 [GPU_CC_GX_BCR] = { 0x9058 },
739 [GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
740 [GPU_CC_ACD_BCR] = { 0x9358 },
741 [GPU_CC_FF_BCR] = { 0x9470 },
742 [GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
743 [GPU_CC_GMU_BCR] = { 0x9314 },
744 [GPU_CC_RBCPR_BCR] = { 0x91e0 },
745 [GPU_CC_XO_BCR] = { 0x9000 },
746 [GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c },
747 };
748
749 static const struct regmap_config gpu_cc_sm4450_regmap_config = {
750 .reg_bits = 32,
751 .reg_stride = 4,
752 .val_bits = 32,
753 .max_register = 0x95c0,
754 .fast_io = true,
755 };
756
757 static const struct qcom_cc_desc gpu_cc_sm4450_desc = {
758 .config = &gpu_cc_sm4450_regmap_config,
759 .clks = gpu_cc_sm4450_clocks,
760 .num_clks = ARRAY_SIZE(gpu_cc_sm4450_clocks),
761 .resets = gpu_cc_sm4450_resets,
762 .num_resets = ARRAY_SIZE(gpu_cc_sm4450_resets),
763 .gdscs = gpu_cc_sm4450_gdscs,
764 .num_gdscs = ARRAY_SIZE(gpu_cc_sm4450_gdscs),
765 };
766
767 static const struct of_device_id gpu_cc_sm4450_match_table[] = {
768 { .compatible = "qcom,sm4450-gpucc" },
769 { }
770 };
771 MODULE_DEVICE_TABLE(of, gpu_cc_sm4450_match_table);
772
gpu_cc_sm4450_probe(struct platform_device * pdev)773 static int gpu_cc_sm4450_probe(struct platform_device *pdev)
774 {
775 struct regmap *regmap;
776
777 regmap = qcom_cc_map(pdev, &gpu_cc_sm4450_desc);
778 if (IS_ERR(regmap))
779 return PTR_ERR(regmap);
780
781 clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
782 clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
783
784 /* Keep some clocks always enabled */
785 qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */
786 qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */
787 qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */
788
789 return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm4450_desc, regmap);
790 }
791
792 static struct platform_driver gpu_cc_sm4450_driver = {
793 .probe = gpu_cc_sm4450_probe,
794 .driver = {
795 .name = "gpucc-sm4450",
796 .of_match_table = gpu_cc_sm4450_match_table,
797 },
798 };
799
800 module_platform_driver(gpu_cc_sm4450_driver);
801
802 MODULE_DESCRIPTION("QTI GPUCC SM4450 Driver");
803 MODULE_LICENSE("GPL");
804