1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10
11 #include <dt-bindings/clock/qcom,kaanapali-gpucc.h>
12
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
15 #include "clk-pll.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
20 #include "common.h"
21 #include "gdsc.h"
22 #include "reset.h"
23
24 enum {
25 DT_BI_TCXO,
26 DT_GPLL0_OUT_MAIN,
27 DT_GPLL0_OUT_MAIN_DIV,
28 };
29
30 enum {
31 P_BI_TCXO,
32 P_GPLL0_OUT_MAIN,
33 P_GPLL0_OUT_MAIN_DIV,
34 P_GPU_CC_PLL0_OUT_EVEN,
35 P_GPU_CC_PLL0_OUT_MAIN,
36 P_GPU_CC_PLL0_OUT_ODD,
37 };
38
39 static const struct pll_vco taycan_eko_t_vco[] = {
40 { 249600000, 2500000000, 0 },
41 };
42
43 /* 950.0 MHz Configuration */
44 static const struct alpha_pll_config gpu_cc_pll0_config = {
45 .l = 0x31,
46 .cal_l = 0x48,
47 .alpha = 0x7aaa,
48 .config_ctl_val = 0x25c400e7,
49 .config_ctl_hi_val = 0x0a8062e0,
50 .config_ctl_hi1_val = 0xf51dea20,
51 .user_ctl_val = 0x00000408,
52 .user_ctl_hi_val = 0x00000002,
53 };
54
55 static struct clk_alpha_pll gpu_cc_pll0 = {
56 .offset = 0x0,
57 .config = &gpu_cc_pll0_config,
58 .vco_table = taycan_eko_t_vco,
59 .num_vco = ARRAY_SIZE(taycan_eko_t_vco),
60 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
61 .clkr = {
62 .hw.init = &(const struct clk_init_data) {
63 .name = "gpu_cc_pll0",
64 .parent_data = &(const struct clk_parent_data) {
65 .index = DT_BI_TCXO,
66 },
67 .num_parents = 1,
68 .ops = &clk_alpha_pll_taycan_eko_t_ops,
69 },
70 },
71 };
72
73 static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = {
74 { 0x1, 2 },
75 { }
76 };
77
78 static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = {
79 .offset = 0x0,
80 .post_div_shift = 10,
81 .post_div_table = post_div_table_gpu_cc_pll0_out_even,
82 .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even),
83 .width = 4,
84 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
85 .clkr.hw.init = &(const struct clk_init_data) {
86 .name = "gpu_cc_pll0_out_even",
87 .parent_hws = (const struct clk_hw*[]) {
88 &gpu_cc_pll0.clkr.hw,
89 },
90 .num_parents = 1,
91 .flags = CLK_SET_RATE_PARENT,
92 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops,
93 },
94 };
95
96 static const struct parent_map gpu_cc_parent_map_0[] = {
97 { P_BI_TCXO, 0 },
98 { P_GPU_CC_PLL0_OUT_MAIN, 1 },
99 { P_GPU_CC_PLL0_OUT_EVEN, 2 },
100 { P_GPU_CC_PLL0_OUT_ODD, 3 },
101 { P_GPLL0_OUT_MAIN, 5 },
102 { P_GPLL0_OUT_MAIN_DIV, 6 },
103 };
104
105 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
106 { .index = DT_BI_TCXO },
107 { .hw = &gpu_cc_pll0.clkr.hw },
108 { .hw = &gpu_cc_pll0_out_even.clkr.hw },
109 { .hw = &gpu_cc_pll0.clkr.hw },
110 { .index = DT_GPLL0_OUT_MAIN },
111 { .index = DT_GPLL0_OUT_MAIN_DIV },
112 };
113
114 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
115 F(19200000, P_BI_TCXO, 1, 0, 0),
116 F(475000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
117 F(575000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
118 F(700000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
119 F(725000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
120 F(750000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
121 { }
122 };
123
124 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
125 .cmd_rcgr = 0x9318,
126 .mnd_width = 0,
127 .hid_width = 5,
128 .parent_map = gpu_cc_parent_map_0,
129 .hw_clk_ctrl = true,
130 .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
131 .clkr.hw.init = &(const struct clk_init_data) {
132 .name = "gpu_cc_gmu_clk_src",
133 .parent_data = gpu_cc_parent_data_0,
134 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
135 .flags = CLK_SET_RATE_PARENT,
136 .ops = &clk_rcg2_shared_ops,
137 },
138 };
139
140 static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
141 F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
142 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
143 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
144 F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
145 { }
146 };
147
148 static struct clk_rcg2 gpu_cc_hub_clk_src = {
149 .cmd_rcgr = 0x93f0,
150 .mnd_width = 0,
151 .hid_width = 5,
152 .parent_map = gpu_cc_parent_map_0,
153 .hw_clk_ctrl = true,
154 .freq_tbl = ftbl_gpu_cc_hub_clk_src,
155 .clkr.hw.init = &(const struct clk_init_data) {
156 .name = "gpu_cc_hub_clk_src",
157 .parent_data = gpu_cc_parent_data_0,
158 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
159 .flags = CLK_SET_RATE_PARENT,
160 .ops = &clk_rcg2_shared_ops,
161 },
162 };
163
164 static struct clk_regmap_div gpu_cc_hub_div_clk_src = {
165 .reg = 0x9430,
166 .shift = 0,
167 .width = 4,
168 .clkr.hw.init = &(const struct clk_init_data) {
169 .name = "gpu_cc_hub_div_clk_src",
170 .parent_hws = (const struct clk_hw*[]) {
171 &gpu_cc_hub_clk_src.clkr.hw,
172 },
173 .num_parents = 1,
174 .flags = CLK_SET_RATE_PARENT,
175 .ops = &clk_regmap_div_ro_ops,
176 },
177 };
178
179 static struct clk_branch gpu_cc_ahb_clk = {
180 .halt_reg = 0x90bc,
181 .halt_check = BRANCH_HALT_DELAY,
182 .clkr = {
183 .enable_reg = 0x90bc,
184 .enable_mask = BIT(0),
185 .hw.init = &(const struct clk_init_data) {
186 .name = "gpu_cc_ahb_clk",
187 .parent_hws = (const struct clk_hw*[]) {
188 &gpu_cc_hub_div_clk_src.clkr.hw,
189 },
190 .num_parents = 1,
191 .flags = CLK_SET_RATE_PARENT,
192 .ops = &clk_branch2_ops,
193 },
194 },
195 };
196
197 static struct clk_branch gpu_cc_cx_accu_shift_clk = {
198 .halt_reg = 0x9104,
199 .halt_check = BRANCH_HALT_VOTED,
200 .clkr = {
201 .enable_reg = 0x9104,
202 .enable_mask = BIT(0),
203 .hw.init = &(const struct clk_init_data) {
204 .name = "gpu_cc_cx_accu_shift_clk",
205 .ops = &clk_branch2_ops,
206 },
207 },
208 };
209
210 static struct clk_branch gpu_cc_cx_gmu_clk = {
211 .halt_reg = 0x90d4,
212 .halt_check = BRANCH_HALT_VOTED,
213 .clkr = {
214 .enable_reg = 0x90d4,
215 .enable_mask = BIT(0),
216 .hw.init = &(const struct clk_init_data) {
217 .name = "gpu_cc_cx_gmu_clk",
218 .parent_hws = (const struct clk_hw*[]) {
219 &gpu_cc_gmu_clk_src.clkr.hw,
220 },
221 .num_parents = 1,
222 .flags = CLK_SET_RATE_PARENT,
223 .ops = &clk_branch2_aon_ops,
224 },
225 },
226 };
227
228 static struct clk_branch gpu_cc_cxo_clk = {
229 .halt_reg = 0x90e4,
230 .halt_check = BRANCH_HALT,
231 .clkr = {
232 .enable_reg = 0x90e4,
233 .enable_mask = BIT(0),
234 .hw.init = &(const struct clk_init_data) {
235 .name = "gpu_cc_cxo_clk",
236 .ops = &clk_branch2_aon_ops,
237 },
238 },
239 };
240
241 static struct clk_branch gpu_cc_demet_clk = {
242 .halt_reg = 0x9010,
243 .halt_check = BRANCH_HALT_VOTED,
244 .clkr = {
245 .enable_reg = 0x9010,
246 .enable_mask = BIT(0),
247 .hw.init = &(const struct clk_init_data) {
248 .name = "gpu_cc_demet_clk",
249 .ops = &clk_branch2_ops,
250 },
251 },
252 };
253
254 static struct clk_branch gpu_cc_dpm_clk = {
255 .halt_reg = 0x9108,
256 .halt_check = BRANCH_HALT,
257 .clkr = {
258 .enable_reg = 0x9108,
259 .enable_mask = BIT(0),
260 .hw.init = &(const struct clk_init_data) {
261 .name = "gpu_cc_dpm_clk",
262 .ops = &clk_branch2_ops,
263 },
264 },
265 };
266
267 static struct clk_branch gpu_cc_freq_measure_clk = {
268 .halt_reg = 0x900c,
269 .halt_check = BRANCH_HALT,
270 .clkr = {
271 .enable_reg = 0x900c,
272 .enable_mask = BIT(0),
273 .hw.init = &(const struct clk_init_data) {
274 .name = "gpu_cc_freq_measure_clk",
275 .ops = &clk_branch2_ops,
276 },
277 },
278 };
279
280 static struct clk_branch gpu_cc_gpu_smmu_vote_clk = {
281 .halt_reg = 0x7000,
282 .halt_check = BRANCH_HALT_VOTED,
283 .clkr = {
284 .enable_reg = 0x7000,
285 .enable_mask = BIT(0),
286 .hw.init = &(const struct clk_init_data) {
287 .name = "gpu_cc_gpu_smmu_vote_clk",
288 .ops = &clk_branch2_ops,
289 },
290 },
291 };
292
293 static struct clk_branch gpu_cc_gx_accu_shift_clk = {
294 .halt_reg = 0x9070,
295 .halt_check = BRANCH_HALT_VOTED,
296 .clkr = {
297 .enable_reg = 0x9070,
298 .enable_mask = BIT(0),
299 .hw.init = &(const struct clk_init_data) {
300 .name = "gpu_cc_gx_accu_shift_clk",
301 .ops = &clk_branch2_ops,
302 },
303 },
304 };
305
306 static struct clk_branch gpu_cc_gx_gmu_clk = {
307 .halt_reg = 0x9060,
308 .halt_check = BRANCH_HALT,
309 .clkr = {
310 .enable_reg = 0x9060,
311 .enable_mask = BIT(0),
312 .hw.init = &(const struct clk_init_data) {
313 .name = "gpu_cc_gx_gmu_clk",
314 .parent_hws = (const struct clk_hw*[]) {
315 &gpu_cc_gmu_clk_src.clkr.hw,
316 },
317 .num_parents = 1,
318 .flags = CLK_SET_RATE_PARENT,
319 .ops = &clk_branch2_ops,
320 },
321 },
322 };
323
324 static struct clk_branch gpu_cc_hub_aon_clk = {
325 .halt_reg = 0x93ec,
326 .halt_check = BRANCH_HALT_VOTED,
327 .clkr = {
328 .enable_reg = 0x93ec,
329 .enable_mask = BIT(0),
330 .hw.init = &(const struct clk_init_data) {
331 .name = "gpu_cc_hub_aon_clk",
332 .parent_hws = (const struct clk_hw*[]) {
333 &gpu_cc_hub_clk_src.clkr.hw,
334 },
335 .num_parents = 1,
336 .flags = CLK_SET_RATE_PARENT,
337 .ops = &clk_branch2_aon_ops,
338 },
339 },
340 };
341
342 static struct clk_branch gpu_cc_hub_cx_int_clk = {
343 .halt_reg = 0x90e8,
344 .halt_check = BRANCH_HALT_VOTED,
345 .clkr = {
346 .enable_reg = 0x90e8,
347 .enable_mask = BIT(0),
348 .hw.init = &(const struct clk_init_data) {
349 .name = "gpu_cc_hub_cx_int_clk",
350 .parent_hws = (const struct clk_hw*[]) {
351 &gpu_cc_hub_clk_src.clkr.hw,
352 },
353 .num_parents = 1,
354 .flags = CLK_SET_RATE_PARENT,
355 .ops = &clk_branch2_aon_ops,
356 },
357 },
358 };
359
360 static struct clk_branch gpu_cc_memnoc_gfx_clk = {
361 .halt_reg = 0x90ec,
362 .halt_check = BRANCH_HALT_VOTED,
363 .clkr = {
364 .enable_reg = 0x90ec,
365 .enable_mask = BIT(0),
366 .hw.init = &(const struct clk_init_data) {
367 .name = "gpu_cc_memnoc_gfx_clk",
368 .ops = &clk_branch2_ops,
369 },
370 },
371 };
372
373 static struct gdsc gpu_cc_cx_gdsc = {
374 .gdscr = 0x9080,
375 .gds_hw_ctrl = 0x9094,
376 .en_rest_wait_val = 0x2,
377 .en_few_wait_val = 0x2,
378 .clk_dis_wait_val = 0x8,
379 .pd = {
380 .name = "gpu_cc_cx_gdsc",
381 },
382 .pwrsts = PWRSTS_OFF_ON,
383 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
384 };
385
386 static struct clk_regmap *gpu_cc_kaanapali_clocks[] = {
387 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
388 [GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr,
389 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
390 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
391 [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
392 [GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr,
393 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
394 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
395 [GPU_CC_GPU_SMMU_VOTE_CLK] = &gpu_cc_gpu_smmu_vote_clk.clkr,
396 [GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr,
397 [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
398 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
399 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
400 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
401 [GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr,
402 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
403 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
404 [GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr,
405 };
406
407 static struct gdsc *gpu_cc_kaanapali_gdscs[] = {
408 [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
409 };
410
411 static const struct qcom_reset_map gpu_cc_kaanapali_resets[] = {
412 [GPU_CC_CB_BCR] = { 0x93a0 },
413 [GPU_CC_CX_BCR] = { 0x907c },
414 [GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
415 [GPU_CC_FF_BCR] = { 0x9470 },
416 [GPU_CC_GMU_BCR] = { 0x9314 },
417 [GPU_CC_GX_BCR] = { 0x905c },
418 [GPU_CC_XO_BCR] = { 0x9000 },
419 };
420
421 static struct clk_alpha_pll *gpu_cc_kaanapali_plls[] = {
422 &gpu_cc_pll0,
423 };
424
425 static const u32 gpu_cc_kaanapali_critical_cbcrs[] = {
426 0x9008, /* GPU_CC_CXO_AON_CLK */
427 0x93e8, /* GPU_CC_RSCC_HUB_AON_CLK */
428 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */
429 };
430
431 static const struct regmap_config gpu_cc_kaanapali_regmap_config = {
432 .reg_bits = 32,
433 .reg_stride = 4,
434 .val_bits = 32,
435 .max_register = 0x95e8,
436 .fast_io = true,
437 };
438
439 static const struct qcom_cc_driver_data gpu_cc_kaanapali_driver_data = {
440 .alpha_plls = gpu_cc_kaanapali_plls,
441 .num_alpha_plls = ARRAY_SIZE(gpu_cc_kaanapali_plls),
442 .clk_cbcrs = gpu_cc_kaanapali_critical_cbcrs,
443 .num_clk_cbcrs = ARRAY_SIZE(gpu_cc_kaanapali_critical_cbcrs),
444 };
445
446 static const struct qcom_cc_desc gpu_cc_kaanapali_desc = {
447 .config = &gpu_cc_kaanapali_regmap_config,
448 .clks = gpu_cc_kaanapali_clocks,
449 .num_clks = ARRAY_SIZE(gpu_cc_kaanapali_clocks),
450 .resets = gpu_cc_kaanapali_resets,
451 .num_resets = ARRAY_SIZE(gpu_cc_kaanapali_resets),
452 .gdscs = gpu_cc_kaanapali_gdscs,
453 .num_gdscs = ARRAY_SIZE(gpu_cc_kaanapali_gdscs),
454 .use_rpm = true,
455 .driver_data = &gpu_cc_kaanapali_driver_data,
456 };
457
458 static const struct of_device_id gpu_cc_kaanapali_match_table[] = {
459 { .compatible = "qcom,kaanapali-gpucc" },
460 { }
461 };
462 MODULE_DEVICE_TABLE(of, gpu_cc_kaanapali_match_table);
463
gpu_cc_kaanapali_probe(struct platform_device * pdev)464 static int gpu_cc_kaanapali_probe(struct platform_device *pdev)
465 {
466 return qcom_cc_probe(pdev, &gpu_cc_kaanapali_desc);
467 }
468
469 static struct platform_driver gpu_cc_kaanapali_driver = {
470 .probe = gpu_cc_kaanapali_probe,
471 .driver = {
472 .name = "gpucc-kaanapali",
473 .of_match_table = gpu_cc_kaanapali_match_table,
474 },
475 };
476
477 module_platform_driver(gpu_cc_kaanapali_driver);
478
479 MODULE_DESCRIPTION("QTI GPUCC Kaanapali Driver");
480 MODULE_LICENSE("GPL");
481