1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Analog Devices AD7768-1 SPI ADC driver
4 *
5 * Copyright 2017 Analog Devices Inc.
6 */
7 #include <linux/array_size.h>
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/completion.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/err.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/sysfs.h>
20 #include <linux/spi/spi.h>
21
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/trigger.h>
26 #include <linux/iio/triggered_buffer.h>
27 #include <linux/iio/trigger_consumer.h>
28
29 /* AD7768 registers definition */
30 #define AD7768_REG_CHIP_TYPE 0x3
31 #define AD7768_REG_PROD_ID_L 0x4
32 #define AD7768_REG_PROD_ID_H 0x5
33 #define AD7768_REG_CHIP_GRADE 0x6
34 #define AD7768_REG_SCRATCH_PAD 0x0A
35 #define AD7768_REG_VENDOR_L 0x0C
36 #define AD7768_REG_VENDOR_H 0x0D
37 #define AD7768_REG_INTERFACE_FORMAT 0x14
38 #define AD7768_REG_POWER_CLOCK 0x15
39 #define AD7768_REG_ANALOG 0x16
40 #define AD7768_REG_ANALOG2 0x17
41 #define AD7768_REG_CONVERSION 0x18
42 #define AD7768_REG_DIGITAL_FILTER 0x19
43 #define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A
44 #define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B
45 #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C
46 #define AD7768_REG_SYNC_RESET 0x1D
47 #define AD7768_REG_GPIO_CONTROL 0x1E
48 #define AD7768_REG_GPIO_WRITE 0x1F
49 #define AD7768_REG_GPIO_READ 0x20
50 #define AD7768_REG_OFFSET_HI 0x21
51 #define AD7768_REG_OFFSET_MID 0x22
52 #define AD7768_REG_OFFSET_LO 0x23
53 #define AD7768_REG_GAIN_HI 0x24
54 #define AD7768_REG_GAIN_MID 0x25
55 #define AD7768_REG_GAIN_LO 0x26
56 #define AD7768_REG_SPI_DIAG_ENABLE 0x28
57 #define AD7768_REG_ADC_DIAG_ENABLE 0x29
58 #define AD7768_REG_DIG_DIAG_ENABLE 0x2A
59 #define AD7768_REG24_ADC_DATA 0x2C
60 #define AD7768_REG_MASTER_STATUS 0x2D
61 #define AD7768_REG_SPI_DIAG_STATUS 0x2E
62 #define AD7768_REG_ADC_DIAG_STATUS 0x2F
63 #define AD7768_REG_DIG_DIAG_STATUS 0x30
64 #define AD7768_REG_MCLK_COUNTER 0x31
65 #define AD7768_REG_COEFF_CONTROL 0x32
66 #define AD7768_REG24_COEFF_DATA 0x33
67 #define AD7768_REG_ACCESS_KEY 0x34
68
69 /* AD7768_REG_POWER_CLOCK */
70 #define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4)
71 #define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x)
72 #define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0)
73 #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x)
74
75 /* AD7768_REG_DIGITAL_FILTER */
76 #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4)
77 #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x)
78 #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0)
79 #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x)
80
81 /* AD7768_REG_CONVERSION */
82 #define AD7768_CONV_MODE_MSK GENMASK(2, 0)
83 #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x)
84
85 enum ad7768_conv_mode {
86 AD7768_CONTINUOUS,
87 AD7768_ONE_SHOT,
88 AD7768_SINGLE,
89 AD7768_PERIODIC,
90 AD7768_STANDBY
91 };
92
93 enum ad7768_pwrmode {
94 AD7768_ECO_MODE = 0,
95 AD7768_MED_MODE = 2,
96 AD7768_FAST_MODE = 3
97 };
98
99 enum ad7768_mclk_div {
100 AD7768_MCLK_DIV_16,
101 AD7768_MCLK_DIV_8,
102 AD7768_MCLK_DIV_4,
103 AD7768_MCLK_DIV_2
104 };
105
106 enum ad7768_dec_rate {
107 AD7768_DEC_RATE_32 = 0,
108 AD7768_DEC_RATE_64 = 1,
109 AD7768_DEC_RATE_128 = 2,
110 AD7768_DEC_RATE_256 = 3,
111 AD7768_DEC_RATE_512 = 4,
112 AD7768_DEC_RATE_1024 = 5,
113 AD7768_DEC_RATE_8 = 9,
114 AD7768_DEC_RATE_16 = 10
115 };
116
117 struct ad7768_clk_configuration {
118 enum ad7768_mclk_div mclk_div;
119 enum ad7768_dec_rate dec_rate;
120 unsigned int clk_div;
121 enum ad7768_pwrmode pwrmode;
122 };
123
124 static const struct ad7768_clk_configuration ad7768_clk_config[] = {
125 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE },
126 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE },
127 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE },
128 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE },
129 { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE },
130 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE },
131 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE },
132 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE },
133 { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE },
134 { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE },
135 { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE },
136 };
137
138 static const struct iio_chan_spec ad7768_channels[] = {
139 {
140 .type = IIO_VOLTAGE,
141 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
142 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
143 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
144 .indexed = 1,
145 .channel = 0,
146 .scan_index = 0,
147 .scan_type = {
148 .sign = 's',
149 .realbits = 24,
150 .storagebits = 32,
151 .shift = 8,
152 .endianness = IIO_BE,
153 },
154 },
155 };
156
157 struct ad7768_state {
158 struct spi_device *spi;
159 struct regmap *regmap;
160 struct regmap *regmap24;
161 struct regulator *vref;
162 struct clk *mclk;
163 unsigned int mclk_freq;
164 unsigned int samp_freq;
165 struct completion completion;
166 struct iio_trigger *trig;
167 struct gpio_desc *gpio_sync_in;
168 struct gpio_desc *gpio_reset;
169 const char *labels[ARRAY_SIZE(ad7768_channels)];
170 /*
171 * DMA (thus cache coherency maintenance) may require the
172 * transfer buffers to live in their own cache lines.
173 */
174 union {
175 struct {
176 __be32 chan;
177 aligned_s64 timestamp;
178 } scan;
179 __be32 d32;
180 u8 d8[2];
181 } data __aligned(IIO_DMA_MINALIGN);
182 };
183
184 static const struct regmap_range ad7768_regmap_rd_ranges[] = {
185 regmap_reg_range(AD7768_REG_CHIP_TYPE, AD7768_REG_CHIP_GRADE),
186 regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD),
187 regmap_reg_range(AD7768_REG_VENDOR_L, AD7768_REG_VENDOR_H),
188 regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GAIN_LO),
189 regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE),
190 regmap_reg_range(AD7768_REG_MASTER_STATUS, AD7768_REG_COEFF_CONTROL),
191 regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY),
192 };
193
194 static const struct regmap_access_table ad7768_regmap_rd_table = {
195 .yes_ranges = ad7768_regmap_rd_ranges,
196 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap_rd_ranges),
197 };
198
199 static const struct regmap_range ad7768_regmap_wr_ranges[] = {
200 regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD),
201 regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GPIO_WRITE),
202 regmap_reg_range(AD7768_REG_OFFSET_HI, AD7768_REG_GAIN_LO),
203 regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE),
204 regmap_reg_range(AD7768_REG_SPI_DIAG_STATUS, AD7768_REG_SPI_DIAG_STATUS),
205 regmap_reg_range(AD7768_REG_COEFF_CONTROL, AD7768_REG_COEFF_CONTROL),
206 regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY),
207 };
208
209 static const struct regmap_access_table ad7768_regmap_wr_table = {
210 .yes_ranges = ad7768_regmap_wr_ranges,
211 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap_wr_ranges),
212 };
213
214 static const struct regmap_config ad7768_regmap_config = {
215 .name = "ad7768-1-8",
216 .reg_bits = 8,
217 .val_bits = 8,
218 .read_flag_mask = BIT(6),
219 .rd_table = &ad7768_regmap_rd_table,
220 .wr_table = &ad7768_regmap_wr_table,
221 .max_register = AD7768_REG_ACCESS_KEY,
222 .use_single_write = true,
223 .use_single_read = true,
224 };
225
226 static const struct regmap_range ad7768_regmap24_rd_ranges[] = {
227 regmap_reg_range(AD7768_REG24_ADC_DATA, AD7768_REG24_ADC_DATA),
228 regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA),
229 };
230
231 static const struct regmap_access_table ad7768_regmap24_rd_table = {
232 .yes_ranges = ad7768_regmap24_rd_ranges,
233 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_rd_ranges),
234 };
235
236 static const struct regmap_range ad7768_regmap24_wr_ranges[] = {
237 regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA),
238 };
239
240 static const struct regmap_access_table ad7768_regmap24_wr_table = {
241 .yes_ranges = ad7768_regmap24_wr_ranges,
242 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_wr_ranges),
243 };
244
245 static const struct regmap_config ad7768_regmap24_config = {
246 .name = "ad7768-1-24",
247 .reg_bits = 8,
248 .val_bits = 24,
249 .read_flag_mask = BIT(6),
250 .rd_table = &ad7768_regmap24_rd_table,
251 .wr_table = &ad7768_regmap24_wr_table,
252 .max_register = AD7768_REG24_COEFF_DATA,
253 };
254
ad7768_set_mode(struct ad7768_state * st,enum ad7768_conv_mode mode)255 static int ad7768_set_mode(struct ad7768_state *st,
256 enum ad7768_conv_mode mode)
257 {
258 return regmap_update_bits(st->regmap, AD7768_REG_CONVERSION,
259 AD7768_CONV_MODE_MSK, AD7768_CONV_MODE(mode));
260 }
261
ad7768_scan_direct(struct iio_dev * indio_dev)262 static int ad7768_scan_direct(struct iio_dev *indio_dev)
263 {
264 struct ad7768_state *st = iio_priv(indio_dev);
265 int readval, ret;
266
267 reinit_completion(&st->completion);
268
269 ret = ad7768_set_mode(st, AD7768_ONE_SHOT);
270 if (ret < 0)
271 return ret;
272
273 ret = wait_for_completion_timeout(&st->completion,
274 msecs_to_jiffies(1000));
275 if (!ret)
276 return -ETIMEDOUT;
277
278 ret = regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &readval);
279 if (ret)
280 return ret;
281
282 /*
283 * Any SPI configuration of the AD7768-1 can only be
284 * performed in continuous conversion mode.
285 */
286 ret = ad7768_set_mode(st, AD7768_CONTINUOUS);
287 if (ret < 0)
288 return ret;
289
290 return readval;
291 }
292
ad7768_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)293 static int ad7768_reg_access(struct iio_dev *indio_dev,
294 unsigned int reg,
295 unsigned int writeval,
296 unsigned int *readval)
297 {
298 struct ad7768_state *st = iio_priv(indio_dev);
299 int ret;
300
301 if (!iio_device_claim_direct(indio_dev))
302 return -EBUSY;
303
304 ret = -EINVAL;
305 if (readval) {
306 if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_rd_table))
307 ret = regmap_read(st->regmap, reg, readval);
308
309 if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_rd_table))
310 ret = regmap_read(st->regmap24, reg, readval);
311
312 } else {
313 if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_wr_table))
314 ret = regmap_write(st->regmap, reg, writeval);
315
316 if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_wr_table))
317 ret = regmap_write(st->regmap24, reg, writeval);
318
319 }
320
321 iio_device_release_direct(indio_dev);
322
323 return ret;
324 }
325
ad7768_set_dig_fil(struct ad7768_state * st,enum ad7768_dec_rate dec_rate)326 static int ad7768_set_dig_fil(struct ad7768_state *st,
327 enum ad7768_dec_rate dec_rate)
328 {
329 unsigned int mode;
330 int ret;
331
332 if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16)
333 mode = AD7768_DIG_FIL_FIL(dec_rate);
334 else
335 mode = AD7768_DIG_FIL_DEC_RATE(dec_rate);
336
337 ret = regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, mode);
338 if (ret < 0)
339 return ret;
340
341 /* A sync-in pulse is required every time the filter dec rate changes */
342 gpiod_set_value(st->gpio_sync_in, 1);
343 gpiod_set_value(st->gpio_sync_in, 0);
344
345 return 0;
346 }
347
ad7768_set_freq(struct ad7768_state * st,unsigned int freq)348 static int ad7768_set_freq(struct ad7768_state *st,
349 unsigned int freq)
350 {
351 unsigned int diff_new, diff_old, pwr_mode, i, idx;
352 int res, ret;
353
354 diff_old = U32_MAX;
355 idx = 0;
356
357 res = DIV_ROUND_CLOSEST(st->mclk_freq, freq);
358
359 /* Find the closest match for the desired sampling frequency */
360 for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
361 diff_new = abs(res - ad7768_clk_config[i].clk_div);
362 if (diff_new < diff_old) {
363 diff_old = diff_new;
364 idx = i;
365 }
366 }
367
368 /*
369 * Set both the mclk_div and pwrmode with a single write to the
370 * POWER_CLOCK register
371 */
372 pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) |
373 AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode);
374 ret = regmap_write(st->regmap, AD7768_REG_POWER_CLOCK, pwr_mode);
375 if (ret < 0)
376 return ret;
377
378 ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate);
379 if (ret < 0)
380 return ret;
381
382 st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq,
383 ad7768_clk_config[idx].clk_div);
384
385 return 0;
386 }
387
ad7768_sampling_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)388 static ssize_t ad7768_sampling_freq_avail(struct device *dev,
389 struct device_attribute *attr,
390 char *buf)
391 {
392 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
393 struct ad7768_state *st = iio_priv(indio_dev);
394 unsigned int freq;
395 int i, len = 0;
396
397 for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
398 freq = DIV_ROUND_CLOSEST(st->mclk_freq,
399 ad7768_clk_config[i].clk_div);
400 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq);
401 }
402
403 buf[len - 1] = '\n';
404
405 return len;
406 }
407
408 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail);
409
ad7768_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)410 static int ad7768_read_raw(struct iio_dev *indio_dev,
411 struct iio_chan_spec const *chan,
412 int *val, int *val2, long info)
413 {
414 struct ad7768_state *st = iio_priv(indio_dev);
415 int scale_uv, ret;
416
417 switch (info) {
418 case IIO_CHAN_INFO_RAW:
419 if (!iio_device_claim_direct(indio_dev))
420 return -EBUSY;
421
422 ret = ad7768_scan_direct(indio_dev);
423
424 iio_device_release_direct(indio_dev);
425 if (ret < 0)
426 return ret;
427 *val = sign_extend32(ret, chan->scan_type.realbits - 1);
428
429 return IIO_VAL_INT;
430
431 case IIO_CHAN_INFO_SCALE:
432 scale_uv = regulator_get_voltage(st->vref);
433 if (scale_uv < 0)
434 return scale_uv;
435
436 *val = (scale_uv * 2) / 1000;
437 *val2 = chan->scan_type.realbits;
438
439 return IIO_VAL_FRACTIONAL_LOG2;
440
441 case IIO_CHAN_INFO_SAMP_FREQ:
442 *val = st->samp_freq;
443
444 return IIO_VAL_INT;
445 }
446
447 return -EINVAL;
448 }
449
ad7768_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)450 static int ad7768_write_raw(struct iio_dev *indio_dev,
451 struct iio_chan_spec const *chan,
452 int val, int val2, long info)
453 {
454 struct ad7768_state *st = iio_priv(indio_dev);
455
456 switch (info) {
457 case IIO_CHAN_INFO_SAMP_FREQ:
458 return ad7768_set_freq(st, val);
459 default:
460 return -EINVAL;
461 }
462 }
463
ad7768_read_label(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,char * label)464 static int ad7768_read_label(struct iio_dev *indio_dev,
465 const struct iio_chan_spec *chan, char *label)
466 {
467 struct ad7768_state *st = iio_priv(indio_dev);
468
469 return sprintf(label, "%s\n", st->labels[chan->channel]);
470 }
471
472 static struct attribute *ad7768_attributes[] = {
473 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
474 NULL
475 };
476
477 static const struct attribute_group ad7768_group = {
478 .attrs = ad7768_attributes,
479 };
480
481 static const struct iio_info ad7768_info = {
482 .attrs = &ad7768_group,
483 .read_raw = &ad7768_read_raw,
484 .write_raw = &ad7768_write_raw,
485 .read_label = ad7768_read_label,
486 .debugfs_reg_access = &ad7768_reg_access,
487 };
488
ad7768_setup(struct ad7768_state * st)489 static int ad7768_setup(struct ad7768_state *st)
490 {
491 int ret;
492
493 st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
494 GPIOD_OUT_HIGH);
495 if (IS_ERR(st->gpio_reset))
496 return PTR_ERR(st->gpio_reset);
497
498 if (st->gpio_reset) {
499 fsleep(10);
500 gpiod_set_value_cansleep(st->gpio_reset, 0);
501 fsleep(200);
502 } else {
503 /*
504 * Two writes to the SPI_RESET[1:0] bits are required to initiate
505 * a software reset. The bits must first be set to 11, and then
506 * to 10. When the sequence is detected, the reset occurs.
507 * See the datasheet, page 70.
508 */
509 ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x3);
510 if (ret)
511 return ret;
512
513 ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x2);
514 if (ret)
515 return ret;
516 }
517
518 st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in",
519 GPIOD_OUT_LOW);
520 if (IS_ERR(st->gpio_sync_in))
521 return PTR_ERR(st->gpio_sync_in);
522
523 /* Set the default sampling frequency to 32000 kSPS */
524 return ad7768_set_freq(st, 32000);
525 }
526
ad7768_trigger_handler(int irq,void * p)527 static irqreturn_t ad7768_trigger_handler(int irq, void *p)
528 {
529 struct iio_poll_func *pf = p;
530 struct iio_dev *indio_dev = pf->indio_dev;
531 struct ad7768_state *st = iio_priv(indio_dev);
532 int ret;
533
534 ret = spi_read(st->spi, &st->data.scan.chan, 3);
535 if (ret < 0)
536 goto out;
537
538 iio_push_to_buffers_with_ts(indio_dev, &st->data.scan,
539 sizeof(st->data.scan),
540 iio_get_time_ns(indio_dev));
541
542 out:
543 iio_trigger_notify_done(indio_dev->trig);
544
545 return IRQ_HANDLED;
546 }
547
ad7768_interrupt(int irq,void * dev_id)548 static irqreturn_t ad7768_interrupt(int irq, void *dev_id)
549 {
550 struct iio_dev *indio_dev = dev_id;
551 struct ad7768_state *st = iio_priv(indio_dev);
552
553 if (iio_buffer_enabled(indio_dev))
554 iio_trigger_poll(st->trig);
555 else
556 complete(&st->completion);
557
558 return IRQ_HANDLED;
559 };
560
ad7768_buffer_postenable(struct iio_dev * indio_dev)561 static int ad7768_buffer_postenable(struct iio_dev *indio_dev)
562 {
563 struct ad7768_state *st = iio_priv(indio_dev);
564
565 /*
566 * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter
567 * continuous read mode. Subsequent data reads do not require an
568 * initial 8-bit write to query the ADC_DATA register.
569 */
570 return regmap_write(st->regmap, AD7768_REG_INTERFACE_FORMAT, 0x01);
571 }
572
ad7768_buffer_predisable(struct iio_dev * indio_dev)573 static int ad7768_buffer_predisable(struct iio_dev *indio_dev)
574 {
575 struct ad7768_state *st = iio_priv(indio_dev);
576 unsigned int unused;
577
578 /*
579 * To exit continuous read mode, perform a single read of the ADC_DATA
580 * reg (0x2C), which allows further configuration of the device.
581 */
582 return regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &unused);
583 }
584
585 static const struct iio_buffer_setup_ops ad7768_buffer_ops = {
586 .postenable = &ad7768_buffer_postenable,
587 .predisable = &ad7768_buffer_predisable,
588 };
589
590 static const struct iio_trigger_ops ad7768_trigger_ops = {
591 .validate_device = iio_trigger_validate_own_device,
592 };
593
ad7768_regulator_disable(void * data)594 static void ad7768_regulator_disable(void *data)
595 {
596 struct ad7768_state *st = data;
597
598 regulator_disable(st->vref);
599 }
600
ad7768_set_channel_label(struct iio_dev * indio_dev,int num_channels)601 static int ad7768_set_channel_label(struct iio_dev *indio_dev,
602 int num_channels)
603 {
604 struct ad7768_state *st = iio_priv(indio_dev);
605 struct device *device = indio_dev->dev.parent;
606 const char *label;
607 int crt_ch = 0;
608
609 device_for_each_child_node_scoped(device, child) {
610 if (fwnode_property_read_u32(child, "reg", &crt_ch))
611 continue;
612
613 if (crt_ch >= num_channels)
614 continue;
615
616 if (fwnode_property_read_string(child, "label", &label))
617 continue;
618
619 st->labels[crt_ch] = label;
620 }
621
622 return 0;
623 }
624
ad7768_triggered_buffer_alloc(struct iio_dev * indio_dev)625 static int ad7768_triggered_buffer_alloc(struct iio_dev *indio_dev)
626 {
627 struct ad7768_state *st = iio_priv(indio_dev);
628 int ret;
629
630 st->trig = devm_iio_trigger_alloc(indio_dev->dev.parent, "%s-dev%d",
631 indio_dev->name,
632 iio_device_id(indio_dev));
633 if (!st->trig)
634 return -ENOMEM;
635
636 st->trig->ops = &ad7768_trigger_ops;
637 iio_trigger_set_drvdata(st->trig, indio_dev);
638 ret = devm_iio_trigger_register(indio_dev->dev.parent, st->trig);
639 if (ret)
640 return ret;
641
642 indio_dev->trig = iio_trigger_get(st->trig);
643
644 return devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev,
645 &iio_pollfunc_store_time,
646 &ad7768_trigger_handler,
647 &ad7768_buffer_ops);
648 }
649
ad7768_probe(struct spi_device * spi)650 static int ad7768_probe(struct spi_device *spi)
651 {
652 struct ad7768_state *st;
653 struct iio_dev *indio_dev;
654 int ret;
655
656 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
657 if (!indio_dev)
658 return -ENOMEM;
659
660 st = iio_priv(indio_dev);
661 /*
662 * Datasheet recommends SDI line to be kept high when data is not being
663 * clocked out of the controller and the spi clock is free running,
664 * to prevent accidental reset.
665 * Since many controllers do not support the SPI_MOSI_IDLE_HIGH flag
666 * yet, only request the MOSI idle state to enable if the controller
667 * supports it.
668 */
669 if (spi->controller->mode_bits & SPI_MOSI_IDLE_HIGH) {
670 spi->mode |= SPI_MOSI_IDLE_HIGH;
671 ret = spi_setup(spi);
672 if (ret < 0)
673 return ret;
674 }
675
676 st->spi = spi;
677
678 st->regmap = devm_regmap_init_spi(spi, &ad7768_regmap_config);
679 if (IS_ERR(st->regmap))
680 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap),
681 "Failed to initialize regmap");
682
683 st->regmap24 = devm_regmap_init_spi(spi, &ad7768_regmap24_config);
684 if (IS_ERR(st->regmap24))
685 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap24),
686 "Failed to initialize regmap24");
687
688 st->vref = devm_regulator_get(&spi->dev, "vref");
689 if (IS_ERR(st->vref))
690 return PTR_ERR(st->vref);
691
692 ret = regulator_enable(st->vref);
693 if (ret) {
694 dev_err(&spi->dev, "Failed to enable specified vref supply\n");
695 return ret;
696 }
697
698 ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st);
699 if (ret)
700 return ret;
701
702 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
703 if (IS_ERR(st->mclk))
704 return PTR_ERR(st->mclk);
705
706 st->mclk_freq = clk_get_rate(st->mclk);
707
708 indio_dev->channels = ad7768_channels;
709 indio_dev->num_channels = ARRAY_SIZE(ad7768_channels);
710 indio_dev->name = spi_get_device_id(spi)->name;
711 indio_dev->info = &ad7768_info;
712 indio_dev->modes = INDIO_DIRECT_MODE;
713
714 ret = ad7768_setup(st);
715 if (ret < 0) {
716 dev_err(&spi->dev, "AD7768 setup failed\n");
717 return ret;
718 }
719
720 init_completion(&st->completion);
721
722 ret = ad7768_set_channel_label(indio_dev, ARRAY_SIZE(ad7768_channels));
723 if (ret)
724 return ret;
725
726 ret = devm_request_irq(&spi->dev, spi->irq,
727 &ad7768_interrupt,
728 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
729 indio_dev->name, indio_dev);
730 if (ret)
731 return ret;
732
733 ret = ad7768_triggered_buffer_alloc(indio_dev);
734 if (ret)
735 return ret;
736
737 return devm_iio_device_register(&spi->dev, indio_dev);
738 }
739
740 static const struct spi_device_id ad7768_id_table[] = {
741 { "ad7768-1", 0 },
742 { }
743 };
744 MODULE_DEVICE_TABLE(spi, ad7768_id_table);
745
746 static const struct of_device_id ad7768_of_match[] = {
747 { .compatible = "adi,ad7768-1" },
748 { }
749 };
750 MODULE_DEVICE_TABLE(of, ad7768_of_match);
751
752 static struct spi_driver ad7768_driver = {
753 .driver = {
754 .name = "ad7768-1",
755 .of_match_table = ad7768_of_match,
756 },
757 .probe = ad7768_probe,
758 .id_table = ad7768_id_table,
759 };
760 module_spi_driver(ad7768_driver);
761
762 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
763 MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver");
764 MODULE_LICENSE("GPL v2");
765