1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * gpio-reg: single register individually fixed-direction GPIOs
4 *
5 * Copyright (C) 2016 Russell King
6 */
7 #include <linux/bits.h>
8 #include <linux/container_of.h>
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/errno.h>
12 #include <linux/io.h>
13 #include <linux/irqdomain.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 #include <linux/types.h>
17
18 #include <linux/gpio/driver.h>
19 #include <linux/gpio/gpio-reg.h>
20
21 struct gpio_reg {
22 struct gpio_chip gc;
23 spinlock_t lock;
24 u32 direction;
25 u32 out;
26 void __iomem *reg;
27 struct irq_domain *irqdomain;
28 const int *irqs;
29 };
30
31 #define to_gpio_reg(x) container_of(x, struct gpio_reg, gc)
32
gpio_reg_get_direction(struct gpio_chip * gc,unsigned offset)33 static int gpio_reg_get_direction(struct gpio_chip *gc, unsigned offset)
34 {
35 struct gpio_reg *r = to_gpio_reg(gc);
36
37 return r->direction & BIT(offset) ? GPIO_LINE_DIRECTION_IN :
38 GPIO_LINE_DIRECTION_OUT;
39 }
40
gpio_reg_direction_output(struct gpio_chip * gc,unsigned offset,int value)41 static int gpio_reg_direction_output(struct gpio_chip *gc, unsigned offset,
42 int value)
43 {
44 struct gpio_reg *r = to_gpio_reg(gc);
45
46 if (r->direction & BIT(offset))
47 return -ENOTSUPP;
48
49 gc->set(gc, offset, value);
50 return 0;
51 }
52
gpio_reg_direction_input(struct gpio_chip * gc,unsigned offset)53 static int gpio_reg_direction_input(struct gpio_chip *gc, unsigned offset)
54 {
55 struct gpio_reg *r = to_gpio_reg(gc);
56
57 return r->direction & BIT(offset) ? 0 : -ENOTSUPP;
58 }
59
gpio_reg_set(struct gpio_chip * gc,unsigned int offset,int value)60 static int gpio_reg_set(struct gpio_chip *gc, unsigned int offset, int value)
61 {
62 struct gpio_reg *r = to_gpio_reg(gc);
63 unsigned long flags;
64 u32 val, mask = BIT(offset);
65
66 spin_lock_irqsave(&r->lock, flags);
67 val = r->out;
68 if (value)
69 val |= mask;
70 else
71 val &= ~mask;
72 r->out = val;
73 writel_relaxed(val, r->reg);
74 spin_unlock_irqrestore(&r->lock, flags);
75
76 return 0;
77 }
78
gpio_reg_get(struct gpio_chip * gc,unsigned offset)79 static int gpio_reg_get(struct gpio_chip *gc, unsigned offset)
80 {
81 struct gpio_reg *r = to_gpio_reg(gc);
82 u32 val, mask = BIT(offset);
83
84 if (r->direction & mask) {
85 /*
86 * double-read the value, some registers latch after the
87 * first read.
88 */
89 readl_relaxed(r->reg);
90 val = readl_relaxed(r->reg);
91 } else {
92 val = r->out;
93 }
94 return !!(val & mask);
95 }
96
gpio_reg_set_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)97 static int gpio_reg_set_multiple(struct gpio_chip *gc, unsigned long *mask,
98 unsigned long *bits)
99 {
100 struct gpio_reg *r = to_gpio_reg(gc);
101 unsigned long flags;
102
103 spin_lock_irqsave(&r->lock, flags);
104 r->out = (r->out & ~*mask) | (*bits & *mask);
105 writel_relaxed(r->out, r->reg);
106 spin_unlock_irqrestore(&r->lock, flags);
107
108 return 0;
109 }
110
gpio_reg_to_irq(struct gpio_chip * gc,unsigned offset)111 static int gpio_reg_to_irq(struct gpio_chip *gc, unsigned offset)
112 {
113 struct gpio_reg *r = to_gpio_reg(gc);
114 int irq = r->irqs[offset];
115
116 if (irq >= 0 && r->irqdomain)
117 irq = irq_find_mapping(r->irqdomain, irq);
118
119 return irq;
120 }
121
122 /**
123 * gpio_reg_init - add a fixed in/out register as gpio
124 * @dev: optional struct device associated with this register
125 * @base: start gpio number, or -1 to allocate
126 * @num: number of GPIOs, maximum 32
127 * @label: GPIO chip label
128 * @direction: bitmask of fixed direction, one per GPIO signal, 1 = in
129 * @def_out: initial GPIO output value
130 * @names: array of %num strings describing each GPIO signal or %NULL
131 * @irqdom: irq domain or %NULL
132 * @irqs: array of %num ints describing the interrupt mapping for each
133 * GPIO signal, or %NULL. If @irqdom is %NULL, then this
134 * describes the Linux interrupt number, otherwise it describes
135 * the hardware interrupt number in the specified irq domain.
136 *
137 * Add a single-register GPIO device containing up to 32 GPIO signals,
138 * where each GPIO has a fixed input or output configuration. Only
139 * input GPIOs are assumed to be readable from the register, and only
140 * then after a double-read. Output values are assumed not to be
141 * readable.
142 */
gpio_reg_init(struct device * dev,void __iomem * reg,int base,int num,const char * label,u32 direction,u32 def_out,const char * const * names,struct irq_domain * irqdom,const int * irqs)143 struct gpio_chip *gpio_reg_init(struct device *dev, void __iomem *reg,
144 int base, int num, const char *label, u32 direction, u32 def_out,
145 const char *const *names, struct irq_domain *irqdom, const int *irqs)
146 {
147 struct gpio_reg *r;
148 int ret;
149
150 if (dev)
151 r = devm_kzalloc(dev, sizeof(*r), GFP_KERNEL);
152 else
153 r = kzalloc(sizeof(*r), GFP_KERNEL);
154
155 if (!r)
156 return ERR_PTR(-ENOMEM);
157
158 spin_lock_init(&r->lock);
159
160 r->gc.label = label;
161 r->gc.get_direction = gpio_reg_get_direction;
162 r->gc.direction_input = gpio_reg_direction_input;
163 r->gc.direction_output = gpio_reg_direction_output;
164 r->gc.set = gpio_reg_set;
165 r->gc.get = gpio_reg_get;
166 r->gc.set_multiple = gpio_reg_set_multiple;
167 if (irqs)
168 r->gc.to_irq = gpio_reg_to_irq;
169 r->gc.base = base;
170 r->gc.ngpio = num;
171 r->gc.names = names;
172 r->direction = direction;
173 r->out = def_out;
174 r->reg = reg;
175 r->irqs = irqs;
176
177 if (dev)
178 ret = devm_gpiochip_add_data(dev, &r->gc, r);
179 else
180 ret = gpiochip_add_data(&r->gc, r);
181
182 return ret ? ERR_PTR(ret) : &r->gc;
183 }
184
gpio_reg_resume(struct gpio_chip * gc)185 int gpio_reg_resume(struct gpio_chip *gc)
186 {
187 struct gpio_reg *r = to_gpio_reg(gc);
188 unsigned long flags;
189
190 spin_lock_irqsave(&r->lock, flags);
191 writel_relaxed(r->out, r->reg);
192 spin_unlock_irqrestore(&r->lock, flags);
193
194 return 0;
195 }
196