1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #ifndef _TXGBE_TYPE_H_ 5 #define _TXGBE_TYPE_H_ 6 7 #include <linux/property.h> 8 #include <linux/irq.h> 9 #include <linux/phy.h> 10 #include "../libwx/wx_type.h" 11 12 /* Device IDs */ 13 #define TXGBE_DEV_ID_SP1000 0x1001 14 #define TXGBE_DEV_ID_WX1820 0x2001 15 #define TXGBE_DEV_ID_AML5010 0x5010 16 #define TXGBE_DEV_ID_AML5110 0x5110 17 #define TXGBE_DEV_ID_AML5025 0x5025 18 #define TXGBE_DEV_ID_AML5125 0x5125 19 #define TXGBE_DEV_ID_AML5040 0x5040 20 #define TXGBE_DEV_ID_AML5140 0x5140 21 22 /* Subsystem IDs */ 23 /* SFP */ 24 #define TXGBE_ID_SP1000_SFP 0x0000 25 #define TXGBE_ID_WX1820_SFP 0x2000 26 #define TXGBE_ID_SFP 0x00 27 28 /* copper */ 29 #define TXGBE_ID_SP1000_XAUI 0x1010 30 #define TXGBE_ID_WX1820_XAUI 0x2010 31 #define TXGBE_ID_XAUI 0x10 32 #define TXGBE_ID_SP1000_SGMII 0x1020 33 #define TXGBE_ID_WX1820_SGMII 0x2020 34 #define TXGBE_ID_SGMII 0x20 35 /* backplane */ 36 #define TXGBE_ID_SP1000_KR_KX_KX4 0x1030 37 #define TXGBE_ID_WX1820_KR_KX_KX4 0x2030 38 #define TXGBE_ID_KR_KX_KX4 0x30 39 /* MAC Interface */ 40 #define TXGBE_ID_SP1000_MAC_XAUI 0x1040 41 #define TXGBE_ID_WX1820_MAC_XAUI 0x2040 42 #define TXGBE_ID_MAC_XAUI 0x40 43 #define TXGBE_ID_SP1000_MAC_SGMII 0x1060 44 #define TXGBE_ID_WX1820_MAC_SGMII 0x2060 45 #define TXGBE_ID_MAC_SGMII 0x60 46 47 /* Combined interface*/ 48 #define TXGBE_ID_SFI_XAUI 0x50 49 50 /* Revision ID */ 51 #define TXGBE_SP_MPW 1 52 53 /**************** SP Registers ****************************/ 54 /* chip control Registers */ 55 #define TXGBE_MIS_RST 0x1000C 56 #define TXGBE_MIS_RST_MAC_RST(_i) BIT(20 - (_i) * 3) 57 #define TXGBE_MIS_PRB_CTL 0x10010 58 #define TXGBE_MIS_PRB_CTL_LAN_UP(_i) BIT(1 - (_i)) 59 /* FMGR Registers */ 60 #define TXGBE_SPI_ILDR_STATUS 0x10120 61 #define TXGBE_SPI_ILDR_STATUS_PERST BIT(0) /* PCIE_PERST is done */ 62 #define TXGBE_SPI_ILDR_STATUS_PWRRST BIT(1) /* Power on reset is done */ 63 #define TXGBE_SPI_ILDR_STATUS_LAN_SW_RST(_i) BIT((_i) + 9) /* lan soft reset done */ 64 65 /* Sensors for PVT(Process Voltage Temperature) */ 66 #define TXGBE_TS_CTL 0x10300 67 #define TXGBE_TS_CTL_EVAL_MD BIT(31) 68 69 /* MAC Misc Registers */ 70 #define TXGBE_MAC_MISC_CTL 0x11F00 71 #define TXGBE_MAC_MISC_CTL_LINK_STS_MOD BIT(0) 72 #define TXGBE_MAC_MISC_CTL_LINK_PCS FIELD_PREP(BIT(0), 0) 73 #define TXGBE_MAC_MISC_CTL_LINK_BOTH FIELD_PREP(BIT(0), 1) 74 /* GPIO register bit */ 75 #define TXGBE_GPIOBIT_0 BIT(0) /* I:tx fault */ 76 #define TXGBE_GPIOBIT_1 BIT(1) /* O:tx disabled */ 77 #define TXGBE_GPIOBIT_2 BIT(2) /* I:sfp module absent */ 78 #define TXGBE_GPIOBIT_3 BIT(3) /* I:rx signal lost */ 79 #define TXGBE_GPIOBIT_4 BIT(4) /* O:rate select, 1G(0) 10G(1) */ 80 #define TXGBE_GPIOBIT_5 BIT(5) /* O:rate select, 1G(0) 10G(1) */ 81 82 /* Extended Interrupt Enable Set */ 83 #define TXGBE_PX_MISC_ETH_LKDN BIT(8) 84 #define TXGBE_PX_MISC_DEV_RST BIT(10) 85 #define TXGBE_PX_MISC_IC_TIMESYNC BIT(11) 86 #define TXGBE_PX_MISC_ETH_EVENT BIT(17) 87 #define TXGBE_PX_MISC_ETH_LK BIT(18) 88 #define TXGBE_PX_MISC_ETH_AN BIT(19) 89 #define TXGBE_PX_MISC_INT_ERR BIT(20) 90 #define TXGBE_PX_MISC_IC_VF_MBOX BIT(23) 91 #define TXGBE_PX_MISC_GPIO BIT(26) 92 #define TXGBE_PX_MISC_IEN_MASK \ 93 (TXGBE_PX_MISC_ETH_LKDN | TXGBE_PX_MISC_DEV_RST | \ 94 TXGBE_PX_MISC_ETH_EVENT | TXGBE_PX_MISC_ETH_LK | \ 95 TXGBE_PX_MISC_ETH_AN | TXGBE_PX_MISC_INT_ERR | \ 96 TXGBE_PX_MISC_IC_VF_MBOX | TXGBE_PX_MISC_IC_TIMESYNC) 97 98 /* Port cfg registers */ 99 #define TXGBE_CFG_PORT_ST 0x14404 100 #define TXGBE_CFG_PORT_ST_LINK_UP BIT(0) 101 #define TXGBE_CFG_PORT_ST_LINK_AML_25G BIT(3) 102 #define TXGBE_CFG_PORT_ST_LINK_AML_10G BIT(4) 103 #define TXGBE_CFG_VXLAN 0x14410 104 #define TXGBE_CFG_VXLAN_GPE 0x14414 105 #define TXGBE_CFG_GENEVE 0x14418 106 107 /* I2C registers */ 108 #define TXGBE_I2C_BASE 0x14900 109 110 /************************************** ETH PHY ******************************/ 111 #define TXGBE_XPCS_IDA_ADDR 0x13000 112 #define TXGBE_XPCS_IDA_DATA 0x13004 113 114 /********************************* Flow Director *****************************/ 115 #define TXGBE_RDB_FDIR_DROP_QUEUE 127 116 #define TXGBE_RDB_FDIR_CTL 0x19500 117 #define TXGBE_RDB_FDIR_CTL_INIT_DONE BIT(3) 118 #define TXGBE_RDB_FDIR_CTL_PERFECT_MATCH BIT(4) 119 #define TXGBE_RDB_FDIR_CTL_DROP_Q(v) FIELD_PREP(GENMASK(14, 8), v) 120 #define TXGBE_RDB_FDIR_CTL_HASH_BITS(v) FIELD_PREP(GENMASK(23, 20), v) 121 #define TXGBE_RDB_FDIR_CTL_MAX_LENGTH(v) FIELD_PREP(GENMASK(27, 24), v) 122 #define TXGBE_RDB_FDIR_CTL_FULL_THRESH(v) FIELD_PREP(GENMASK(31, 28), v) 123 #define TXGBE_RDB_FDIR_IP6(_i) (0x1950C + ((_i) * 4)) /* 0-2 */ 124 #define TXGBE_RDB_FDIR_SA 0x19518 125 #define TXGBE_RDB_FDIR_DA 0x1951C 126 #define TXGBE_RDB_FDIR_PORT 0x19520 127 #define TXGBE_RDB_FDIR_PORT_DESTINATION_SHIFT 16 128 #define TXGBE_RDB_FDIR_FLEX 0x19524 129 #define TXGBE_RDB_FDIR_FLEX_FLEX_SHIFT 16 130 #define TXGBE_RDB_FDIR_HASH 0x19528 131 #define TXGBE_RDB_FDIR_HASH_SIG_SW_INDEX(v) FIELD_PREP(GENMASK(31, 16), v) 132 #define TXGBE_RDB_FDIR_HASH_BUCKET_VALID BIT(15) 133 #define TXGBE_RDB_FDIR_CMD 0x1952C 134 #define TXGBE_RDB_FDIR_CMD_CMD_MASK GENMASK(1, 0) 135 #define TXGBE_RDB_FDIR_CMD_CMD(v) FIELD_PREP(GENMASK(1, 0), v) 136 #define TXGBE_RDB_FDIR_CMD_CMD_ADD_FLOW TXGBE_RDB_FDIR_CMD_CMD(1) 137 #define TXGBE_RDB_FDIR_CMD_CMD_REMOVE_FLOW TXGBE_RDB_FDIR_CMD_CMD(2) 138 #define TXGBE_RDB_FDIR_CMD_CMD_QUERY_REM_FILT TXGBE_RDB_FDIR_CMD_CMD(3) 139 #define TXGBE_RDB_FDIR_CMD_FILTER_VALID BIT(2) 140 #define TXGBE_RDB_FDIR_CMD_FILTER_UPDATE BIT(3) 141 #define TXGBE_RDB_FDIR_CMD_FLOW_TYPE(v) FIELD_PREP(GENMASK(6, 5), v) 142 #define TXGBE_RDB_FDIR_CMD_DROP BIT(9) 143 #define TXGBE_RDB_FDIR_CMD_LAST BIT(11) 144 #define TXGBE_RDB_FDIR_CMD_QUEUE_EN BIT(15) 145 #define TXGBE_RDB_FDIR_CMD_RX_QUEUE(v) FIELD_PREP(GENMASK(22, 16), v) 146 #define TXGBE_RDB_FDIR_CMD_VT_POOL(v) FIELD_PREP(GENMASK(29, 24), v) 147 #define TXGBE_RDB_FDIR_DA4_MSK 0x1953C 148 #define TXGBE_RDB_FDIR_SA4_MSK 0x19540 149 #define TXGBE_RDB_FDIR_TCP_MSK 0x19544 150 #define TXGBE_RDB_FDIR_UDP_MSK 0x19548 151 #define TXGBE_RDB_FDIR_SCTP_MSK 0x19560 152 #define TXGBE_RDB_FDIR_HKEY 0x19568 153 #define TXGBE_RDB_FDIR_SKEY 0x1956C 154 #define TXGBE_RDB_FDIR_OTHER_MSK 0x19570 155 #define TXGBE_RDB_FDIR_OTHER_MSK_POOL BIT(2) 156 #define TXGBE_RDB_FDIR_OTHER_MSK_L4P BIT(3) 157 #define TXGBE_RDB_FDIR_FLEX_CFG(_i) (0x19580 + ((_i) * 4)) 158 #define TXGBE_RDB_FDIR_FLEX_CFG_FIELD0 GENMASK(7, 0) 159 #define TXGBE_RDB_FDIR_FLEX_CFG_BASE_MAC FIELD_PREP(GENMASK(1, 0), 0) 160 #define TXGBE_RDB_FDIR_FLEX_CFG_MSK BIT(2) 161 #define TXGBE_RDB_FDIR_FLEX_CFG_OFST(v) FIELD_PREP(GENMASK(7, 3), v) 162 163 /*************************** Amber Lite Registers ****************************/ 164 #define TXGBE_PX_PF_BME 0x4B8 165 #define TXGBE_AML_MAC_TX_CFG 0x11000 166 #define TXGBE_AML_MAC_TX_CFG_TE BIT(0) 167 #define TXGBE_AML_MAC_TX_CFG_SPEED_MASK GENMASK(30, 27) 168 #define TXGBE_AML_MAC_TX_CFG_SPEED_40G FIELD_PREP(GENMASK(30, 27), 0) 169 #define TXGBE_AML_MAC_TX_CFG_SPEED_25G FIELD_PREP(GENMASK(30, 27), 2) 170 #define TXGBE_AML_MAC_TX_CFG_SPEED_10G FIELD_PREP(GENMASK(30, 27), 8) 171 #define TXGBE_RDM_RSC_CTL 0x1200C 172 #define TXGBE_RDM_RSC_CTL_FREE_CTL BIT(7) 173 174 /* Checksum and EEPROM pointers */ 175 #define TXGBE_EEPROM_LAST_WORD 0x800 176 #define TXGBE_EEPROM_CHECKSUM 0x2F 177 #define TXGBE_EEPROM_SUM 0xBABA 178 #define TXGBE_EEPROM_VERSION_L 0x1D 179 #define TXGBE_EEPROM_VERSION_H 0x1E 180 #define TXGBE_ISCSI_BOOT_CONFIG 0x07 181 #define TXGBE_EEPROM_I2C_SRART_PTR 0x580 182 #define TXGBE_EEPROM_I2C_END_PTR 0x800 183 184 #define TXGBE_MAX_MSIX_VECTORS 64 185 #define TXGBE_MAX_FDIR_INDICES 63 186 #define TXGBE_MAX_RSS_INDICES 63 187 188 #define TXGBE_MAX_RX_QUEUES (TXGBE_MAX_FDIR_INDICES + 1) 189 #define TXGBE_MAX_TX_QUEUES (TXGBE_MAX_FDIR_INDICES + 1) 190 191 #define TXGBE_MAX_TXQ 128 192 #define TXGBE_MAX_RXQ 128 193 #define TXGBE_RAR_ENTRIES 128 194 #define TXGBE_MC_TBL_SIZE 128 195 #define TXGBE_VFT_TBL_SIZE 128 196 #define TXGBE_RX_PB_SIZE 512 197 #define TXGBE_TDB_PB_SZ (160 * 1024) /* 160KB Packet Buffer */ 198 199 #define TXGBE_MAX_VFS_DRV_LIMIT 63 200 201 #define TXGBE_DEFAULT_ATR_SAMPLE_RATE 20 202 203 /* Software ATR hash keys */ 204 #define TXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 205 #define TXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 206 207 /* Software ATR input stream values and masks */ 208 #define TXGBE_ATR_HASH_MASK 0x7fff 209 #define TXGBE_ATR_L4TYPE_MASK 0x3 210 #define TXGBE_ATR_L4TYPE_UDP 0x1 211 #define TXGBE_ATR_L4TYPE_TCP 0x2 212 #define TXGBE_ATR_L4TYPE_SCTP 0x3 213 #define TXGBE_ATR_L4TYPE_IPV6_MASK 0x4 214 #define TXGBE_ATR_L4TYPE_TUNNEL_MASK 0x10 215 216 enum txgbe_atr_flow_type { 217 TXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, 218 TXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, 219 TXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, 220 TXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, 221 TXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, 222 TXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, 223 TXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, 224 TXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, 225 TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4 = 0x10, 226 TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4 = 0x11, 227 TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4 = 0x12, 228 TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4 = 0x13, 229 TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6 = 0x14, 230 TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6 = 0x15, 231 TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6 = 0x16, 232 TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6 = 0x17, 233 }; 234 235 /* Flow Director ATR input struct. */ 236 union txgbe_atr_input { 237 /* Byte layout in order, all values with MSB first: 238 * 239 * vm_pool - 1 byte 240 * flow_type - 1 byte 241 * vlan_id - 2 bytes 242 * dst_ip - 16 bytes 243 * src_ip - 16 bytes 244 * src_port - 2 bytes 245 * dst_port - 2 bytes 246 * flex_bytes - 2 bytes 247 * bkt_hash - 2 bytes 248 */ 249 struct { 250 u8 vm_pool; 251 u8 flow_type; 252 __be16 vlan_id; 253 __be32 dst_ip[4]; 254 __be32 src_ip[4]; 255 __be16 src_port; 256 __be16 dst_port; 257 __be16 flex_bytes; 258 __be16 bkt_hash; 259 } formatted; 260 __be32 dword_stream[11]; 261 }; 262 263 /* Flow Director compressed ATR hash input struct */ 264 union txgbe_atr_hash_dword { 265 struct { 266 u8 vm_pool; 267 u8 flow_type; 268 __be16 vlan_id; 269 } formatted; 270 __be32 ip; 271 struct { 272 __be16 src; 273 __be16 dst; 274 } port; 275 __be16 flex_bytes; 276 __be32 dword; 277 }; 278 279 enum txgbe_fdir_pballoc_type { 280 TXGBE_FDIR_PBALLOC_NONE = 0, 281 TXGBE_FDIR_PBALLOC_64K = 1, 282 TXGBE_FDIR_PBALLOC_128K = 2, 283 TXGBE_FDIR_PBALLOC_256K = 3, 284 }; 285 286 struct txgbe_fdir_filter { 287 struct hlist_node fdir_node; 288 union txgbe_atr_input filter; 289 u16 sw_idx; 290 u64 action; 291 }; 292 293 /* TX/RX descriptor defines */ 294 #define TXGBE_DEFAULT_TXD 512 295 #define TXGBE_DEFAULT_TX_WORK 256 296 297 #if (PAGE_SIZE < 8192) 298 #define TXGBE_DEFAULT_RXD 512 299 #define TXGBE_DEFAULT_RX_WORK 256 300 #else 301 #define TXGBE_DEFAULT_RXD 256 302 #define TXGBE_DEFAULT_RX_WORK 128 303 #endif 304 305 #define TXGBE_INTR_MISC(A) BIT((A)->num_q_vectors) 306 #define TXGBE_INTR_QALL(A) (TXGBE_INTR_MISC(A) - 1) 307 308 #define TXGBE_MAX_EITR GENMASK(11, 3) 309 310 extern char txgbe_driver_name[]; 311 312 void txgbe_down(struct wx *wx); 313 void txgbe_up(struct wx *wx); 314 int txgbe_setup_tc(struct net_device *dev, u8 tc); 315 void txgbe_do_reset(struct net_device *netdev); 316 317 #define TXGBE_LINK_SPEED_10GB_FULL 4 318 #define TXGBE_LINK_SPEED_25GB_FULL 0x10 319 320 #define TXGBE_SFF_IDENTIFIER_SFP 0x3 321 #define TXGBE_SFF_DA_PASSIVE_CABLE 0x4 322 #define TXGBE_SFF_DA_ACTIVE_CABLE 0x8 323 #define TXGBE_SFF_DA_SPEC_ACTIVE_LIMIT 0x4 324 #define TXGBE_SFF_FCPI4_LIMITING 0x3 325 #define TXGBE_SFF_10GBASESR_CAPABLE 0x10 326 #define TXGBE_SFF_10GBASELR_CAPABLE 0x20 327 #define TXGBE_SFF_25GBASESR_CAPABLE 0x2 328 #define TXGBE_SFF_25GBASELR_CAPABLE 0x3 329 #define TXGBE_SFF_25GBASEER_CAPABLE 0x4 330 #define TXGBE_SFF_25GBASECR_91FEC 0xB 331 #define TXGBE_SFF_25GBASECR_74FEC 0xC 332 #define TXGBE_SFF_25GBASECR_NOFEC 0xD 333 334 #define TXGBE_PHY_FEC_RS BIT(0) 335 #define TXGBE_PHY_FEC_BASER BIT(1) 336 #define TXGBE_PHY_FEC_OFF BIT(2) 337 #define TXGBE_PHY_FEC_AUTO (TXGBE_PHY_FEC_OFF | \ 338 TXGBE_PHY_FEC_BASER |\ 339 TXGBE_PHY_FEC_RS) 340 341 #define FW_PHY_GET_LINK_CMD 0xC0 342 #define FW_PHY_SET_LINK_CMD 0xC1 343 #define FW_READ_SFP_INFO_CMD 0xC5 344 345 struct txgbe_sfp_id { 346 u8 identifier; /* A0H 0x00 */ 347 u8 com_1g_code; /* A0H 0x06 */ 348 u8 com_10g_code; /* A0H 0x03 */ 349 u8 com_25g_code; /* A0H 0x24 */ 350 u8 cable_spec; /* A0H 0x3C */ 351 u8 cable_tech; /* A0H 0x08 */ 352 u8 vendor_oui0; /* A0H 0x25 */ 353 u8 vendor_oui1; /* A0H 0x26 */ 354 u8 vendor_oui2; /* A0H 0x27 */ 355 u8 reserved[3]; 356 }; 357 358 struct txgbe_hic_i2c_read { 359 struct wx_hic_hdr hdr; 360 struct txgbe_sfp_id id; 361 }; 362 363 struct txgbe_hic_ephy_setlink { 364 struct wx_hic_hdr hdr; 365 u8 speed; 366 u8 duplex; 367 u8 autoneg; 368 u8 fec_mode; 369 u8 resv[4]; 370 }; 371 372 struct txgbe_hic_ephy_getlink { 373 struct wx_hic_hdr hdr; 374 u8 speed; 375 u8 duplex; 376 u8 autoneg; 377 u8 flow_ctl; 378 u8 power; 379 u8 fec_mode; 380 u8 resv[6]; 381 }; 382 383 #define NODE_PROP(_NAME, _PROP) \ 384 (const struct software_node) { \ 385 .name = _NAME, \ 386 .properties = _PROP, \ 387 } 388 389 enum txgbe_swnodes { 390 SWNODE_GPIO = 0, 391 SWNODE_I2C, 392 SWNODE_SFP, 393 SWNODE_PHYLINK, 394 SWNODE_MAX 395 }; 396 397 struct txgbe_nodes { 398 char gpio_name[32]; 399 char i2c_name[32]; 400 char sfp_name[32]; 401 char phylink_name[32]; 402 struct property_entry gpio_props[1]; 403 struct property_entry i2c_props[3]; 404 struct property_entry sfp_props[8]; 405 struct property_entry phylink_props[2]; 406 struct software_node_ref_args i2c_ref[1]; 407 struct software_node_ref_args gpio0_ref[1]; 408 struct software_node_ref_args gpio1_ref[1]; 409 struct software_node_ref_args gpio2_ref[1]; 410 struct software_node_ref_args gpio3_ref[1]; 411 struct software_node_ref_args gpio4_ref[1]; 412 struct software_node_ref_args gpio5_ref[1]; 413 struct software_node_ref_args sfp_ref[1]; 414 struct software_node swnodes[SWNODE_MAX]; 415 const struct software_node *group[SWNODE_MAX + 1]; 416 }; 417 418 enum txgbe_misc_irqs { 419 TXGBE_IRQ_LINK = 0, 420 TXGBE_IRQ_GPIO, 421 TXGBE_IRQ_MAX 422 }; 423 424 struct txgbe_irq { 425 struct irq_chip chip; 426 struct irq_domain *domain; 427 int nirqs; 428 int irq; 429 }; 430 431 struct txgbe { 432 struct wx *wx; 433 struct txgbe_nodes nodes; 434 struct txgbe_irq misc; 435 struct phylink_pcs *pcs; 436 struct platform_device *sfp_dev; 437 struct platform_device *i2c_dev; 438 struct clk_lookup *clock; 439 struct clk *clk; 440 struct gpio_chip *gpio; 441 unsigned int link_irq; 442 unsigned int gpio_irq; 443 u32 eicr; 444 445 /* flow director */ 446 struct hlist_head fdir_filter_list; 447 union txgbe_atr_input fdir_mask; 448 int fdir_filter_count; 449 spinlock_t fdir_perfect_lock; /* spinlock for FDIR */ 450 451 DECLARE_PHY_INTERFACE_MASK(sfp_interfaces); 452 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); 453 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 454 u8 link_port; 455 }; 456 457 #endif /* _TXGBE_TYPE_H_ */ 458