1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _PSP_TEE_GFX_IF_H_ 25 #define _PSP_TEE_GFX_IF_H_ 26 27 #define PSP_GFX_CMD_BUF_VERSION 0x00000001 28 29 #define GFX_CMD_STATUS_MASK 0x0000FFFF 30 #define GFX_CMD_ID_MASK 0x000F0000 31 #define GFX_CMD_RESERVED_MASK 0x7FF00000 32 #define GFX_CMD_RESPONSE_MASK 0x80000000 33 34 /* USBC PD FW version retrieval command */ 35 #define C2PMSG_CMD_GFX_USB_PD_FW_VER 0x2000000 36 37 /* TEE Gfx Command IDs for the register interface. 38 * Command ID must be between 0x00010000 and 0x000F0000. 39 */ 40 enum psp_gfx_crtl_cmd_id 41 { 42 GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */ 43 GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */ 44 GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */ 45 GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */ 46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */ 47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */ 48 GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */ 49 GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */ 50 GFX_CTRL_CMD_ID_CONSUME_CMD = 0x00090000, /* send interrupt to psp for updating write pointer of vf */ 51 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */ 52 53 GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */ 54 }; 55 56 typedef enum 57 { 58 GFX_CTRL_ADDR_TYPE_AUTO_DETECT = 0, 59 GFX_CTRL_ADDR_TYPE_SYS_PHY_ADDR, 60 GFX_CTRL_ADDR_TYPE_GPU_PHY_ADDR, 61 GFX_CTRL_ADDR_TYPE_GPU_VIRT_ADDR 62 } GFX_CTRL_ADDR_TYPE; 63 64 /*----------------------------------------------------------------------------- 65 NOTE: All physical addresses used in this interface are actually 66 GPU Virtual Addresses. 67 */ 68 69 70 /* Control registers of the TEE Gfx interface. These are located in 71 * SRBM-to-PSP mailbox registers (total 8 registers). 72 */ 73 struct psp_gfx_ctrl 74 { 75 volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */ 76 volatile uint32_t rbi_wptr; /* +4 Write pointer (index) of RBI ring */ 77 volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */ 78 volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */ 79 volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */ 80 volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/ 81 volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */ 82 volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */ 83 84 }; 85 86 87 /* Response flag is set in the command when command is completed by PSP. 88 * Used in the GFX_CTRL.CmdResp. 89 * When PSP GFX I/F is initialized, the flag is set. 90 */ 91 #define GFX_FLAG_RESPONSE 0x80000000 92 93 /* TEE Gfx Command IDs for the ring buffer interface. */ 94 enum psp_gfx_cmd_id 95 { 96 GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */ 97 GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */ 98 GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */ 99 GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */ 100 GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */ 101 GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */ 102 GFX_CMD_ID_DESTROY_TMR = 0x00000007, /* destroy TMR region */ 103 GFX_CMD_ID_SAVE_RESTORE = 0x00000008, /* save/restore HW IP FW */ 104 GFX_CMD_ID_SETUP_VMR = 0x00000009, /* setup VMR region */ 105 GFX_CMD_ID_DESTROY_VMR = 0x0000000A, /* destroy VMR region */ 106 GFX_CMD_ID_PROG_REG = 0x0000000B, /* program regs */ 107 GFX_CMD_ID_GET_FW_ATTESTATION = 0x0000000F, /* Query GPUVA of the Fw Attestation DB */ 108 /* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */ 109 GFX_CMD_ID_LOAD_TOC = 0x00000020, /* Load TOC and obtain TMR size */ 110 GFX_CMD_ID_AUTOLOAD_RLC = 0x00000021, /* Indicates all graphics fw loaded, start RLC autoload */ 111 GFX_CMD_ID_BOOT_CFG = 0x00000022, /* Boot Config */ 112 GFX_CMD_ID_SRIOV_SPATIAL_PART = 0x00000027, /* Configure spatial partitioning mode */ 113 /*IDs of performance monitoring/profiling*/ 114 GFX_CMD_ID_CONFIG_SQ_PERFMON = 0x00000046, /* Config CGTT_SQ_CLK_CTRL */ 115 /* Dynamic memory partitioninig (NPS mode change)*/ 116 GFX_CMD_ID_FB_NPS_MODE = 0x00000048, /* Configure memory partitioning mode */ 117 GFX_CMD_ID_PERF_HW = 0x0000004C, /* performance monitor */ 118 GFX_CMD_ID_FB_FW_RESERV_ADDR = 0x00000050, /* Query FW reservation addr */ 119 GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR = 0x00000051, /* Query FW reservation extended addr */ 120 GFX_CMD_ID_UAL_GET_INTERFACE_VER = 0x00000053, /* Get UAL interface version */ 121 GFX_CMD_ID_UAL_GET_CONFIG = 0x00000054, /* Get UAL full config */ 122 GFX_CMD_ID_UAL_SET_PPOD_CONFIG = 0x00000055, /* Set UAL config */ 123 GFX_CMD_ID_UAL_SET_VPOD_CONFIG = 0x00000056, /* Set UAL vPod config */ 124 GFX_CMD_ID_UAL_SET_STATION_CONFIG= 0x00000057, /* Set UAL Station config */ 125 GFX_CMD_ID_UAL_SET_NPA_CONFIG = 0x00000059, /* Set UAL NPA config and VMID */ 126 GFX_CMD_ID_UAL_SEND_COMPLETION = 0x0000005A, /* Ack from driver after UAL config completion */ 127 GFX_CMD_ID_SET_MMHUB_ECO_SEC_LEVEL = 0x0000005D, /* Set MMHUB ECO sec lvls on VCN block */ 128 }; 129 130 /* PSP boot config sub-commands */ 131 enum psp_gfx_boot_config_cmd 132 { 133 BOOTCFG_CMD_SET = 1, /* Set boot configuration settings */ 134 BOOTCFG_CMD_GET = 2, /* Get boot configuration settings */ 135 BOOTCFG_CMD_INVALIDATE = 3 /* Reset current boot configuration settings to VBIOS defaults */ 136 }; 137 138 /* PSP boot config bitmask values */ 139 enum psp_gfx_boot_config 140 { 141 BOOT_CONFIG_GECC = 0x1, 142 }; 143 144 /* Command to load Trusted Application binary into PSP OS. */ 145 struct psp_gfx_cmd_load_ta 146 { 147 uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */ 148 uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */ 149 uint32_t app_len; /* length of the TA binary in bytes */ 150 uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */ 151 uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */ 152 uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */ 153 154 /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided 155 * for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead 156 * of using global persistent buffer. 157 */ 158 }; 159 160 161 /* Command to Unload Trusted Application binary from PSP OS. */ 162 struct psp_gfx_cmd_unload_ta 163 { 164 uint32_t session_id; /* Session ID of the loaded TA to be unloaded */ 165 166 }; 167 168 169 /* Shared buffers for InvokeCommand. 170 */ 171 struct psp_gfx_buf_desc 172 { 173 uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */ 174 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */ 175 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */ 176 177 }; 178 179 /* Max number of descriptors for one shared buffer (in how many different 180 * physical locations one shared buffer can be stored). If buffer is too much 181 * fragmented, error will be returned. 182 */ 183 #define GFX_BUF_MAX_DESC 64 184 185 struct psp_gfx_buf_list 186 { 187 uint32_t num_desc; /* number of buffer descriptors in the list */ 188 uint32_t total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */ 189 struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */ 190 191 /* total 776 bytes */ 192 }; 193 194 /* Command to execute InvokeCommand entry point of the TA. */ 195 struct psp_gfx_cmd_invoke_cmd 196 { 197 uint32_t session_id; /* Session ID of the TA to be executed */ 198 uint32_t ta_cmd_id; /* Command ID to be sent to TA */ 199 struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */ 200 201 }; 202 203 204 /* Command to setup TMR region. */ 205 struct psp_gfx_cmd_setup_tmr 206 { 207 uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */ 208 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */ 209 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */ 210 union { 211 struct { 212 uint32_t sriov_enabled:1; /* whether the device runs under SR-IOV*/ 213 uint32_t virt_phy_addr:1; /* driver passes both virtual and physical address to PSP*/ 214 uint32_t reserved:30; 215 } bitfield; 216 uint32_t tmr_flags; 217 }; 218 uint32_t system_phy_addr_lo; /* bits [31:0] of system physical address of TMR buffer (must be 4 KB aligned) */ 219 uint32_t system_phy_addr_hi; /* bits [63:32] of system physical address of TMR buffer */ 220 221 }; 222 223 /* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */ 224 enum psp_gfx_fw_type { 225 GFX_FW_TYPE_NONE = 0, /* */ 226 GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */ 227 GFX_FW_TYPE_CP_PFP = 2, /* CP-PFP VG + RV */ 228 GFX_FW_TYPE_CP_CE = 3, /* CP-CE VG + RV */ 229 GFX_FW_TYPE_CP_MEC = 4, /* CP-MEC FW VG + RV */ 230 GFX_FW_TYPE_CP_MEC_ME1 = 5, /* CP-MEC Jump Table 1 VG + RV */ 231 GFX_FW_TYPE_CP_MEC_ME2 = 6, /* CP-MEC Jump Table 2 VG */ 232 GFX_FW_TYPE_RLC_V = 7, /* RLC-V VG */ 233 GFX_FW_TYPE_RLC_G = 8, /* RLC-G VG + RV */ 234 GFX_FW_TYPE_SDMA0 = 9, /* SDMA0 VG + RV */ 235 GFX_FW_TYPE_SDMA1 = 10, /* SDMA1 VG */ 236 GFX_FW_TYPE_DMCU_ERAM = 11, /* DMCU-ERAM VG + RV */ 237 GFX_FW_TYPE_DMCU_ISR = 12, /* DMCU-ISR VG + RV */ 238 GFX_FW_TYPE_VCN = 13, /* VCN RV */ 239 GFX_FW_TYPE_UVD = 14, /* UVD VG */ 240 GFX_FW_TYPE_VCE = 15, /* VCE VG */ 241 GFX_FW_TYPE_ISP = 16, /* ISP RV */ 242 GFX_FW_TYPE_ACP = 17, /* ACP RV */ 243 GFX_FW_TYPE_SMU = 18, /* SMU VG */ 244 GFX_FW_TYPE_MMSCH = 19, /* MMSCH VG */ 245 GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20, /* RLC GPM VG + RV */ 246 GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21, /* RLC SRM VG + RV */ 247 GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL = 22, /* RLC CNTL VG + RV */ 248 GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */ 249 GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */ 250 GFX_FW_TYPE_RLC_P = 25, /* RLC P NV */ 251 GFX_FW_TYPE_RLC_IRAM = 26, /* RLC_IRAM NV */ 252 GFX_FW_TYPE_GLOBAL_TAP_DELAYS = 27, /* GLOBAL TAP DELAYS NV */ 253 GFX_FW_TYPE_SE0_TAP_DELAYS = 28, /* SE0 TAP DELAYS NV */ 254 GFX_FW_TYPE_SE1_TAP_DELAYS = 29, /* SE1 TAP DELAYS NV */ 255 GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS = 30, /* GLOBAL SE0/1 SKEW DELAYS NV */ 256 GFX_FW_TYPE_SDMA0_JT = 31, /* SDMA0 JT NV */ 257 GFX_FW_TYPE_SDMA1_JT = 32, /* SDNA1 JT NV */ 258 GFX_FW_TYPE_CP_MES = 33, /* CP MES NV */ 259 GFX_FW_TYPE_MES_STACK = 34, /* MES STACK NV */ 260 GFX_FW_TYPE_RLC_SRM_DRAM_SR = 35, /* RLC SRM DRAM NV */ 261 GFX_FW_TYPE_RLCG_SCRATCH_SR = 36, /* RLCG SCRATCH NV */ 262 GFX_FW_TYPE_RLCP_SCRATCH_SR = 37, /* RLCP SCRATCH NV */ 263 GFX_FW_TYPE_RLCV_SCRATCH_SR = 38, /* RLCV SCRATCH NV */ 264 GFX_FW_TYPE_RLX6_DRAM_SR = 39, /* RLX6 DRAM NV */ 265 GFX_FW_TYPE_SDMA0_PG_CONTEXT = 40, /* SDMA0 PG CONTEXT NV */ 266 GFX_FW_TYPE_SDMA1_PG_CONTEXT = 41, /* SDMA1 PG CONTEXT NV */ 267 GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM = 42, /* GLOBAL MUX SEL RAM NV */ 268 GFX_FW_TYPE_SE0_MUX_SELECT_RAM = 43, /* SE0 MUX SEL RAM NV */ 269 GFX_FW_TYPE_SE1_MUX_SELECT_RAM = 44, /* SE1 MUX SEL RAM NV */ 270 GFX_FW_TYPE_ACCUM_CTRL_RAM = 45, /* ACCUM CTRL RAM NV */ 271 GFX_FW_TYPE_RLCP_CAM = 46, /* RLCP CAM NV */ 272 GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47, /* RLC SPP CAM EXT NV */ 273 GFX_FW_TYPE_RLC_DRAM_BOOT = 48, /* RLC DRAM BOOT NV */ 274 GFX_FW_TYPE_VCN0_RAM = 49, /* VCN_RAM NV + RN */ 275 GFX_FW_TYPE_VCN1_RAM = 50, /* VCN_RAM NV + RN */ 276 GFX_FW_TYPE_DMUB = 51, /* DMUB RN */ 277 GFX_FW_TYPE_SDMA2 = 52, /* SDMA2 MI */ 278 GFX_FW_TYPE_SDMA3 = 53, /* SDMA3 MI */ 279 GFX_FW_TYPE_SDMA4 = 54, /* SDMA4 MI */ 280 GFX_FW_TYPE_SDMA5 = 55, /* SDMA5 MI */ 281 GFX_FW_TYPE_SDMA6 = 56, /* SDMA6 MI */ 282 GFX_FW_TYPE_SDMA7 = 57, /* SDMA7 MI */ 283 GFX_FW_TYPE_VCN1 = 58, /* VCN1 MI */ 284 GFX_FW_TYPE_CAP = 62, /* CAP_FW */ 285 GFX_FW_TYPE_SE2_TAP_DELAYS = 65, /* SE2 TAP DELAYS NV */ 286 GFX_FW_TYPE_SE3_TAP_DELAYS = 66, /* SE3 TAP DELAYS NV */ 287 GFX_FW_TYPE_REG_LIST = 67, /* REG_LIST MI */ 288 GFX_FW_TYPE_IMU_I = 68, /* IMU Instruction FW SOC21 */ 289 GFX_FW_TYPE_IMU_D = 69, /* IMU Data FW SOC21 */ 290 GFX_FW_TYPE_LSDMA = 70, /* LSDMA FW SOC21 */ 291 GFX_FW_TYPE_SDMA_UCODE_TH0 = 71, /* SDMA Thread 0/CTX SOC21 */ 292 GFX_FW_TYPE_SDMA_UCODE_TH1 = 72, /* SDMA Thread 1/CTL SOC21 */ 293 GFX_FW_TYPE_PPTABLE = 73, /* PPTABLE SOC21 */ 294 GFX_FW_TYPE_DISCRETE_USB4 = 74, /* dUSB4 FW SOC21 */ 295 GFX_FW_TYPE_TA = 75, /* SRIOV TA FW UUID SOC21 */ 296 GFX_FW_TYPE_RS64_MES = 76, /* RS64 MES ucode SOC21 */ 297 GFX_FW_TYPE_RS64_MES_STACK = 77, /* RS64 MES stack ucode SOC21 */ 298 GFX_FW_TYPE_RS64_KIQ = 78, /* RS64 KIQ ucode SOC21 */ 299 GFX_FW_TYPE_RS64_KIQ_STACK = 79, /* RS64 KIQ Heap stack SOC21 */ 300 GFX_FW_TYPE_ISP_DATA = 80, /* ISP DATA SOC21 */ 301 GFX_FW_TYPE_CP_MES_KIQ = 81, /* MES KIQ ucode SOC21 */ 302 GFX_FW_TYPE_MES_KIQ_STACK = 82, /* MES KIQ stack SOC21 */ 303 GFX_FW_TYPE_UMSCH_DATA = 83, /* User Mode Scheduler Data SOC21 */ 304 GFX_FW_TYPE_UMSCH_UCODE = 84, /* User Mode Scheduler Ucode SOC21 */ 305 GFX_FW_TYPE_UMSCH_CMD_BUFFER = 85, /* User Mode Scheduler Command Buffer SOC21 */ 306 GFX_FW_TYPE_USB_DP_COMBO_PHY = 86, /* USB-Display port Combo SOC21 */ 307 GFX_FW_TYPE_RS64_PFP = 87, /* RS64 PFP SOC21 */ 308 GFX_FW_TYPE_RS64_ME = 88, /* RS64 ME SOC21 */ 309 GFX_FW_TYPE_RS64_MEC = 89, /* RS64 MEC SOC21 */ 310 GFX_FW_TYPE_RS64_PFP_P0_STACK = 90, /* RS64 PFP stack P0 SOC21 */ 311 GFX_FW_TYPE_RS64_PFP_P1_STACK = 91, /* RS64 PFP stack P1 SOC21 */ 312 GFX_FW_TYPE_RS64_ME_P0_STACK = 92, /* RS64 ME stack P0 SOC21 */ 313 GFX_FW_TYPE_RS64_ME_P1_STACK = 93, /* RS64 ME stack P1 SOC21 */ 314 GFX_FW_TYPE_RS64_MEC_P0_STACK = 94, /* RS64 MEC stack P0 SOC21 */ 315 GFX_FW_TYPE_RS64_MEC_P1_STACK = 95, /* RS64 MEC stack P1 SOC21 */ 316 GFX_FW_TYPE_RS64_MEC_P2_STACK = 96, /* RS64 MEC stack P2 SOC21 */ 317 GFX_FW_TYPE_RS64_MEC_P3_STACK = 97, /* RS64 MEC stack P3 SOC21 */ 318 GFX_FW_TYPE_RLX6_UCODE_CORE1 = 98, /* RLCV_IRAM MI */ 319 GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1 = 99, /* RLCV DRAM BOOT MI */ 320 GFX_FW_TYPE_VPEC_FW1 = 100, /* VPEC FW1 To Save VPE */ 321 GFX_FW_TYPE_VPEC_FW2 = 101, /* VPEC FW2 To Save VPE */ 322 GFX_FW_TYPE_VPE = 102, 323 GFX_FW_TYPE_JPEG_RAM = 128, /**< JPEG Command buffer */ 324 GFX_FW_TYPE_P2S_TABLE = 129, 325 GFX_FW_TYPE_RS64_MEC_P4_STACK = 133, /* RS64 MEC stack P4 */ 326 GFX_FW_TYPE_RS64_MEC_P5_STACK = 134, /* RS64 MEC stack P5 */ 327 GFX_FW_TYPE_RS64_MEC_P6_STACK = 135, /* RS64 MEC stack P6 */ 328 GFX_FW_TYPE_RS64_MEC_P7_STACK = 136, /* RS64 MEC stack P7 */ 329 GFX_FW_TYPE_MP5 = 158, /* MP5 ucode */ 330 GFX_FW_TYPE_MAX 331 }; 332 333 /* Command to load HW IP FW. */ 334 struct psp_gfx_cmd_load_ip_fw 335 { 336 uint32_t fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */ 337 uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */ 338 uint32_t fw_size; /* FW buffer size in bytes */ 339 enum psp_gfx_fw_type fw_type; /* FW type */ 340 341 }; 342 343 /* Command to save/restore HW IP FW. */ 344 struct psp_gfx_cmd_save_restore_ip_fw 345 { 346 uint32_t save_fw; /* if set, command is used for saving fw otherwise for resetoring*/ 347 uint32_t save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */ 348 uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */ 349 uint32_t buf_size; /* Size of the save/restore buffer in bytes */ 350 enum psp_gfx_fw_type fw_type; /* FW type */ 351 }; 352 353 /* Command to setup register program */ 354 struct psp_gfx_cmd_reg_prog { 355 uint32_t reg_value; 356 uint32_t reg_id; 357 }; 358 359 /* Command to load TOC */ 360 struct psp_gfx_cmd_load_toc 361 { 362 uint32_t toc_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */ 363 uint32_t toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */ 364 uint32_t toc_size; /* FW buffer size in bytes */ 365 }; 366 367 /* Dynamic boot configuration */ 368 struct psp_gfx_cmd_boot_cfg 369 { 370 uint32_t timestamp; /* calendar time as number of seconds */ 371 enum psp_gfx_boot_config_cmd sub_cmd; /* sub-command indicating how to process command data */ 372 uint32_t boot_config; /* dynamic boot configuration bitmask */ 373 uint32_t boot_config_valid; /* dynamic boot configuration valid bits bitmask */ 374 }; 375 376 struct psp_gfx_cmd_sriov_spatial_part { 377 uint32_t mode; 378 uint32_t override_ips; 379 uint32_t override_xcds_avail; 380 uint32_t override_this_aid; 381 }; 382 383 /*Structure for sq performance monitoring/profiling enable/disable*/ 384 struct psp_gfx_cmd_config_sq_perfmon { 385 uint32_t gfx_xcp_mask; 386 uint8_t core_override; 387 uint8_t reg_override; 388 uint8_t perfmon_override; 389 uint8_t reserved[5]; 390 }; 391 392 struct psp_gfx_cmd_fb_memory_part { 393 uint32_t mode; /* requested NPS mode */ 394 uint32_t resvd; 395 }; 396 397 struct psp_gfx_cmd_req_perf_hw { 398 uint32_t req; 399 uint32_t ptl_state; 400 uint32_t pref_format1; 401 uint32_t pref_format2; 402 }; 403 404 #define PSP_GFX_MAX_LOCAL_GPUS_UAL_V1 16 /* max gpu per local node */ 405 #define PSP_GFX_UAL_MAX_STATIONS_V1 64 /* max UALink stations */ 406 #define PSP_GFX_UAL_MAX_ACC_BIT_MASK 32 /* max accelerator bit mask 32*32 */ 407 408 /* Interrupt category identifiers (upper byte) - ASP interrupts to Driver */ 409 410 /* Commands from ASP */ 411 #define PSP_GFX_INT_CTXT_UAL_CAT_CMD 0x01000000 412 /* Mask for Command bits */ 413 #define PSP_GFX_INT_CTXT_UAL_CAT_CMD_MASK 0x000000FF 414 /* Notifications from ASP */ 415 #define PSP_GFX_INT_CTXT_UAL_CAT_NOTIFY 0x02000000 416 /* Mask for category bits */ 417 #define PSP_GFX_INT_CTXT_UAL_CAT_MASK 0xFF000000 418 419 #define PSP_GFX_INT_CTXT_UAL_CMD_CFG_UPDATE_ID 0x00000001 420 #define PSP_GFX_INT_CTXT_UAL_CMD_PAUSE_ID 0x00000002 421 #define PSP_GFX_INT_CTXT_UAL_CMD_RESUME_ID 0x00000003 422 423 /* Command interrupts from ASP (GIM must execute action) */ 424 #define PSP_GFX_INT_CTXT_UAL_CMD_CFG_UPDATE \ 425 (PSP_GFX_INT_CTXT_UAL_CAT_CMD | PSP_GFX_INT_CTXT_UAL_CMD_CFG_UPDATE_ID) 426 427 #define PSP_GFX_INT_CTXT_UAL_CMD_PAUSE \ 428 (PSP_GFX_INT_CTXT_UAL_CAT_CMD | PSP_GFX_INT_CTXT_UAL_CMD_PAUSE_ID) 429 430 #define PSP_GFX_INT_CTXT_UAL_CMD_RESUME \ 431 (PSP_GFX_INT_CTXT_UAL_CAT_CMD | PSP_GFX_INT_CTXT_UAL_CMD_RESUME_ID) 432 433 enum psp_gfx_ual_npa_address_mode { 434 PSP_GFX_UAL_NPA_ADDRESS_MODE_SOURCE_ALIASING = 0, 435 PSP_GFX_UAL_NPA_ADDRESS_MODE_SOURCE_IDENTIFICATION = 1, 436 PSP_GFX_UAL_NPA_ADDRESS_MODE_MAX 437 }; 438 439 enum psp_gfx_ual_ports_per_station 440 { 441 PSP_GFX_UAL_PPS_1 = 1, // 1x 800Gbps 442 PSP_GFX_UAL_PPS_2 = 2, // 2x 400Gbps 443 PSP_GFX_UAL_PPS_4 = 4 // 4x 200Gbps 444 }; 445 446 enum psp_gfx_ual_link_type 447 { 448 PSP_GFX_UALOE = 0, 449 PSP_GFX_UALLINK = 1, 450 PSP_GFX_UALMAX 451 }; 452 453 enum psp_gfx_ual_config_state 454 { 455 UAL_CFG_IDLE = 0, 456 UAL_CFG_PPOD = 1, 457 UAL_CFG_VPOD = 2, 458 UAL_CFG_PAUSE = 3, 459 UAL_CFG_STATION = 4, 460 UAL_CFG_COMPLETE = 5, 461 UAL_CFG_INVALID = 0xFF 462 }; 463 464 struct psp_gfx_cmd_set_ppod_config_ual_v1 465 { 466 uint32_t accelerator_id; // Accelerator ID 467 uint8_t ppod_id[16]; // Physical Pod ID 468 uint32_t ppod_size; // number of gpu in physical pod 469 uint32_t bandwidth; // Bandwidth 470 uint32_t latency; // Latency 471 uint32_t local_accelerators[PSP_GFX_MAX_LOCAL_GPUS_UAL_V1]; // local accelerator list, sorted in socket-id order 472 }; 473 474 struct psp_gfx_cmd_set_vpod_config_ual_v1 475 { 476 uint32_t vpod_id; // vPod ID 477 uint32_t vpod_size; // number of gpu in virtual pod 478 uint32_t vpod_active_accelerators[PSP_GFX_UAL_MAX_ACC_BIT_MASK]; // accelerator ID list in each vPOD 479 enum psp_gfx_ual_npa_address_mode addr_mode; // NPA Addressing Mode 480 }; 481 482 struct psp_gfx_cmd_station_config_ual_v1 483 { 484 /* Number of valid stations in this configuration 485 * Only lane_en_bitmap[0..n_stations-1] will be processed. 486 */ 487 uint8_t num_stations; 488 /* Station configuration flags 489 * 490 * Bit [3:0]: PortPerStation (PPS) - 1, 2, or 4 491 * Bit [7:4]: Reserved 492 */ 493 uint8_t station_flag; 494 uint8_t reserved[2]; /* Future use / alignment padding */ 495 /* Bitmap of enabled lanes for each station 496 * in logical station order. 497 */ 498 uint8_t lane_en_bitmap[PSP_GFX_UAL_MAX_STATIONS_V1]; 499 }; 500 501 struct psp_gfx_cmd_get_config_ual_v1 502 { 503 uint32_t ual_cfg_addr_hi; // UAL Config Buffer Address Hi 504 uint32_t ual_cfg_addr_lo; // UAL Config Buffer Address Lo 505 uint32_t ual_cfg_size; // UAL Config Buffer Size 506 GFX_CTRL_ADDR_TYPE addr_type; // Buffer Address Type 507 }; 508 509 struct psp_gfx_get_config_ual_v1 { 510 enum psp_gfx_ual_link_type link_type; 511 uint32_t accelerator_id; 512 uint8_t ppod_id[16]; 513 uint32_t ppod_size; 514 uint32_t bandwidth; 515 uint32_t latency; 516 uint32_t vpod_id; 517 uint32_t vpod_size; 518 uint32_t vpod_active_accelerators[PSP_GFX_UAL_MAX_ACC_BIT_MASK]; 519 enum psp_gfx_ual_npa_address_mode addr_mode; 520 enum psp_gfx_ual_config_state config_state; 521 }; 522 523 struct psp_gfx_cmd_send_completion_ual_v1 524 { 525 uint32_t cmd_id; 526 uint32_t status; 527 }; 528 529 struct psp_gfx_cmd_set_npa_config_ual_v1 { 530 uint32_t vmid; 531 uint32_t enable_npa_translation; 532 }; 533 534 /* All GFX ring buffer commands. */ 535 union psp_gfx_commands 536 { 537 struct psp_gfx_cmd_load_ta cmd_load_ta; 538 struct psp_gfx_cmd_unload_ta cmd_unload_ta; 539 struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd; 540 struct psp_gfx_cmd_setup_tmr cmd_setup_tmr; 541 struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw; 542 struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw; 543 struct psp_gfx_cmd_reg_prog cmd_setup_reg_prog; 544 struct psp_gfx_cmd_setup_tmr cmd_setup_vmr; 545 struct psp_gfx_cmd_load_toc cmd_load_toc; 546 struct psp_gfx_cmd_boot_cfg boot_cfg; 547 struct psp_gfx_cmd_sriov_spatial_part cmd_spatial_part; 548 struct psp_gfx_cmd_config_sq_perfmon config_sq_perfmon; 549 struct psp_gfx_cmd_fb_memory_part cmd_memory_part; 550 struct psp_gfx_cmd_req_perf_hw cmd_req_perf_hw; 551 struct psp_gfx_cmd_get_config_ual_v1 cmd_get_config_ual; 552 struct psp_gfx_cmd_set_ppod_config_ual_v1 cmd_set_ppod_config_ual; 553 struct psp_gfx_cmd_set_vpod_config_ual_v1 cmd_set_vpod_config_ual; 554 struct psp_gfx_cmd_station_config_ual_v1 cmd_set_station_config_ual; 555 struct psp_gfx_cmd_send_completion_ual_v1 cmd_send_completion_ual; 556 struct psp_gfx_cmd_set_npa_config_ual_v1 cmd_set_npa_config_ual; 557 }; 558 559 struct psp_gfx_uresp_reserved 560 { 561 uint32_t reserved[8]; 562 }; 563 564 /* Command-specific response for Fw Attestation Db */ 565 struct psp_gfx_uresp_fwar_db_info 566 { 567 uint32_t fwar_db_addr_lo; 568 uint32_t fwar_db_addr_hi; 569 }; 570 571 /* Command-specific response for boot config. */ 572 struct psp_gfx_uresp_bootcfg { 573 uint32_t boot_cfg; /* boot config data */ 574 }; 575 576 /* Command-specific response for fw reserve info */ 577 struct psp_gfx_uresp_fw_reserve_info { 578 uint32_t reserve_base_address_hi; 579 uint32_t reserve_base_address_lo; 580 uint32_t reserve_size; 581 }; 582 583 struct psp_gfx_uresp_perf_hw { 584 uint32_t resp; 585 uint32_t ptl_state; 586 uint32_t pref_format1; 587 uint32_t pref_format2; 588 }; 589 590 struct psp_gfx_uresp_get_intf_ver_ual 591 { 592 uint32_t intf_ver; /* [31:16] major version, [15:0] minor version */ 593 }; 594 595 struct psp_gfx_uresp_get_config_ual_v1 596 { 597 uint32_t resp_size; 598 }; 599 600 /* Union of command-specific responses for GPCOM ring. */ 601 union psp_gfx_uresp { 602 struct psp_gfx_uresp_reserved reserved; 603 struct psp_gfx_uresp_bootcfg boot_cfg; 604 struct psp_gfx_uresp_fwar_db_info fwar_db_info; 605 struct psp_gfx_uresp_fw_reserve_info fw_reserve_info; 606 struct psp_gfx_uresp_perf_hw perf_hw_info; 607 struct psp_gfx_uresp_get_config_ual_v1 get_config_ual; 608 struct psp_gfx_uresp_get_intf_ver_ual get_intf_ver_ual; 609 }; 610 611 /* Structure of GFX Response buffer. 612 * For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI 613 * it is separate buffer. 614 */ 615 struct psp_gfx_resp 616 { 617 uint32_t status; /* +0 status of command execution */ 618 uint32_t session_id; /* +4 session ID in response to LoadTa command */ 619 uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */ 620 uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */ 621 uint32_t tmr_size; /* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */ 622 623 uint32_t reserved[11]; 624 625 union psp_gfx_uresp uresp; /* +64 response union containing command-specific responses */ 626 627 /* total 96 bytes */ 628 }; 629 630 /* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi 631 * and psp_gfx_rb_frame.cmd_buf_addr_lo. 632 */ 633 struct psp_gfx_cmd_resp 634 { 635 uint32_t buf_size; /* +0 total size of the buffer in bytes */ 636 uint32_t buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */ 637 uint32_t cmd_id; /* +8 command ID */ 638 639 /* These fields are used for RBI only. They are all 0 in GPCOM commands 640 */ 641 uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */ 642 uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */ 643 uint32_t resp_offset; /* +20 offset within response buffer */ 644 uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */ 645 646 union psp_gfx_commands cmd; /* +28 command specific structures */ 647 648 uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28]; 649 650 /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response 651 * is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo. 652 */ 653 struct psp_gfx_resp resp; /* +864 response */ 654 655 uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)]; 656 657 /* total size 1024 bytes */ 658 }; 659 660 661 #define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/ 662 663 /* Structure of the Ring Buffer Frame */ 664 struct psp_gfx_rb_frame 665 { 666 uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */ 667 uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */ 668 uint32_t cmd_buf_size; /* +8 command buffer size in bytes */ 669 uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */ 670 uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */ 671 uint32_t fence_value; /* +20 Fence value */ 672 uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */ 673 uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */ 674 uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */ 675 uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */ 676 uint8_t reserved1[2]; /* +34 reserved, must be 0 */ 677 uint32_t reserved2[7]; /* +36 reserved, must be 0 */ 678 /* total 64 bytes */ 679 }; 680 681 #define PSP_ERR_UNKNOWN_COMMAND 0x00000100 682 683 enum tee_error_code { 684 TEE_SUCCESS = 0x00000000, 685 TEE_ERROR_CANCEL = 0xFFFF0002, 686 TEE_ERROR_NOT_SUPPORTED = 0xFFFF000A, 687 }; 688 689 #endif /* _PSP_TEE_GFX_IF_H_ */ 690