1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 /* Linux PRO/1000 Ethernet Driver main header file */
5
6 #ifndef _E1000_H_
7 #define _E1000_H_
8
9 #include <linux/bitops.h>
10 #include <linux/types.h>
11 #include <linux/timer.h>
12 #include <linux/workqueue.h>
13 #include <linux/io.h>
14 #include <linux/netdevice.h>
15 #include <linux/pci.h>
16 #include <linux/crc32.h>
17 #include <linux/if_vlan.h>
18 #include <linux/timecounter.h>
19 #include <linux/net_tstamp.h>
20 #include <linux/ptp_clock_kernel.h>
21 #include <linux/ptp_classify.h>
22 #include <linux/mii.h>
23 #include <linux/mdio.h>
24 #include <linux/mutex.h>
25 #include <linux/pm_qos.h>
26 #include "hw.h"
27
28 struct e1000_info;
29
30 #define e_dbg(format, arg...) \
31 netdev_dbg(hw->adapter->netdev, format, ## arg)
32 #define e_err(format, arg...) \
33 netdev_err(adapter->netdev, format, ## arg)
34 #define e_info(format, arg...) \
35 netdev_info(adapter->netdev, format, ## arg)
36 #define e_warn(format, arg...) \
37 netdev_warn(adapter->netdev, format, ## arg)
38 #define e_notice(format, arg...) \
39 netdev_notice(adapter->netdev, format, ## arg)
40
41 /* Interrupt modes, as used by the IntMode parameter */
42 #define E1000E_INT_MODE_LEGACY 0
43 #define E1000E_INT_MODE_MSI 1
44 #define E1000E_INT_MODE_MSIX 2
45
46 /* Tx/Rx descriptor defines */
47 #define E1000_DEFAULT_TXD 256
48 #define E1000_MAX_TXD 4096
49 #define E1000_MIN_TXD 64
50
51 #define E1000_DEFAULT_RXD 256
52 #define E1000_MAX_RXD 4096
53 #define E1000_MIN_RXD 64
54
55 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
56 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
57
58 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
59
60 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
61 /* How many Rx Buffers do we bundle into one write to the hardware ? */
62 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
63
64 #define AUTO_ALL_MODES 0
65 #define E1000_EEPROM_APME 0x0400
66
67 #define E1000_MNG_VLAN_NONE (-1)
68
69 #define DEFAULT_JUMBO 9234
70
71 /* Time to wait before putting the device into D3 if there's no link (in ms). */
72 #define LINK_TIMEOUT 100
73
74 /* Count for polling __E1000_RESET condition every 10-20msec.
75 * Experimentation has shown the reset can take approximately 210msec.
76 */
77 #define E1000_CHECK_RESET_COUNT 25
78
79 #define PCICFG_DESC_RING_STATUS 0xe4
80 #define FLUSH_DESC_REQUIRED 0x100
81
82 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
83 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
84 * WTHRESH=4, so a setting of 5 gives the most efficient bus
85 * utilization but to avoid possible Tx stalls, set it to 1
86 */
87 #define E1000_TXDCTL_DMA_BURST_ENABLE \
88 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
89 E1000_TXDCTL_COUNT_DESC | \
90 (1u << 16) | /* wthresh must be +1 more than desired */\
91 (1u << 8) | /* hthresh */ \
92 0x1f) /* pthresh */
93
94 #define E1000_RXDCTL_DMA_BURST_ENABLE \
95 (0x01000000 | /* set descriptor granularity */ \
96 (4u << 16) | /* set writeback threshold */ \
97 (4u << 8) | /* set prefetch threshold */ \
98 0x20) /* set hthresh */
99
100 #define E1000_TIDV_FPD BIT(31)
101 #define E1000_RDTR_FPD BIT(31)
102
103 enum e1000_boards {
104 board_82571,
105 board_82572,
106 board_82573,
107 board_82574,
108 board_82583,
109 board_80003es2lan,
110 board_ich8lan,
111 board_ich9lan,
112 board_ich10lan,
113 board_pchlan,
114 board_pch2lan,
115 board_pch_lpt,
116 board_pch_spt,
117 board_pch_cnp,
118 board_pch_tgp,
119 board_pch_adp,
120 board_pch_mtp
121 };
122
123 struct e1000_ps_page {
124 struct page *page;
125 u64 dma; /* must be u64 - written to hw */
126 };
127
128 /* wrappers around a pointer to a socket buffer,
129 * so a DMA handle can be stored along with the buffer
130 */
131 struct e1000_buffer {
132 dma_addr_t dma;
133 struct sk_buff *skb;
134 union {
135 /* Tx */
136 struct {
137 unsigned long time_stamp;
138 u16 length;
139 u16 next_to_watch;
140 unsigned int segs;
141 unsigned int bytecount;
142 u16 mapped_as_page;
143 };
144 /* Rx */
145 struct {
146 /* arrays of page information for packet split */
147 struct e1000_ps_page *ps_pages;
148 struct page *page;
149 };
150 };
151 };
152
153 struct e1000_ring {
154 struct e1000_adapter *adapter; /* back pointer to adapter */
155 void *desc; /* pointer to ring memory */
156 dma_addr_t dma; /* phys address of ring */
157 unsigned int size; /* length of ring in bytes */
158 unsigned int count; /* number of desc. in ring */
159
160 u16 next_to_use;
161 u16 next_to_clean;
162
163 void __iomem *head;
164 void __iomem *tail;
165
166 /* array of buffer information structs */
167 struct e1000_buffer *buffer_info;
168
169 char name[IFNAMSIZ + 5];
170 u32 ims_val;
171 u32 itr_val;
172 void __iomem *itr_register;
173 int set_itr;
174
175 struct sk_buff *rx_skb_top;
176 };
177
178 /* PHY register snapshot values */
179 struct e1000_phy_regs {
180 u16 bmcr; /* basic mode control register */
181 u16 bmsr; /* basic mode status register */
182 u16 advertise; /* auto-negotiation advertisement */
183 u16 lpa; /* link partner ability register */
184 u16 expansion; /* auto-negotiation expansion reg */
185 u16 ctrl1000; /* 1000BASE-T control register */
186 u16 stat1000; /* 1000BASE-T status register */
187 u16 estatus; /* extended status register */
188 };
189
190 /* board specific private data structure */
191 struct e1000_adapter {
192 struct timer_list watchdog_timer;
193 struct timer_list phy_info_timer;
194 struct timer_list blink_timer;
195
196 struct work_struct reset_task;
197 struct work_struct watchdog_task;
198
199 const struct e1000_info *ei;
200
201 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
202 u32 bd_number;
203 u32 rx_buffer_len;
204 u16 mng_vlan_id;
205 u16 link_speed;
206 u16 link_duplex;
207 u16 eeprom_vers;
208
209 /* track device up/down/testing state */
210 unsigned long state;
211
212 /* Interrupt Throttle Rate */
213 u32 itr;
214 u32 itr_setting;
215 u16 tx_itr;
216 u16 rx_itr;
217
218 /* Tx - one ring per active queue */
219 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
220 u32 tx_fifo_limit;
221
222 struct napi_struct napi;
223
224 unsigned int uncorr_errors; /* uncorrectable ECC errors */
225 unsigned int corr_errors; /* correctable ECC errors */
226 unsigned int restart_queue;
227 u32 txd_cmd;
228
229 bool detect_tx_hung;
230 bool tx_hang_recheck;
231 u8 tx_timeout_factor;
232
233 u32 tx_int_delay;
234 u32 tx_abs_int_delay;
235
236 unsigned int total_tx_bytes;
237 unsigned int total_tx_packets;
238 unsigned int total_rx_bytes;
239 unsigned int total_rx_packets;
240
241 /* Tx stats */
242 u64 tpt_old;
243 u64 colc_old;
244 u32 gotc;
245 u64 gotc_old;
246 u32 tx_timeout_count;
247 u32 tx_fifo_head;
248 u32 tx_head_addr;
249 u32 tx_fifo_size;
250 u32 tx_dma_failed;
251 u32 tx_hwtstamp_timeouts;
252 u32 tx_hwtstamp_skipped;
253
254 /* Rx */
255 bool (*clean_rx)(struct e1000_ring *ring, int *work_done,
256 int work_to_do) ____cacheline_aligned_in_smp;
257 void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count,
258 gfp_t gfp);
259 struct e1000_ring *rx_ring;
260
261 u32 rx_int_delay;
262 u32 rx_abs_int_delay;
263
264 /* Rx stats */
265 u64 hw_csum_err;
266 u64 hw_csum_good;
267 u64 rx_hdr_split;
268 u32 gorc;
269 u64 gorc_old;
270 u32 alloc_rx_buff_failed;
271 u32 rx_dma_failed;
272 u32 rx_hwtstamp_cleared;
273
274 unsigned int rx_ps_pages;
275 u16 rx_ps_bsize0;
276 u32 max_frame_size;
277 u32 min_frame_size;
278
279 /* OS defined structs */
280 struct net_device *netdev;
281 struct pci_dev *pdev;
282
283 /* structs defined in e1000_hw.h */
284 struct e1000_hw hw;
285
286 spinlock_t stats64_lock; /* protects statistics counters */
287 struct e1000_hw_stats stats;
288 struct e1000_phy_info phy_info;
289 struct e1000_phy_stats phy_stats;
290
291 /* Snapshot of PHY registers */
292 struct e1000_phy_regs phy_regs;
293
294 struct e1000_ring test_tx_ring;
295 struct e1000_ring test_rx_ring;
296 u32 test_icr;
297
298 u32 msg_enable;
299 unsigned int num_vectors;
300 struct msix_entry *msix_entries;
301 int int_mode;
302 u32 eiac_mask;
303
304 u32 eeprom_wol;
305 u32 wol;
306 u32 pba;
307 u32 max_hw_frame_size;
308
309 bool fc_autoneg;
310
311 unsigned int flags;
312 unsigned int flags2;
313 struct work_struct downshift_task;
314 struct work_struct update_phy_task;
315 struct work_struct print_hang_task;
316
317 int phy_hang_count;
318
319 u16 tx_ring_count;
320 u16 rx_ring_count;
321
322 struct hwtstamp_config hwtstamp_config;
323 struct delayed_work systim_overflow_work;
324 struct sk_buff *tx_hwtstamp_skb;
325 unsigned long tx_hwtstamp_start;
326 struct work_struct tx_hwtstamp_work;
327 spinlock_t systim_lock; /* protects SYSTIML/H regsters */
328 struct cyclecounter cc;
329 struct timecounter tc;
330 struct ptp_clock *ptp_clock;
331 struct ptp_clock_info ptp_clock_info;
332 struct pm_qos_request pm_qos_req;
333 long ptp_delta;
334
335 u16 eee_advert;
336 };
337
338 struct e1000_info {
339 enum e1000_mac_type mac;
340 unsigned int flags;
341 unsigned int flags2;
342 u32 pba;
343 u32 max_hw_frame_size;
344 s32 (*get_variants)(struct e1000_adapter *);
345 const struct e1000_mac_operations *mac_ops;
346 const struct e1000_phy_operations *phy_ops;
347 const struct e1000_nvm_operations *nvm_ops;
348 };
349
350 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
351
352 /* The system time is maintained by a 64-bit counter comprised of the 32-bit
353 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
354 * its resolution) is based on the contents of the TIMINCA register - it
355 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
356 * For the best accuracy, the incperiod should be as small as possible. The
357 * incvalue is scaled by a factor as large as possible (while still fitting
358 * in bits 23:0) so that relatively small clock corrections can be made.
359 *
360 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
361 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
362 * bits to count nanoseconds leaving the rest for fractional nonseconds.
363 *
364 * Any given INCVALUE also has an associated maximum adjustment value. This
365 * maximum adjustment value is the largest increase (or decrease) which can be
366 * safely applied without overflowing the INCVALUE. Since INCVALUE has
367 * a maximum range of 24 bits, its largest value is 0xFFFFFF.
368 *
369 * To understand where the maximum value comes from, consider the following
370 * equation:
371 *
372 * new_incval = base_incval + (base_incval * adjustment) / 1billion
373 *
374 * To avoid overflow that means:
375 * max_incval = base_incval + (base_incval * max_adj) / billion
376 *
377 * Re-arranging:
378 * max_adj = floor(((max_incval - base_incval) * 1billion) / 1billion)
379 */
380 #define INCVALUE_96MHZ 125
381 #define INCVALUE_SHIFT_96MHZ 17
382 #define INCPERIOD_SHIFT_96MHZ 2
383 #define INCPERIOD_96MHZ (12 >> INCPERIOD_SHIFT_96MHZ)
384 #define MAX_PPB_96MHZ 23999900 /* 23,999,900 ppb */
385
386 #define INCVALUE_25MHZ 40
387 #define INCVALUE_SHIFT_25MHZ 18
388 #define INCPERIOD_25MHZ 1
389 #define MAX_PPB_25MHZ 599999900 /* 599,999,900 ppb */
390
391 #define INCVALUE_24MHZ 125
392 #define INCVALUE_SHIFT_24MHZ 14
393 #define INCPERIOD_24MHZ 3
394 #define MAX_PPB_24MHZ 999999999 /* 999,999,999 ppb */
395
396 #define INCVALUE_38400KHZ 26
397 #define INCVALUE_SHIFT_38400KHZ 19
398 #define INCPERIOD_38400KHZ 1
399 #define MAX_PPB_38400KHZ 230769100 /* 230,769,100 ppb */
400
401 /* Another drawback of scaling the incvalue by a large factor is the
402 * 64-bit SYSTIM register overflows more quickly. This is dealt with
403 * by simply reading the clock before it overflows.
404 *
405 * Clock ns bits Overflows after
406 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
407 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
408 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
409 */
410 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
411 #define E1000_MAX_82574_SYSTIM_REREADS 50
412 #define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL)
413
414 /* hardware capability, feature, and workaround flags */
415 #define FLAG_HAS_AMT BIT(0)
416 #define FLAG_HAS_FLASH BIT(1)
417 #define FLAG_HAS_HW_VLAN_FILTER BIT(2)
418 #define FLAG_HAS_WOL BIT(3)
419 /* reserved BIT(4) */
420 #define FLAG_HAS_CTRLEXT_ON_LOAD BIT(5)
421 #define FLAG_HAS_SWSM_ON_LOAD BIT(6)
422 #define FLAG_HAS_JUMBO_FRAMES BIT(7)
423 #define FLAG_READ_ONLY_NVM BIT(8)
424 #define FLAG_IS_ICH BIT(9)
425 #define FLAG_HAS_MSIX BIT(10)
426 #define FLAG_HAS_SMART_POWER_DOWN BIT(11)
427 #define FLAG_IS_QUAD_PORT_A BIT(12)
428 #define FLAG_IS_QUAD_PORT BIT(13)
429 #define FLAG_HAS_HW_TIMESTAMP BIT(14)
430 #define FLAG_APME_IN_WUC BIT(15)
431 #define FLAG_APME_IN_CTRL3 BIT(16)
432 #define FLAG_APME_CHECK_PORT_B BIT(17)
433 #define FLAG_DISABLE_FC_PAUSE_TIME BIT(18)
434 #define FLAG_NO_WAKE_UCAST BIT(19)
435 #define FLAG_MNG_PT_ENABLED BIT(20)
436 #define FLAG_RESET_OVERWRITES_LAA BIT(21)
437 #define FLAG_TARC_SPEED_MODE_BIT BIT(22)
438 #define FLAG_TARC_SET_BIT_ZERO BIT(23)
439 #define FLAG_RX_NEEDS_RESTART BIT(24)
440 #define FLAG_LSC_GIG_SPEED_DROP BIT(25)
441 #define FLAG_SMART_POWER_DOWN BIT(26)
442 #define FLAG_MSI_ENABLED BIT(27)
443 /* reserved BIT(28) */
444 #define FLAG_TSO_FORCE BIT(29)
445 #define FLAG_RESTART_NOW BIT(30)
446 #define FLAG_MSI_TEST_FAILED BIT(31)
447
448 #define FLAG2_CRC_STRIPPING BIT(0)
449 #define FLAG2_HAS_PHY_WAKEUP BIT(1)
450 #define FLAG2_IS_DISCARDING BIT(2)
451 #define FLAG2_DISABLE_ASPM_L1 BIT(3)
452 #define FLAG2_HAS_PHY_STATS BIT(4)
453 #define FLAG2_HAS_EEE BIT(5)
454 #define FLAG2_DMA_BURST BIT(6)
455 #define FLAG2_DISABLE_ASPM_L0S BIT(7)
456 #define FLAG2_DISABLE_AIM BIT(8)
457 #define FLAG2_CHECK_PHY_HANG BIT(9)
458 #define FLAG2_NO_DISABLE_RX BIT(10)
459 #define FLAG2_PCIM2PCI_ARBITER_WA BIT(11)
460 #define FLAG2_DFLT_CRC_STRIPPING BIT(12)
461 #define FLAG2_CHECK_RX_HWTSTAMP BIT(13)
462 #define FLAG2_CHECK_SYSTIM_OVERFLOW BIT(14)
463 #define FLAG2_ENABLE_S0IX_FLOWS BIT(15)
464
465 #define E1000_RX_DESC_PS(R, i) \
466 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
467 #define E1000_RX_DESC_EXT(R, i) \
468 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
469 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
470 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
471 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
472
473 enum e1000_state_t {
474 __E1000_TESTING,
475 __E1000_RESETTING,
476 __E1000_ACCESS_SHARED_RESOURCE,
477 __E1000_DOWN
478 };
479
480 enum latency_range {
481 lowest_latency = 0,
482 low_latency = 1,
483 bulk_latency = 2,
484 latency_invalid = 255
485 };
486
487 extern char e1000e_driver_name[];
488
489 void e1000e_check_options(struct e1000_adapter *adapter);
490 void e1000e_set_ethtool_ops(struct net_device *netdev);
491
492 int e1000e_open(struct net_device *netdev);
493 int e1000e_close(struct net_device *netdev);
494 void e1000e_up(struct e1000_adapter *adapter);
495 void e1000e_down(struct e1000_adapter *adapter, bool reset);
496 void e1000e_reinit_locked(struct e1000_adapter *adapter);
497 void e1000e_reset(struct e1000_adapter *adapter);
498 void e1000e_power_up_phy(struct e1000_adapter *adapter);
499 int e1000e_setup_rx_resources(struct e1000_ring *ring);
500 int e1000e_setup_tx_resources(struct e1000_ring *ring);
501 void e1000e_free_rx_resources(struct e1000_ring *ring);
502 void e1000e_free_tx_resources(struct e1000_ring *ring);
503 void e1000e_get_stats64(struct net_device *netdev,
504 struct rtnl_link_stats64 *stats);
505 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
506 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
507 void e1000e_get_hw_control(struct e1000_adapter *adapter);
508 void e1000e_release_hw_control(struct e1000_adapter *adapter);
509 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
510
511 extern unsigned int copybreak;
512
513 extern const struct e1000_info e1000_82571_info;
514 extern const struct e1000_info e1000_82572_info;
515 extern const struct e1000_info e1000_82573_info;
516 extern const struct e1000_info e1000_82574_info;
517 extern const struct e1000_info e1000_82583_info;
518 extern const struct e1000_info e1000_ich8_info;
519 extern const struct e1000_info e1000_ich9_info;
520 extern const struct e1000_info e1000_ich10_info;
521 extern const struct e1000_info e1000_pch_info;
522 extern const struct e1000_info e1000_pch2_info;
523 extern const struct e1000_info e1000_pch_lpt_info;
524 extern const struct e1000_info e1000_pch_spt_info;
525 extern const struct e1000_info e1000_pch_cnp_info;
526 extern const struct e1000_info e1000_pch_tgp_info;
527 extern const struct e1000_info e1000_pch_adp_info;
528 extern const struct e1000_info e1000_pch_mtp_info;
529 extern const struct e1000_info e1000_es2_info;
530
531 void e1000e_ptp_init(struct e1000_adapter *adapter);
532 void e1000e_ptp_remove(struct e1000_adapter *adapter);
533
534 u64 e1000e_read_systim(struct e1000_adapter *adapter,
535 struct ptp_system_timestamp *sts);
536
e1000_phy_hw_reset(struct e1000_hw * hw)537 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
538 {
539 return hw->phy.ops.reset(hw);
540 }
541
e1e_rphy(struct e1000_hw * hw,u32 offset,u16 * data)542 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
543 {
544 return hw->phy.ops.read_reg(hw, offset, data);
545 }
546
e1e_rphy_locked(struct e1000_hw * hw,u32 offset,u16 * data)547 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
548 {
549 return hw->phy.ops.read_reg_locked(hw, offset, data);
550 }
551
e1e_wphy(struct e1000_hw * hw,u32 offset,u16 data)552 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
553 {
554 return hw->phy.ops.write_reg(hw, offset, data);
555 }
556
e1e_wphy_locked(struct e1000_hw * hw,u32 offset,u16 data)557 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
558 {
559 return hw->phy.ops.write_reg_locked(hw, offset, data);
560 }
561
562 void e1000e_reload_nvm_generic(struct e1000_hw *hw);
563
e1000e_read_mac_addr(struct e1000_hw * hw)564 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
565 {
566 if (hw->mac.ops.read_mac_addr)
567 return hw->mac.ops.read_mac_addr(hw);
568
569 return e1000_read_mac_addr_generic(hw);
570 }
571
e1000_validate_nvm_checksum(struct e1000_hw * hw)572 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
573 {
574 return hw->nvm.ops.validate(hw);
575 }
576
e1000e_update_nvm_checksum(struct e1000_hw * hw)577 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
578 {
579 return hw->nvm.ops.update(hw);
580 }
581
e1000_read_nvm(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)582 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
583 u16 *data)
584 {
585 return hw->nvm.ops.read(hw, offset, words, data);
586 }
587
e1000_write_nvm(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)588 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
589 u16 *data)
590 {
591 return hw->nvm.ops.write(hw, offset, words, data);
592 }
593
e1000_get_phy_info(struct e1000_hw * hw)594 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
595 {
596 return hw->phy.ops.get_info(hw);
597 }
598
__er32(struct e1000_hw * hw,unsigned long reg)599 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
600 {
601 return readl(hw->hw_addr + reg);
602 }
603
604 #define er32(reg) __er32(hw, E1000_##reg)
605
606 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);
607
608 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
609
610 #define e1e_flush() er32(STATUS)
611
612 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
613 (__ew32((a), (reg + ((offset) << 2)), (value)))
614
615 #define E1000_READ_REG_ARRAY(a, reg, offset) \
616 (readl((a)->hw_addr + reg + ((offset) << 2)))
617
618 #endif /* _E1000_H_ */
619