1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022-2023 Intel Corporation 4 */ 5 6 #ifndef _XE_GT_TYPES_H_ 7 #define _XE_GT_TYPES_H_ 8 9 #include "xe_device_types.h" 10 #include "xe_force_wake_types.h" 11 #include "xe_gt_idle_types.h" 12 #include "xe_gt_sriov_pf_types.h" 13 #include "xe_gt_sriov_vf_types.h" 14 #include "xe_gt_stats_types.h" 15 #include "xe_hw_engine_types.h" 16 #include "xe_hw_fence_types.h" 17 #include "xe_oa_types.h" 18 #include "xe_reg_sr_types.h" 19 #include "xe_sa_types.h" 20 #include "xe_tlb_inval_types.h" 21 #include "xe_uc_types.h" 22 23 struct xe_exec_queue_ops; 24 struct xe_migrate; 25 struct xe_ring_ops; 26 27 enum xe_gt_type { 28 XE_GT_TYPE_UNINITIALIZED, 29 XE_GT_TYPE_MAIN, 30 XE_GT_TYPE_MEDIA, 31 }; 32 33 enum xe_gt_eu_type { 34 XE_GT_EU_TYPE_SIMD8, 35 XE_GT_EU_TYPE_SIMD16, 36 }; 37 38 #define XE_MAX_DSS_FUSE_REGS 4 39 #define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS) 40 #define XE_MAX_EU_FUSE_REGS 1 41 #define XE_MAX_EU_FUSE_BITS (32 * XE_MAX_EU_FUSE_REGS) 42 #define XE_MAX_L3_BANK_MASK_BITS 64 43 44 typedef unsigned long xe_dss_mask_t[BITS_TO_LONGS(XE_MAX_DSS_FUSE_BITS)]; 45 typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(XE_MAX_EU_FUSE_BITS)]; 46 typedef unsigned long xe_l3_bank_mask_t[BITS_TO_LONGS(XE_MAX_L3_BANK_MASK_BITS)]; 47 48 /* 49 * The hardware has multiple kinds of multicast register ranges that need 50 * special register steering (and future platforms are expected to add 51 * additional types). 52 * 53 * During driver startup, we initialize the steering control register to 54 * direct reads to a slice/subslice that are valid for the 'subslice' class 55 * of multicast registers. If another type of steering does not have any 56 * overlap in valid steering targets with 'subslice' style registers, we will 57 * need to explicitly re-steer reads of registers of the other type. 58 * 59 * Only the replication types that may need additional non-default steering 60 * are listed here. 61 */ 62 enum xe_steering_type { 63 L3BANK, 64 NODE, 65 MSLICE, 66 LNCF, 67 DSS, 68 OADDRM, 69 SQIDI_PSMI, 70 71 /* 72 * Although most GAM ranges must be steered to (0,0) and thus use the 73 * INSTANCE0 type farther down, some platforms have special rules 74 * for specific subtypes that require steering to (1,0) instead. 75 */ 76 GAM1, 77 78 /* 79 * On some platforms there are multiple types of MCR registers that 80 * will always return a non-terminated value at instance (0, 0). We'll 81 * lump those all into a single category to keep things simple. 82 */ 83 INSTANCE0, 84 85 /* 86 * Register ranges that don't need special steering for each register: 87 * it's sufficient to keep the HW-default for the selector, or only 88 * change it once, on GT initialization. This needs to be the last 89 * steering type. 90 */ 91 IMPLICIT_STEERING, 92 NUM_STEERING_TYPES 93 }; 94 95 #define gt_to_tile(gt__) \ 96 _Generic(gt__, \ 97 const struct xe_gt * : (const struct xe_tile *)((gt__)->tile), \ 98 struct xe_gt * : (gt__)->tile) 99 100 #define gt_to_xe(gt__) \ 101 _Generic(gt__, \ 102 const struct xe_gt * : (const struct xe_device *)(gt_to_tile(gt__)->xe), \ 103 struct xe_gt * : gt_to_tile(gt__)->xe) 104 105 /** 106 * struct xe_gt - A "Graphics Technology" unit of the GPU 107 * 108 * A GT ("Graphics Technology") is the subset of a GPU primarily responsible 109 * for implementing the graphics, compute, and/or media IP. It encapsulates 110 * the hardware engines, programmable execution units, and GuC. Each GT has 111 * its own handling of power management (RC6+forcewake) and multicast register 112 * steering. 113 * 114 * A GPU/tile may have a single GT that supplies all graphics, compute, and 115 * media functionality, or the graphics/compute and media may be split into 116 * separate GTs within a tile. 117 */ 118 struct xe_gt { 119 /** @tile: Backpointer to GT's tile */ 120 struct xe_tile *tile; 121 122 /** @info: GT info */ 123 struct { 124 /** @info.type: type of GT */ 125 enum xe_gt_type type; 126 /** @info.reference_clock: clock frequency */ 127 u32 reference_clock; 128 /** @info.timestamp_base: GT timestamp base */ 129 u32 timestamp_base; 130 /** 131 * @info.engine_mask: mask of engines present on GT. Some of 132 * them may be reserved in runtime and not available for user. 133 * See @user_engines.mask 134 */ 135 u64 engine_mask; 136 /** @info.gmdid: raw GMD_ID value from hardware */ 137 u32 gmdid; 138 /** 139 * @multi_queue_engine_class_mask: Bitmask of engine classes with 140 * multi queue support enabled. 141 */ 142 u16 multi_queue_engine_class_mask; 143 /** @info.id: Unique ID of this GT within the PCI Device */ 144 u8 id; 145 /** @info.has_indirect_ring_state: GT has indirect ring state support */ 146 u8 has_indirect_ring_state:1; 147 /** 148 * @info.has_xe2_blt_instructions: GT supports Xe2-style MEM_SET 149 * and MEM_COPY blitter functionality. Note that despite the 150 * name, some Xe1 platforms may also support this "Xe2-style" 151 * feature. 152 */ 153 u8 has_xe2_blt_instructions:1; 154 /** 155 * @info.num_geometry_xecore_fuse_regs: Number of 32b-bit fuse 156 * registers the geometry XeCore mask spans. 157 */ 158 u8 num_geometry_xecore_fuse_regs; 159 /** 160 * @info.num_compute_xecore_fuse_regs: Number of 32b-bit fuse 161 * registers the compute XeCore mask spans. 162 */ 163 u8 num_compute_xecore_fuse_regs; 164 } info; 165 166 #if IS_ENABLED(CONFIG_DEBUG_FS) 167 /** @stats: GT stats */ 168 struct xe_gt_stats __percpu *stats; 169 #endif 170 171 /** 172 * @mmio: mmio info for GT. All GTs within a tile share the same 173 * register space, but have their own copy of GSI registers at a 174 * specific offset. 175 */ 176 struct xe_mmio mmio; 177 178 /** 179 * @pm: power management info for GT. The driver uses the GT's 180 * "force wake" interface to wake up specific parts of the GT hardware 181 * from C6 sleep states and ensure the hardware remains awake while it 182 * is being actively used. 183 */ 184 struct { 185 /** @pm.fw: force wake for GT */ 186 struct xe_force_wake fw; 187 } pm; 188 189 /** @sriov: virtualization data related to GT */ 190 union { 191 /** @sriov.pf: PF data. Valid only if driver is running as PF */ 192 struct xe_gt_sriov_pf pf; 193 /** @sriov.vf: VF data. Valid only if driver is running as VF */ 194 struct xe_gt_sriov_vf vf; 195 } sriov; 196 197 /** 198 * @reg_sr: table with registers to be restored on GT init/resume/reset 199 */ 200 struct xe_reg_sr reg_sr; 201 202 /** @reset: state for GT resets */ 203 struct { 204 /** 205 * @reset.worker: work so GT resets can done async allowing to reset 206 * code to safely flush all code paths 207 */ 208 struct work_struct worker; 209 } reset; 210 211 /** @tlb_inval: TLB invalidation state */ 212 struct xe_tlb_inval tlb_inval; 213 214 /** 215 * @ccs_mode: Number of compute engines enabled. 216 * Allows fixed mapping of available compute slices to compute engines. 217 * By default only the first available compute engine is enabled and all 218 * available compute slices are allocated to it. 219 */ 220 u32 ccs_mode; 221 222 /** @usm: unified shared memory state */ 223 struct { 224 /** 225 * @usm.bb_pool: Pool from which batchbuffers, for USM operations 226 * (e.g. migrations, fixing page tables), are allocated. 227 * Dedicated pool needed so USM operations do not get blocked 228 * behind any user operations which may have resulted in a 229 * fault. 230 */ 231 struct xe_sa_manager *bb_pool; 232 /** 233 * @usm.reserved_bcs_instance: reserved BCS instance used for USM 234 * operations (e.g. migrations, fixing page tables) 235 */ 236 u16 reserved_bcs_instance; 237 } usm; 238 239 /** @ordered_wq: used to serialize GT resets and TDRs */ 240 struct workqueue_struct *ordered_wq; 241 242 /** @uc: micro controllers on the GT */ 243 struct xe_uc uc; 244 245 /** @gtidle: idle properties of GT */ 246 struct xe_gt_idle gtidle; 247 248 /** @exec_queue_ops: submission backend exec queue operations */ 249 const struct xe_exec_queue_ops *exec_queue_ops; 250 251 /** 252 * @ring_ops: ring operations for this hw engine (1 per engine class) 253 */ 254 const struct xe_ring_ops *ring_ops[XE_ENGINE_CLASS_MAX]; 255 256 /** @fence_irq: fence IRQs (1 per engine class) */ 257 struct xe_hw_fence_irq fence_irq[XE_ENGINE_CLASS_MAX]; 258 259 /** @default_lrc: default LRC state */ 260 void *default_lrc[XE_ENGINE_CLASS_MAX]; 261 262 /** @hw_engines: hardware engines on the GT */ 263 struct xe_hw_engine hw_engines[XE_NUM_HW_ENGINES]; 264 265 /** @eclass: per hardware engine class interface on the GT */ 266 struct xe_hw_engine_class_intf eclass[XE_ENGINE_CLASS_MAX]; 267 268 /** @sysfs: sysfs' kobj used by xe_gt_sysfs */ 269 struct kobject *sysfs; 270 271 /** @freq: Main GT freq sysfs control */ 272 struct kobject *freq; 273 274 /** @mocs: info */ 275 struct { 276 /** @mocs.uc_index: UC index */ 277 u8 uc_index; 278 /** @mocs.wb_index: WB index, only used on L3_CCS platforms */ 279 u8 wb_index; 280 } mocs; 281 282 /** @fuse_topo: GT topology reported by fuse registers */ 283 struct { 284 /** @fuse_topo.g_dss_mask: dual-subslices usable by geometry */ 285 xe_dss_mask_t g_dss_mask; 286 287 /** @fuse_topo.c_dss_mask: dual-subslices usable by compute */ 288 xe_dss_mask_t c_dss_mask; 289 290 /** @fuse_topo.eu_mask_per_dss: EU mask per DSS*/ 291 xe_eu_mask_t eu_mask_per_dss; 292 293 /** @fuse_topo.l3_bank_mask: L3 bank mask */ 294 xe_l3_bank_mask_t l3_bank_mask; 295 296 /** 297 * @fuse_topo.eu_type: type/width of EU stored in 298 * fuse_topo.eu_mask_per_dss 299 */ 300 enum xe_gt_eu_type eu_type; 301 } fuse_topo; 302 303 /** @steering: register steering for individual HW units */ 304 struct { 305 /** @steering.ranges: register ranges used for this steering type */ 306 const struct xe_mmio_range *ranges; 307 308 /** @steering.group_target: target to steer accesses to */ 309 u16 group_target; 310 /** @steering.instance_target: instance to steer accesses to */ 311 u16 instance_target; 312 /** @steering.initialized: Whether this steering range is initialized */ 313 bool initialized; 314 } steering[NUM_STEERING_TYPES]; 315 316 /** 317 * @steering_dss_per_grp: number of DSS per steering group (gslice, 318 * cslice, etc.). 319 */ 320 unsigned int steering_dss_per_grp; 321 322 /** 323 * @mcr_lock: protects the MCR_SELECTOR register for the duration 324 * of a steered operation 325 */ 326 spinlock_t mcr_lock; 327 328 /** 329 * @global_invl_lock: protects the register for the duration 330 * of a global invalidation of l2 cache 331 */ 332 spinlock_t global_invl_lock; 333 334 /** @wa_active: keep track of active workarounds */ 335 struct { 336 /** @wa_active.gt: bitmap with active GT workarounds */ 337 unsigned long *gt; 338 /** @wa_active.engine: bitmap with active engine workarounds */ 339 unsigned long *engine; 340 /** @wa_active.lrc: bitmap with active LRC workarounds */ 341 unsigned long *lrc; 342 /** @wa_active.oob: bitmap with active OOB workarounds */ 343 unsigned long *oob; 344 /** 345 * @wa_active.oob_initialized: mark oob as initialized to help 346 * detecting misuse of XE_GT_WA() - it can only be called on 347 * initialization after OOB WAs have been processed 348 */ 349 bool oob_initialized; 350 } wa_active; 351 352 /** @tuning_active: keep track of active tunings */ 353 struct { 354 /** @tuning_active.gt: bitmap with active GT tunings */ 355 unsigned long *gt; 356 /** @tuning_active.engine: bitmap with active engine tunings */ 357 unsigned long *engine; 358 /** @tuning_active.lrc: bitmap with active LRC tunings */ 359 unsigned long *lrc; 360 } tuning_active; 361 362 /** @user_engines: engines present in GT and available to userspace */ 363 struct { 364 /** 365 * @user_engines.mask: like @info->engine_mask, but take in 366 * consideration only engines available to userspace 367 */ 368 u64 mask; 369 370 /** 371 * @user_engines.instances_per_class: aggregate per class the 372 * number of engines available to userspace 373 */ 374 u8 instances_per_class[XE_ENGINE_CLASS_MAX]; 375 } user_engines; 376 377 /** @oa: oa observation subsystem per gt info */ 378 struct xe_oa_gt oa; 379 380 /** @eu_stall: EU stall counters subsystem per gt info */ 381 struct xe_eu_stall_gt *eu_stall; 382 }; 383 384 #endif 385