1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "umc_v12_0.h" 60 #include "hdp_v4_0.h" 61 #include "mca_v3_0.h" 62 63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 64 65 #include "amdgpu_ras.h" 66 #include "amdgpu_xgmi.h" 67 68 /* add these here since we already include dce12 headers and these are for DCN */ 69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 77 78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 80 81 #define MAX_MEM_RANGES 8 82 83 static const char * const gfxhub_client_ids[] = { 84 "CB", 85 "DB", 86 "IA", 87 "WD", 88 "CPF", 89 "CPC", 90 "CPG", 91 "RLC", 92 "TCP", 93 "SQC (inst)", 94 "SQC (data)", 95 "SQG", 96 "PA", 97 }; 98 99 static const char *mmhub_client_ids_raven[][2] = { 100 [0][0] = "MP1", 101 [1][0] = "MP0", 102 [2][0] = "VCN", 103 [3][0] = "VCNU", 104 [4][0] = "HDP", 105 [5][0] = "DCE", 106 [13][0] = "UTCL2", 107 [19][0] = "TLS", 108 [26][0] = "OSS", 109 [27][0] = "SDMA0", 110 [0][1] = "MP1", 111 [1][1] = "MP0", 112 [2][1] = "VCN", 113 [3][1] = "VCNU", 114 [4][1] = "HDP", 115 [5][1] = "XDP", 116 [6][1] = "DBGU0", 117 [7][1] = "DCE", 118 [8][1] = "DCEDWB0", 119 [9][1] = "DCEDWB1", 120 [26][1] = "OSS", 121 [27][1] = "SDMA0", 122 }; 123 124 static const char *mmhub_client_ids_renoir[][2] = { 125 [0][0] = "MP1", 126 [1][0] = "MP0", 127 [2][0] = "HDP", 128 [4][0] = "DCEDMC", 129 [5][0] = "DCEVGA", 130 [13][0] = "UTCL2", 131 [19][0] = "TLS", 132 [26][0] = "OSS", 133 [27][0] = "SDMA0", 134 [28][0] = "VCN", 135 [29][0] = "VCNU", 136 [30][0] = "JPEG", 137 [0][1] = "MP1", 138 [1][1] = "MP0", 139 [2][1] = "HDP", 140 [3][1] = "XDP", 141 [6][1] = "DBGU0", 142 [7][1] = "DCEDMC", 143 [8][1] = "DCEVGA", 144 [9][1] = "DCEDWB", 145 [26][1] = "OSS", 146 [27][1] = "SDMA0", 147 [28][1] = "VCN", 148 [29][1] = "VCNU", 149 [30][1] = "JPEG", 150 }; 151 152 static const char *mmhub_client_ids_vega10[][2] = { 153 [0][0] = "MP0", 154 [1][0] = "UVD", 155 [2][0] = "UVDU", 156 [3][0] = "HDP", 157 [13][0] = "UTCL2", 158 [14][0] = "OSS", 159 [15][0] = "SDMA1", 160 [32+0][0] = "VCE0", 161 [32+1][0] = "VCE0U", 162 [32+2][0] = "XDMA", 163 [32+3][0] = "DCE", 164 [32+4][0] = "MP1", 165 [32+14][0] = "SDMA0", 166 [0][1] = "MP0", 167 [1][1] = "UVD", 168 [2][1] = "UVDU", 169 [3][1] = "DBGU0", 170 [4][1] = "HDP", 171 [5][1] = "XDP", 172 [14][1] = "OSS", 173 [15][1] = "SDMA0", 174 [32+0][1] = "VCE0", 175 [32+1][1] = "VCE0U", 176 [32+2][1] = "XDMA", 177 [32+3][1] = "DCE", 178 [32+4][1] = "DCEDWB", 179 [32+5][1] = "MP1", 180 [32+6][1] = "DBGU1", 181 [32+14][1] = "SDMA1", 182 }; 183 184 static const char *mmhub_client_ids_vega12[][2] = { 185 [0][0] = "MP0", 186 [1][0] = "VCE0", 187 [2][0] = "VCE0U", 188 [3][0] = "HDP", 189 [13][0] = "UTCL2", 190 [14][0] = "OSS", 191 [15][0] = "SDMA1", 192 [32+0][0] = "DCE", 193 [32+1][0] = "XDMA", 194 [32+2][0] = "UVD", 195 [32+3][0] = "UVDU", 196 [32+4][0] = "MP1", 197 [32+15][0] = "SDMA0", 198 [0][1] = "MP0", 199 [1][1] = "VCE0", 200 [2][1] = "VCE0U", 201 [3][1] = "DBGU0", 202 [4][1] = "HDP", 203 [5][1] = "XDP", 204 [14][1] = "OSS", 205 [15][1] = "SDMA0", 206 [32+0][1] = "DCE", 207 [32+1][1] = "DCEDWB", 208 [32+2][1] = "XDMA", 209 [32+3][1] = "UVD", 210 [32+4][1] = "UVDU", 211 [32+5][1] = "MP1", 212 [32+6][1] = "DBGU1", 213 [32+15][1] = "SDMA1", 214 }; 215 216 static const char *mmhub_client_ids_vega20[][2] = { 217 [0][0] = "XDMA", 218 [1][0] = "DCE", 219 [2][0] = "VCE0", 220 [3][0] = "VCE0U", 221 [4][0] = "UVD", 222 [5][0] = "UVD1U", 223 [13][0] = "OSS", 224 [14][0] = "HDP", 225 [15][0] = "SDMA0", 226 [32+0][0] = "UVD", 227 [32+1][0] = "UVDU", 228 [32+2][0] = "MP1", 229 [32+3][0] = "MP0", 230 [32+12][0] = "UTCL2", 231 [32+14][0] = "SDMA1", 232 [0][1] = "XDMA", 233 [1][1] = "DCE", 234 [2][1] = "DCEDWB", 235 [3][1] = "VCE0", 236 [4][1] = "VCE0U", 237 [5][1] = "UVD1", 238 [6][1] = "UVD1U", 239 [7][1] = "DBGU0", 240 [8][1] = "XDP", 241 [13][1] = "OSS", 242 [14][1] = "HDP", 243 [15][1] = "SDMA0", 244 [32+0][1] = "UVD", 245 [32+1][1] = "UVDU", 246 [32+2][1] = "DBGU1", 247 [32+3][1] = "MP1", 248 [32+4][1] = "MP0", 249 [32+14][1] = "SDMA1", 250 }; 251 252 static const char *mmhub_client_ids_arcturus[][2] = { 253 [0][0] = "DBGU1", 254 [1][0] = "XDP", 255 [2][0] = "MP1", 256 [14][0] = "HDP", 257 [171][0] = "JPEG", 258 [172][0] = "VCN", 259 [173][0] = "VCNU", 260 [203][0] = "JPEG1", 261 [204][0] = "VCN1", 262 [205][0] = "VCN1U", 263 [256][0] = "SDMA0", 264 [257][0] = "SDMA1", 265 [258][0] = "SDMA2", 266 [259][0] = "SDMA3", 267 [260][0] = "SDMA4", 268 [261][0] = "SDMA5", 269 [262][0] = "SDMA6", 270 [263][0] = "SDMA7", 271 [384][0] = "OSS", 272 [0][1] = "DBGU1", 273 [1][1] = "XDP", 274 [2][1] = "MP1", 275 [14][1] = "HDP", 276 [171][1] = "JPEG", 277 [172][1] = "VCN", 278 [173][1] = "VCNU", 279 [203][1] = "JPEG1", 280 [204][1] = "VCN1", 281 [205][1] = "VCN1U", 282 [256][1] = "SDMA0", 283 [257][1] = "SDMA1", 284 [258][1] = "SDMA2", 285 [259][1] = "SDMA3", 286 [260][1] = "SDMA4", 287 [261][1] = "SDMA5", 288 [262][1] = "SDMA6", 289 [263][1] = "SDMA7", 290 [384][1] = "OSS", 291 }; 292 293 static const char *mmhub_client_ids_aldebaran[][2] = { 294 [2][0] = "MP1", 295 [3][0] = "MP0", 296 [32+1][0] = "DBGU_IO0", 297 [32+2][0] = "DBGU_IO2", 298 [32+4][0] = "MPIO", 299 [96+11][0] = "JPEG0", 300 [96+12][0] = "VCN0", 301 [96+13][0] = "VCNU0", 302 [128+11][0] = "JPEG1", 303 [128+12][0] = "VCN1", 304 [128+13][0] = "VCNU1", 305 [160+1][0] = "XDP", 306 [160+14][0] = "HDP", 307 [256+0][0] = "SDMA0", 308 [256+1][0] = "SDMA1", 309 [256+2][0] = "SDMA2", 310 [256+3][0] = "SDMA3", 311 [256+4][0] = "SDMA4", 312 [384+0][0] = "OSS", 313 [2][1] = "MP1", 314 [3][1] = "MP0", 315 [32+1][1] = "DBGU_IO0", 316 [32+2][1] = "DBGU_IO2", 317 [32+4][1] = "MPIO", 318 [96+11][1] = "JPEG0", 319 [96+12][1] = "VCN0", 320 [96+13][1] = "VCNU0", 321 [128+11][1] = "JPEG1", 322 [128+12][1] = "VCN1", 323 [128+13][1] = "VCNU1", 324 [160+1][1] = "XDP", 325 [160+14][1] = "HDP", 326 [256+0][1] = "SDMA0", 327 [256+1][1] = "SDMA1", 328 [256+2][1] = "SDMA2", 329 [256+3][1] = "SDMA3", 330 [256+4][1] = "SDMA4", 331 [384+0][1] = "OSS", 332 }; 333 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 337 }; 338 339 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 342 }; 343 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 345 (0x000143c0 + 0x00000000), 346 (0x000143c0 + 0x00000800), 347 (0x000143c0 + 0x00001000), 348 (0x000143c0 + 0x00001800), 349 (0x000543c0 + 0x00000000), 350 (0x000543c0 + 0x00000800), 351 (0x000543c0 + 0x00001000), 352 (0x000543c0 + 0x00001800), 353 (0x000943c0 + 0x00000000), 354 (0x000943c0 + 0x00000800), 355 (0x000943c0 + 0x00001000), 356 (0x000943c0 + 0x00001800), 357 (0x000d43c0 + 0x00000000), 358 (0x000d43c0 + 0x00000800), 359 (0x000d43c0 + 0x00001000), 360 (0x000d43c0 + 0x00001800), 361 (0x001143c0 + 0x00000000), 362 (0x001143c0 + 0x00000800), 363 (0x001143c0 + 0x00001000), 364 (0x001143c0 + 0x00001800), 365 (0x001543c0 + 0x00000000), 366 (0x001543c0 + 0x00000800), 367 (0x001543c0 + 0x00001000), 368 (0x001543c0 + 0x00001800), 369 (0x001943c0 + 0x00000000), 370 (0x001943c0 + 0x00000800), 371 (0x001943c0 + 0x00001000), 372 (0x001943c0 + 0x00001800), 373 (0x001d43c0 + 0x00000000), 374 (0x001d43c0 + 0x00000800), 375 (0x001d43c0 + 0x00001000), 376 (0x001d43c0 + 0x00001800), 377 }; 378 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 380 (0x000143e0 + 0x00000000), 381 (0x000143e0 + 0x00000800), 382 (0x000143e0 + 0x00001000), 383 (0x000143e0 + 0x00001800), 384 (0x000543e0 + 0x00000000), 385 (0x000543e0 + 0x00000800), 386 (0x000543e0 + 0x00001000), 387 (0x000543e0 + 0x00001800), 388 (0x000943e0 + 0x00000000), 389 (0x000943e0 + 0x00000800), 390 (0x000943e0 + 0x00001000), 391 (0x000943e0 + 0x00001800), 392 (0x000d43e0 + 0x00000000), 393 (0x000d43e0 + 0x00000800), 394 (0x000d43e0 + 0x00001000), 395 (0x000d43e0 + 0x00001800), 396 (0x001143e0 + 0x00000000), 397 (0x001143e0 + 0x00000800), 398 (0x001143e0 + 0x00001000), 399 (0x001143e0 + 0x00001800), 400 (0x001543e0 + 0x00000000), 401 (0x001543e0 + 0x00000800), 402 (0x001543e0 + 0x00001000), 403 (0x001543e0 + 0x00001800), 404 (0x001943e0 + 0x00000000), 405 (0x001943e0 + 0x00000800), 406 (0x001943e0 + 0x00001000), 407 (0x001943e0 + 0x00001800), 408 (0x001d43e0 + 0x00000000), 409 (0x001d43e0 + 0x00000800), 410 (0x001d43e0 + 0x00001000), 411 (0x001d43e0 + 0x00001800), 412 }; 413 414 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 415 struct amdgpu_irq_src *src, 416 unsigned int type, 417 enum amdgpu_interrupt_state state) 418 { 419 u32 bits, i, tmp, reg; 420 421 /* Devices newer then VEGA10/12 shall have these programming 422 * sequences performed by PSP BL 423 */ 424 if (adev->asic_type >= CHIP_VEGA20) 425 return 0; 426 427 bits = 0x7f; 428 429 switch (state) { 430 case AMDGPU_IRQ_STATE_DISABLE: 431 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 432 reg = ecc_umc_mcumc_ctrl_addrs[i]; 433 tmp = RREG32(reg); 434 tmp &= ~bits; 435 WREG32(reg, tmp); 436 } 437 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 438 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 439 tmp = RREG32(reg); 440 tmp &= ~bits; 441 WREG32(reg, tmp); 442 } 443 break; 444 case AMDGPU_IRQ_STATE_ENABLE: 445 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 446 reg = ecc_umc_mcumc_ctrl_addrs[i]; 447 tmp = RREG32(reg); 448 tmp |= bits; 449 WREG32(reg, tmp); 450 } 451 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 452 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 453 tmp = RREG32(reg); 454 tmp |= bits; 455 WREG32(reg, tmp); 456 } 457 break; 458 default: 459 break; 460 } 461 462 return 0; 463 } 464 465 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 466 struct amdgpu_irq_src *src, 467 unsigned int type, 468 enum amdgpu_interrupt_state state) 469 { 470 struct amdgpu_vmhub *hub; 471 u32 tmp, reg, bits, i, j; 472 473 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 480 481 switch (state) { 482 case AMDGPU_IRQ_STATE_DISABLE: 483 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 484 hub = &adev->vmhub[j]; 485 for (i = 0; i < 16; i++) { 486 reg = hub->vm_context0_cntl + i; 487 488 /* This works because this interrupt is only 489 * enabled at init/resume and disabled in 490 * fini/suspend, so the overall state doesn't 491 * change over the course of suspend/resume. 492 */ 493 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 494 continue; 495 496 if (j >= AMDGPU_MMHUB0(0)) 497 tmp = RREG32_SOC15_IP(MMHUB, reg); 498 else 499 tmp = RREG32_XCC(reg, j); 500 501 tmp &= ~bits; 502 503 if (j >= AMDGPU_MMHUB0(0)) 504 WREG32_SOC15_IP(MMHUB, reg, tmp); 505 else 506 WREG32_XCC(reg, tmp, j); 507 } 508 } 509 break; 510 case AMDGPU_IRQ_STATE_ENABLE: 511 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 512 hub = &adev->vmhub[j]; 513 for (i = 0; i < 16; i++) { 514 reg = hub->vm_context0_cntl + i; 515 516 /* This works because this interrupt is only 517 * enabled at init/resume and disabled in 518 * fini/suspend, so the overall state doesn't 519 * change over the course of suspend/resume. 520 */ 521 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 522 continue; 523 524 if (j >= AMDGPU_MMHUB0(0)) 525 tmp = RREG32_SOC15_IP(MMHUB, reg); 526 else 527 tmp = RREG32_XCC(reg, j); 528 529 tmp |= bits; 530 531 if (j >= AMDGPU_MMHUB0(0)) 532 WREG32_SOC15_IP(MMHUB, reg, tmp); 533 else 534 WREG32_XCC(reg, tmp, j); 535 } 536 } 537 break; 538 default: 539 break; 540 } 541 542 return 0; 543 } 544 545 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 546 struct amdgpu_irq_src *source, 547 struct amdgpu_iv_entry *entry) 548 { 549 bool retry_fault = !!(entry->src_data[1] & 0x80); 550 bool write_fault = !!(entry->src_data[1] & 0x20); 551 uint32_t status = 0, cid = 0, rw = 0, fed = 0; 552 struct amdgpu_task_info *task_info; 553 struct amdgpu_vmhub *hub; 554 const char *mmhub_cid; 555 const char *hub_name; 556 unsigned int vmhub; 557 u64 addr; 558 uint32_t cam_index = 0; 559 int ret, xcc_id = 0; 560 uint32_t node_id; 561 562 node_id = entry->node_id; 563 564 addr = (u64)entry->src_data[0] << 12; 565 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 566 567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 568 hub_name = "mmhub0"; 569 vmhub = AMDGPU_MMHUB0(node_id / 4); 570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 571 hub_name = "mmhub1"; 572 vmhub = AMDGPU_MMHUB1(0); 573 } else { 574 hub_name = "gfxhub0"; 575 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 577 node_id); 578 if (xcc_id < 0) 579 xcc_id = 0; 580 } 581 vmhub = xcc_id; 582 } 583 hub = &adev->vmhub[vmhub]; 584 585 if (retry_fault) { 586 if (adev->irq.retry_cam_enabled) { 587 /* Delegate it to a different ring if the hardware hasn't 588 * already done it. 589 */ 590 if (entry->ih == &adev->irq.ih) { 591 amdgpu_irq_delegate(adev, entry, 8); 592 return 1; 593 } 594 595 cam_index = entry->src_data[2] & 0x3ff; 596 597 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 598 addr, entry->timestamp, write_fault); 599 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 600 if (ret) 601 return 1; 602 } else { 603 /* Process it onyl if it's the first fault for this address */ 604 if (entry->ih != &adev->irq.ih_soft && 605 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 606 entry->timestamp)) 607 return 1; 608 609 /* Delegate it to a different ring if the hardware hasn't 610 * already done it. 611 */ 612 if (entry->ih == &adev->irq.ih) { 613 amdgpu_irq_delegate(adev, entry, 8); 614 return 1; 615 } 616 617 /* Try to handle the recoverable page faults by filling page 618 * tables 619 */ 620 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 621 addr, entry->timestamp, write_fault)) 622 return 1; 623 } 624 } 625 626 if (!printk_ratelimit()) 627 return 0; 628 629 dev_err(adev->dev, 630 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name, 631 retry_fault ? "retry" : "no-retry", 632 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 633 634 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 635 if (task_info) { 636 dev_err(adev->dev, 637 " for process %s pid %d thread %s pid %d)\n", 638 task_info->process_name, task_info->tgid, 639 task_info->task_name, task_info->pid); 640 amdgpu_vm_put_task_info(task_info); 641 } 642 643 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 644 addr, entry->client_id, 645 soc15_ih_clientid_name[entry->client_id]); 646 647 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 648 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 649 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 650 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 651 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 652 653 if (amdgpu_sriov_vf(adev)) 654 return 0; 655 656 /* 657 * Issue a dummy read to wait for the status register to 658 * be updated to avoid reading an incorrect value due to 659 * the new fast GRBM interface. 660 */ 661 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 662 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 663 RREG32(hub->vm_l2_pro_fault_status); 664 665 status = RREG32(hub->vm_l2_pro_fault_status); 666 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 667 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 668 fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED); 669 670 /* for fed error, kfd will handle it, return directly */ 671 if (fed && amdgpu_ras_is_poison_mode_supported(adev) && 672 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2))) 673 return 0; 674 675 if (!amdgpu_sriov_vf(adev)) 676 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 677 678 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 679 680 dev_err(adev->dev, 681 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 682 status); 683 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 684 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 685 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 686 gfxhub_client_ids[cid], 687 cid); 688 } else { 689 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 690 case IP_VERSION(9, 0, 0): 691 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 692 break; 693 case IP_VERSION(9, 3, 0): 694 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 695 break; 696 case IP_VERSION(9, 4, 0): 697 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 698 break; 699 case IP_VERSION(9, 4, 1): 700 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 701 break; 702 case IP_VERSION(9, 1, 0): 703 case IP_VERSION(9, 2, 0): 704 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 705 break; 706 case IP_VERSION(1, 5, 0): 707 case IP_VERSION(2, 4, 0): 708 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 709 break; 710 case IP_VERSION(1, 8, 0): 711 case IP_VERSION(9, 4, 2): 712 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 713 break; 714 default: 715 mmhub_cid = NULL; 716 break; 717 } 718 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 719 mmhub_cid ? mmhub_cid : "unknown", cid); 720 } 721 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 722 REG_GET_FIELD(status, 723 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 724 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 725 REG_GET_FIELD(status, 726 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 727 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 728 REG_GET_FIELD(status, 729 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 730 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 731 REG_GET_FIELD(status, 732 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 733 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 734 return 0; 735 } 736 737 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 738 .set = gmc_v9_0_vm_fault_interrupt_state, 739 .process = gmc_v9_0_process_interrupt, 740 }; 741 742 743 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 744 .set = gmc_v9_0_ecc_interrupt_state, 745 .process = amdgpu_umc_process_ecc_irq, 746 }; 747 748 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 749 { 750 adev->gmc.vm_fault.num_types = 1; 751 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 752 753 if (!amdgpu_sriov_vf(adev) && 754 !adev->gmc.xgmi.connected_to_cpu && 755 !adev->gmc.is_app_apu) { 756 adev->gmc.ecc_irq.num_types = 1; 757 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 758 } 759 } 760 761 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 762 uint32_t flush_type) 763 { 764 u32 req = 0; 765 766 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 767 PER_VMID_INVALIDATE_REQ, 1 << vmid); 768 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 769 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 770 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 771 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 772 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 773 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 774 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 775 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 776 777 return req; 778 } 779 780 /** 781 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 782 * 783 * @adev: amdgpu_device pointer 784 * @vmhub: vmhub type 785 * 786 */ 787 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 788 uint32_t vmhub) 789 { 790 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 791 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 792 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 793 return false; 794 795 return ((vmhub == AMDGPU_MMHUB0(0) || 796 vmhub == AMDGPU_MMHUB1(0)) && 797 (!amdgpu_sriov_vf(adev)) && 798 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 799 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 800 } 801 802 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 803 uint8_t vmid, uint16_t *p_pasid) 804 { 805 uint32_t value; 806 807 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 808 + vmid); 809 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 810 811 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 812 } 813 814 /* 815 * GART 816 * VMID 0 is the physical GPU addresses as used by the kernel. 817 * VMIDs 1-15 are used for userspace clients and are handled 818 * by the amdgpu vm/hsa code. 819 */ 820 821 /** 822 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 823 * 824 * @adev: amdgpu_device pointer 825 * @vmid: vm instance to flush 826 * @vmhub: which hub to flush 827 * @flush_type: the flush type 828 * 829 * Flush the TLB for the requested page table using certain type. 830 */ 831 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 832 uint32_t vmhub, uint32_t flush_type) 833 { 834 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 835 u32 j, inv_req, tmp, sem, req, ack, inst; 836 const unsigned int eng = 17; 837 struct amdgpu_vmhub *hub; 838 839 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 840 841 hub = &adev->vmhub[vmhub]; 842 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 843 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 844 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 845 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 846 847 if (vmhub >= AMDGPU_MMHUB0(0)) 848 inst = 0; 849 else 850 inst = vmhub; 851 852 /* This is necessary for SRIOV as well as for GFXOFF to function 853 * properly under bare metal 854 */ 855 if (adev->gfx.kiq[inst].ring.sched.ready && 856 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 857 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 858 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 859 860 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 861 1 << vmid, inst); 862 return; 863 } 864 865 /* This path is needed before KIQ/MES/GFXOFF are set up */ 866 spin_lock(&adev->gmc.invalidate_lock); 867 868 /* 869 * It may lose gpuvm invalidate acknowldege state across power-gating 870 * off cycle, add semaphore acquire before invalidation and semaphore 871 * release after invalidation to avoid entering power gated state 872 * to WA the Issue 873 */ 874 875 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 876 if (use_semaphore) { 877 for (j = 0; j < adev->usec_timeout; j++) { 878 /* a read return value of 1 means semaphore acquire */ 879 if (vmhub >= AMDGPU_MMHUB0(0)) 880 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); 881 else 882 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst)); 883 if (tmp & 0x1) 884 break; 885 udelay(1); 886 } 887 888 if (j >= adev->usec_timeout) 889 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 890 } 891 892 if (vmhub >= AMDGPU_MMHUB0(0)) 893 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); 894 else 895 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst)); 896 897 /* 898 * Issue a dummy read to wait for the ACK register to 899 * be cleared to avoid a false ACK due to the new fast 900 * GRBM interface. 901 */ 902 if ((vmhub == AMDGPU_GFXHUB(0)) && 903 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 904 RREG32_NO_KIQ(req); 905 906 for (j = 0; j < adev->usec_timeout; j++) { 907 if (vmhub >= AMDGPU_MMHUB0(0)) 908 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); 909 else 910 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst)); 911 if (tmp & (1 << vmid)) 912 break; 913 udelay(1); 914 } 915 916 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 917 if (use_semaphore) { 918 /* 919 * add semaphore release after invalidation, 920 * write with 0 means semaphore release 921 */ 922 if (vmhub >= AMDGPU_MMHUB0(0)) 923 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst)); 924 else 925 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst)); 926 } 927 928 spin_unlock(&adev->gmc.invalidate_lock); 929 930 if (j < adev->usec_timeout) 931 return; 932 933 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 934 } 935 936 /** 937 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 938 * 939 * @adev: amdgpu_device pointer 940 * @pasid: pasid to be flush 941 * @flush_type: the flush type 942 * @all_hub: flush all hubs 943 * @inst: is used to select which instance of KIQ to use for the invalidation 944 * 945 * Flush the TLB for the requested pasid. 946 */ 947 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 948 uint16_t pasid, uint32_t flush_type, 949 bool all_hub, uint32_t inst) 950 { 951 uint16_t queried; 952 int i, vmid; 953 954 for (vmid = 1; vmid < 16; vmid++) { 955 bool valid; 956 957 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 958 &queried); 959 if (!valid || queried != pasid) 960 continue; 961 962 if (all_hub) { 963 for_each_set_bit(i, adev->vmhubs_mask, 964 AMDGPU_MAX_VMHUBS) 965 gmc_v9_0_flush_gpu_tlb(adev, vmid, i, 966 flush_type); 967 } else { 968 gmc_v9_0_flush_gpu_tlb(adev, vmid, 969 AMDGPU_GFXHUB(0), 970 flush_type); 971 } 972 } 973 } 974 975 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 976 unsigned int vmid, uint64_t pd_addr) 977 { 978 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 979 struct amdgpu_device *adev = ring->adev; 980 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 981 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 982 unsigned int eng = ring->vm_inv_eng; 983 984 /* 985 * It may lose gpuvm invalidate acknowldege state across power-gating 986 * off cycle, add semaphore acquire before invalidation and semaphore 987 * release after invalidation to avoid entering power gated state 988 * to WA the Issue 989 */ 990 991 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 992 if (use_semaphore) 993 /* a read return value of 1 means semaphore acuqire */ 994 amdgpu_ring_emit_reg_wait(ring, 995 hub->vm_inv_eng0_sem + 996 hub->eng_distance * eng, 0x1, 0x1); 997 998 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 999 (hub->ctx_addr_distance * vmid), 1000 lower_32_bits(pd_addr)); 1001 1002 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1003 (hub->ctx_addr_distance * vmid), 1004 upper_32_bits(pd_addr)); 1005 1006 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1007 hub->eng_distance * eng, 1008 hub->vm_inv_eng0_ack + 1009 hub->eng_distance * eng, 1010 req, 1 << vmid); 1011 1012 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1013 if (use_semaphore) 1014 /* 1015 * add semaphore release after invalidation, 1016 * write with 0 means semaphore release 1017 */ 1018 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1019 hub->eng_distance * eng, 0); 1020 1021 return pd_addr; 1022 } 1023 1024 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 1025 unsigned int pasid) 1026 { 1027 struct amdgpu_device *adev = ring->adev; 1028 uint32_t reg; 1029 1030 /* Do nothing because there's no lut register for mmhub1. */ 1031 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1032 return; 1033 1034 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1035 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1036 else 1037 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1038 1039 amdgpu_ring_emit_wreg(ring, reg, pasid); 1040 } 1041 1042 /* 1043 * PTE format on VEGA 10: 1044 * 63:59 reserved 1045 * 58:57 mtype 1046 * 56 F 1047 * 55 L 1048 * 54 P 1049 * 53 SW 1050 * 52 T 1051 * 50:48 reserved 1052 * 47:12 4k physical page base address 1053 * 11:7 fragment 1054 * 6 write 1055 * 5 read 1056 * 4 exe 1057 * 3 Z 1058 * 2 snooped 1059 * 1 system 1060 * 0 valid 1061 * 1062 * PDE format on VEGA 10: 1063 * 63:59 block fragment size 1064 * 58:55 reserved 1065 * 54 P 1066 * 53:48 reserved 1067 * 47:6 physical base address of PD or PTE 1068 * 5:3 reserved 1069 * 2 C 1070 * 1 system 1071 * 0 valid 1072 */ 1073 1074 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1075 1076 { 1077 switch (flags) { 1078 case AMDGPU_VM_MTYPE_DEFAULT: 1079 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1080 case AMDGPU_VM_MTYPE_NC: 1081 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1082 case AMDGPU_VM_MTYPE_WC: 1083 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_WC); 1084 case AMDGPU_VM_MTYPE_RW: 1085 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_RW); 1086 case AMDGPU_VM_MTYPE_CC: 1087 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_CC); 1088 case AMDGPU_VM_MTYPE_UC: 1089 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC); 1090 default: 1091 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1092 } 1093 } 1094 1095 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1096 uint64_t *addr, uint64_t *flags) 1097 { 1098 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1099 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1100 BUG_ON(*addr & 0xFFFF00000000003FULL); 1101 1102 if (!adev->gmc.translate_further) 1103 return; 1104 1105 if (level == AMDGPU_VM_PDB1) { 1106 /* Set the block fragment size */ 1107 if (!(*flags & AMDGPU_PDE_PTE)) 1108 *flags |= AMDGPU_PDE_BFS(0x9); 1109 1110 } else if (level == AMDGPU_VM_PDB0) { 1111 if (*flags & AMDGPU_PDE_PTE) { 1112 *flags &= ~AMDGPU_PDE_PTE; 1113 if (!(*flags & AMDGPU_PTE_VALID)) 1114 *addr |= 1 << PAGE_SHIFT; 1115 } else { 1116 *flags |= AMDGPU_PTE_TF; 1117 } 1118 } 1119 } 1120 1121 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1122 struct amdgpu_bo *bo, 1123 struct amdgpu_bo_va_mapping *mapping, 1124 uint64_t *flags) 1125 { 1126 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1127 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM; 1128 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT); 1129 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1130 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1131 struct amdgpu_vm *vm = mapping->bo_va->base.vm; 1132 unsigned int mtype_local, mtype; 1133 bool snoop = false; 1134 bool is_local; 1135 1136 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1137 case IP_VERSION(9, 4, 1): 1138 case IP_VERSION(9, 4, 2): 1139 if (is_vram) { 1140 if (bo_adev == adev) { 1141 if (uncached) 1142 mtype = MTYPE_UC; 1143 else if (coherent) 1144 mtype = MTYPE_CC; 1145 else 1146 mtype = MTYPE_RW; 1147 /* FIXME: is this still needed? Or does 1148 * amdgpu_ttm_tt_pde_flags already handle this? 1149 */ 1150 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 1151 IP_VERSION(9, 4, 2) || 1152 amdgpu_ip_version(adev, GC_HWIP, 0) == 1153 IP_VERSION(9, 4, 3)) && 1154 adev->gmc.xgmi.connected_to_cpu) 1155 snoop = true; 1156 } else { 1157 if (uncached || coherent) 1158 mtype = MTYPE_UC; 1159 else 1160 mtype = MTYPE_NC; 1161 if (mapping->bo_va->is_xgmi) 1162 snoop = true; 1163 } 1164 } else { 1165 if (uncached || coherent) 1166 mtype = MTYPE_UC; 1167 else 1168 mtype = MTYPE_NC; 1169 /* FIXME: is this still needed? Or does 1170 * amdgpu_ttm_tt_pde_flags already handle this? 1171 */ 1172 snoop = true; 1173 } 1174 break; 1175 case IP_VERSION(9, 4, 3): 1176 case IP_VERSION(9, 4, 4): 1177 /* Only local VRAM BOs or system memory on non-NUMA APUs 1178 * can be assumed to be local in their entirety. Choose 1179 * MTYPE_NC as safe fallback for all system memory BOs on 1180 * NUMA systems. Their MTYPE can be overridden per-page in 1181 * gmc_v9_0_override_vm_pte_flags. 1182 */ 1183 mtype_local = MTYPE_RW; 1184 if (amdgpu_mtype_local == 1) { 1185 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1186 mtype_local = MTYPE_NC; 1187 } else if (amdgpu_mtype_local == 2) { 1188 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1189 mtype_local = MTYPE_CC; 1190 } else { 1191 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1192 } 1193 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1194 num_possible_nodes() <= 1) || 1195 (is_vram && adev == bo_adev && 1196 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1197 snoop = true; 1198 if (uncached) { 1199 mtype = MTYPE_UC; 1200 } else if (ext_coherent) { 1201 if (adev->rev_id) 1202 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1203 else 1204 mtype = MTYPE_UC; 1205 } else if (adev->flags & AMD_IS_APU) { 1206 mtype = is_local ? mtype_local : MTYPE_NC; 1207 } else { 1208 /* dGPU */ 1209 if (is_local) 1210 mtype = mtype_local; 1211 else if (is_vram) 1212 mtype = MTYPE_NC; 1213 else 1214 mtype = MTYPE_UC; 1215 } 1216 1217 break; 1218 default: 1219 if (uncached || coherent) 1220 mtype = MTYPE_UC; 1221 else 1222 mtype = MTYPE_NC; 1223 1224 /* FIXME: is this still needed? Or does 1225 * amdgpu_ttm_tt_pde_flags already handle this? 1226 */ 1227 if (!is_vram) 1228 snoop = true; 1229 } 1230 1231 if (mtype != MTYPE_NC) 1232 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype); 1233 1234 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1235 } 1236 1237 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1238 struct amdgpu_bo_va_mapping *mapping, 1239 uint64_t *flags) 1240 { 1241 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1242 1243 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1244 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1245 1246 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1247 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1248 1249 if (mapping->flags & AMDGPU_PTE_PRT) { 1250 *flags |= AMDGPU_PTE_PRT; 1251 *flags &= ~AMDGPU_PTE_VALID; 1252 } 1253 1254 if (bo && bo->tbo.resource) 1255 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo, 1256 mapping, flags); 1257 } 1258 1259 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1260 struct amdgpu_vm *vm, 1261 uint64_t addr, uint64_t *flags) 1262 { 1263 int local_node, nid; 1264 1265 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1266 * memory can use more efficient MTYPEs. 1267 */ 1268 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3) && 1269 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) 1270 return; 1271 1272 /* Only direct-mapped memory allows us to determine the NUMA node from 1273 * the DMA address. 1274 */ 1275 if (!adev->ram_is_direct_mapped) { 1276 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n"); 1277 return; 1278 } 1279 1280 /* MTYPE_NC is the same default and can be overridden. 1281 * MTYPE_UC will be present if the memory is extended-coherent 1282 * and can also be overridden. 1283 */ 1284 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1285 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) && 1286 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1287 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) { 1288 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n"); 1289 return; 1290 } 1291 1292 /* FIXME: Only supported on native mode for now. For carve-out, the 1293 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1294 * memory partitions are not associated with different NUMA nodes. 1295 */ 1296 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1297 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1298 } else { 1299 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); 1300 return; 1301 } 1302 1303 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1304 * page or NUMA nodes. 1305 */ 1306 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1307 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n"); 1308 return; 1309 } 1310 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1311 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1312 vm->mem_id, local_node, nid); 1313 if (nid == local_node) { 1314 uint64_t old_flags = *flags; 1315 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) == 1316 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) { 1317 unsigned int mtype_local = MTYPE_RW; 1318 1319 if (amdgpu_mtype_local == 1) 1320 mtype_local = MTYPE_NC; 1321 else if (amdgpu_mtype_local == 2) 1322 mtype_local = MTYPE_CC; 1323 1324 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local); 1325 } else if (adev->rev_id) { 1326 /* MTYPE_UC case */ 1327 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC); 1328 } 1329 1330 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n", 1331 old_flags, *flags); 1332 } 1333 } 1334 1335 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1336 { 1337 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1338 unsigned int size; 1339 1340 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1341 1342 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1343 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1344 } else { 1345 u32 viewport; 1346 1347 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1348 case IP_VERSION(1, 0, 0): 1349 case IP_VERSION(1, 0, 1): 1350 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1351 size = (REG_GET_FIELD(viewport, 1352 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1353 REG_GET_FIELD(viewport, 1354 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1355 4); 1356 break; 1357 case IP_VERSION(2, 1, 0): 1358 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1359 size = (REG_GET_FIELD(viewport, 1360 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1361 REG_GET_FIELD(viewport, 1362 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1363 4); 1364 break; 1365 default: 1366 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1367 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1368 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1369 4); 1370 break; 1371 } 1372 } 1373 1374 return size; 1375 } 1376 1377 static enum amdgpu_memory_partition 1378 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) 1379 { 1380 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 1381 1382 if (adev->nbio.funcs->get_memory_partition_mode) 1383 mode = adev->nbio.funcs->get_memory_partition_mode(adev, 1384 supp_modes); 1385 1386 return mode; 1387 } 1388 1389 static enum amdgpu_memory_partition 1390 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) 1391 { 1392 if (amdgpu_sriov_vf(adev)) 1393 return AMDGPU_NPS1_PARTITION_MODE; 1394 1395 return gmc_v9_0_get_memory_partition(adev, NULL); 1396 } 1397 1398 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1399 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1400 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1401 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1402 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1403 .map_mtype = gmc_v9_0_map_mtype, 1404 .get_vm_pde = gmc_v9_0_get_vm_pde, 1405 .get_vm_pte = gmc_v9_0_get_vm_pte, 1406 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1407 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1408 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition, 1409 }; 1410 1411 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1412 { 1413 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1414 } 1415 1416 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1417 { 1418 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1419 case IP_VERSION(6, 0, 0): 1420 adev->umc.funcs = &umc_v6_0_funcs; 1421 break; 1422 case IP_VERSION(6, 1, 1): 1423 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1424 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1425 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1426 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1427 adev->umc.retire_unit = 1; 1428 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1429 adev->umc.ras = &umc_v6_1_ras; 1430 break; 1431 case IP_VERSION(6, 1, 2): 1432 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1433 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1434 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1435 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1436 adev->umc.retire_unit = 1; 1437 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1438 adev->umc.ras = &umc_v6_1_ras; 1439 break; 1440 case IP_VERSION(6, 7, 0): 1441 adev->umc.max_ras_err_cnt_per_query = 1442 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1443 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1444 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1445 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1446 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1447 if (!adev->gmc.xgmi.connected_to_cpu) 1448 adev->umc.ras = &umc_v6_7_ras; 1449 if (1 & adev->smuio.funcs->get_die_id(adev)) 1450 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1451 else 1452 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1453 break; 1454 case IP_VERSION(12, 0, 0): 1455 adev->umc.max_ras_err_cnt_per_query = 1456 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1457 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1458 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1459 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1460 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1461 adev->umc.active_mask = adev->aid_mask; 1462 adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1463 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1464 adev->umc.ras = &umc_v12_0_ras; 1465 break; 1466 default: 1467 break; 1468 } 1469 } 1470 1471 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1472 { 1473 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1474 case IP_VERSION(9, 4, 1): 1475 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1476 break; 1477 case IP_VERSION(9, 4, 2): 1478 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1479 break; 1480 case IP_VERSION(1, 8, 0): 1481 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1482 break; 1483 default: 1484 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1485 break; 1486 } 1487 } 1488 1489 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1490 { 1491 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1492 case IP_VERSION(9, 4, 0): 1493 adev->mmhub.ras = &mmhub_v1_0_ras; 1494 break; 1495 case IP_VERSION(9, 4, 1): 1496 adev->mmhub.ras = &mmhub_v9_4_ras; 1497 break; 1498 case IP_VERSION(9, 4, 2): 1499 adev->mmhub.ras = &mmhub_v1_7_ras; 1500 break; 1501 case IP_VERSION(1, 8, 0): 1502 adev->mmhub.ras = &mmhub_v1_8_ras; 1503 break; 1504 default: 1505 /* mmhub ras is not available */ 1506 break; 1507 } 1508 } 1509 1510 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1511 { 1512 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1513 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 1514 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1515 else 1516 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1517 } 1518 1519 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1520 { 1521 adev->hdp.ras = &hdp_v4_0_ras; 1522 } 1523 1524 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1525 { 1526 struct amdgpu_mca *mca = &adev->mca; 1527 1528 /* is UMC the right IP to check for MCA? Maybe DF? */ 1529 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1530 case IP_VERSION(6, 7, 0): 1531 if (!adev->gmc.xgmi.connected_to_cpu) { 1532 mca->mp0.ras = &mca_v3_0_mp0_ras; 1533 mca->mp1.ras = &mca_v3_0_mp1_ras; 1534 mca->mpio.ras = &mca_v3_0_mpio_ras; 1535 } 1536 break; 1537 default: 1538 break; 1539 } 1540 } 1541 1542 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1543 { 1544 if (!adev->gmc.xgmi.connected_to_cpu) 1545 adev->gmc.xgmi.ras = &xgmi_ras; 1546 } 1547 1548 static int gmc_v9_0_early_init(void *handle) 1549 { 1550 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1551 1552 /* 1553 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1554 * in their IP discovery tables 1555 */ 1556 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1557 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1558 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1559 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 1560 adev->gmc.xgmi.supported = true; 1561 1562 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1563 adev->gmc.xgmi.supported = true; 1564 adev->gmc.xgmi.connected_to_cpu = 1565 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1566 } 1567 1568 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1569 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 1570 enum amdgpu_pkg_type pkg_type = 1571 adev->smuio.funcs->get_pkg_type(adev); 1572 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1573 * and the APU, can be in used two possible modes: 1574 * - carveout mode 1575 * - native APU mode 1576 * "is_app_apu" can be used to identify the APU in the native 1577 * mode. 1578 */ 1579 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1580 !pci_resource_len(adev->pdev, 0)); 1581 } 1582 1583 gmc_v9_0_set_gmc_funcs(adev); 1584 gmc_v9_0_set_irq_funcs(adev); 1585 gmc_v9_0_set_umc_funcs(adev); 1586 gmc_v9_0_set_mmhub_funcs(adev); 1587 gmc_v9_0_set_mmhub_ras_funcs(adev); 1588 gmc_v9_0_set_gfxhub_funcs(adev); 1589 gmc_v9_0_set_hdp_ras_funcs(adev); 1590 gmc_v9_0_set_mca_ras_funcs(adev); 1591 gmc_v9_0_set_xgmi_ras_funcs(adev); 1592 1593 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1594 adev->gmc.shared_aperture_end = 1595 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1596 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1597 adev->gmc.private_aperture_end = 1598 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1599 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1600 1601 return 0; 1602 } 1603 1604 static int gmc_v9_0_late_init(void *handle) 1605 { 1606 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1607 int r; 1608 1609 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1610 if (r) 1611 return r; 1612 1613 /* 1614 * Workaround performance drop issue with VBIOS enables partial 1615 * writes, while disables HBM ECC for vega10. 1616 */ 1617 if (!amdgpu_sriov_vf(adev) && 1618 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1619 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1620 if (adev->df.funcs && 1621 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1622 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1623 } 1624 } 1625 1626 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1627 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); 1628 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP); 1629 } 1630 1631 r = amdgpu_gmc_ras_late_init(adev); 1632 if (r) 1633 return r; 1634 1635 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1636 } 1637 1638 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1639 struct amdgpu_gmc *mc) 1640 { 1641 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1642 1643 amdgpu_gmc_set_agp_default(adev, mc); 1644 1645 /* add the xgmi offset of the physical node */ 1646 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1647 if (adev->gmc.xgmi.connected_to_cpu) { 1648 amdgpu_gmc_sysvm_location(adev, mc); 1649 } else { 1650 amdgpu_gmc_vram_location(adev, mc, base); 1651 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 1652 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 1653 amdgpu_gmc_agp_location(adev, mc); 1654 } 1655 /* base offset of vram pages */ 1656 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1657 1658 /* XXX: add the xgmi offset of the physical node? */ 1659 adev->vm_manager.vram_base_offset += 1660 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1661 } 1662 1663 /** 1664 * gmc_v9_0_mc_init - initialize the memory controller driver params 1665 * 1666 * @adev: amdgpu_device pointer 1667 * 1668 * Look up the amount of vram, vram width, and decide how to place 1669 * vram and gart within the GPU's physical address space. 1670 * Returns 0 for success. 1671 */ 1672 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1673 { 1674 int r; 1675 1676 /* size in MB on si */ 1677 if (!adev->gmc.is_app_apu) { 1678 adev->gmc.mc_vram_size = 1679 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1680 } else { 1681 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1682 adev->gmc.mc_vram_size = 0; 1683 } 1684 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1685 1686 if (!(adev->flags & AMD_IS_APU) && 1687 !adev->gmc.xgmi.connected_to_cpu) { 1688 r = amdgpu_device_resize_fb_bar(adev); 1689 if (r) 1690 return r; 1691 } 1692 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1693 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1694 1695 #ifdef CONFIG_X86_64 1696 /* 1697 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1698 * interface can use VRAM through here as it appears system reserved 1699 * memory in host address space. 1700 * 1701 * For APUs, VRAM is just the stolen system memory and can be accessed 1702 * directly. 1703 * 1704 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1705 */ 1706 1707 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1708 if ((!amdgpu_sriov_vf(adev) && 1709 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1710 (adev->gmc.xgmi.supported && 1711 adev->gmc.xgmi.connected_to_cpu)) { 1712 adev->gmc.aper_base = 1713 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1714 adev->gmc.xgmi.physical_node_id * 1715 adev->gmc.xgmi.node_segment_size; 1716 adev->gmc.aper_size = adev->gmc.real_vram_size; 1717 } 1718 1719 #endif 1720 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1721 1722 /* set the gart size */ 1723 if (amdgpu_gart_size == -1) { 1724 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1725 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1726 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1727 case IP_VERSION(9, 4, 0): 1728 case IP_VERSION(9, 4, 1): 1729 case IP_VERSION(9, 4, 2): 1730 case IP_VERSION(9, 4, 3): 1731 case IP_VERSION(9, 4, 4): 1732 default: 1733 adev->gmc.gart_size = 512ULL << 20; 1734 break; 1735 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1736 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1737 case IP_VERSION(9, 3, 0): 1738 adev->gmc.gart_size = 1024ULL << 20; 1739 break; 1740 } 1741 } else { 1742 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1743 } 1744 1745 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1746 1747 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1748 1749 return 0; 1750 } 1751 1752 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1753 { 1754 int r; 1755 1756 if (adev->gart.bo) { 1757 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1758 return 0; 1759 } 1760 1761 if (adev->gmc.xgmi.connected_to_cpu) { 1762 adev->gmc.vmid0_page_table_depth = 1; 1763 adev->gmc.vmid0_page_table_block_size = 12; 1764 } else { 1765 adev->gmc.vmid0_page_table_depth = 0; 1766 adev->gmc.vmid0_page_table_block_size = 0; 1767 } 1768 1769 /* Initialize common gart structure */ 1770 r = amdgpu_gart_init(adev); 1771 if (r) 1772 return r; 1773 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1774 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) | 1775 AMDGPU_PTE_EXECUTABLE; 1776 1777 if (!adev->gmc.real_vram_size) { 1778 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1779 r = amdgpu_gart_table_ram_alloc(adev); 1780 if (r) 1781 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1782 } else { 1783 r = amdgpu_gart_table_vram_alloc(adev); 1784 if (r) 1785 return r; 1786 1787 if (adev->gmc.xgmi.connected_to_cpu) 1788 r = amdgpu_gmc_pdb0_alloc(adev); 1789 } 1790 1791 return r; 1792 } 1793 1794 /** 1795 * gmc_v9_0_save_registers - saves regs 1796 * 1797 * @adev: amdgpu_device pointer 1798 * 1799 * This saves potential register values that should be 1800 * restored upon resume 1801 */ 1802 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1803 { 1804 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1805 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1806 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1807 } 1808 1809 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) 1810 { 1811 enum amdgpu_memory_partition mode; 1812 u32 supp_modes; 1813 bool valid; 1814 1815 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes); 1816 1817 /* Mode detected by hardware not present in supported modes */ 1818 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1819 !(BIT(mode - 1) & supp_modes)) 1820 return false; 1821 1822 switch (mode) { 1823 case UNKNOWN_MEMORY_PARTITION_MODE: 1824 case AMDGPU_NPS1_PARTITION_MODE: 1825 valid = (adev->gmc.num_mem_partitions == 1); 1826 break; 1827 case AMDGPU_NPS2_PARTITION_MODE: 1828 valid = (adev->gmc.num_mem_partitions == 2); 1829 break; 1830 case AMDGPU_NPS4_PARTITION_MODE: 1831 valid = (adev->gmc.num_mem_partitions == 3 || 1832 adev->gmc.num_mem_partitions == 4); 1833 break; 1834 default: 1835 valid = false; 1836 } 1837 1838 return valid; 1839 } 1840 1841 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid) 1842 { 1843 int i; 1844 1845 /* Check if node with id 'nid' is present in 'node_ids' array */ 1846 for (i = 0; i < num_ids; ++i) 1847 if (node_ids[i] == nid) 1848 return true; 1849 1850 return false; 1851 } 1852 1853 static void 1854 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev, 1855 struct amdgpu_mem_partition_info *mem_ranges) 1856 { 1857 struct amdgpu_numa_info numa_info; 1858 int node_ids[MAX_MEM_RANGES]; 1859 int num_ranges = 0, ret; 1860 int num_xcc, xcc_id; 1861 uint32_t xcc_mask; 1862 1863 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1864 xcc_mask = (1U << num_xcc) - 1; 1865 1866 for_each_inst(xcc_id, xcc_mask) { 1867 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1868 if (ret) 1869 continue; 1870 1871 if (numa_info.nid == NUMA_NO_NODE) { 1872 mem_ranges[0].size = numa_info.size; 1873 mem_ranges[0].numa.node = numa_info.nid; 1874 num_ranges = 1; 1875 break; 1876 } 1877 1878 if (gmc_v9_0_is_node_present(node_ids, num_ranges, 1879 numa_info.nid)) 1880 continue; 1881 1882 node_ids[num_ranges] = numa_info.nid; 1883 mem_ranges[num_ranges].numa.node = numa_info.nid; 1884 mem_ranges[num_ranges].size = numa_info.size; 1885 ++num_ranges; 1886 } 1887 1888 adev->gmc.num_mem_partitions = num_ranges; 1889 } 1890 1891 static void 1892 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, 1893 struct amdgpu_mem_partition_info *mem_ranges) 1894 { 1895 enum amdgpu_memory_partition mode; 1896 u32 start_addr = 0, size; 1897 int i, r, l; 1898 1899 mode = gmc_v9_0_query_memory_partition(adev); 1900 1901 switch (mode) { 1902 case UNKNOWN_MEMORY_PARTITION_MODE: 1903 case AMDGPU_NPS1_PARTITION_MODE: 1904 adev->gmc.num_mem_partitions = 1; 1905 break; 1906 case AMDGPU_NPS2_PARTITION_MODE: 1907 adev->gmc.num_mem_partitions = 2; 1908 break; 1909 case AMDGPU_NPS4_PARTITION_MODE: 1910 if (adev->flags & AMD_IS_APU) 1911 adev->gmc.num_mem_partitions = 3; 1912 else 1913 adev->gmc.num_mem_partitions = 4; 1914 break; 1915 default: 1916 adev->gmc.num_mem_partitions = 1; 1917 break; 1918 } 1919 1920 /* Use NPS range info, if populated */ 1921 r = amdgpu_gmc_get_nps_memranges(adev, mem_ranges, 1922 adev->gmc.num_mem_partitions); 1923 if (!r) { 1924 l = 0; 1925 for (i = 1; i < adev->gmc.num_mem_partitions; ++i) { 1926 if (mem_ranges[i].range.lpfn > 1927 mem_ranges[i - 1].range.lpfn) 1928 l = i; 1929 } 1930 1931 } else { 1932 /* Fallback to sw based calculation */ 1933 size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT; 1934 size /= adev->gmc.num_mem_partitions; 1935 1936 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 1937 mem_ranges[i].range.fpfn = start_addr; 1938 mem_ranges[i].size = 1939 ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 1940 mem_ranges[i].range.lpfn = start_addr + size - 1; 1941 start_addr += size; 1942 } 1943 1944 l = adev->gmc.num_mem_partitions - 1; 1945 } 1946 1947 /* Adjust the last one */ 1948 mem_ranges[l].range.lpfn = 1949 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 1950 mem_ranges[l].size = 1951 adev->gmc.real_vram_size - 1952 ((u64)mem_ranges[l].range.fpfn << AMDGPU_GPU_PAGE_SHIFT); 1953 } 1954 1955 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) 1956 { 1957 bool valid; 1958 1959 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES, 1960 sizeof(struct amdgpu_mem_partition_info), 1961 GFP_KERNEL); 1962 if (!adev->gmc.mem_partitions) 1963 return -ENOMEM; 1964 1965 /* TODO : Get the range from PSP/Discovery for dGPU */ 1966 if (adev->gmc.is_app_apu) 1967 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 1968 else 1969 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 1970 1971 if (amdgpu_sriov_vf(adev)) 1972 valid = true; 1973 else 1974 valid = gmc_v9_0_validate_partition_info(adev); 1975 if (!valid) { 1976 /* TODO: handle invalid case */ 1977 dev_WARN(adev->dev, 1978 "Mem ranges not matching with hardware config"); 1979 } 1980 1981 return 0; 1982 } 1983 1984 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 1985 { 1986 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1987 adev->gmc.vram_width = 128 * 64; 1988 } 1989 1990 static int gmc_v9_0_sw_init(void *handle) 1991 { 1992 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1994 unsigned long inst_mask = adev->aid_mask; 1995 1996 adev->gfxhub.funcs->init(adev); 1997 1998 adev->mmhub.funcs->init(adev); 1999 2000 spin_lock_init(&adev->gmc.invalidate_lock); 2001 2002 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2003 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 2004 gmc_v9_4_3_init_vram_info(adev); 2005 } else if (!adev->bios) { 2006 if (adev->flags & AMD_IS_APU) { 2007 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 2008 adev->gmc.vram_width = 64 * 64; 2009 } else { 2010 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 2011 adev->gmc.vram_width = 128 * 64; 2012 } 2013 } else { 2014 r = amdgpu_atomfirmware_get_vram_info(adev, 2015 &vram_width, &vram_type, &vram_vendor); 2016 if (amdgpu_sriov_vf(adev)) 2017 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 2018 * and DF related registers is not readable, seems hardcord is the 2019 * only way to set the correct vram_width 2020 */ 2021 adev->gmc.vram_width = 2048; 2022 else if (amdgpu_emu_mode != 1) 2023 adev->gmc.vram_width = vram_width; 2024 2025 if (!adev->gmc.vram_width) { 2026 int chansize, numchan; 2027 2028 /* hbm memory channel size */ 2029 if (adev->flags & AMD_IS_APU) 2030 chansize = 64; 2031 else 2032 chansize = 128; 2033 if (adev->df.funcs && 2034 adev->df.funcs->get_hbm_channel_number) { 2035 numchan = adev->df.funcs->get_hbm_channel_number(adev); 2036 adev->gmc.vram_width = numchan * chansize; 2037 } 2038 } 2039 2040 adev->gmc.vram_type = vram_type; 2041 adev->gmc.vram_vendor = vram_vendor; 2042 } 2043 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2044 case IP_VERSION(9, 1, 0): 2045 case IP_VERSION(9, 2, 2): 2046 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2047 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2048 2049 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 2050 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2051 } else { 2052 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 2053 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 2054 adev->gmc.translate_further = 2055 adev->vm_manager.num_level > 1; 2056 } 2057 break; 2058 case IP_VERSION(9, 0, 1): 2059 case IP_VERSION(9, 2, 1): 2060 case IP_VERSION(9, 4, 0): 2061 case IP_VERSION(9, 3, 0): 2062 case IP_VERSION(9, 4, 2): 2063 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2064 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2065 2066 /* 2067 * To fulfill 4-level page support, 2068 * vm size is 256TB (48bit), maximum size of Vega10, 2069 * block size 512 (9bit) 2070 */ 2071 2072 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2073 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 2074 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2075 break; 2076 case IP_VERSION(9, 4, 1): 2077 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2078 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2079 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 2080 2081 /* Keep the vm size same with Vega20 */ 2082 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2083 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2084 break; 2085 case IP_VERSION(9, 4, 3): 2086 case IP_VERSION(9, 4, 4): 2087 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 2088 NUM_XCC(adev->gfx.xcc_mask)); 2089 2090 inst_mask <<= AMDGPU_MMHUB0(0); 2091 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 2092 2093 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2094 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2095 break; 2096 default: 2097 break; 2098 } 2099 2100 /* This interrupt is VMC page fault.*/ 2101 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 2102 &adev->gmc.vm_fault); 2103 if (r) 2104 return r; 2105 2106 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 2107 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 2108 &adev->gmc.vm_fault); 2109 if (r) 2110 return r; 2111 } 2112 2113 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 2114 &adev->gmc.vm_fault); 2115 2116 if (r) 2117 return r; 2118 2119 if (!amdgpu_sriov_vf(adev) && 2120 !adev->gmc.xgmi.connected_to_cpu && 2121 !adev->gmc.is_app_apu) { 2122 /* interrupt sent to DF. */ 2123 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 2124 &adev->gmc.ecc_irq); 2125 if (r) 2126 return r; 2127 } 2128 2129 /* Set the internal MC address mask 2130 * This is the max address of the GPU's 2131 * internal address space. 2132 */ 2133 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 2134 2135 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 2136 IP_VERSION(9, 4, 2) ? 2137 48 : 2138 44; 2139 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2140 if (r) { 2141 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 2142 return r; 2143 } 2144 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2145 2146 r = gmc_v9_0_mc_init(adev); 2147 if (r) 2148 return r; 2149 2150 amdgpu_gmc_get_vbios_allocations(adev); 2151 2152 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2153 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 2154 r = gmc_v9_0_init_mem_ranges(adev); 2155 if (r) 2156 return r; 2157 } 2158 2159 /* Memory manager */ 2160 r = amdgpu_bo_init(adev); 2161 if (r) 2162 return r; 2163 2164 r = gmc_v9_0_gart_init(adev); 2165 if (r) 2166 return r; 2167 2168 /* 2169 * number of VMs 2170 * VMID 0 is reserved for System 2171 * amdgpu graphics/compute will use VMIDs 1..n-1 2172 * amdkfd will use VMIDs n..15 2173 * 2174 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2175 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2176 * for video processing. 2177 */ 2178 adev->vm_manager.first_kfd_vmid = 2179 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2180 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2181 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2182 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) ? 2183 3 : 2184 8; 2185 2186 amdgpu_vm_manager_init(adev); 2187 2188 gmc_v9_0_save_registers(adev); 2189 2190 r = amdgpu_gmc_ras_sw_init(adev); 2191 if (r) 2192 return r; 2193 2194 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2195 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 2196 amdgpu_gmc_sysfs_init(adev); 2197 2198 return 0; 2199 } 2200 2201 static int gmc_v9_0_sw_fini(void *handle) 2202 { 2203 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2204 2205 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2206 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 2207 amdgpu_gmc_sysfs_fini(adev); 2208 2209 amdgpu_gmc_ras_fini(adev); 2210 amdgpu_gem_force_release(adev); 2211 amdgpu_vm_manager_fini(adev); 2212 if (!adev->gmc.real_vram_size) { 2213 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2214 amdgpu_gart_table_ram_free(adev); 2215 } else { 2216 amdgpu_gart_table_vram_free(adev); 2217 } 2218 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2219 amdgpu_bo_fini(adev); 2220 2221 adev->gmc.num_mem_partitions = 0; 2222 kfree(adev->gmc.mem_partitions); 2223 2224 return 0; 2225 } 2226 2227 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2228 { 2229 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2230 case IP_VERSION(9, 0, 0): 2231 if (amdgpu_sriov_vf(adev)) 2232 break; 2233 fallthrough; 2234 case IP_VERSION(9, 4, 0): 2235 soc15_program_register_sequence(adev, 2236 golden_settings_mmhub_1_0_0, 2237 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2238 soc15_program_register_sequence(adev, 2239 golden_settings_athub_1_0_0, 2240 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2241 break; 2242 case IP_VERSION(9, 1, 0): 2243 case IP_VERSION(9, 2, 0): 2244 /* TODO for renoir */ 2245 soc15_program_register_sequence(adev, 2246 golden_settings_athub_1_0_0, 2247 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2248 break; 2249 default: 2250 break; 2251 } 2252 } 2253 2254 /** 2255 * gmc_v9_0_restore_registers - restores regs 2256 * 2257 * @adev: amdgpu_device pointer 2258 * 2259 * This restores register values, saved at suspend. 2260 */ 2261 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2262 { 2263 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2264 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2265 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2266 WARN_ON(adev->gmc.sdpif_register != 2267 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2268 } 2269 } 2270 2271 /** 2272 * gmc_v9_0_gart_enable - gart enable 2273 * 2274 * @adev: amdgpu_device pointer 2275 */ 2276 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2277 { 2278 int r; 2279 2280 if (adev->gmc.xgmi.connected_to_cpu) 2281 amdgpu_gmc_init_pdb0(adev); 2282 2283 if (adev->gart.bo == NULL) { 2284 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2285 return -EINVAL; 2286 } 2287 2288 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2289 2290 if (!adev->in_s0ix) { 2291 r = adev->gfxhub.funcs->gart_enable(adev); 2292 if (r) 2293 return r; 2294 } 2295 2296 r = adev->mmhub.funcs->gart_enable(adev); 2297 if (r) 2298 return r; 2299 2300 DRM_INFO("PCIE GART of %uM enabled.\n", 2301 (unsigned int)(adev->gmc.gart_size >> 20)); 2302 if (adev->gmc.pdb0_bo) 2303 DRM_INFO("PDB0 located at 0x%016llX\n", 2304 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2305 DRM_INFO("PTB located at 0x%016llX\n", 2306 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2307 2308 return 0; 2309 } 2310 2311 static int gmc_v9_0_hw_init(void *handle) 2312 { 2313 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2314 bool value; 2315 int i, r; 2316 2317 adev->gmc.flush_pasid_uses_kiq = true; 2318 2319 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush 2320 * (type 2), which flushes both. Due to a race condition with 2321 * concurrent memory accesses using the same TLB cache line, we still 2322 * need a second TLB flush after this. 2323 */ 2324 adev->gmc.flush_tlb_needs_extra_type_2 = 2325 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && 2326 adev->gmc.xgmi.num_physical_nodes; 2327 /* 2328 * TODO: This workaround is badly documented and had a buggy 2329 * implementation. We should probably verify what we do here. 2330 */ 2331 adev->gmc.flush_tlb_needs_extra_type_0 = 2332 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 2333 adev->rev_id == 0; 2334 2335 /* The sequence of these two function calls matters.*/ 2336 gmc_v9_0_init_golden_registers(adev); 2337 2338 if (adev->mode_info.num_crtc) { 2339 /* Lockout access through VGA aperture*/ 2340 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2341 /* disable VGA render */ 2342 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2343 } 2344 2345 if (adev->mmhub.funcs->update_power_gating) 2346 adev->mmhub.funcs->update_power_gating(adev, true); 2347 2348 adev->hdp.funcs->init_registers(adev); 2349 2350 /* After HDP is initialized, flush HDP.*/ 2351 adev->hdp.funcs->flush_hdp(adev, NULL); 2352 2353 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2354 value = false; 2355 else 2356 value = true; 2357 2358 if (!amdgpu_sriov_vf(adev)) { 2359 if (!adev->in_s0ix) 2360 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2361 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2362 } 2363 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2364 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2365 continue; 2366 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2367 } 2368 2369 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2370 adev->umc.funcs->init_registers(adev); 2371 2372 r = gmc_v9_0_gart_enable(adev); 2373 if (r) 2374 return r; 2375 2376 if (amdgpu_emu_mode == 1) 2377 return amdgpu_gmc_vram_checking(adev); 2378 2379 return 0; 2380 } 2381 2382 /** 2383 * gmc_v9_0_gart_disable - gart disable 2384 * 2385 * @adev: amdgpu_device pointer 2386 * 2387 * This disables all VM page table. 2388 */ 2389 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2390 { 2391 if (!adev->in_s0ix) 2392 adev->gfxhub.funcs->gart_disable(adev); 2393 adev->mmhub.funcs->gart_disable(adev); 2394 } 2395 2396 static int gmc_v9_0_hw_fini(void *handle) 2397 { 2398 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2399 2400 gmc_v9_0_gart_disable(adev); 2401 2402 if (amdgpu_sriov_vf(adev)) { 2403 /* full access mode, so don't touch any GMC register */ 2404 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2405 return 0; 2406 } 2407 2408 /* 2409 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2410 * a correct cached state for GMC. Otherwise, the "gate" again 2411 * operation on S3 resuming will fail due to wrong cached state. 2412 */ 2413 if (adev->mmhub.funcs->update_power_gating) 2414 adev->mmhub.funcs->update_power_gating(adev, false); 2415 2416 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2417 2418 if (adev->gmc.ecc_irq.funcs && 2419 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2420 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 2421 2422 return 0; 2423 } 2424 2425 static int gmc_v9_0_suspend(void *handle) 2426 { 2427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2428 2429 return gmc_v9_0_hw_fini(adev); 2430 } 2431 2432 static int gmc_v9_0_resume(void *handle) 2433 { 2434 int r; 2435 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2436 2437 r = gmc_v9_0_hw_init(adev); 2438 if (r) 2439 return r; 2440 2441 amdgpu_vmid_reset_all(adev); 2442 2443 return 0; 2444 } 2445 2446 static bool gmc_v9_0_is_idle(void *handle) 2447 { 2448 /* MC is always ready in GMC v9.*/ 2449 return true; 2450 } 2451 2452 static int gmc_v9_0_wait_for_idle(void *handle) 2453 { 2454 /* There is no need to wait for MC idle in GMC v9.*/ 2455 return 0; 2456 } 2457 2458 static int gmc_v9_0_soft_reset(void *handle) 2459 { 2460 /* XXX for emulation.*/ 2461 return 0; 2462 } 2463 2464 static int gmc_v9_0_set_clockgating_state(void *handle, 2465 enum amd_clockgating_state state) 2466 { 2467 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2468 2469 adev->mmhub.funcs->set_clockgating(adev, state); 2470 2471 athub_v1_0_set_clockgating(adev, state); 2472 2473 return 0; 2474 } 2475 2476 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2477 { 2478 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2479 2480 adev->mmhub.funcs->get_clockgating(adev, flags); 2481 2482 athub_v1_0_get_clockgating(adev, flags); 2483 } 2484 2485 static int gmc_v9_0_set_powergating_state(void *handle, 2486 enum amd_powergating_state state) 2487 { 2488 return 0; 2489 } 2490 2491 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2492 .name = "gmc_v9_0", 2493 .early_init = gmc_v9_0_early_init, 2494 .late_init = gmc_v9_0_late_init, 2495 .sw_init = gmc_v9_0_sw_init, 2496 .sw_fini = gmc_v9_0_sw_fini, 2497 .hw_init = gmc_v9_0_hw_init, 2498 .hw_fini = gmc_v9_0_hw_fini, 2499 .suspend = gmc_v9_0_suspend, 2500 .resume = gmc_v9_0_resume, 2501 .is_idle = gmc_v9_0_is_idle, 2502 .wait_for_idle = gmc_v9_0_wait_for_idle, 2503 .soft_reset = gmc_v9_0_soft_reset, 2504 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2505 .set_powergating_state = gmc_v9_0_set_powergating_state, 2506 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2507 }; 2508 2509 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2510 .type = AMD_IP_BLOCK_TYPE_GMC, 2511 .major = 9, 2512 .minor = 0, 2513 .rev = 0, 2514 .funcs = &gmc_v9_0_ip_funcs, 2515 }; 2516