1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/pci.h>
26
27 #include <drm/drm_cache.h>
28
29 #include "amdgpu.h"
30 #include "gmc_v9_0.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "amdgpu_gem.h"
33
34 #include "gc/gc_9_0_sh_mask.h"
35 #include "dce/dce_12_0_offset.h"
36 #include "dce/dce_12_0_sh_mask.h"
37 #include "vega10_enum.h"
38 #include "mmhub/mmhub_1_0_offset.h"
39 #include "athub/athub_1_0_sh_mask.h"
40 #include "athub/athub_1_0_offset.h"
41 #include "oss/osssys_4_0_offset.h"
42
43 #include "soc15.h"
44 #include "soc15d.h"
45 #include "soc15_common.h"
46 #include "umc/umc_6_0_sh_mask.h"
47
48 #include "gfxhub_v1_0.h"
49 #include "mmhub_v1_0.h"
50 #include "athub_v1_0.h"
51 #include "gfxhub_v1_1.h"
52 #include "gfxhub_v1_2.h"
53 #include "mmhub_v9_4.h"
54 #include "mmhub_v1_7.h"
55 #include "mmhub_v1_8.h"
56 #include "umc_v6_1.h"
57 #include "umc_v6_0.h"
58 #include "umc_v6_7.h"
59 #include "umc_v12_0.h"
60 #include "hdp_v4_0.h"
61 #include "mca_v3_0.h"
62
63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
64
65 #include "amdgpu_ras.h"
66 #include "amdgpu_xgmi.h"
67
68 /* add these here since we already include dce12 headers and these are for DCN */
69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d
76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2
77
78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea
79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2
80
81 #define MAX_MEM_RANGES 8
82
83 static const char * const gfxhub_client_ids[] = {
84 "CB",
85 "DB",
86 "IA",
87 "WD",
88 "CPF",
89 "CPC",
90 "CPG",
91 "RLC",
92 "TCP",
93 "SQC (inst)",
94 "SQC (data)",
95 "SQG",
96 "PA",
97 };
98
99 static const char *mmhub_client_ids_raven[][2] = {
100 [0][0] = "MP1",
101 [1][0] = "MP0",
102 [2][0] = "VCN",
103 [3][0] = "VCNU",
104 [4][0] = "HDP",
105 [5][0] = "DCE",
106 [13][0] = "UTCL2",
107 [19][0] = "TLS",
108 [26][0] = "OSS",
109 [27][0] = "SDMA0",
110 [0][1] = "MP1",
111 [1][1] = "MP0",
112 [2][1] = "VCN",
113 [3][1] = "VCNU",
114 [4][1] = "HDP",
115 [5][1] = "XDP",
116 [6][1] = "DBGU0",
117 [7][1] = "DCE",
118 [8][1] = "DCEDWB0",
119 [9][1] = "DCEDWB1",
120 [26][1] = "OSS",
121 [27][1] = "SDMA0",
122 };
123
124 static const char *mmhub_client_ids_renoir[][2] = {
125 [0][0] = "MP1",
126 [1][0] = "MP0",
127 [2][0] = "HDP",
128 [4][0] = "DCEDMC",
129 [5][0] = "DCEVGA",
130 [13][0] = "UTCL2",
131 [19][0] = "TLS",
132 [26][0] = "OSS",
133 [27][0] = "SDMA0",
134 [28][0] = "VCN",
135 [29][0] = "VCNU",
136 [30][0] = "JPEG",
137 [0][1] = "MP1",
138 [1][1] = "MP0",
139 [2][1] = "HDP",
140 [3][1] = "XDP",
141 [6][1] = "DBGU0",
142 [7][1] = "DCEDMC",
143 [8][1] = "DCEVGA",
144 [9][1] = "DCEDWB",
145 [26][1] = "OSS",
146 [27][1] = "SDMA0",
147 [28][1] = "VCN",
148 [29][1] = "VCNU",
149 [30][1] = "JPEG",
150 };
151
152 static const char *mmhub_client_ids_vega10[][2] = {
153 [0][0] = "MP0",
154 [1][0] = "UVD",
155 [2][0] = "UVDU",
156 [3][0] = "HDP",
157 [13][0] = "UTCL2",
158 [14][0] = "OSS",
159 [15][0] = "SDMA1",
160 [32+0][0] = "VCE0",
161 [32+1][0] = "VCE0U",
162 [32+2][0] = "XDMA",
163 [32+3][0] = "DCE",
164 [32+4][0] = "MP1",
165 [32+14][0] = "SDMA0",
166 [0][1] = "MP0",
167 [1][1] = "UVD",
168 [2][1] = "UVDU",
169 [3][1] = "DBGU0",
170 [4][1] = "HDP",
171 [5][1] = "XDP",
172 [14][1] = "OSS",
173 [15][1] = "SDMA0",
174 [32+0][1] = "VCE0",
175 [32+1][1] = "VCE0U",
176 [32+2][1] = "XDMA",
177 [32+3][1] = "DCE",
178 [32+4][1] = "DCEDWB",
179 [32+5][1] = "MP1",
180 [32+6][1] = "DBGU1",
181 [32+14][1] = "SDMA1",
182 };
183
184 static const char *mmhub_client_ids_vega12[][2] = {
185 [0][0] = "MP0",
186 [1][0] = "VCE0",
187 [2][0] = "VCE0U",
188 [3][0] = "HDP",
189 [13][0] = "UTCL2",
190 [14][0] = "OSS",
191 [15][0] = "SDMA1",
192 [32+0][0] = "DCE",
193 [32+1][0] = "XDMA",
194 [32+2][0] = "UVD",
195 [32+3][0] = "UVDU",
196 [32+4][0] = "MP1",
197 [32+15][0] = "SDMA0",
198 [0][1] = "MP0",
199 [1][1] = "VCE0",
200 [2][1] = "VCE0U",
201 [3][1] = "DBGU0",
202 [4][1] = "HDP",
203 [5][1] = "XDP",
204 [14][1] = "OSS",
205 [15][1] = "SDMA0",
206 [32+0][1] = "DCE",
207 [32+1][1] = "DCEDWB",
208 [32+2][1] = "XDMA",
209 [32+3][1] = "UVD",
210 [32+4][1] = "UVDU",
211 [32+5][1] = "MP1",
212 [32+6][1] = "DBGU1",
213 [32+15][1] = "SDMA1",
214 };
215
216 static const char *mmhub_client_ids_vega20[][2] = {
217 [0][0] = "XDMA",
218 [1][0] = "DCE",
219 [2][0] = "VCE0",
220 [3][0] = "VCE0U",
221 [4][0] = "UVD",
222 [5][0] = "UVD1U",
223 [13][0] = "OSS",
224 [14][0] = "HDP",
225 [15][0] = "SDMA0",
226 [32+0][0] = "UVD",
227 [32+1][0] = "UVDU",
228 [32+2][0] = "MP1",
229 [32+3][0] = "MP0",
230 [32+12][0] = "UTCL2",
231 [32+14][0] = "SDMA1",
232 [0][1] = "XDMA",
233 [1][1] = "DCE",
234 [2][1] = "DCEDWB",
235 [3][1] = "VCE0",
236 [4][1] = "VCE0U",
237 [5][1] = "UVD1",
238 [6][1] = "UVD1U",
239 [7][1] = "DBGU0",
240 [8][1] = "XDP",
241 [13][1] = "OSS",
242 [14][1] = "HDP",
243 [15][1] = "SDMA0",
244 [32+0][1] = "UVD",
245 [32+1][1] = "UVDU",
246 [32+2][1] = "DBGU1",
247 [32+3][1] = "MP1",
248 [32+4][1] = "MP0",
249 [32+14][1] = "SDMA1",
250 };
251
252 static const char *mmhub_client_ids_arcturus[][2] = {
253 [0][0] = "DBGU1",
254 [1][0] = "XDP",
255 [2][0] = "MP1",
256 [14][0] = "HDP",
257 [171][0] = "JPEG",
258 [172][0] = "VCN",
259 [173][0] = "VCNU",
260 [203][0] = "JPEG1",
261 [204][0] = "VCN1",
262 [205][0] = "VCN1U",
263 [256][0] = "SDMA0",
264 [257][0] = "SDMA1",
265 [258][0] = "SDMA2",
266 [259][0] = "SDMA3",
267 [260][0] = "SDMA4",
268 [261][0] = "SDMA5",
269 [262][0] = "SDMA6",
270 [263][0] = "SDMA7",
271 [384][0] = "OSS",
272 [0][1] = "DBGU1",
273 [1][1] = "XDP",
274 [2][1] = "MP1",
275 [14][1] = "HDP",
276 [171][1] = "JPEG",
277 [172][1] = "VCN",
278 [173][1] = "VCNU",
279 [203][1] = "JPEG1",
280 [204][1] = "VCN1",
281 [205][1] = "VCN1U",
282 [256][1] = "SDMA0",
283 [257][1] = "SDMA1",
284 [258][1] = "SDMA2",
285 [259][1] = "SDMA3",
286 [260][1] = "SDMA4",
287 [261][1] = "SDMA5",
288 [262][1] = "SDMA6",
289 [263][1] = "SDMA7",
290 [384][1] = "OSS",
291 };
292
293 static const char *mmhub_client_ids_aldebaran[][2] = {
294 [2][0] = "MP1",
295 [3][0] = "MP0",
296 [32+1][0] = "DBGU_IO0",
297 [32+2][0] = "DBGU_IO2",
298 [32+4][0] = "MPIO",
299 [96+11][0] = "JPEG0",
300 [96+12][0] = "VCN0",
301 [96+13][0] = "VCNU0",
302 [128+11][0] = "JPEG1",
303 [128+12][0] = "VCN1",
304 [128+13][0] = "VCNU1",
305 [160+1][0] = "XDP",
306 [160+14][0] = "HDP",
307 [256+0][0] = "SDMA0",
308 [256+1][0] = "SDMA1",
309 [256+2][0] = "SDMA2",
310 [256+3][0] = "SDMA3",
311 [256+4][0] = "SDMA4",
312 [384+0][0] = "OSS",
313 [2][1] = "MP1",
314 [3][1] = "MP0",
315 [32+1][1] = "DBGU_IO0",
316 [32+2][1] = "DBGU_IO2",
317 [32+4][1] = "MPIO",
318 [96+11][1] = "JPEG0",
319 [96+12][1] = "VCN0",
320 [96+13][1] = "VCNU0",
321 [128+11][1] = "JPEG1",
322 [128+12][1] = "VCN1",
323 [128+13][1] = "VCNU1",
324 [160+1][1] = "XDP",
325 [160+14][1] = "HDP",
326 [256+0][1] = "SDMA0",
327 [256+1][1] = "SDMA1",
328 [256+2][1] = "SDMA2",
329 [256+3][1] = "SDMA3",
330 [256+4][1] = "SDMA4",
331 [384+0][1] = "OSS",
332 };
333
334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = {
335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
337 };
338
339 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = {
340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
342 };
343
344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
345 (0x000143c0 + 0x00000000),
346 (0x000143c0 + 0x00000800),
347 (0x000143c0 + 0x00001000),
348 (0x000143c0 + 0x00001800),
349 (0x000543c0 + 0x00000000),
350 (0x000543c0 + 0x00000800),
351 (0x000543c0 + 0x00001000),
352 (0x000543c0 + 0x00001800),
353 (0x000943c0 + 0x00000000),
354 (0x000943c0 + 0x00000800),
355 (0x000943c0 + 0x00001000),
356 (0x000943c0 + 0x00001800),
357 (0x000d43c0 + 0x00000000),
358 (0x000d43c0 + 0x00000800),
359 (0x000d43c0 + 0x00001000),
360 (0x000d43c0 + 0x00001800),
361 (0x001143c0 + 0x00000000),
362 (0x001143c0 + 0x00000800),
363 (0x001143c0 + 0x00001000),
364 (0x001143c0 + 0x00001800),
365 (0x001543c0 + 0x00000000),
366 (0x001543c0 + 0x00000800),
367 (0x001543c0 + 0x00001000),
368 (0x001543c0 + 0x00001800),
369 (0x001943c0 + 0x00000000),
370 (0x001943c0 + 0x00000800),
371 (0x001943c0 + 0x00001000),
372 (0x001943c0 + 0x00001800),
373 (0x001d43c0 + 0x00000000),
374 (0x001d43c0 + 0x00000800),
375 (0x001d43c0 + 0x00001000),
376 (0x001d43c0 + 0x00001800),
377 };
378
379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
380 (0x000143e0 + 0x00000000),
381 (0x000143e0 + 0x00000800),
382 (0x000143e0 + 0x00001000),
383 (0x000143e0 + 0x00001800),
384 (0x000543e0 + 0x00000000),
385 (0x000543e0 + 0x00000800),
386 (0x000543e0 + 0x00001000),
387 (0x000543e0 + 0x00001800),
388 (0x000943e0 + 0x00000000),
389 (0x000943e0 + 0x00000800),
390 (0x000943e0 + 0x00001000),
391 (0x000943e0 + 0x00001800),
392 (0x000d43e0 + 0x00000000),
393 (0x000d43e0 + 0x00000800),
394 (0x000d43e0 + 0x00001000),
395 (0x000d43e0 + 0x00001800),
396 (0x001143e0 + 0x00000000),
397 (0x001143e0 + 0x00000800),
398 (0x001143e0 + 0x00001000),
399 (0x001143e0 + 0x00001800),
400 (0x001543e0 + 0x00000000),
401 (0x001543e0 + 0x00000800),
402 (0x001543e0 + 0x00001000),
403 (0x001543e0 + 0x00001800),
404 (0x001943e0 + 0x00000000),
405 (0x001943e0 + 0x00000800),
406 (0x001943e0 + 0x00001000),
407 (0x001943e0 + 0x00001800),
408 (0x001d43e0 + 0x00000000),
409 (0x001d43e0 + 0x00000800),
410 (0x001d43e0 + 0x00001000),
411 (0x001d43e0 + 0x00001800),
412 };
413
gmc_v9_0_is_multi_chiplet(struct amdgpu_device * adev)414 static inline bool gmc_v9_0_is_multi_chiplet(struct amdgpu_device *adev)
415 {
416 return !!adev->aid_mask;
417 }
418
gmc_v9_0_ecc_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)419 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
420 struct amdgpu_irq_src *src,
421 unsigned int type,
422 enum amdgpu_interrupt_state state)
423 {
424 u32 bits, i, tmp, reg;
425
426 /* Devices newer then VEGA10/12 shall have these programming
427 * sequences performed by PSP BL
428 */
429 if (adev->asic_type >= CHIP_VEGA20)
430 return 0;
431
432 bits = 0x7f;
433
434 switch (state) {
435 case AMDGPU_IRQ_STATE_DISABLE:
436 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
437 reg = ecc_umc_mcumc_ctrl_addrs[i];
438 tmp = RREG32(reg);
439 tmp &= ~bits;
440 WREG32(reg, tmp);
441 }
442 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
443 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
444 tmp = RREG32(reg);
445 tmp &= ~bits;
446 WREG32(reg, tmp);
447 }
448 break;
449 case AMDGPU_IRQ_STATE_ENABLE:
450 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
451 reg = ecc_umc_mcumc_ctrl_addrs[i];
452 tmp = RREG32(reg);
453 tmp |= bits;
454 WREG32(reg, tmp);
455 }
456 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
457 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
458 tmp = RREG32(reg);
459 tmp |= bits;
460 WREG32(reg, tmp);
461 }
462 break;
463 default:
464 break;
465 }
466
467 return 0;
468 }
469
gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)470 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
471 struct amdgpu_irq_src *src,
472 unsigned int type,
473 enum amdgpu_interrupt_state state)
474 {
475 struct amdgpu_vmhub *hub;
476 u32 tmp, reg, bits, i, j;
477
478 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
479 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
480 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
481 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
482 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
483 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
484 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
485
486 switch (state) {
487 case AMDGPU_IRQ_STATE_DISABLE:
488 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
489 hub = &adev->vmhub[j];
490 for (i = 0; i < 16; i++) {
491 reg = hub->vm_context0_cntl + i;
492
493 /* This works because this interrupt is only
494 * enabled at init/resume and disabled in
495 * fini/suspend, so the overall state doesn't
496 * change over the course of suspend/resume.
497 */
498 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
499 continue;
500
501 if (j >= AMDGPU_MMHUB0(0))
502 tmp = RREG32_SOC15_IP(MMHUB, reg);
503 else
504 tmp = RREG32_XCC(reg, j);
505
506 tmp &= ~bits;
507
508 if (j >= AMDGPU_MMHUB0(0))
509 WREG32_SOC15_IP(MMHUB, reg, tmp);
510 else
511 WREG32_XCC(reg, tmp, j);
512 }
513 }
514 break;
515 case AMDGPU_IRQ_STATE_ENABLE:
516 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
517 hub = &adev->vmhub[j];
518 for (i = 0; i < 16; i++) {
519 reg = hub->vm_context0_cntl + i;
520
521 /* This works because this interrupt is only
522 * enabled at init/resume and disabled in
523 * fini/suspend, so the overall state doesn't
524 * change over the course of suspend/resume.
525 */
526 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
527 continue;
528
529 if (j >= AMDGPU_MMHUB0(0))
530 tmp = RREG32_SOC15_IP(MMHUB, reg);
531 else
532 tmp = RREG32_XCC(reg, j);
533
534 tmp |= bits;
535
536 if (j >= AMDGPU_MMHUB0(0))
537 WREG32_SOC15_IP(MMHUB, reg, tmp);
538 else
539 WREG32_XCC(reg, tmp, j);
540 }
541 }
542 break;
543 default:
544 break;
545 }
546
547 return 0;
548 }
549
gmc_v9_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)550 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
551 struct amdgpu_irq_src *source,
552 struct amdgpu_iv_entry *entry)
553 {
554 bool retry_fault = !!(entry->src_data[1] & 0x80);
555 bool write_fault = !!(entry->src_data[1] & 0x20);
556 uint32_t status = 0, cid = 0, rw = 0, fed = 0;
557 struct amdgpu_task_info *task_info;
558 struct amdgpu_vmhub *hub;
559 const char *mmhub_cid;
560 const char *hub_name;
561 unsigned int vmhub;
562 u64 addr;
563 uint32_t cam_index = 0;
564 int ret, xcc_id = 0;
565 uint32_t node_id;
566
567 node_id = entry->node_id;
568
569 addr = (u64)entry->src_data[0] << 12;
570 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
571
572 if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
573 hub_name = "mmhub0";
574 vmhub = AMDGPU_MMHUB0(node_id / 4);
575 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
576 hub_name = "mmhub1";
577 vmhub = AMDGPU_MMHUB1(0);
578 } else {
579 hub_name = "gfxhub0";
580 if (adev->gfx.funcs->ih_node_to_logical_xcc) {
581 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev,
582 node_id);
583 if (xcc_id < 0)
584 xcc_id = 0;
585 }
586 vmhub = xcc_id;
587 }
588 hub = &adev->vmhub[vmhub];
589
590 if (retry_fault) {
591 if (adev->irq.retry_cam_enabled) {
592 /* Delegate it to a different ring if the hardware hasn't
593 * already done it.
594 */
595 if (entry->ih == &adev->irq.ih) {
596 amdgpu_irq_delegate(adev, entry, 8);
597 return 1;
598 }
599
600 cam_index = entry->src_data[2] & 0x3ff;
601
602 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id,
603 addr, entry->timestamp, write_fault);
604 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index);
605 if (ret)
606 return 1;
607 } else {
608 /* Process it onyl if it's the first fault for this address */
609 if (entry->ih != &adev->irq.ih_soft &&
610 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
611 entry->timestamp))
612 return 1;
613
614 /* Delegate it to a different ring if the hardware hasn't
615 * already done it.
616 */
617 if (entry->ih == &adev->irq.ih) {
618 amdgpu_irq_delegate(adev, entry, 8);
619 return 1;
620 }
621
622 /* Try to handle the recoverable page faults by filling page
623 * tables
624 */
625 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id,
626 addr, entry->timestamp, write_fault))
627 return 1;
628 }
629 }
630
631 if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault))
632 return 1;
633
634 if (!printk_ratelimit())
635 return 0;
636
637 dev_err(adev->dev,
638 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name,
639 retry_fault ? "retry" : "no-retry",
640 entry->src_id, entry->ring_id, entry->vmid, entry->pasid);
641
642 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
643 if (task_info) {
644 dev_err(adev->dev,
645 " for process %s pid %d thread %s pid %d)\n",
646 task_info->process_name, task_info->tgid,
647 task_info->task_name, task_info->pid);
648 amdgpu_vm_put_task_info(task_info);
649 }
650
651 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n",
652 addr, entry->client_id,
653 soc15_ih_clientid_name[entry->client_id]);
654
655 if (gmc_v9_0_is_multi_chiplet(adev))
656 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n",
657 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4,
658 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : "");
659
660 if (amdgpu_sriov_vf(adev))
661 return 0;
662
663 /*
664 * Issue a dummy read to wait for the status register to
665 * be updated to avoid reading an incorrect value due to
666 * the new fast GRBM interface.
667 */
668 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) &&
669 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)))
670 RREG32(hub->vm_l2_pro_fault_status);
671
672 status = RREG32(hub->vm_l2_pro_fault_status);
673 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
674 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
675 fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED);
676
677 /* for fed error, kfd will handle it, return directly */
678 if (fed && amdgpu_ras_is_poison_mode_supported(adev) &&
679 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2)))
680 return 0;
681
682 /* Only print L2 fault status if the status register could be read and
683 * contains useful information
684 */
685 if (!status)
686 return 0;
687
688 if (!amdgpu_sriov_vf(adev))
689 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
690
691 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub);
692
693 dev_err(adev->dev,
694 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
695 status);
696 if (entry->vmid_src == AMDGPU_GFXHUB(0)) {
697 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
698 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
699 gfxhub_client_ids[cid],
700 cid);
701 } else {
702 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
703 case IP_VERSION(9, 0, 0):
704 mmhub_cid = mmhub_client_ids_vega10[cid][rw];
705 break;
706 case IP_VERSION(9, 3, 0):
707 mmhub_cid = mmhub_client_ids_vega12[cid][rw];
708 break;
709 case IP_VERSION(9, 4, 0):
710 mmhub_cid = mmhub_client_ids_vega20[cid][rw];
711 break;
712 case IP_VERSION(9, 4, 1):
713 mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
714 break;
715 case IP_VERSION(9, 1, 0):
716 case IP_VERSION(9, 2, 0):
717 mmhub_cid = mmhub_client_ids_raven[cid][rw];
718 break;
719 case IP_VERSION(1, 5, 0):
720 case IP_VERSION(2, 4, 0):
721 mmhub_cid = mmhub_client_ids_renoir[cid][rw];
722 break;
723 case IP_VERSION(1, 8, 0):
724 case IP_VERSION(9, 4, 2):
725 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];
726 break;
727 default:
728 mmhub_cid = NULL;
729 break;
730 }
731 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
732 mmhub_cid ? mmhub_cid : "unknown", cid);
733 }
734 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
735 REG_GET_FIELD(status,
736 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
737 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
738 REG_GET_FIELD(status,
739 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
740 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
741 REG_GET_FIELD(status,
742 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
743 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
744 REG_GET_FIELD(status,
745 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
746 dev_err(adev->dev, "\t RW: 0x%x\n", rw);
747 return 0;
748 }
749
750 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
751 .set = gmc_v9_0_vm_fault_interrupt_state,
752 .process = gmc_v9_0_process_interrupt,
753 };
754
755
756 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
757 .set = gmc_v9_0_ecc_interrupt_state,
758 .process = amdgpu_umc_process_ecc_irq,
759 };
760
gmc_v9_0_set_irq_funcs(struct amdgpu_device * adev)761 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
762 {
763 adev->gmc.vm_fault.num_types = 1;
764 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
765
766 if (!amdgpu_sriov_vf(adev) &&
767 !adev->gmc.xgmi.connected_to_cpu &&
768 !adev->gmc.is_app_apu) {
769 adev->gmc.ecc_irq.num_types = 1;
770 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
771 }
772 }
773
gmc_v9_0_get_invalidate_req(unsigned int vmid,uint32_t flush_type)774 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
775 uint32_t flush_type)
776 {
777 u32 req = 0;
778
779 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
780 PER_VMID_INVALIDATE_REQ, 1 << vmid);
781 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
782 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
783 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
784 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
785 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
786 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
787 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
788 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
789
790 return req;
791 }
792
793 /**
794 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
795 *
796 * @adev: amdgpu_device pointer
797 * @vmhub: vmhub type
798 *
799 */
gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device * adev,uint32_t vmhub)800 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
801 uint32_t vmhub)
802 {
803 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
804 gmc_v9_0_is_multi_chiplet(adev))
805 return false;
806
807 return ((vmhub == AMDGPU_MMHUB0(0) ||
808 vmhub == AMDGPU_MMHUB1(0)) &&
809 (!amdgpu_sriov_vf(adev)) &&
810 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
811 (adev->apu_flags & AMD_APU_IS_PICASSO))));
812 }
813
gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device * adev,uint8_t vmid,uint16_t * p_pasid)814 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
815 uint8_t vmid, uint16_t *p_pasid)
816 {
817 uint32_t value;
818
819 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
820 + vmid);
821 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
822
823 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
824 }
825
826 /*
827 * GART
828 * VMID 0 is the physical GPU addresses as used by the kernel.
829 * VMIDs 1-15 are used for userspace clients and are handled
830 * by the amdgpu vm/hsa code.
831 */
832
833 /**
834 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
835 *
836 * @adev: amdgpu_device pointer
837 * @vmid: vm instance to flush
838 * @vmhub: which hub to flush
839 * @flush_type: the flush type
840 *
841 * Flush the TLB for the requested page table using certain type.
842 */
gmc_v9_0_flush_gpu_tlb(struct amdgpu_device * adev,uint32_t vmid,uint32_t vmhub,uint32_t flush_type)843 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
844 uint32_t vmhub, uint32_t flush_type)
845 {
846 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
847 u32 j, inv_req, tmp, sem, req, ack, inst;
848 const unsigned int eng = 17;
849 struct amdgpu_vmhub *hub;
850
851 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS);
852
853 hub = &adev->vmhub[vmhub];
854 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
855 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng;
856 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
857 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
858
859 if (vmhub >= AMDGPU_MMHUB0(0))
860 inst = 0;
861 else
862 inst = vmhub;
863
864 /* This is necessary for SRIOV as well as for GFXOFF to function
865 * properly under bare metal
866 */
867 if (adev->gfx.kiq[inst].ring.sched.ready &&
868 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
869 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
870 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
871
872 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
873 1 << vmid, inst);
874 return;
875 }
876
877 /* This path is needed before KIQ/MES/GFXOFF are set up */
878 spin_lock(&adev->gmc.invalidate_lock);
879
880 /*
881 * It may lose gpuvm invalidate acknowldege state across power-gating
882 * off cycle, add semaphore acquire before invalidation and semaphore
883 * release after invalidation to avoid entering power gated state
884 * to WA the Issue
885 */
886
887 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
888 if (use_semaphore) {
889 for (j = 0; j < adev->usec_timeout; j++) {
890 /* a read return value of 1 means semaphore acquire */
891 if (vmhub >= AMDGPU_MMHUB0(0))
892 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst));
893 else
894 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst));
895 if (tmp & 0x1)
896 break;
897 udelay(1);
898 }
899
900 if (j >= adev->usec_timeout)
901 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
902 }
903
904 if (vmhub >= AMDGPU_MMHUB0(0))
905 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst));
906 else
907 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst));
908
909 /*
910 * Issue a dummy read to wait for the ACK register to
911 * be cleared to avoid a false ACK due to the new fast
912 * GRBM interface.
913 */
914 if ((vmhub == AMDGPU_GFXHUB(0)) &&
915 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)))
916 RREG32_NO_KIQ(req);
917
918 for (j = 0; j < adev->usec_timeout; j++) {
919 if (vmhub >= AMDGPU_MMHUB0(0))
920 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst));
921 else
922 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst));
923 if (tmp & (1 << vmid))
924 break;
925 udelay(1);
926 }
927
928 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
929 if (use_semaphore) {
930 /*
931 * add semaphore release after invalidation,
932 * write with 0 means semaphore release
933 */
934 if (vmhub >= AMDGPU_MMHUB0(0))
935 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst));
936 else
937 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst));
938 }
939
940 spin_unlock(&adev->gmc.invalidate_lock);
941
942 if (j < adev->usec_timeout)
943 return;
944
945 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
946 }
947
948 /**
949 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
950 *
951 * @adev: amdgpu_device pointer
952 * @pasid: pasid to be flush
953 * @flush_type: the flush type
954 * @all_hub: flush all hubs
955 * @inst: is used to select which instance of KIQ to use for the invalidation
956 *
957 * Flush the TLB for the requested pasid.
958 */
gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device * adev,uint16_t pasid,uint32_t flush_type,bool all_hub,uint32_t inst)959 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
960 uint16_t pasid, uint32_t flush_type,
961 bool all_hub, uint32_t inst)
962 {
963 uint16_t queried;
964 int i, vmid;
965
966 for (vmid = 1; vmid < 16; vmid++) {
967 bool valid;
968
969 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
970 &queried);
971 if (!valid || queried != pasid)
972 continue;
973
974 if (all_hub) {
975 for_each_set_bit(i, adev->vmhubs_mask,
976 AMDGPU_MAX_VMHUBS)
977 gmc_v9_0_flush_gpu_tlb(adev, vmid, i,
978 flush_type);
979 } else {
980 gmc_v9_0_flush_gpu_tlb(adev, vmid,
981 AMDGPU_GFXHUB(0),
982 flush_type);
983 }
984 }
985 }
986
gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)987 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
988 unsigned int vmid, uint64_t pd_addr)
989 {
990 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
991 struct amdgpu_device *adev = ring->adev;
992 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub];
993 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
994 unsigned int eng = ring->vm_inv_eng;
995
996 /*
997 * It may lose gpuvm invalidate acknowldege state across power-gating
998 * off cycle, add semaphore acquire before invalidation and semaphore
999 * release after invalidation to avoid entering power gated state
1000 * to WA the Issue
1001 */
1002
1003 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
1004 if (use_semaphore)
1005 /* a read return value of 1 means semaphore acuqire */
1006 amdgpu_ring_emit_reg_wait(ring,
1007 hub->vm_inv_eng0_sem +
1008 hub->eng_distance * eng, 0x1, 0x1);
1009
1010 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
1011 (hub->ctx_addr_distance * vmid),
1012 lower_32_bits(pd_addr));
1013
1014 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1015 (hub->ctx_addr_distance * vmid),
1016 upper_32_bits(pd_addr));
1017
1018 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
1019 hub->eng_distance * eng,
1020 hub->vm_inv_eng0_ack +
1021 hub->eng_distance * eng,
1022 req, 1 << vmid);
1023
1024 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
1025 if (use_semaphore)
1026 /*
1027 * add semaphore release after invalidation,
1028 * write with 0 means semaphore release
1029 */
1030 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
1031 hub->eng_distance * eng, 0);
1032
1033 return pd_addr;
1034 }
1035
gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring * ring,unsigned int vmid,unsigned int pasid)1036 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
1037 unsigned int pasid)
1038 {
1039 struct amdgpu_device *adev = ring->adev;
1040 uint32_t reg;
1041
1042 /* Do nothing because there's no lut register for mmhub1. */
1043 if (ring->vm_hub == AMDGPU_MMHUB1(0))
1044 return;
1045
1046 if (ring->vm_hub == AMDGPU_GFXHUB(0))
1047 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
1048 else
1049 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
1050
1051 amdgpu_ring_emit_wreg(ring, reg, pasid);
1052 }
1053
1054 /*
1055 * PTE format on VEGA 10:
1056 * 63:59 reserved
1057 * 58:57 mtype
1058 * 56 F
1059 * 55 L
1060 * 54 P
1061 * 53 SW
1062 * 52 T
1063 * 50:48 reserved
1064 * 47:12 4k physical page base address
1065 * 11:7 fragment
1066 * 6 write
1067 * 5 read
1068 * 4 exe
1069 * 3 Z
1070 * 2 snooped
1071 * 1 system
1072 * 0 valid
1073 *
1074 * PDE format on VEGA 10:
1075 * 63:59 block fragment size
1076 * 58:55 reserved
1077 * 54 P
1078 * 53:48 reserved
1079 * 47:6 physical base address of PD or PTE
1080 * 5:3 reserved
1081 * 2 C
1082 * 1 system
1083 * 0 valid
1084 */
1085
gmc_v9_0_map_mtype(struct amdgpu_device * adev,uint32_t flags)1086 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
1087
1088 {
1089 switch (flags) {
1090 case AMDGPU_VM_MTYPE_DEFAULT:
1091 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC);
1092 case AMDGPU_VM_MTYPE_NC:
1093 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC);
1094 case AMDGPU_VM_MTYPE_WC:
1095 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_WC);
1096 case AMDGPU_VM_MTYPE_RW:
1097 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_RW);
1098 case AMDGPU_VM_MTYPE_CC:
1099 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_CC);
1100 case AMDGPU_VM_MTYPE_UC:
1101 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC);
1102 default:
1103 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC);
1104 }
1105 }
1106
gmc_v9_0_get_vm_pde(struct amdgpu_device * adev,int level,uint64_t * addr,uint64_t * flags)1107 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
1108 uint64_t *addr, uint64_t *flags)
1109 {
1110 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
1111 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
1112 BUG_ON(*addr & 0xFFFF00000000003FULL);
1113
1114 if (!adev->gmc.translate_further)
1115 return;
1116
1117 if (level == AMDGPU_VM_PDB1) {
1118 /* Set the block fragment size */
1119 if (!(*flags & AMDGPU_PDE_PTE))
1120 *flags |= AMDGPU_PDE_BFS(0x9);
1121
1122 } else if (level == AMDGPU_VM_PDB0) {
1123 if (*flags & AMDGPU_PDE_PTE) {
1124 *flags &= ~AMDGPU_PDE_PTE;
1125 if (!(*flags & AMDGPU_PTE_VALID))
1126 *addr |= 1 << PAGE_SHIFT;
1127 } else {
1128 *flags |= AMDGPU_PTE_TF;
1129 }
1130 }
1131 }
1132
gmc_v9_0_get_coherence_flags(struct amdgpu_device * adev,struct amdgpu_bo * bo,struct amdgpu_bo_va_mapping * mapping,uint64_t * flags)1133 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,
1134 struct amdgpu_bo *bo,
1135 struct amdgpu_bo_va_mapping *mapping,
1136 uint64_t *flags)
1137 {
1138 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1139 bool is_vram = bo->tbo.resource &&
1140 bo->tbo.resource->mem_type == TTM_PL_VRAM;
1141 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
1142 AMDGPU_GEM_CREATE_EXT_COHERENT);
1143 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT;
1144 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED;
1145 struct amdgpu_vm *vm = mapping->bo_va->base.vm;
1146 unsigned int mtype_local, mtype;
1147 uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0);
1148 bool snoop = false;
1149 bool is_local;
1150
1151 dma_resv_assert_held(bo->tbo.base.resv);
1152
1153 switch (gc_ip_version) {
1154 case IP_VERSION(9, 4, 1):
1155 case IP_VERSION(9, 4, 2):
1156 if (is_vram) {
1157 if (bo_adev == adev) {
1158 if (uncached)
1159 mtype = MTYPE_UC;
1160 else if (coherent)
1161 mtype = MTYPE_CC;
1162 else
1163 mtype = MTYPE_RW;
1164 /* FIXME: is this still needed? Or does
1165 * amdgpu_ttm_tt_pde_flags already handle this?
1166 */
1167 if (gc_ip_version == IP_VERSION(9, 4, 2) &&
1168 adev->gmc.xgmi.connected_to_cpu)
1169 snoop = true;
1170 } else {
1171 if (uncached || coherent)
1172 mtype = MTYPE_UC;
1173 else
1174 mtype = MTYPE_NC;
1175 if (mapping->bo_va->is_xgmi)
1176 snoop = true;
1177 }
1178 } else {
1179 if (uncached || coherent)
1180 mtype = MTYPE_UC;
1181 else
1182 mtype = MTYPE_NC;
1183 /* FIXME: is this still needed? Or does
1184 * amdgpu_ttm_tt_pde_flags already handle this?
1185 */
1186 snoop = true;
1187 }
1188 break;
1189 case IP_VERSION(9, 4, 3):
1190 case IP_VERSION(9, 4, 4):
1191 case IP_VERSION(9, 5, 0):
1192 /* Only local VRAM BOs or system memory on non-NUMA APUs
1193 * can be assumed to be local in their entirety. Choose
1194 * MTYPE_NC as safe fallback for all system memory BOs on
1195 * NUMA systems. Their MTYPE can be overridden per-page in
1196 * gmc_v9_0_override_vm_pte_flags.
1197 */
1198 mtype_local = MTYPE_RW;
1199 if (amdgpu_mtype_local == 1) {
1200 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n");
1201 mtype_local = MTYPE_NC;
1202 } else if (amdgpu_mtype_local == 2) {
1203 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n");
1204 mtype_local = MTYPE_CC;
1205 } else {
1206 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n");
1207 }
1208 is_local = (!is_vram && (adev->flags & AMD_IS_APU) &&
1209 num_possible_nodes() <= 1) ||
1210 (is_vram && adev == bo_adev &&
1211 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id);
1212 snoop = true;
1213 if (uncached) {
1214 mtype = MTYPE_UC;
1215 } else if (ext_coherent) {
1216 mtype = is_local ? MTYPE_CC : MTYPE_UC;
1217 } else if (adev->flags & AMD_IS_APU) {
1218 mtype = is_local ? mtype_local : MTYPE_NC;
1219 } else {
1220 /* dGPU */
1221 if (is_local)
1222 mtype = mtype_local;
1223 else if (gc_ip_version < IP_VERSION(9, 5, 0) && !is_vram)
1224 mtype = MTYPE_UC;
1225 else
1226 mtype = MTYPE_NC;
1227 }
1228
1229 break;
1230 default:
1231 if (uncached || coherent)
1232 mtype = MTYPE_UC;
1233 else
1234 mtype = MTYPE_NC;
1235
1236 /* FIXME: is this still needed? Or does
1237 * amdgpu_ttm_tt_pde_flags already handle this?
1238 */
1239 if (!is_vram)
1240 snoop = true;
1241 }
1242
1243 if (mtype != MTYPE_NC)
1244 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype);
1245
1246 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;
1247 }
1248
gmc_v9_0_get_vm_pte(struct amdgpu_device * adev,struct amdgpu_bo_va_mapping * mapping,uint64_t * flags)1249 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
1250 struct amdgpu_bo_va_mapping *mapping,
1251 uint64_t *flags)
1252 {
1253 struct amdgpu_bo *bo = mapping->bo_va->base.bo;
1254
1255 *flags &= ~AMDGPU_PTE_EXECUTABLE;
1256 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1257
1258 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1259 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
1260
1261 if (mapping->flags & AMDGPU_PTE_PRT) {
1262 *flags |= AMDGPU_PTE_PRT;
1263 *flags &= ~AMDGPU_PTE_VALID;
1264 }
1265
1266 if ((*flags & AMDGPU_PTE_VALID) && bo)
1267 gmc_v9_0_get_coherence_flags(adev, bo, mapping, flags);
1268 }
1269
gmc_v9_0_override_vm_pte_flags(struct amdgpu_device * adev,struct amdgpu_vm * vm,uint64_t addr,uint64_t * flags)1270 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,
1271 struct amdgpu_vm *vm,
1272 uint64_t addr, uint64_t *flags)
1273 {
1274 int local_node, nid;
1275
1276 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system
1277 * memory can use more efficient MTYPEs.
1278 */
1279 if (!(adev->flags & AMD_IS_APU) ||
1280 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3))
1281 return;
1282
1283 /* Only direct-mapped memory allows us to determine the NUMA node from
1284 * the DMA address.
1285 */
1286 if (!adev->ram_is_direct_mapped) {
1287 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n");
1288 return;
1289 }
1290
1291 /* MTYPE_NC is the same default and can be overridden.
1292 * MTYPE_UC will be present if the memory is extended-coherent
1293 * and can also be overridden.
1294 */
1295 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) !=
1296 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) &&
1297 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) !=
1298 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) {
1299 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n");
1300 return;
1301 }
1302
1303 /* FIXME: Only supported on native mode for now. For carve-out, the
1304 * NUMA affinity of the GPU/VM needs to come from the PCI info because
1305 * memory partitions are not associated with different NUMA nodes.
1306 */
1307 if (adev->gmc.is_app_apu && vm->mem_id >= 0) {
1308 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node;
1309 } else {
1310 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n");
1311 return;
1312 }
1313
1314 /* Only handle real RAM. Mappings of PCIe resources don't have struct
1315 * page or NUMA nodes.
1316 */
1317 if (!page_is_ram(addr >> PAGE_SHIFT)) {
1318 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n");
1319 return;
1320 }
1321 nid = pfn_to_nid(addr >> PAGE_SHIFT);
1322 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n",
1323 vm->mem_id, local_node, nid);
1324 if (nid == local_node) {
1325 uint64_t old_flags = *flags;
1326 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) ==
1327 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) {
1328 unsigned int mtype_local = MTYPE_RW;
1329
1330 if (amdgpu_mtype_local == 1)
1331 mtype_local = MTYPE_NC;
1332 else if (amdgpu_mtype_local == 2)
1333 mtype_local = MTYPE_CC;
1334
1335 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local);
1336 } else {
1337 /* MTYPE_UC case */
1338 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC);
1339 }
1340
1341 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n",
1342 old_flags, *flags);
1343 }
1344 }
1345
gmc_v9_0_get_vbios_fb_size(struct amdgpu_device * adev)1346 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1347 {
1348 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1349 unsigned int size;
1350
1351 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */
1352
1353 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1354 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1355 } else {
1356 u32 viewport;
1357
1358 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1359 case IP_VERSION(1, 0, 0):
1360 case IP_VERSION(1, 0, 1):
1361 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1362 size = (REG_GET_FIELD(viewport,
1363 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1364 REG_GET_FIELD(viewport,
1365 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1366 4);
1367 break;
1368 case IP_VERSION(2, 1, 0):
1369 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);
1370 size = (REG_GET_FIELD(viewport,
1371 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1372 REG_GET_FIELD(viewport,
1373 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1374 4);
1375 break;
1376 default:
1377 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1378 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1379 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1380 4);
1381 break;
1382 }
1383 }
1384
1385 return size;
1386 }
1387
1388 static enum amdgpu_memory_partition
gmc_v9_0_get_memory_partition(struct amdgpu_device * adev,u32 * supp_modes)1389 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes)
1390 {
1391 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE;
1392
1393 if (adev->nbio.funcs->get_memory_partition_mode)
1394 mode = adev->nbio.funcs->get_memory_partition_mode(adev,
1395 supp_modes);
1396
1397 return mode;
1398 }
1399
1400 static enum amdgpu_memory_partition
gmc_v9_0_query_vf_memory_partition(struct amdgpu_device * adev)1401 gmc_v9_0_query_vf_memory_partition(struct amdgpu_device *adev)
1402 {
1403 switch (adev->gmc.num_mem_partitions) {
1404 case 0:
1405 return UNKNOWN_MEMORY_PARTITION_MODE;
1406 case 1:
1407 return AMDGPU_NPS1_PARTITION_MODE;
1408 case 2:
1409 return AMDGPU_NPS2_PARTITION_MODE;
1410 case 4:
1411 return AMDGPU_NPS4_PARTITION_MODE;
1412 default:
1413 return AMDGPU_NPS1_PARTITION_MODE;
1414 }
1415
1416 return AMDGPU_NPS1_PARTITION_MODE;
1417 }
1418
1419 static enum amdgpu_memory_partition
gmc_v9_0_query_memory_partition(struct amdgpu_device * adev)1420 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev)
1421 {
1422 if (amdgpu_sriov_vf(adev))
1423 return gmc_v9_0_query_vf_memory_partition(adev);
1424
1425 return gmc_v9_0_get_memory_partition(adev, NULL);
1426 }
1427
gmc_v9_0_need_reset_on_init(struct amdgpu_device * adev)1428 static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev)
1429 {
1430 if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested &&
1431 adev->nbio.funcs->is_nps_switch_requested(adev)) {
1432 adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS;
1433 return true;
1434 }
1435
1436 return false;
1437 }
1438
1439 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
1440 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
1441 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
1442 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
1443 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
1444 .map_mtype = gmc_v9_0_map_mtype,
1445 .get_vm_pde = gmc_v9_0_get_vm_pde,
1446 .get_vm_pte = gmc_v9_0_get_vm_pte,
1447 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags,
1448 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
1449 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition,
1450 .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition,
1451 .need_reset_on_init = &gmc_v9_0_need_reset_on_init,
1452 };
1453
gmc_v9_0_set_gmc_funcs(struct amdgpu_device * adev)1454 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
1455 {
1456 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
1457 }
1458
gmc_v9_0_set_umc_funcs(struct amdgpu_device * adev)1459 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
1460 {
1461 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
1462 case IP_VERSION(6, 0, 0):
1463 adev->umc.funcs = &umc_v6_0_funcs;
1464 break;
1465 case IP_VERSION(6, 1, 1):
1466 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1467 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1468 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1469 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1470 adev->umc.retire_unit = 1;
1471 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1472 adev->umc.ras = &umc_v6_1_ras;
1473 break;
1474 case IP_VERSION(6, 1, 2):
1475 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1476 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1477 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1478 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
1479 adev->umc.retire_unit = 1;
1480 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1481 adev->umc.ras = &umc_v6_1_ras;
1482 break;
1483 case IP_VERSION(6, 7, 0):
1484 adev->umc.max_ras_err_cnt_per_query =
1485 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL;
1486 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
1487 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
1488 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
1489 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2);
1490 if (!adev->gmc.xgmi.connected_to_cpu)
1491 adev->umc.ras = &umc_v6_7_ras;
1492 if (1 & adev->smuio.funcs->get_die_id(adev))
1493 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];
1494 else
1495 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];
1496 break;
1497 case IP_VERSION(12, 0, 0):
1498 case IP_VERSION(12, 5, 0):
1499 adev->umc.max_ras_err_cnt_per_query =
1500 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
1501 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM;
1502 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM;
1503 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM;
1504 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET;
1505 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1506 adev->umc.ras = &umc_v12_0_ras;
1507 break;
1508 default:
1509 break;
1510 }
1511 }
1512
gmc_v9_0_set_mmhub_funcs(struct amdgpu_device * adev)1513 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
1514 {
1515 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
1516 case IP_VERSION(9, 4, 1):
1517 adev->mmhub.funcs = &mmhub_v9_4_funcs;
1518 break;
1519 case IP_VERSION(9, 4, 2):
1520 adev->mmhub.funcs = &mmhub_v1_7_funcs;
1521 break;
1522 case IP_VERSION(1, 8, 0):
1523 case IP_VERSION(1, 8, 1):
1524 adev->mmhub.funcs = &mmhub_v1_8_funcs;
1525 break;
1526 default:
1527 adev->mmhub.funcs = &mmhub_v1_0_funcs;
1528 break;
1529 }
1530 }
1531
gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device * adev)1532 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
1533 {
1534 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
1535 case IP_VERSION(9, 4, 0):
1536 adev->mmhub.ras = &mmhub_v1_0_ras;
1537 break;
1538 case IP_VERSION(9, 4, 1):
1539 adev->mmhub.ras = &mmhub_v9_4_ras;
1540 break;
1541 case IP_VERSION(9, 4, 2):
1542 adev->mmhub.ras = &mmhub_v1_7_ras;
1543 break;
1544 case IP_VERSION(1, 8, 0):
1545 case IP_VERSION(1, 8, 1):
1546 adev->mmhub.ras = &mmhub_v1_8_ras;
1547 break;
1548 default:
1549 /* mmhub ras is not available */
1550 break;
1551 }
1552 }
1553
gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device * adev)1554 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
1555 {
1556 if (gmc_v9_0_is_multi_chiplet(adev))
1557 adev->gfxhub.funcs = &gfxhub_v1_2_funcs;
1558 else
1559 adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
1560 }
1561
gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device * adev)1562 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
1563 {
1564 adev->hdp.ras = &hdp_v4_0_ras;
1565 }
1566
gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device * adev)1567 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev)
1568 {
1569 struct amdgpu_mca *mca = &adev->mca;
1570
1571 /* is UMC the right IP to check for MCA? Maybe DF? */
1572 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
1573 case IP_VERSION(6, 7, 0):
1574 if (!adev->gmc.xgmi.connected_to_cpu) {
1575 mca->mp0.ras = &mca_v3_0_mp0_ras;
1576 mca->mp1.ras = &mca_v3_0_mp1_ras;
1577 mca->mpio.ras = &mca_v3_0_mpio_ras;
1578 }
1579 break;
1580 default:
1581 break;
1582 }
1583 }
1584
gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device * adev)1585 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev)
1586 {
1587 if (!adev->gmc.xgmi.connected_to_cpu)
1588 adev->gmc.xgmi.ras = &xgmi_ras;
1589 }
1590
gmc_v9_0_init_nps_details(struct amdgpu_device * adev)1591 static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev)
1592 {
1593 enum amdgpu_memory_partition mode;
1594 uint32_t supp_modes;
1595 int i;
1596
1597 adev->gmc.supported_nps_modes = 0;
1598
1599 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU))
1600 return;
1601
1602 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes);
1603
1604 /* Mode detected by hardware and supported modes available */
1605 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && supp_modes) {
1606 while ((i = ffs(supp_modes))) {
1607 if (AMDGPU_ALL_NPS_MASK & BIT(i))
1608 adev->gmc.supported_nps_modes |= BIT(i);
1609 supp_modes &= supp_modes - 1;
1610 }
1611 } else {
1612 /*TODO: Check PSP version also which supports NPS switch. Otherwise keep
1613 * supported modes as 0.
1614 */
1615 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1616 case IP_VERSION(9, 4, 3):
1617 case IP_VERSION(9, 4, 4):
1618 adev->gmc.supported_nps_modes =
1619 BIT(AMDGPU_NPS1_PARTITION_MODE) |
1620 BIT(AMDGPU_NPS4_PARTITION_MODE);
1621 break;
1622 default:
1623 break;
1624 }
1625 }
1626 }
1627
gmc_v9_0_early_init(struct amdgpu_ip_block * ip_block)1628 static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block)
1629 {
1630 struct amdgpu_device *adev = ip_block->adev;
1631
1632 /*
1633 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined
1634 * in their IP discovery tables
1635 */
1636 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) ||
1637 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||
1638 gmc_v9_0_is_multi_chiplet(adev))
1639 adev->gmc.xgmi.supported = true;
1640
1641 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) {
1642 adev->gmc.xgmi.supported = true;
1643 adev->gmc.xgmi.connected_to_cpu =
1644 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
1645 }
1646
1647 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) {
1648 enum amdgpu_pkg_type pkg_type =
1649 adev->smuio.funcs->get_pkg_type(adev);
1650 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present
1651 * and the APU, can be in used two possible modes:
1652 * - carveout mode
1653 * - native APU mode
1654 * "is_app_apu" can be used to identify the APU in the native
1655 * mode.
1656 */
1657 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU &&
1658 !pci_resource_len(adev->pdev, 0));
1659 }
1660
1661 gmc_v9_0_set_gmc_funcs(adev);
1662 gmc_v9_0_set_irq_funcs(adev);
1663 gmc_v9_0_set_umc_funcs(adev);
1664 gmc_v9_0_set_mmhub_funcs(adev);
1665 gmc_v9_0_set_mmhub_ras_funcs(adev);
1666 gmc_v9_0_set_gfxhub_funcs(adev);
1667 gmc_v9_0_set_hdp_ras_funcs(adev);
1668 gmc_v9_0_set_mca_ras_funcs(adev);
1669 gmc_v9_0_set_xgmi_ras_funcs(adev);
1670
1671 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1672 adev->gmc.shared_aperture_end =
1673 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1674 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1675 adev->gmc.private_aperture_end =
1676 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1677 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
1678
1679 return 0;
1680 }
1681
gmc_v9_0_late_init(struct amdgpu_ip_block * ip_block)1682 static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block)
1683 {
1684 struct amdgpu_device *adev = ip_block->adev;
1685 int r;
1686
1687 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
1688 if (r)
1689 return r;
1690
1691 /*
1692 * Workaround performance drop issue with VBIOS enables partial
1693 * writes, while disables HBM ECC for vega10.
1694 */
1695 if (!amdgpu_sriov_vf(adev) &&
1696 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) {
1697 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
1698 if (adev->df.funcs &&
1699 adev->df.funcs->enable_ecc_force_par_wr_rmw)
1700 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
1701 }
1702 }
1703
1704 if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1705 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
1706 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP);
1707 }
1708
1709 r = amdgpu_gmc_ras_late_init(adev);
1710 if (r)
1711 return r;
1712
1713 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1714 }
1715
gmc_v9_0_vram_gtt_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)1716 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
1717 struct amdgpu_gmc *mc)
1718 {
1719 u64 base = adev->mmhub.funcs->get_fb_location(adev);
1720
1721 amdgpu_gmc_set_agp_default(adev, mc);
1722
1723 /* add the xgmi offset of the physical node */
1724 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1725 if (adev->gmc.xgmi.connected_to_cpu) {
1726 amdgpu_gmc_sysvm_location(adev, mc);
1727 } else {
1728 amdgpu_gmc_vram_location(adev, mc, base);
1729 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);
1730 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1))
1731 amdgpu_gmc_agp_location(adev, mc);
1732 }
1733 /* base offset of vram pages */
1734 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1735
1736 /* XXX: add the xgmi offset of the physical node? */
1737 adev->vm_manager.vram_base_offset +=
1738 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1739 }
1740
1741 /**
1742 * gmc_v9_0_mc_init - initialize the memory controller driver params
1743 *
1744 * @adev: amdgpu_device pointer
1745 *
1746 * Look up the amount of vram, vram width, and decide how to place
1747 * vram and gart within the GPU's physical address space.
1748 * Returns 0 for success.
1749 */
gmc_v9_0_mc_init(struct amdgpu_device * adev)1750 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1751 {
1752 int r;
1753
1754 /* size in MB on si */
1755 if (!adev->gmc.is_app_apu) {
1756 adev->gmc.mc_vram_size =
1757 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1758 } else {
1759 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n");
1760 adev->gmc.mc_vram_size = 0;
1761 }
1762 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1763
1764 if (!(adev->flags & AMD_IS_APU) &&
1765 !adev->gmc.xgmi.connected_to_cpu) {
1766 r = amdgpu_device_resize_fb_bar(adev);
1767 if (r)
1768 return r;
1769 }
1770 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1771 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1772
1773 #ifdef CONFIG_X86_64
1774 /*
1775 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi
1776 * interface can use VRAM through here as it appears system reserved
1777 * memory in host address space.
1778 *
1779 * For APUs, VRAM is just the stolen system memory and can be accessed
1780 * directly.
1781 *
1782 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR.
1783 */
1784
1785 /* check whether both host-gpu and gpu-gpu xgmi links exist */
1786 if ((!amdgpu_sriov_vf(adev) &&
1787 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) ||
1788 (adev->gmc.xgmi.supported &&
1789 adev->gmc.xgmi.connected_to_cpu)) {
1790 adev->gmc.aper_base =
1791 adev->gfxhub.funcs->get_mc_fb_offset(adev) +
1792 adev->gmc.xgmi.physical_node_id *
1793 adev->gmc.xgmi.node_segment_size;
1794 adev->gmc.aper_size = adev->gmc.real_vram_size;
1795 }
1796
1797 #endif
1798 adev->gmc.visible_vram_size = adev->gmc.aper_size;
1799
1800 /* set the gart size */
1801 if (amdgpu_gart_size == -1) {
1802 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1803 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */
1804 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */
1805 case IP_VERSION(9, 4, 0):
1806 case IP_VERSION(9, 4, 1):
1807 case IP_VERSION(9, 4, 2):
1808 case IP_VERSION(9, 4, 3):
1809 case IP_VERSION(9, 4, 4):
1810 case IP_VERSION(9, 5, 0):
1811 default:
1812 adev->gmc.gart_size = 512ULL << 20;
1813 break;
1814 case IP_VERSION(9, 1, 0): /* DCE SG support */
1815 case IP_VERSION(9, 2, 2): /* DCE SG support */
1816 case IP_VERSION(9, 3, 0):
1817 adev->gmc.gart_size = 1024ULL << 20;
1818 break;
1819 }
1820 } else {
1821 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1822 }
1823
1824 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
1825
1826 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1827
1828 return 0;
1829 }
1830
gmc_v9_0_gart_init(struct amdgpu_device * adev)1831 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1832 {
1833 int r;
1834
1835 if (adev->gart.bo) {
1836 WARN(1, "VEGA10 PCIE GART already initialized\n");
1837 return 0;
1838 }
1839
1840 if (adev->gmc.xgmi.connected_to_cpu) {
1841 adev->gmc.vmid0_page_table_depth = 1;
1842 adev->gmc.vmid0_page_table_block_size = 12;
1843 } else {
1844 adev->gmc.vmid0_page_table_depth = 0;
1845 adev->gmc.vmid0_page_table_block_size = 0;
1846 }
1847
1848 /* Initialize common gart structure */
1849 r = amdgpu_gart_init(adev);
1850 if (r)
1851 return r;
1852 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1853 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) |
1854 AMDGPU_PTE_EXECUTABLE;
1855
1856 if (!adev->gmc.real_vram_size) {
1857 dev_info(adev->dev, "Put GART in system memory for APU\n");
1858 r = amdgpu_gart_table_ram_alloc(adev);
1859 if (r)
1860 dev_err(adev->dev, "Failed to allocate GART in system memory\n");
1861 } else {
1862 r = amdgpu_gart_table_vram_alloc(adev);
1863 if (r)
1864 return r;
1865
1866 if (adev->gmc.xgmi.connected_to_cpu)
1867 r = amdgpu_gmc_pdb0_alloc(adev);
1868 }
1869
1870 return r;
1871 }
1872
1873 /**
1874 * gmc_v9_0_save_registers - saves regs
1875 *
1876 * @adev: amdgpu_device pointer
1877 *
1878 * This saves potential register values that should be
1879 * restored upon resume
1880 */
gmc_v9_0_save_registers(struct amdgpu_device * adev)1881 static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1882 {
1883 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) ||
1884 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1)))
1885 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1886 }
1887
gmc_v9_0_validate_partition_info(struct amdgpu_device * adev)1888 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev)
1889 {
1890 enum amdgpu_memory_partition mode;
1891 u32 supp_modes;
1892 bool valid;
1893
1894 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes);
1895
1896 /* Mode detected by hardware not present in supported modes */
1897 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) &&
1898 !(BIT(mode - 1) & supp_modes))
1899 return false;
1900
1901 switch (mode) {
1902 case UNKNOWN_MEMORY_PARTITION_MODE:
1903 case AMDGPU_NPS1_PARTITION_MODE:
1904 valid = (adev->gmc.num_mem_partitions == 1);
1905 break;
1906 case AMDGPU_NPS2_PARTITION_MODE:
1907 valid = (adev->gmc.num_mem_partitions == 2);
1908 break;
1909 case AMDGPU_NPS4_PARTITION_MODE:
1910 valid = (adev->gmc.num_mem_partitions == 3 ||
1911 adev->gmc.num_mem_partitions == 4);
1912 break;
1913 default:
1914 valid = false;
1915 }
1916
1917 return valid;
1918 }
1919
gmc_v9_0_is_node_present(int * node_ids,int num_ids,int nid)1920 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid)
1921 {
1922 int i;
1923
1924 /* Check if node with id 'nid' is present in 'node_ids' array */
1925 for (i = 0; i < num_ids; ++i)
1926 if (node_ids[i] == nid)
1927 return true;
1928
1929 return false;
1930 }
1931
1932 static void
gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device * adev,struct amdgpu_mem_partition_info * mem_ranges)1933 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev,
1934 struct amdgpu_mem_partition_info *mem_ranges)
1935 {
1936 struct amdgpu_numa_info numa_info;
1937 int node_ids[MAX_MEM_RANGES];
1938 int num_ranges = 0, ret;
1939 int num_xcc, xcc_id;
1940 uint32_t xcc_mask;
1941
1942 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1943 xcc_mask = (1U << num_xcc) - 1;
1944
1945 for_each_inst(xcc_id, xcc_mask) {
1946 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info);
1947 if (ret)
1948 continue;
1949
1950 if (numa_info.nid == NUMA_NO_NODE) {
1951 mem_ranges[0].size = numa_info.size;
1952 mem_ranges[0].numa.node = numa_info.nid;
1953 num_ranges = 1;
1954 break;
1955 }
1956
1957 if (gmc_v9_0_is_node_present(node_ids, num_ranges,
1958 numa_info.nid))
1959 continue;
1960
1961 node_ids[num_ranges] = numa_info.nid;
1962 mem_ranges[num_ranges].numa.node = numa_info.nid;
1963 mem_ranges[num_ranges].size = numa_info.size;
1964 ++num_ranges;
1965 }
1966
1967 adev->gmc.num_mem_partitions = num_ranges;
1968 }
1969
1970 static void
gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device * adev,struct amdgpu_mem_partition_info * mem_ranges)1971 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev,
1972 struct amdgpu_mem_partition_info *mem_ranges)
1973 {
1974 enum amdgpu_memory_partition mode;
1975 u32 start_addr = 0, size;
1976 int i, r, l;
1977
1978 mode = gmc_v9_0_query_memory_partition(adev);
1979
1980 switch (mode) {
1981 case UNKNOWN_MEMORY_PARTITION_MODE:
1982 adev->gmc.num_mem_partitions = 0;
1983 break;
1984 case AMDGPU_NPS1_PARTITION_MODE:
1985 adev->gmc.num_mem_partitions = 1;
1986 break;
1987 case AMDGPU_NPS2_PARTITION_MODE:
1988 adev->gmc.num_mem_partitions = 2;
1989 break;
1990 case AMDGPU_NPS4_PARTITION_MODE:
1991 if (adev->flags & AMD_IS_APU)
1992 adev->gmc.num_mem_partitions = 3;
1993 else
1994 adev->gmc.num_mem_partitions = 4;
1995 break;
1996 default:
1997 adev->gmc.num_mem_partitions = 1;
1998 break;
1999 }
2000
2001 /* Use NPS range info, if populated */
2002 r = amdgpu_gmc_get_nps_memranges(adev, mem_ranges,
2003 &adev->gmc.num_mem_partitions);
2004 if (!r) {
2005 l = 0;
2006 for (i = 1; i < adev->gmc.num_mem_partitions; ++i) {
2007 if (mem_ranges[i].range.lpfn >
2008 mem_ranges[i - 1].range.lpfn)
2009 l = i;
2010 }
2011
2012 } else {
2013 if (!adev->gmc.num_mem_partitions) {
2014 dev_err(adev->dev,
2015 "Not able to detect NPS mode, fall back to NPS1");
2016 adev->gmc.num_mem_partitions = 1;
2017 }
2018 /* Fallback to sw based calculation */
2019 size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT;
2020 size /= adev->gmc.num_mem_partitions;
2021
2022 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) {
2023 mem_ranges[i].range.fpfn = start_addr;
2024 mem_ranges[i].size =
2025 ((u64)size << AMDGPU_GPU_PAGE_SHIFT);
2026 mem_ranges[i].range.lpfn = start_addr + size - 1;
2027 start_addr += size;
2028 }
2029
2030 l = adev->gmc.num_mem_partitions - 1;
2031 }
2032
2033 /* Adjust the last one */
2034 mem_ranges[l].range.lpfn =
2035 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1;
2036 mem_ranges[l].size =
2037 adev->gmc.real_vram_size -
2038 ((u64)mem_ranges[l].range.fpfn << AMDGPU_GPU_PAGE_SHIFT);
2039 }
2040
gmc_v9_0_init_mem_ranges(struct amdgpu_device * adev)2041 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev)
2042 {
2043 bool valid;
2044
2045 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES,
2046 sizeof(struct amdgpu_mem_partition_info),
2047 GFP_KERNEL);
2048 if (!adev->gmc.mem_partitions)
2049 return -ENOMEM;
2050
2051 /* TODO : Get the range from PSP/Discovery for dGPU */
2052 if (adev->gmc.is_app_apu)
2053 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions);
2054 else
2055 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions);
2056
2057 if (amdgpu_sriov_vf(adev))
2058 valid = true;
2059 else
2060 valid = gmc_v9_0_validate_partition_info(adev);
2061 if (!valid) {
2062 /* TODO: handle invalid case */
2063 dev_WARN(adev->dev,
2064 "Mem ranges not matching with hardware config");
2065 }
2066
2067 return 0;
2068 }
2069
gmc_v9_4_3_init_vram_info(struct amdgpu_device * adev)2070 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev)
2071 {
2072 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
2073 adev->gmc.vram_width = 128 * 64;
2074
2075 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))
2076 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E;
2077 }
2078
gmc_v9_0_sw_init(struct amdgpu_ip_block * ip_block)2079 static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block)
2080 {
2081 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits;
2082 struct amdgpu_device *adev = ip_block->adev;
2083 unsigned long inst_mask = adev->aid_mask;
2084
2085 adev->gfxhub.funcs->init(adev);
2086
2087 adev->mmhub.funcs->init(adev);
2088
2089 spin_lock_init(&adev->gmc.invalidate_lock);
2090
2091 if (gmc_v9_0_is_multi_chiplet(adev)) {
2092 gmc_v9_4_3_init_vram_info(adev);
2093 } else if (!adev->bios) {
2094 if (adev->flags & AMD_IS_APU) {
2095 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
2096 adev->gmc.vram_width = 64 * 64;
2097 } else {
2098 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
2099 adev->gmc.vram_width = 128 * 64;
2100 }
2101 } else {
2102 r = amdgpu_atomfirmware_get_vram_info(adev,
2103 &vram_width, &vram_type, &vram_vendor);
2104 if (amdgpu_sriov_vf(adev))
2105 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
2106 * and DF related registers is not readable, seems hardcord is the
2107 * only way to set the correct vram_width
2108 */
2109 adev->gmc.vram_width = 2048;
2110 else if (amdgpu_emu_mode != 1)
2111 adev->gmc.vram_width = vram_width;
2112
2113 if (!adev->gmc.vram_width) {
2114 int chansize, numchan;
2115
2116 /* hbm memory channel size */
2117 if (adev->flags & AMD_IS_APU)
2118 chansize = 64;
2119 else
2120 chansize = 128;
2121 if (adev->df.funcs &&
2122 adev->df.funcs->get_hbm_channel_number) {
2123 numchan = adev->df.funcs->get_hbm_channel_number(adev);
2124 adev->gmc.vram_width = numchan * chansize;
2125 }
2126 }
2127
2128 adev->gmc.vram_type = vram_type;
2129 adev->gmc.vram_vendor = vram_vendor;
2130 }
2131 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2132 case IP_VERSION(9, 1, 0):
2133 case IP_VERSION(9, 2, 2):
2134 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2135 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2136
2137 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
2138 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2139 } else {
2140 /* vm_size is 128TB + 512GB for legacy 3-level page support */
2141 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
2142 adev->gmc.translate_further =
2143 adev->vm_manager.num_level > 1;
2144 }
2145 break;
2146 case IP_VERSION(9, 0, 1):
2147 case IP_VERSION(9, 2, 1):
2148 case IP_VERSION(9, 4, 0):
2149 case IP_VERSION(9, 3, 0):
2150 case IP_VERSION(9, 4, 2):
2151 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2152 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2153
2154 /*
2155 * To fulfill 4-level page support,
2156 * vm size is 256TB (48bit), maximum size of Vega10,
2157 * block size 512 (9bit)
2158 */
2159
2160 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2161 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2))
2162 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2163 break;
2164 case IP_VERSION(9, 4, 1):
2165 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2166 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2167 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask);
2168
2169 /* Keep the vm size same with Vega20 */
2170 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2171 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2172 break;
2173 case IP_VERSION(9, 4, 3):
2174 case IP_VERSION(9, 4, 4):
2175 case IP_VERSION(9, 5, 0):
2176 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0),
2177 NUM_XCC(adev->gfx.xcc_mask));
2178
2179 inst_mask <<= AMDGPU_MMHUB0(0);
2180 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32);
2181
2182 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2183 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2184 break;
2185 default:
2186 break;
2187 }
2188
2189 /* This interrupt is VMC page fault.*/
2190 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
2191 &adev->gmc.vm_fault);
2192 if (r)
2193 return r;
2194
2195 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) {
2196 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
2197 &adev->gmc.vm_fault);
2198 if (r)
2199 return r;
2200 }
2201
2202 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
2203 &adev->gmc.vm_fault);
2204
2205 if (r)
2206 return r;
2207
2208 if (!amdgpu_sriov_vf(adev) &&
2209 !adev->gmc.xgmi.connected_to_cpu &&
2210 !adev->gmc.is_app_apu) {
2211 /* interrupt sent to DF. */
2212 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
2213 &adev->gmc.ecc_irq);
2214 if (r)
2215 return r;
2216 }
2217
2218 /* Set the internal MC address mask
2219 * This is the max address of the GPU's
2220 * internal address space.
2221 */
2222 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
2223
2224 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >=
2225 IP_VERSION(9, 4, 2) ?
2226 48 :
2227 44;
2228 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits));
2229 if (r) {
2230 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
2231 return r;
2232 }
2233 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits);
2234
2235 r = gmc_v9_0_mc_init(adev);
2236 if (r)
2237 return r;
2238
2239 amdgpu_gmc_get_vbios_allocations(adev);
2240
2241 if (gmc_v9_0_is_multi_chiplet(adev)) {
2242 r = gmc_v9_0_init_mem_ranges(adev);
2243 if (r)
2244 return r;
2245 }
2246
2247 /* Memory manager */
2248 r = amdgpu_bo_init(adev);
2249 if (r)
2250 return r;
2251
2252 r = gmc_v9_0_gart_init(adev);
2253 if (r)
2254 return r;
2255
2256 gmc_v9_0_init_nps_details(adev);
2257 /*
2258 * number of VMs
2259 * VMID 0 is reserved for System
2260 * amdgpu graphics/compute will use VMIDs 1..n-1
2261 * amdkfd will use VMIDs n..15
2262 *
2263 * The first KFD VMID is 8 for GPUs with graphics, 3 for
2264 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
2265 * for video processing.
2266 */
2267 adev->vm_manager.first_kfd_vmid =
2268 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||
2269 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
2270 gmc_v9_0_is_multi_chiplet(adev)) ?
2271 3 :
2272 8;
2273
2274 amdgpu_vm_manager_init(adev);
2275
2276 gmc_v9_0_save_registers(adev);
2277
2278 r = amdgpu_gmc_ras_sw_init(adev);
2279 if (r)
2280 return r;
2281
2282 if (gmc_v9_0_is_multi_chiplet(adev))
2283 amdgpu_gmc_sysfs_init(adev);
2284
2285 return 0;
2286 }
2287
gmc_v9_0_sw_fini(struct amdgpu_ip_block * ip_block)2288 static int gmc_v9_0_sw_fini(struct amdgpu_ip_block *ip_block)
2289 {
2290 struct amdgpu_device *adev = ip_block->adev;
2291
2292 if (gmc_v9_0_is_multi_chiplet(adev))
2293 amdgpu_gmc_sysfs_fini(adev);
2294
2295 amdgpu_gmc_ras_fini(adev);
2296 amdgpu_gem_force_release(adev);
2297 amdgpu_vm_manager_fini(adev);
2298 if (!adev->gmc.real_vram_size) {
2299 dev_info(adev->dev, "Put GART in system memory for APU free\n");
2300 amdgpu_gart_table_ram_free(adev);
2301 } else {
2302 amdgpu_gart_table_vram_free(adev);
2303 }
2304 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0);
2305 amdgpu_bo_fini(adev);
2306
2307 adev->gmc.num_mem_partitions = 0;
2308 kfree(adev->gmc.mem_partitions);
2309
2310 return 0;
2311 }
2312
gmc_v9_0_init_golden_registers(struct amdgpu_device * adev)2313 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
2314 {
2315 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
2316 case IP_VERSION(9, 0, 0):
2317 if (amdgpu_sriov_vf(adev))
2318 break;
2319 fallthrough;
2320 case IP_VERSION(9, 4, 0):
2321 soc15_program_register_sequence(adev,
2322 golden_settings_mmhub_1_0_0,
2323 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
2324 soc15_program_register_sequence(adev,
2325 golden_settings_athub_1_0_0,
2326 ARRAY_SIZE(golden_settings_athub_1_0_0));
2327 break;
2328 case IP_VERSION(9, 1, 0):
2329 case IP_VERSION(9, 2, 0):
2330 /* TODO for renoir */
2331 soc15_program_register_sequence(adev,
2332 golden_settings_athub_1_0_0,
2333 ARRAY_SIZE(golden_settings_athub_1_0_0));
2334 break;
2335 default:
2336 break;
2337 }
2338 }
2339
2340 /**
2341 * gmc_v9_0_restore_registers - restores regs
2342 *
2343 * @adev: amdgpu_device pointer
2344 *
2345 * This restores register values, saved at suspend.
2346 */
gmc_v9_0_restore_registers(struct amdgpu_device * adev)2347 void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
2348 {
2349 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) ||
2350 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) {
2351 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
2352 WARN_ON(adev->gmc.sdpif_register !=
2353 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
2354 }
2355 }
2356
2357 /**
2358 * gmc_v9_0_gart_enable - gart enable
2359 *
2360 * @adev: amdgpu_device pointer
2361 */
gmc_v9_0_gart_enable(struct amdgpu_device * adev)2362 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
2363 {
2364 int r;
2365
2366 if (adev->gmc.xgmi.connected_to_cpu)
2367 amdgpu_gmc_init_pdb0(adev);
2368
2369 if (adev->gart.bo == NULL) {
2370 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
2371 return -EINVAL;
2372 }
2373
2374 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
2375
2376 if (!adev->in_s0ix) {
2377 r = adev->gfxhub.funcs->gart_enable(adev);
2378 if (r)
2379 return r;
2380 }
2381
2382 r = adev->mmhub.funcs->gart_enable(adev);
2383 if (r)
2384 return r;
2385
2386 DRM_INFO("PCIE GART of %uM enabled.\n",
2387 (unsigned int)(adev->gmc.gart_size >> 20));
2388 if (adev->gmc.pdb0_bo)
2389 DRM_INFO("PDB0 located at 0x%016llX\n",
2390 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo));
2391 DRM_INFO("PTB located at 0x%016llX\n",
2392 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
2393
2394 return 0;
2395 }
2396
gmc_v9_0_hw_init(struct amdgpu_ip_block * ip_block)2397 static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block)
2398 {
2399 struct amdgpu_device *adev = ip_block->adev;
2400 bool value;
2401 int i, r;
2402
2403 adev->gmc.flush_pasid_uses_kiq = true;
2404
2405 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush
2406 * (type 2), which flushes both. Due to a race condition with
2407 * concurrent memory accesses using the same TLB cache line, we still
2408 * need a second TLB flush after this.
2409 */
2410 adev->gmc.flush_tlb_needs_extra_type_2 =
2411 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) &&
2412 adev->gmc.xgmi.num_physical_nodes;
2413
2414 /* The sequence of these two function calls matters.*/
2415 gmc_v9_0_init_golden_registers(adev);
2416
2417 if (adev->mode_info.num_crtc) {
2418 /* Lockout access through VGA aperture*/
2419 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
2420 /* disable VGA render */
2421 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
2422 }
2423
2424 if (adev->mmhub.funcs->update_power_gating)
2425 adev->mmhub.funcs->update_power_gating(adev, true);
2426
2427 adev->hdp.funcs->init_registers(adev);
2428
2429 /* After HDP is initialized, flush HDP.*/
2430 amdgpu_device_flush_hdp(adev, NULL);
2431
2432 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
2433 value = false;
2434 else
2435 value = true;
2436
2437 if (!amdgpu_sriov_vf(adev)) {
2438 if (!adev->in_s0ix)
2439 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
2440 adev->mmhub.funcs->set_fault_enable_default(adev, value);
2441 }
2442 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
2443 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0)))
2444 continue;
2445 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
2446 }
2447
2448 if (adev->umc.funcs && adev->umc.funcs->init_registers)
2449 adev->umc.funcs->init_registers(adev);
2450
2451 r = gmc_v9_0_gart_enable(adev);
2452 if (r)
2453 return r;
2454
2455 if (amdgpu_emu_mode == 1)
2456 return amdgpu_gmc_vram_checking(adev);
2457
2458 return 0;
2459 }
2460
2461 /**
2462 * gmc_v9_0_gart_disable - gart disable
2463 *
2464 * @adev: amdgpu_device pointer
2465 *
2466 * This disables all VM page table.
2467 */
gmc_v9_0_gart_disable(struct amdgpu_device * adev)2468 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
2469 {
2470 if (!adev->in_s0ix)
2471 adev->gfxhub.funcs->gart_disable(adev);
2472 adev->mmhub.funcs->gart_disable(adev);
2473 }
2474
gmc_v9_0_hw_fini(struct amdgpu_ip_block * ip_block)2475 static int gmc_v9_0_hw_fini(struct amdgpu_ip_block *ip_block)
2476 {
2477 struct amdgpu_device *adev = ip_block->adev;
2478
2479 gmc_v9_0_gart_disable(adev);
2480
2481 if (amdgpu_sriov_vf(adev)) {
2482 /* full access mode, so don't touch any GMC register */
2483 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
2484 return 0;
2485 }
2486
2487 /*
2488 * Pair the operations did in gmc_v9_0_hw_init and thus maintain
2489 * a correct cached state for GMC. Otherwise, the "gate" again
2490 * operation on S3 resuming will fail due to wrong cached state.
2491 */
2492 if (adev->mmhub.funcs->update_power_gating)
2493 adev->mmhub.funcs->update_power_gating(adev, false);
2494
2495 /*
2496 * For minimal init, late_init is not called, hence VM fault/RAS irqs
2497 * are not enabled.
2498 */
2499 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) {
2500 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
2501
2502 if (adev->gmc.ecc_irq.funcs &&
2503 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
2504 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
2505 }
2506
2507 return 0;
2508 }
2509
gmc_v9_0_suspend(struct amdgpu_ip_block * ip_block)2510 static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block)
2511 {
2512 return gmc_v9_0_hw_fini(ip_block);
2513 }
2514
gmc_v9_0_resume(struct amdgpu_ip_block * ip_block)2515 static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block)
2516 {
2517 struct amdgpu_device *adev = ip_block->adev;
2518 int r;
2519
2520 /* If a reset is done for NPS mode switch, read the memory range
2521 * information again.
2522 */
2523 if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) {
2524 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions);
2525 adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS;
2526 }
2527
2528 r = gmc_v9_0_hw_init(ip_block);
2529 if (r)
2530 return r;
2531
2532 amdgpu_vmid_reset_all(ip_block->adev);
2533
2534 return 0;
2535 }
2536
gmc_v9_0_is_idle(struct amdgpu_ip_block * ip_block)2537 static bool gmc_v9_0_is_idle(struct amdgpu_ip_block *ip_block)
2538 {
2539 /* MC is always ready in GMC v9.*/
2540 return true;
2541 }
2542
gmc_v9_0_wait_for_idle(struct amdgpu_ip_block * ip_block)2543 static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
2544 {
2545 /* There is no need to wait for MC idle in GMC v9.*/
2546 return 0;
2547 }
2548
gmc_v9_0_soft_reset(struct amdgpu_ip_block * ip_block)2549 static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block)
2550 {
2551 /* XXX for emulation.*/
2552 return 0;
2553 }
2554
gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)2555 static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
2556 enum amd_clockgating_state state)
2557 {
2558 struct amdgpu_device *adev = ip_block->adev;
2559
2560 adev->mmhub.funcs->set_clockgating(adev, state);
2561
2562 athub_v1_0_set_clockgating(adev, state);
2563
2564 return 0;
2565 }
2566
gmc_v9_0_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)2567 static void gmc_v9_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
2568 {
2569 struct amdgpu_device *adev = ip_block->adev;
2570
2571 adev->mmhub.funcs->get_clockgating(adev, flags);
2572
2573 athub_v1_0_get_clockgating(adev, flags);
2574 }
2575
gmc_v9_0_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)2576 static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
2577 enum amd_powergating_state state)
2578 {
2579 return 0;
2580 }
2581
2582 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
2583 .name = "gmc_v9_0",
2584 .early_init = gmc_v9_0_early_init,
2585 .late_init = gmc_v9_0_late_init,
2586 .sw_init = gmc_v9_0_sw_init,
2587 .sw_fini = gmc_v9_0_sw_fini,
2588 .hw_init = gmc_v9_0_hw_init,
2589 .hw_fini = gmc_v9_0_hw_fini,
2590 .suspend = gmc_v9_0_suspend,
2591 .resume = gmc_v9_0_resume,
2592 .is_idle = gmc_v9_0_is_idle,
2593 .wait_for_idle = gmc_v9_0_wait_for_idle,
2594 .soft_reset = gmc_v9_0_soft_reset,
2595 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
2596 .set_powergating_state = gmc_v9_0_set_powergating_state,
2597 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
2598 };
2599
2600 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = {
2601 .type = AMD_IP_BLOCK_TYPE_GMC,
2602 .major = 9,
2603 .minor = 0,
2604 .rev = 0,
2605 .funcs = &gmc_v9_0_ip_funcs,
2606 };
2607