xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
1 /*
2  * Copyright 2015 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "priv.h"
25 
26 #include <nvif/class.h>
27 
28 int
gm200_fifo_runq_nr(struct nvkm_fifo * fifo)29 gm200_fifo_runq_nr(struct nvkm_fifo *fifo)
30 {
31 	return nvkm_rd32(fifo->engine.subdev.device, 0x002004) & 0x000000ff;
32 }
33 
34 int
gm200_fifo_chid_nr(struct nvkm_fifo * fifo)35 gm200_fifo_chid_nr(struct nvkm_fifo *fifo)
36 {
37 	return nvkm_rd32(fifo->engine.subdev.device, 0x002008);
38 }
39 
40 static const struct nvkm_fifo_func
41 gm200_fifo = {
42 	.chid_nr = gm200_fifo_chid_nr,
43 	.chid_ctor = gk110_fifo_chid_ctor,
44 	.runq_nr = gm200_fifo_runq_nr,
45 	.runl_ctor = gk104_fifo_runl_ctor,
46 	.init = gk104_fifo_init,
47 	.init_pbdmas = gk104_fifo_init_pbdmas,
48 	.intr = gk104_fifo_intr,
49 	.intr_mmu_fault_unit = gm107_fifo_intr_mmu_fault_unit,
50 	.intr_ctxsw_timeout = gf100_fifo_intr_ctxsw_timeout,
51 	.mmu_fault = &gm107_fifo_mmu_fault,
52 	.nonstall = &gf100_fifo_nonstall,
53 	.runl = &gm107_runl,
54 	.runq = &gk208_runq,
55 	.engn = &gk104_engn,
56 	.engn_ce = &gk104_engn_ce,
57 	.cgrp = {{ 0, 0,  KEPLER_CHANNEL_GROUP_A  }, &gk110_cgrp },
58 	.chan = {{ 0, 0, MAXWELL_CHANNEL_GPFIFO_A }, &gm107_chan },
59 };
60 
61 int
gm200_fifo_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_fifo ** pfifo)62 gm200_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
63 	       struct nvkm_fifo **pfifo)
64 {
65 	return nvkm_fifo_new_(&gm200_fifo, device, type, inst, pfifo);
66 }
67