1 /*
2 * Copyright 2016 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "priv.h"
25 #include "chan.h"
26 #include "runl.h"
27
28 #include <core/gpuobj.h>
29 #include <subdev/fault.h>
30
31 #include <nvif/class.h>
32
33 const struct nvkm_chan_func
34 gm107_chan = {
35 .inst = &gf100_chan_inst,
36 .userd = &gk104_chan_userd,
37 .ramfc = &gk104_chan_ramfc,
38 .bind = gk104_chan_bind_inst,
39 .unbind = gk104_chan_unbind,
40 .start = gk104_chan_start,
41 .stop = gk104_chan_stop,
42 .preempt = gk110_chan_preempt,
43 };
44
45 static void
gm107_runl_insert_chan(struct nvkm_chan * chan,struct nvkm_memory * memory,u64 offset)46 gm107_runl_insert_chan(struct nvkm_chan *chan, struct nvkm_memory *memory, u64 offset)
47 {
48 nvkm_wo32(memory, offset + 0, chan->id);
49 nvkm_wo32(memory, offset + 4, chan->inst->addr >> 12);
50 }
51
52 const struct nvkm_runl_func
53 gm107_runl = {
54 .size = 8,
55 .update = nv50_runl_update,
56 .insert_cgrp = gk110_runl_insert_cgrp,
57 .insert_chan = gm107_runl_insert_chan,
58 .commit = gk104_runl_commit,
59 .wait = nv50_runl_wait,
60 .pending = gk104_runl_pending,
61 .block = gk104_runl_block,
62 .allow = gk104_runl_allow,
63 .fault_clear = gk104_runl_fault_clear,
64 .preempt_pending = gf100_runl_preempt_pending,
65 };
66
67 static const struct nvkm_enum
68 gm107_fifo_mmu_fault_engine[] = {
69 { 0x01, "DISPLAY" },
70 { 0x02, "CAPTURE" },
71 { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
72 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
73 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
74 { 0x06, "SCHED" },
75 { 0x07, "HOST0" },
76 { 0x08, "HOST1" },
77 { 0x09, "HOST2" },
78 { 0x0a, "HOST3" },
79 { 0x0b, "HOST4" },
80 { 0x0c, "HOST5" },
81 { 0x0d, "HOST6" },
82 { 0x0e, "HOST7" },
83 { 0x0f, "HOSTSR" },
84 { 0x13, "PERF" },
85 { 0x17, "PMU" },
86 { 0x18, "PTP" },
87 {}
88 };
89
90 const struct nvkm_fifo_func_mmu_fault
91 gm107_fifo_mmu_fault = {
92 .recover = gf100_fifo_mmu_fault_recover,
93 .access = gf100_fifo_mmu_fault_access,
94 .engine = gm107_fifo_mmu_fault_engine,
95 .reason = gk104_fifo_mmu_fault_reason,
96 .hubclient = gk104_fifo_mmu_fault_hubclient,
97 .gpcclient = gk104_fifo_mmu_fault_gpcclient,
98 };
99
100 void
gm107_fifo_intr_mmu_fault_unit(struct nvkm_fifo * fifo,int unit)101 gm107_fifo_intr_mmu_fault_unit(struct nvkm_fifo *fifo, int unit)
102 {
103 struct nvkm_device *device = fifo->engine.subdev.device;
104 u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
105 u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
106 u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
107 u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
108 struct nvkm_fault_data info;
109
110 info.inst = (u64)inst << 12;
111 info.addr = ((u64)vahi << 32) | valo;
112 info.time = 0;
113 info.engine = unit;
114 info.valid = 1;
115 info.gpc = (type & 0x1f000000) >> 24;
116 info.client = (type & 0x00003f00) >> 8;
117 info.access = (type & 0x00000080) >> 7;
118 info.hub = (type & 0x00000040) >> 6;
119 info.reason = (type & 0x0000000f);
120
121 nvkm_fifo_fault(fifo, &info);
122 }
123
124 static int
gm107_fifo_chid_nr(struct nvkm_fifo * fifo)125 gm107_fifo_chid_nr(struct nvkm_fifo *fifo)
126 {
127 return 2048;
128 }
129
130 static const struct nvkm_fifo_func
131 gm107_fifo = {
132 .chid_nr = gm107_fifo_chid_nr,
133 .chid_ctor = gk110_fifo_chid_ctor,
134 .runq_nr = gf100_fifo_runq_nr,
135 .runl_ctor = gk104_fifo_runl_ctor,
136 .init = gk104_fifo_init,
137 .init_pbdmas = gk104_fifo_init_pbdmas,
138 .intr = gk104_fifo_intr,
139 .intr_mmu_fault_unit = gm107_fifo_intr_mmu_fault_unit,
140 .intr_ctxsw_timeout = gf100_fifo_intr_ctxsw_timeout,
141 .mmu_fault = &gm107_fifo_mmu_fault,
142 .nonstall = &gf100_fifo_nonstall,
143 .runl = &gm107_runl,
144 .runq = &gk208_runq,
145 .engn = &gk104_engn,
146 .engn_ce = &gk104_engn_ce,
147 .cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &gk110_cgrp },
148 .chan = {{ 0, 0, KEPLER_CHANNEL_GPFIFO_B }, &gm107_chan },
149 };
150
151 int
gm107_fifo_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_fifo ** pfifo)152 gm107_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
153 struct nvkm_fifo **pfifo)
154 {
155 return nvkm_fifo_new_(&gm107_fifo, device, type, inst, pfifo);
156 }
157