1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ARM GIC v2m MSI(-X) support
4 * Support for Message Signaled Interrupts for systems that
5 * implement ARM Generic Interrupt Controller: GICv2m.
6 *
7 * Copyright (C) 2014 Advanced Micro Devices, Inc.
8 * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
9 * Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
10 * Brandon Anderson <brandon.anderson@amd.com>
11 */
12
13 #define pr_fmt(fmt) "GICv2m: " fmt
14
15 #include <linux/acpi.h>
16 #include <linux/iommu.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/msi.h>
22 #include <linux/of_address.h>
23 #include <linux/of_pci.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
28
29 #include "irq-msi-lib.h"
30
31 /*
32 * MSI_TYPER:
33 * [31:26] Reserved
34 * [25:16] lowest SPI assigned to MSI
35 * [15:10] Reserved
36 * [9:0] Numer of SPIs assigned to MSI
37 */
38 #define V2M_MSI_TYPER 0x008
39 #define V2M_MSI_TYPER_BASE_SHIFT 16
40 #define V2M_MSI_TYPER_BASE_MASK 0x3FF
41 #define V2M_MSI_TYPER_NUM_MASK 0x3FF
42 #define V2M_MSI_SETSPI_NS 0x040
43 #define V2M_MIN_SPI 32
44 #define V2M_MAX_SPI 1019
45 #define V2M_MSI_IIDR 0xFCC
46
47 #define V2M_MSI_TYPER_BASE_SPI(x) \
48 (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
49
50 #define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK)
51
52 /* APM X-Gene with GICv2m MSI_IIDR register value */
53 #define XGENE_GICV2M_MSI_IIDR 0x06000170
54
55 /* Broadcom NS2 GICv2m MSI_IIDR register value */
56 #define BCM_NS2_GICV2M_MSI_IIDR 0x0000013f
57
58 /* List of flags for specific v2m implementation */
59 #define GICV2M_NEEDS_SPI_OFFSET 0x00000001
60 #define GICV2M_GRAVITON_ADDRESS_ONLY 0x00000002
61
62 static LIST_HEAD(v2m_nodes);
63 static DEFINE_SPINLOCK(v2m_lock);
64
65 struct v2m_data {
66 struct list_head entry;
67 struct fwnode_handle *fwnode;
68 struct resource res; /* GICv2m resource */
69 void __iomem *base; /* GICv2m virt address */
70 u32 spi_start; /* The SPI number that MSIs start */
71 u32 nr_spis; /* The number of SPIs for MSIs */
72 u32 spi_offset; /* offset to be subtracted from SPI number */
73 unsigned long *bm; /* MSI vector bitmap */
74 u32 flags; /* v2m flags for specific implementation */
75 };
76
gicv2m_get_msi_addr(struct v2m_data * v2m,int hwirq)77 static phys_addr_t gicv2m_get_msi_addr(struct v2m_data *v2m, int hwirq)
78 {
79 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
80 return v2m->res.start | ((hwirq - 32) << 3);
81 else
82 return v2m->res.start + V2M_MSI_SETSPI_NS;
83 }
84
gicv2m_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)85 static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
86 {
87 struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
88 phys_addr_t addr = gicv2m_get_msi_addr(v2m, data->hwirq);
89
90 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
91 msg->data = 0;
92 else
93 msg->data = data->hwirq;
94 if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
95 msg->data -= v2m->spi_offset;
96
97 msi_msg_set_addr(irq_data_get_msi_desc(data), msg, addr);
98 }
99
100 static struct irq_chip gicv2m_irq_chip = {
101 .name = "GICv2m",
102 .irq_mask = irq_chip_mask_parent,
103 .irq_unmask = irq_chip_unmask_parent,
104 .irq_eoi = irq_chip_eoi_parent,
105 .irq_set_affinity = irq_chip_set_affinity_parent,
106 .irq_compose_msi_msg = gicv2m_compose_msi_msg,
107 };
108
gicv2m_irq_gic_domain_alloc(struct irq_domain * domain,unsigned int virq,irq_hw_number_t hwirq)109 static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
110 unsigned int virq,
111 irq_hw_number_t hwirq)
112 {
113 struct irq_fwspec fwspec;
114 struct irq_data *d;
115 int err;
116
117 if (is_of_node(domain->parent->fwnode)) {
118 fwspec.fwnode = domain->parent->fwnode;
119 fwspec.param_count = 3;
120 fwspec.param[0] = 0;
121 fwspec.param[1] = hwirq - 32;
122 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
123 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
124 fwspec.fwnode = domain->parent->fwnode;
125 fwspec.param_count = 2;
126 fwspec.param[0] = hwirq;
127 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
128 } else {
129 return -EINVAL;
130 }
131
132 err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
133 if (err)
134 return err;
135
136 /* Configure the interrupt line to be edge */
137 d = irq_domain_get_irq_data(domain->parent, virq);
138 d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
139 return 0;
140 }
141
gicv2m_unalloc_msi(struct v2m_data * v2m,unsigned int hwirq,int nr_irqs)142 static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq,
143 int nr_irqs)
144 {
145 spin_lock(&v2m_lock);
146 bitmap_release_region(v2m->bm, hwirq - v2m->spi_start,
147 get_count_order(nr_irqs));
148 spin_unlock(&v2m_lock);
149 }
150
gicv2m_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)151 static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
152 unsigned int nr_irqs, void *args)
153 {
154 msi_alloc_info_t *info = args;
155 struct v2m_data *v2m = NULL, *tmp;
156 int hwirq, offset, i, err = 0;
157
158 spin_lock(&v2m_lock);
159 list_for_each_entry(tmp, &v2m_nodes, entry) {
160 offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis,
161 get_count_order(nr_irqs));
162 if (offset >= 0) {
163 v2m = tmp;
164 break;
165 }
166 }
167 spin_unlock(&v2m_lock);
168
169 if (!v2m)
170 return -ENOSPC;
171
172 hwirq = v2m->spi_start + offset;
173
174 err = iommu_dma_prepare_msi(info->desc,
175 gicv2m_get_msi_addr(v2m, hwirq));
176 if (err)
177 return err;
178
179 for (i = 0; i < nr_irqs; i++) {
180 err = gicv2m_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
181 if (err)
182 goto fail;
183
184 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
185 &gicv2m_irq_chip, v2m);
186 }
187
188 return 0;
189
190 fail:
191 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
192 gicv2m_unalloc_msi(v2m, hwirq, nr_irqs);
193 return err;
194 }
195
gicv2m_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)196 static void gicv2m_irq_domain_free(struct irq_domain *domain,
197 unsigned int virq, unsigned int nr_irqs)
198 {
199 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
200 struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
201
202 gicv2m_unalloc_msi(v2m, d->hwirq, nr_irqs);
203 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
204 }
205
206 static const struct irq_domain_ops gicv2m_domain_ops = {
207 .select = msi_lib_irq_domain_select,
208 .alloc = gicv2m_irq_domain_alloc,
209 .free = gicv2m_irq_domain_free,
210 };
211
is_msi_spi_valid(u32 base,u32 num)212 static bool is_msi_spi_valid(u32 base, u32 num)
213 {
214 if (base < V2M_MIN_SPI) {
215 pr_err("Invalid MSI base SPI (base:%u)\n", base);
216 return false;
217 }
218
219 if ((num == 0) || (base + num > V2M_MAX_SPI)) {
220 pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
221 num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
222 return false;
223 }
224
225 return true;
226 }
227
gicv2m_teardown(void)228 static void __init gicv2m_teardown(void)
229 {
230 struct v2m_data *v2m, *tmp;
231
232 list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
233 list_del(&v2m->entry);
234 bitmap_free(v2m->bm);
235 iounmap(v2m->base);
236 of_node_put(to_of_node(v2m->fwnode));
237 if (is_fwnode_irqchip(v2m->fwnode))
238 irq_domain_free_fwnode(v2m->fwnode);
239 kfree(v2m);
240 }
241 }
242
243
244 #define GICV2M_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
245 MSI_FLAG_USE_DEF_CHIP_OPS | \
246 MSI_FLAG_PCI_MSI_MASK_PARENT)
247
248 #define GICV2M_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \
249 MSI_FLAG_PCI_MSIX | \
250 MSI_FLAG_MULTI_PCI_MSI)
251
252 static struct msi_parent_ops gicv2m_msi_parent_ops = {
253 .supported_flags = GICV2M_MSI_FLAGS_SUPPORTED,
254 .required_flags = GICV2M_MSI_FLAGS_REQUIRED,
255 .chip_flags = MSI_CHIP_FLAG_SET_EOI | MSI_CHIP_FLAG_SET_ACK,
256 .bus_select_token = DOMAIN_BUS_NEXUS,
257 .bus_select_mask = MATCH_PCI_MSI | MATCH_PLATFORM_MSI,
258 .prefix = "GICv2m-",
259 .init_dev_msi_info = msi_lib_init_dev_msi_info,
260 };
261
gicv2m_allocate_domains(struct irq_domain * parent)262 static __init int gicv2m_allocate_domains(struct irq_domain *parent)
263 {
264 struct irq_domain *inner_domain;
265 struct v2m_data *v2m;
266
267 v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
268 if (!v2m)
269 return 0;
270
271 inner_domain = irq_domain_create_hierarchy(parent, 0, 0, v2m->fwnode,
272 &gicv2m_domain_ops, v2m);
273 if (!inner_domain) {
274 pr_err("Failed to create GICv2m domain\n");
275 return -ENOMEM;
276 }
277
278 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
279 inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;
280 inner_domain->msi_parent_ops = &gicv2m_msi_parent_ops;
281 return 0;
282 }
283
gicv2m_init_one(struct fwnode_handle * fwnode,u32 spi_start,u32 nr_spis,struct resource * res,u32 flags)284 static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
285 u32 spi_start, u32 nr_spis,
286 struct resource *res, u32 flags)
287 {
288 int ret;
289 struct v2m_data *v2m;
290
291 v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
292 if (!v2m)
293 return -ENOMEM;
294
295 INIT_LIST_HEAD(&v2m->entry);
296 v2m->fwnode = fwnode;
297 v2m->flags = flags;
298
299 memcpy(&v2m->res, res, sizeof(struct resource));
300
301 v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
302 if (!v2m->base) {
303 pr_err("Failed to map GICv2m resource\n");
304 ret = -ENOMEM;
305 goto err_free_v2m;
306 }
307
308 if (spi_start && nr_spis) {
309 v2m->spi_start = spi_start;
310 v2m->nr_spis = nr_spis;
311 } else {
312 u32 typer;
313
314 /* Graviton should always have explicit spi_start/nr_spis */
315 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) {
316 ret = -EINVAL;
317 goto err_iounmap;
318 }
319 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
320
321 v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
322 v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
323 }
324
325 if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
326 ret = -EINVAL;
327 goto err_iounmap;
328 }
329
330 /*
331 * APM X-Gene GICv2m implementation has an erratum where
332 * the MSI data needs to be the offset from the spi_start
333 * in order to trigger the correct MSI interrupt. This is
334 * different from the standard GICv2m implementation where
335 * the MSI data is the absolute value within the range from
336 * spi_start to (spi_start + num_spis).
337 *
338 * Broadcom NS2 GICv2m implementation has an erratum where the MSI data
339 * is 'spi_number - 32'
340 *
341 * Reading that register fails on the Graviton implementation
342 */
343 if (!(v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)) {
344 switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {
345 case XGENE_GICV2M_MSI_IIDR:
346 v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
347 v2m->spi_offset = v2m->spi_start;
348 break;
349 case BCM_NS2_GICV2M_MSI_IIDR:
350 v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
351 v2m->spi_offset = 32;
352 break;
353 }
354 }
355 v2m->bm = bitmap_zalloc(v2m->nr_spis, GFP_KERNEL);
356 if (!v2m->bm) {
357 ret = -ENOMEM;
358 goto err_iounmap;
359 }
360
361 list_add_tail(&v2m->entry, &v2m_nodes);
362
363 pr_info("range%pR, SPI[%d:%d]\n", res,
364 v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
365 return 0;
366
367 err_iounmap:
368 iounmap(v2m->base);
369 err_free_v2m:
370 kfree(v2m);
371 return ret;
372 }
373
374 static __initconst struct of_device_id gicv2m_device_id[] = {
375 { .compatible = "arm,gic-v2m-frame", },
376 {},
377 };
378
gicv2m_of_init(struct fwnode_handle * parent_handle,struct irq_domain * parent)379 static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
380 struct irq_domain *parent)
381 {
382 int ret = 0;
383 struct device_node *node = to_of_node(parent_handle);
384 struct device_node *child;
385
386 for (child = of_find_matching_node(node, gicv2m_device_id); child;
387 child = of_find_matching_node(child, gicv2m_device_id)) {
388 u32 spi_start = 0, nr_spis = 0;
389 struct resource res;
390
391 if (!of_property_read_bool(child, "msi-controller"))
392 continue;
393
394 ret = of_address_to_resource(child, 0, &res);
395 if (ret) {
396 pr_err("Failed to allocate v2m resource.\n");
397 break;
398 }
399
400 if (!of_property_read_u32(child, "arm,msi-base-spi",
401 &spi_start) &&
402 !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
403 pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
404 spi_start, nr_spis);
405
406 ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis,
407 &res, 0);
408 if (ret)
409 break;
410 }
411
412 if (ret && child)
413 of_node_put(child);
414 if (!ret)
415 ret = gicv2m_allocate_domains(parent);
416 if (ret)
417 gicv2m_teardown();
418 return ret;
419 }
420
421 #ifdef CONFIG_ACPI
422 static int acpi_num_msi;
423
gicv2m_get_fwnode(struct device * dev)424 static __init struct fwnode_handle *gicv2m_get_fwnode(struct device *dev)
425 {
426 struct v2m_data *data;
427
428 if (WARN_ON(acpi_num_msi <= 0))
429 return NULL;
430
431 /* We only return the fwnode of the first MSI frame. */
432 data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
433 if (!data)
434 return NULL;
435
436 return data->fwnode;
437 }
438
acpi_check_amazon_graviton_quirks(void)439 static __init bool acpi_check_amazon_graviton_quirks(void)
440 {
441 static struct acpi_table_madt *madt;
442 acpi_status status;
443 bool rc = false;
444
445 #define ACPI_AMZN_OEM_ID "AMAZON"
446
447 status = acpi_get_table(ACPI_SIG_MADT, 0,
448 (struct acpi_table_header **)&madt);
449
450 if (ACPI_FAILURE(status) || !madt)
451 return rc;
452 rc = !memcmp(madt->header.oem_id, ACPI_AMZN_OEM_ID, ACPI_OEM_ID_SIZE);
453 acpi_put_table((struct acpi_table_header *)madt);
454
455 return rc;
456 }
457
458 static int __init
acpi_parse_madt_msi(union acpi_subtable_headers * header,const unsigned long end)459 acpi_parse_madt_msi(union acpi_subtable_headers *header,
460 const unsigned long end)
461 {
462 int ret;
463 struct resource res;
464 u32 spi_start = 0, nr_spis = 0;
465 struct acpi_madt_generic_msi_frame *m;
466 struct fwnode_handle *fwnode;
467 u32 flags = 0;
468
469 m = (struct acpi_madt_generic_msi_frame *)header;
470 if (BAD_MADT_ENTRY(m, end))
471 return -EINVAL;
472
473 res.start = m->base_address;
474 res.end = m->base_address + SZ_4K - 1;
475 res.flags = IORESOURCE_MEM;
476
477 if (acpi_check_amazon_graviton_quirks()) {
478 pr_info("applying Amazon Graviton quirk\n");
479 res.end = res.start + SZ_8K - 1;
480 flags |= GICV2M_GRAVITON_ADDRESS_ONLY;
481 gicv2m_msi_parent_ops.supported_flags &= ~MSI_FLAG_MULTI_PCI_MSI;
482 }
483
484 if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
485 spi_start = m->spi_base;
486 nr_spis = m->spi_count;
487
488 pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
489 spi_start, nr_spis);
490 }
491
492 fwnode = irq_domain_alloc_fwnode(&res.start);
493 if (!fwnode) {
494 pr_err("Unable to allocate GICv2m domain token\n");
495 return -EINVAL;
496 }
497
498 ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res, flags);
499 if (ret)
500 irq_domain_free_fwnode(fwnode);
501
502 return ret;
503 }
504
gicv2m_acpi_init(struct irq_domain * parent)505 static int __init gicv2m_acpi_init(struct irq_domain *parent)
506 {
507 int ret;
508
509 if (acpi_num_msi > 0)
510 return 0;
511
512 acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
513 acpi_parse_madt_msi, 0);
514
515 if (acpi_num_msi <= 0)
516 goto err_out;
517
518 ret = gicv2m_allocate_domains(parent);
519 if (ret)
520 goto err_out;
521
522 pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);
523
524 return 0;
525
526 err_out:
527 gicv2m_teardown();
528 return -EINVAL;
529 }
530 #else /* CONFIG_ACPI */
gicv2m_acpi_init(struct irq_domain * parent)531 static int __init gicv2m_acpi_init(struct irq_domain *parent)
532 {
533 return -EINVAL;
534 }
535 #endif /* CONFIG_ACPI */
536
gicv2m_init(struct fwnode_handle * parent_handle,struct irq_domain * parent)537 int __init gicv2m_init(struct fwnode_handle *parent_handle,
538 struct irq_domain *parent)
539 {
540 if (is_of_node(parent_handle))
541 return gicv2m_of_init(parent_handle, parent);
542
543 return gicv2m_acpi_init(parent);
544 }
545