1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "amdgpu.h"
25 #include "gfxhub_v3_0_3.h"
26
27 #include "gc/gc_11_0_3_offset.h"
28 #include "gc/gc_11_0_3_sh_mask.h"
29 #include "navi10_enum.h"
30 #include "soc15_common.h"
31
32 #define regGCVM_L2_CNTL3_DEFAULT 0x80100007
33 #define regGCVM_L2_CNTL4_DEFAULT 0x000000c1
34 #define regGCVM_L2_CNTL5_DEFAULT 0x00003fe0
35
36 static const char * const gfxhub_client_ids[] = {
37 "CB/DB",
38 "Reserved",
39 "GE1",
40 "GE2",
41 "CPF",
42 "CPC",
43 "CPG",
44 "RLC",
45 "TCP",
46 "SQC (inst)",
47 "SQC (data)",
48 "SQG",
49 "Reserved",
50 "SDMA0",
51 "SDMA1",
52 "GCR",
53 "SDMA2",
54 "SDMA3",
55 };
56
gfxhub_v3_0_3_get_invalidate_req(unsigned int vmid,uint32_t flush_type)57 static uint32_t gfxhub_v3_0_3_get_invalidate_req(unsigned int vmid,
58 uint32_t flush_type)
59 {
60 u32 req = 0;
61
62 /* invalidate using legacy mode on vmid*/
63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
64 PER_VMID_INVALIDATE_REQ, 1 << vmid);
65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
70 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
71 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
72 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
73
74 return req;
75 }
76
77 static void
gfxhub_v3_0_3_print_l2_protection_fault_status(struct amdgpu_device * adev,uint32_t status)78 gfxhub_v3_0_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
79 uint32_t status)
80 {
81 u32 cid = REG_GET_FIELD(status,
82 GCVM_L2_PROTECTION_FAULT_STATUS, CID);
83
84 dev_err(adev->dev,
85 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
86 status);
87 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
88 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],
89 cid);
90 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
91 REG_GET_FIELD(status,
92 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
93 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
94 REG_GET_FIELD(status,
95 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
96 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
97 REG_GET_FIELD(status,
98 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
99 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
100 REG_GET_FIELD(status,
101 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
102 dev_err(adev->dev, "\t RW: 0x%lx\n",
103 REG_GET_FIELD(status,
104 GCVM_L2_PROTECTION_FAULT_STATUS, RW));
105 }
106
gfxhub_v3_0_3_get_fb_location(struct amdgpu_device * adev)107 static u64 gfxhub_v3_0_3_get_fb_location(struct amdgpu_device *adev)
108 {
109 u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);
110
111 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
112 base <<= 24;
113
114 return base;
115 }
116
gfxhub_v3_0_3_get_mc_fb_offset(struct amdgpu_device * adev)117 static u64 gfxhub_v3_0_3_get_mc_fb_offset(struct amdgpu_device *adev)
118 {
119 return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;
120 }
121
gfxhub_v3_0_3_setup_vm_pt_regs(struct amdgpu_device * adev,uint32_t vmid,uint64_t page_table_base)122 static void gfxhub_v3_0_3_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
123 uint64_t page_table_base)
124 {
125 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
126
127 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
128 hub->ctx_addr_distance * vmid,
129 lower_32_bits(page_table_base));
130
131 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
132 hub->ctx_addr_distance * vmid,
133 upper_32_bits(page_table_base));
134 }
135
gfxhub_v3_0_3_init_gart_aperture_regs(struct amdgpu_device * adev)136 static void gfxhub_v3_0_3_init_gart_aperture_regs(struct amdgpu_device *adev)
137 {
138 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
139
140 gfxhub_v3_0_3_setup_vm_pt_regs(adev, 0, pt_base);
141
142 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
143 (u32)(adev->gmc.gart_start >> 12));
144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
145 (u32)(adev->gmc.gart_start >> 44));
146
147 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
148 (u32)(adev->gmc.gart_end >> 12));
149 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
150 (u32)(adev->gmc.gart_end >> 44));
151 }
152
gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device * adev)153 static void gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device *adev)
154 {
155 uint64_t value;
156
157 if (amdgpu_sriov_vf(adev))
158 return;
159
160 /* Disable AGP. */
161 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0);
162 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
163 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
164
165 /* Program the system aperture low logical page number. */
166 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
167 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
168 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
169 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
170
171 /* Set default page address. */
172 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
173 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
174 (u32)(value >> 12));
175 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
176 (u32)(value >> 44));
177
178 /* Program "protection fault". */
179 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
180 (u32)(adev->dummy_page_addr >> 12));
181 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
182 (u32)((u64)adev->dummy_page_addr >> 44));
183
184 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
185 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
186 }
187
188
gfxhub_v3_0_3_init_tlb_regs(struct amdgpu_device * adev)189 static void gfxhub_v3_0_3_init_tlb_regs(struct amdgpu_device *adev)
190 {
191 uint32_t tmp;
192
193 /* Setup TLB control */
194 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
195
196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
199 ENABLE_ADVANCED_DRIVER_MODEL, 1);
200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
201 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
202 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
203 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
204 MTYPE, MTYPE_UC); /* UC, uncached */
205
206 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
207 }
208
gfxhub_v3_0_3_init_cache_regs(struct amdgpu_device * adev)209 static void gfxhub_v3_0_3_init_cache_regs(struct amdgpu_device *adev)
210 {
211 uint32_t tmp;
212
213 /* These registers are not accessible to VF-SRIOV.
214 * The PF will program them instead.
215 */
216 if (amdgpu_sriov_vf(adev))
217 return;
218
219 /* Setup L2 cache */
220 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);
221 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
222 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
224 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
225 /* XXX for emulation, Refer to closed source code.*/
226 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
227 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
228 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
230 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
231 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);
232
233 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);
234 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
236 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);
237
238 tmp = regGCVM_L2_CNTL3_DEFAULT;
239 if (adev->gmc.translate_further) {
240 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
241 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
242 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
243 } else {
244 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
245 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
246 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
247 }
248 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);
249
250 tmp = regGCVM_L2_CNTL4_DEFAULT;
251 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
252 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
253 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);
254
255 tmp = regGCVM_L2_CNTL5_DEFAULT;
256 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
257 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);
258 }
259
gfxhub_v3_0_3_enable_system_domain(struct amdgpu_device * adev)260 static void gfxhub_v3_0_3_enable_system_domain(struct amdgpu_device *adev)
261 {
262 uint32_t tmp;
263
264 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);
265 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
266 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
267 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
268 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
269 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);
270 }
271
gfxhub_v3_0_3_disable_identity_aperture(struct amdgpu_device * adev)272 static void gfxhub_v3_0_3_disable_identity_aperture(struct amdgpu_device *adev)
273 {
274 /* These registers are not accessible to VF-SRIOV.
275 * The PF will program them instead.
276 */
277 if (amdgpu_sriov_vf(adev))
278 return;
279
280 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
281 0xFFFFFFFF);
282 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
283 0x0000000F);
284
285 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
286 0);
287 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
288 0);
289
290 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
291 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
292
293 }
294
gfxhub_v3_0_3_setup_vmid_config(struct amdgpu_device * adev)295 static void gfxhub_v3_0_3_setup_vmid_config(struct amdgpu_device *adev)
296 {
297 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
298 int i;
299 uint32_t tmp;
300
301 for (i = 0; i <= 14; i++) {
302 tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
303 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
304 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
305 adev->vm_manager.num_level);
306 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
307 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
308 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
309 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
310 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
311 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
312 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
313 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
314 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
315 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
316 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
317 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
318 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
319 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
320 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
321 PAGE_TABLE_BLOCK_SIZE,
322 adev->vm_manager.block_size - 9);
323 /* Send no-retry XNACK on fault to suppress VM fault storm. */
324 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
325 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
326 !amdgpu_noretry);
327 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL,
328 i * hub->ctx_distance, tmp);
329 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
330 i * hub->ctx_addr_distance, 0);
331 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
332 i * hub->ctx_addr_distance, 0);
333 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
334 i * hub->ctx_addr_distance,
335 lower_32_bits(adev->vm_manager.max_pfn - 1));
336 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
337 i * hub->ctx_addr_distance,
338 upper_32_bits(adev->vm_manager.max_pfn - 1));
339 }
340
341 hub->vm_cntx_cntl = tmp;
342 }
343
gfxhub_v3_0_3_program_invalidation(struct amdgpu_device * adev)344 static void gfxhub_v3_0_3_program_invalidation(struct amdgpu_device *adev)
345 {
346 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
347 unsigned int i;
348
349 for (i = 0 ; i < 18; ++i) {
350 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
351 i * hub->eng_addr_distance, 0xffffffff);
352 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
353 i * hub->eng_addr_distance, 0x1f);
354 }
355 }
356
gfxhub_v3_0_3_gart_enable(struct amdgpu_device * adev)357 static int gfxhub_v3_0_3_gart_enable(struct amdgpu_device *adev)
358 {
359 /* GART Enable. */
360 gfxhub_v3_0_3_init_gart_aperture_regs(adev);
361 gfxhub_v3_0_3_init_system_aperture_regs(adev);
362 gfxhub_v3_0_3_init_tlb_regs(adev);
363 gfxhub_v3_0_3_init_cache_regs(adev);
364
365 gfxhub_v3_0_3_enable_system_domain(adev);
366 gfxhub_v3_0_3_disable_identity_aperture(adev);
367 gfxhub_v3_0_3_setup_vmid_config(adev);
368 gfxhub_v3_0_3_program_invalidation(adev);
369
370 return 0;
371 }
372
gfxhub_v3_0_3_gart_disable(struct amdgpu_device * adev)373 static void gfxhub_v3_0_3_gart_disable(struct amdgpu_device *adev)
374 {
375 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
376 u32 tmp;
377 u32 i;
378
379 /* Disable all tables */
380 for (i = 0; i < 16; i++)
381 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL,
382 i * hub->ctx_distance, 0);
383
384 /* Setup TLB control */
385 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
386 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
387 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
388 ENABLE_ADVANCED_DRIVER_MODEL, 0);
389 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
390
391 /* Setup L2 cache */
392 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
393 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0);
394 }
395
396 /**
397 * gfxhub_v3_0_3_set_fault_enable_default - update GART/VM fault handling
398 *
399 * @adev: amdgpu_device pointer
400 * @value: true redirects VM faults to the default page
401 */
gfxhub_v3_0_3_set_fault_enable_default(struct amdgpu_device * adev,bool value)402 static void gfxhub_v3_0_3_set_fault_enable_default(struct amdgpu_device *adev,
403 bool value)
404 {
405 u32 tmp;
406
407 /* These registers are not accessible to VF-SRIOV.
408 * The PF will program them instead.
409 */
410 if (amdgpu_sriov_vf(adev))
411 return;
412
413 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
414 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
415 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
416 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
417 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
418 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
419 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
420 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
421 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
422 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
423 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
424 value);
425 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
426 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
427 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
428 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
429 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
430 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
431 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
432 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
433 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
434 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
435 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
436 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
437 if (!value) {
438 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
439 CRASH_ON_NO_RETRY_FAULT, 1);
440 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
441 CRASH_ON_RETRY_FAULT, 1);
442 }
443 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
444 }
445
446 static const struct amdgpu_vmhub_funcs gfxhub_v3_0_3_vmhub_funcs = {
447 .print_l2_protection_fault_status = gfxhub_v3_0_3_print_l2_protection_fault_status,
448 .get_invalidate_req = gfxhub_v3_0_3_get_invalidate_req,
449 };
450
gfxhub_v3_0_3_init(struct amdgpu_device * adev)451 static void gfxhub_v3_0_3_init(struct amdgpu_device *adev)
452 {
453 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
454
455 hub->ctx0_ptb_addr_lo32 =
456 SOC15_REG_OFFSET(GC, 0,
457 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
458 hub->ctx0_ptb_addr_hi32 =
459 SOC15_REG_OFFSET(GC, 0,
460 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
461 hub->vm_inv_eng0_sem =
462 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM);
463 hub->vm_inv_eng0_req =
464 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ);
465 hub->vm_inv_eng0_ack =
466 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK);
467 hub->vm_context0_cntl =
468 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL);
469 hub->vm_l2_pro_fault_status =
470 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS);
471 hub->vm_l2_pro_fault_cntl =
472 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
473
474 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL;
475 hub->ctx_addr_distance = regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
476 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
477 hub->eng_distance = regGCVM_INVALIDATE_ENG1_REQ -
478 regGCVM_INVALIDATE_ENG0_REQ;
479 hub->eng_addr_distance = regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
480 regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
481
482 hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
483 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
484 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
485 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
486 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
487 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
488 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
489
490 hub->vmhub_funcs = &gfxhub_v3_0_3_vmhub_funcs;
491 }
492
493 const struct amdgpu_gfxhub_funcs gfxhub_v3_0_3_funcs = {
494 .get_fb_location = gfxhub_v3_0_3_get_fb_location,
495 .get_mc_fb_offset = gfxhub_v3_0_3_get_mc_fb_offset,
496 .setup_vm_pt_regs = gfxhub_v3_0_3_setup_vm_pt_regs,
497 .gart_enable = gfxhub_v3_0_3_gart_enable,
498 .gart_disable = gfxhub_v3_0_3_gart_disable,
499 .set_fault_enable_default = gfxhub_v3_0_3_set_fault_enable_default,
500 .init = gfxhub_v3_0_3_init,
501 };
502