1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/delay.h>
24 #include <linux/kernel.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include "amdgpu.h"
29 #include "amdgpu_gfx.h"
30 #include "amdgpu_psp.h"
31 #include "amdgpu_smu.h"
32 #include "imu_v12_0.h"
33 #include "soc24.h"
34 #include "nvd.h"
35
36 #include "gc/gc_12_0_0_offset.h"
37 #include "gc/gc_12_0_0_sh_mask.h"
38 #include "soc24_enum.h"
39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h"
40
41 #include "soc15.h"
42 #include "clearstate_gfx12.h"
43 #include "v12_structs.h"
44 #include "gfx_v12_0.h"
45 #include "nbif_v6_3_1.h"
46 #include "mes_v12_0.h"
47 #include "mes_userqueue.h"
48 #include "amdgpu_userq_fence.h"
49
50 #define GFX12_NUM_GFX_RINGS 1
51 #define GFX12_MEC_HPD_SIZE 2048
52
53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
54
55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100
56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000
57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01
59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000
60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000
61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000
62
63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006
64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100
66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509
67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000
69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501
70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000
71
72
73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin");
74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin");
75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin");
76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin");
77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin");
78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin");
79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin");
80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin");
81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin");
82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc_kicker.bin");
83 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin");
84
85 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = {
86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
88 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
91 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
94 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
99 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
101 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
115 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
116 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
117 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
118 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
120 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
121 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
122 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
125 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32),
128 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
133 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
134 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),
137 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),
138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),
139 /* cp header registers */
140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
147 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
148 /* SE status registers */
149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
152 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)
153 };
154
155 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = {
156 /* compute registers */
157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),
196 /* cp header registers */
197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
204 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
205 };
206
207 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = {
208 /* gfx queue registers */
209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
229 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
233 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
234 /* cp header registers */
235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
242 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
250 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
251 };
252
253 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = {
254 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f),
255 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000),
256 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020)
257 };
258
259 static const struct soc15_reg_golden golden_settings_gc_12_0[] = {
260 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000),
261 };
262
263 #define DEFAULT_SH_MEM_CONFIG \
264 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
265 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
266 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
267
268 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev);
269 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev);
270 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev);
271 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev);
272 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev);
273 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev);
274 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,
275 struct amdgpu_cu_info *cu_info);
276 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev);
277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
278 u32 sh_num, u32 instance, int xcc_id);
279 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
280
281 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
282 uint32_t val);
283 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
284 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
285 uint16_t pasid, uint32_t flush_type,
286 bool all_hub, uint8_t dst_sel);
287 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
288 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
289 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
290 bool enable);
291
gfx_v12_0_kiq_set_resources(struct amdgpu_ring * kiq_ring,uint64_t queue_mask)292 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
293 uint64_t queue_mask)
294 {
295 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
296 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
297 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
298 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
299 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
300 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
301 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
302 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
303 amdgpu_ring_write(kiq_ring, 0);
304 }
305
gfx_v12_0_kiq_map_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring)306 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring,
307 struct amdgpu_ring *ring)
308 {
309 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
310 uint64_t wptr_addr = ring->wptr_gpu_addr;
311 uint32_t me = 0, eng_sel = 0;
312
313 switch (ring->funcs->type) {
314 case AMDGPU_RING_TYPE_COMPUTE:
315 me = 1;
316 eng_sel = 0;
317 break;
318 case AMDGPU_RING_TYPE_GFX:
319 me = 0;
320 eng_sel = 4;
321 break;
322 case AMDGPU_RING_TYPE_MES:
323 me = 2;
324 eng_sel = 5;
325 break;
326 default:
327 WARN_ON(1);
328 }
329
330 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
331 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
332 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
333 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
334 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
335 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
336 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
337 PACKET3_MAP_QUEUES_ME((me)) |
338 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
339 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
340 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
341 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
342 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
343 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
344 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
345 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
346 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
347 }
348
gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq)349 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
350 struct amdgpu_ring *ring,
351 enum amdgpu_unmap_queues_action action,
352 u64 gpu_addr, u64 seq)
353 {
354 struct amdgpu_device *adev = kiq_ring->adev;
355 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
356
357 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
358 amdgpu_mes_unmap_legacy_queue(adev, ring, action,
359 gpu_addr, seq, 0);
360 return;
361 }
362
363 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
364 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
365 PACKET3_UNMAP_QUEUES_ACTION(action) |
366 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
367 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
368 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
369 amdgpu_ring_write(kiq_ring,
370 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
371
372 if (action == PREEMPT_QUEUES_NO_UNMAP) {
373 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
374 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
375 amdgpu_ring_write(kiq_ring, seq);
376 } else {
377 amdgpu_ring_write(kiq_ring, 0);
378 amdgpu_ring_write(kiq_ring, 0);
379 amdgpu_ring_write(kiq_ring, 0);
380 }
381 }
382
gfx_v12_0_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq)383 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring,
384 struct amdgpu_ring *ring,
385 u64 addr, u64 seq)
386 {
387 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
388
389 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
390 amdgpu_ring_write(kiq_ring,
391 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
392 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
393 PACKET3_QUERY_STATUS_COMMAND(2));
394 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
395 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
396 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
397 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
398 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
399 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
400 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
401 }
402
gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub)403 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
404 uint16_t pasid,
405 uint32_t flush_type,
406 bool all_hub)
407 {
408 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
409 }
410
411 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = {
412 .kiq_set_resources = gfx_v12_0_kiq_set_resources,
413 .kiq_map_queues = gfx_v12_0_kiq_map_queues,
414 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues,
415 .kiq_query_status = gfx_v12_0_kiq_query_status,
416 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs,
417 .set_resources_size = 8,
418 .map_queues_size = 7,
419 .unmap_queues_size = 6,
420 .query_status_size = 7,
421 .invalidate_tlbs_size = 2,
422 };
423
gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device * adev)424 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
425 {
426 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs;
427 }
428
gfx_v12_0_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)429 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
430 int mem_space, int opt, uint32_t addr0,
431 uint32_t addr1, uint32_t ref,
432 uint32_t mask, uint32_t inv)
433 {
434 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
435 amdgpu_ring_write(ring,
436 /* memory (1) or register (0) */
437 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
438 WAIT_REG_MEM_OPERATION(opt) | /* wait */
439 WAIT_REG_MEM_FUNCTION(3) | /* equal */
440 WAIT_REG_MEM_ENGINE(eng_sel)));
441
442 if (mem_space)
443 BUG_ON(addr0 & 0x3); /* Dword align */
444 amdgpu_ring_write(ring, addr0);
445 amdgpu_ring_write(ring, addr1);
446 amdgpu_ring_write(ring, ref);
447 amdgpu_ring_write(ring, mask);
448 amdgpu_ring_write(ring, inv); /* poll interval */
449 }
450
gfx_v12_0_ring_test_ring(struct amdgpu_ring * ring)451 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring)
452 {
453 struct amdgpu_device *adev = ring->adev;
454 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
455 uint32_t tmp = 0;
456 unsigned i;
457 int r;
458
459 WREG32(scratch, 0xCAFEDEAD);
460 r = amdgpu_ring_alloc(ring, 5);
461 if (r) {
462 drm_err(adev_to_drm(adev),
463 "cp failed to lock ring %d (%d).\n",
464 ring->idx, r);
465 return r;
466 }
467
468 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {
469 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
470 } else {
471 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
472 amdgpu_ring_write(ring, scratch -
473 PACKET3_SET_UCONFIG_REG_START);
474 amdgpu_ring_write(ring, 0xDEADBEEF);
475 }
476 amdgpu_ring_commit(ring);
477
478 for (i = 0; i < adev->usec_timeout; i++) {
479 tmp = RREG32(scratch);
480 if (tmp == 0xDEADBEEF)
481 break;
482 if (amdgpu_emu_mode == 1)
483 msleep(1);
484 else
485 udelay(1);
486 }
487
488 if (i >= adev->usec_timeout)
489 r = -ETIMEDOUT;
490 return r;
491 }
492
gfx_v12_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)493 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
494 {
495 struct amdgpu_device *adev = ring->adev;
496 struct amdgpu_ib ib;
497 struct dma_fence *f = NULL;
498 unsigned index;
499 uint64_t gpu_addr;
500 uint32_t *cpu_ptr;
501 long r;
502
503 /* MES KIQ fw hasn't indirect buffer support for now */
504 if (adev->enable_mes_kiq &&
505 ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
506 return 0;
507
508 memset(&ib, 0, sizeof(ib));
509
510 r = amdgpu_device_wb_get(adev, &index);
511 if (r)
512 return r;
513
514 gpu_addr = adev->wb.gpu_addr + (index * 4);
515 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
516 cpu_ptr = &adev->wb.wb[index];
517
518 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
519 if (r) {
520 drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r);
521 goto err1;
522 }
523
524 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
526 ib.ptr[2] = lower_32_bits(gpu_addr);
527 ib.ptr[3] = upper_32_bits(gpu_addr);
528 ib.ptr[4] = 0xDEADBEEF;
529 ib.length_dw = 5;
530
531 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
532 if (r)
533 goto err2;
534
535 r = dma_fence_wait_timeout(f, false, timeout);
536 if (r == 0) {
537 r = -ETIMEDOUT;
538 goto err2;
539 } else if (r < 0) {
540 goto err2;
541 }
542
543 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
544 r = 0;
545 else
546 r = -EINVAL;
547 err2:
548 amdgpu_ib_free(&ib, NULL);
549 dma_fence_put(f);
550 err1:
551 amdgpu_device_wb_free(adev, index);
552 return r;
553 }
554
gfx_v12_0_free_microcode(struct amdgpu_device * adev)555 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev)
556 {
557 amdgpu_ucode_release(&adev->gfx.pfp_fw);
558 amdgpu_ucode_release(&adev->gfx.me_fw);
559 amdgpu_ucode_release(&adev->gfx.rlc_fw);
560 amdgpu_ucode_release(&adev->gfx.mec_fw);
561
562 kfree(adev->gfx.rlc.register_list_format);
563 }
564
gfx_v12_0_init_toc_microcode(struct amdgpu_device * adev,const char * ucode_prefix)565 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix)
566 {
567 const struct psp_firmware_header_v1_0 *toc_hdr;
568 int err = 0;
569
570 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw,
571 AMDGPU_UCODE_REQUIRED,
572 "amdgpu/%s_toc.bin", ucode_prefix);
573 if (err)
574 goto out;
575
576 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
577 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
578 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
579 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
580 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
581 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
582 return 0;
583 out:
584 amdgpu_ucode_release(&adev->psp.toc_fw);
585 return err;
586 }
587
gfx_v12_0_init_microcode(struct amdgpu_device * adev)588 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev)
589 {
590 char ucode_prefix[30];
591 int err;
592 const struct rlc_firmware_header_v2_0 *rlc_hdr;
593 uint16_t version_major;
594 uint16_t version_minor;
595
596 DRM_DEBUG("\n");
597
598 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
599
600 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
601 AMDGPU_UCODE_REQUIRED,
602 "amdgpu/%s_pfp.bin", ucode_prefix);
603 if (err)
604 goto out;
605
606 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version(
607 (union amdgpu_firmware_header *)
608 adev->gfx.pfp_fw->data, 2, 0);
609 if (adev->gfx.rs64_enable)
610 dev_dbg(adev->dev, "CP RS64 enable\n");
611
612 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);
613 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
614
615 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
616 AMDGPU_UCODE_REQUIRED,
617 "amdgpu/%s_me.bin", ucode_prefix);
618 if (err)
619 goto out;
620 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);
621 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
622
623 if (!amdgpu_sriov_vf(adev)) {
624 if (amdgpu_is_kicker_fw(adev))
625 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
626 AMDGPU_UCODE_REQUIRED,
627 "amdgpu/%s_rlc_kicker.bin", ucode_prefix);
628 else
629 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
630 AMDGPU_UCODE_REQUIRED,
631 "amdgpu/%s_rlc.bin", ucode_prefix);
632 if (err)
633 goto out;
634 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
635 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
636 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
637 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
638 if (err)
639 goto out;
640 }
641
642 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
643 AMDGPU_UCODE_REQUIRED,
644 "amdgpu/%s_mec.bin", ucode_prefix);
645 if (err)
646 goto out;
647 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);
648 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);
649 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);
650
651 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
652 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix);
653
654 /* only one MEC for gfx 12 */
655 adev->gfx.mec2_fw = NULL;
656
657 if (adev->gfx.imu.funcs) {
658 if (adev->gfx.imu.funcs->init_microcode) {
659 err = adev->gfx.imu.funcs->init_microcode(adev);
660 if (err)
661 dev_err(adev->dev, "Failed to load imu firmware!\n");
662 }
663 }
664
665 out:
666 if (err) {
667 amdgpu_ucode_release(&adev->gfx.pfp_fw);
668 amdgpu_ucode_release(&adev->gfx.me_fw);
669 amdgpu_ucode_release(&adev->gfx.rlc_fw);
670 amdgpu_ucode_release(&adev->gfx.mec_fw);
671 }
672
673 return err;
674 }
675
gfx_v12_0_get_csb_size(struct amdgpu_device * adev)676 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev)
677 {
678 u32 count = 0;
679 const struct cs_section_def *sect = NULL;
680 const struct cs_extent_def *ext = NULL;
681
682 count += 1;
683
684 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) {
685 if (sect->id == SECT_CONTEXT) {
686 for (ext = sect->section; ext->extent != NULL; ++ext)
687 count += 2 + ext->reg_count;
688 } else
689 return 0;
690 }
691
692 return count;
693 }
694
gfx_v12_0_get_csb_buffer(struct amdgpu_device * adev,u32 * buffer)695 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)
696 {
697 u32 count = 0, clustercount = 0, i;
698 const struct cs_section_def *sect = NULL;
699 const struct cs_extent_def *ext = NULL;
700
701 if (adev->gfx.rlc.cs_data == NULL)
702 return;
703 if (buffer == NULL)
704 return;
705
706 count += 1;
707
708 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
709 if (sect->id == SECT_CONTEXT) {
710 for (ext = sect->section; ext->extent != NULL; ++ext) {
711 clustercount++;
712 buffer[count++] = ext->reg_count;
713 buffer[count++] = ext->reg_index;
714
715 for (i = 0; i < ext->reg_count; i++)
716 buffer[count++] = cpu_to_le32(ext->extent[i]);
717 }
718 } else
719 return;
720 }
721
722 buffer[0] = clustercount;
723 }
724
gfx_v12_0_rlc_fini(struct amdgpu_device * adev)725 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev)
726 {
727 /* clear state block */
728 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
729 &adev->gfx.rlc.clear_state_gpu_addr,
730 (void **)&adev->gfx.rlc.cs_ptr);
731
732 /* jump table block */
733 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
734 &adev->gfx.rlc.cp_table_gpu_addr,
735 (void **)&adev->gfx.rlc.cp_table_ptr);
736 }
737
gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device * adev)738 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
739 {
740 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
741
742 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
743 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
744 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
745 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
746 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
747 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
748 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
749 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
750 adev->gfx.rlc.rlcg_reg_access_supported = true;
751 }
752
gfx_v12_0_rlc_init(struct amdgpu_device * adev)753 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev)
754 {
755 const struct cs_section_def *cs_data;
756 int r;
757
758 adev->gfx.rlc.cs_data = gfx12_cs_data;
759
760 cs_data = adev->gfx.rlc.cs_data;
761
762 if (cs_data) {
763 /* init clear state block */
764 r = amdgpu_gfx_rlc_init_csb(adev);
765 if (r)
766 return r;
767 }
768
769 /* init spm vmid with 0xf */
770 if (adev->gfx.rlc.funcs->update_spm_vmid)
771 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf);
772
773 return 0;
774 }
775
gfx_v12_0_mec_fini(struct amdgpu_device * adev)776 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev)
777 {
778 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
779 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
780 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL);
781 }
782
gfx_v12_0_me_init(struct amdgpu_device * adev)783 static void gfx_v12_0_me_init(struct amdgpu_device *adev)
784 {
785 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
786
787 amdgpu_gfx_graphics_queue_acquire(adev);
788 }
789
gfx_v12_0_mec_init(struct amdgpu_device * adev)790 static int gfx_v12_0_mec_init(struct amdgpu_device *adev)
791 {
792 int r;
793 u32 *hpd;
794 size_t mec_hpd_size;
795
796 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
797
798 /* take ownership of the relevant compute queues */
799 amdgpu_gfx_compute_queue_acquire(adev);
800 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE;
801
802 if (mec_hpd_size) {
803 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
804 AMDGPU_GEM_DOMAIN_GTT,
805 &adev->gfx.mec.hpd_eop_obj,
806 &adev->gfx.mec.hpd_eop_gpu_addr,
807 (void **)&hpd);
808 if (r) {
809 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
810 gfx_v12_0_mec_fini(adev);
811 return r;
812 }
813
814 memset(hpd, 0, mec_hpd_size);
815
816 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
817 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
818 }
819
820 return 0;
821 }
822
wave_read_ind(struct amdgpu_device * adev,uint32_t wave,uint32_t address)823 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
824 {
825 WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
826 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
827 (address << SQ_IND_INDEX__INDEX__SHIFT));
828 return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
829 }
830
wave_read_regs(struct amdgpu_device * adev,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)831 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
832 uint32_t thread, uint32_t regno,
833 uint32_t num, uint32_t *out)
834 {
835 WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
836 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
837 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
838 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
839 (SQ_IND_INDEX__AUTO_INCR_MASK));
840 while (num--)
841 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
842 }
843
gfx_v12_0_read_wave_data(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)844 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev,
845 uint32_t xcc_id,
846 uint32_t simd, uint32_t wave,
847 uint32_t *dst, int *no_fields)
848 {
849 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE
850 * field when performing a select_se_sh so it should be
851 * zero here */
852 WARN_ON(simd != 0);
853
854 /* type 4 wave data */
855 dst[(*no_fields)++] = 4;
856 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
867 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
868 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
869 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
870 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV);
871 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV);
872 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER);
873 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL);
874 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE);
875 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE);
876 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO);
877 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI);
878 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE);
879 }
880
gfx_v12_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)881 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev,
882 uint32_t xcc_id, uint32_t simd,
883 uint32_t wave, uint32_t start,
884 uint32_t size, uint32_t *dst)
885 {
886 WARN_ON(simd != 0);
887
888 wave_read_regs(
889 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
890 dst);
891 }
892
gfx_v12_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst)893 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev,
894 uint32_t xcc_id, uint32_t simd,
895 uint32_t wave, uint32_t thread,
896 uint32_t start, uint32_t size,
897 uint32_t *dst)
898 {
899 wave_read_regs(
900 adev, wave, thread,
901 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
902 }
903
gfx_v12_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm,u32 xcc_id)904 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev,
905 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
906 {
907 soc24_grbm_select(adev, me, pipe, q, vm);
908 }
909
910 /* all sizes are in bytes */
911 #define MQD_SHADOW_BASE_SIZE 73728
912 #define MQD_SHADOW_BASE_ALIGNMENT 256
913 #define MQD_FWWORKAREA_SIZE 484
914 #define MQD_FWWORKAREA_ALIGNMENT 256
915
gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device * adev,struct amdgpu_gfx_shadow_info * shadow_info)916 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev,
917 struct amdgpu_gfx_shadow_info *shadow_info)
918 {
919 /* for gfx */
920 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;
921 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;
922 shadow_info->csa_size = MQD_FWWORKAREA_SIZE;
923 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;
924 /* for compute */
925 shadow_info->eop_size = GFX12_MEC_HPD_SIZE;
926 shadow_info->eop_alignment = 256;
927 }
928
gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device * adev,struct amdgpu_gfx_shadow_info * shadow_info,bool skip_check)929 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev,
930 struct amdgpu_gfx_shadow_info *shadow_info,
931 bool skip_check)
932 {
933 if (adev->gfx.cp_gfx_shadow || skip_check) {
934 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info);
935 return 0;
936 }
937
938 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));
939 return -EINVAL;
940 }
941
942 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = {
943 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter,
944 .select_se_sh = &gfx_v12_0_select_se_sh,
945 .read_wave_data = &gfx_v12_0_read_wave_data,
946 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs,
947 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs,
948 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q,
949 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk,
950 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info,
951 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask,
952 };
953
gfx_v12_0_gpu_early_init(struct amdgpu_device * adev)954 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev)
955 {
956
957 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
958 case IP_VERSION(12, 0, 0):
959 case IP_VERSION(12, 0, 1):
960 adev->gfx.config.max_hw_contexts = 8;
961 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
962 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
963 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
964 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
965 break;
966 default:
967 BUG();
968 break;
969 }
970
971 return 0;
972 }
973
gfx_v12_0_gfx_ring_init(struct amdgpu_device * adev,int ring_id,int me,int pipe,int queue)974 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
975 int me, int pipe, int queue)
976 {
977 int r;
978 struct amdgpu_ring *ring;
979 unsigned int irq_type;
980
981 ring = &adev->gfx.gfx_ring[ring_id];
982
983 ring->me = me;
984 ring->pipe = pipe;
985 ring->queue = queue;
986
987 ring->ring_obj = NULL;
988 ring->use_doorbell = true;
989
990 if (!ring_id)
991 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
992 else
993 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
994 ring->vm_hub = AMDGPU_GFXHUB(0);
995 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
996
997 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
998 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
999 AMDGPU_RING_PRIO_DEFAULT, NULL);
1000 if (r)
1001 return r;
1002 return 0;
1003 }
1004
gfx_v12_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)1005 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1006 int mec, int pipe, int queue)
1007 {
1008 int r;
1009 unsigned irq_type;
1010 struct amdgpu_ring *ring;
1011 unsigned int hw_prio;
1012
1013 ring = &adev->gfx.compute_ring[ring_id];
1014
1015 /* mec0 is me1 */
1016 ring->me = mec + 1;
1017 ring->pipe = pipe;
1018 ring->queue = queue;
1019
1020 ring->ring_obj = NULL;
1021 ring->use_doorbell = true;
1022 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1023 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1024 + (ring_id * GFX12_MEC_HPD_SIZE);
1025 ring->vm_hub = AMDGPU_GFXHUB(0);
1026 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1027
1028 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1029 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1030 + ring->pipe;
1031 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
1032 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
1033 /* type-2 packets are deprecated on MEC, use type-3 instead */
1034 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1035 hw_prio, NULL);
1036 if (r)
1037 return r;
1038
1039 return 0;
1040 }
1041
1042 static struct {
1043 SOC24_FIRMWARE_ID id;
1044 unsigned int offset;
1045 unsigned int size;
1046 unsigned int size_x16;
1047 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX];
1048
1049 #define RLC_TOC_OFFSET_DWUNIT 8
1050 #define RLC_SIZE_MULTIPLE 1024
1051 #define RLC_TOC_UMF_SIZE_inM 23ULL
1052 #define RLC_TOC_FORMAT_API 165ULL
1053
gfx_v12_0_parse_rlc_toc(struct amdgpu_device * adev,void * rlc_toc)1054 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc)
1055 {
1056 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc;
1057
1058 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) {
1059 rlc_autoload_info[ucode->id].id = ucode->id;
1060 rlc_autoload_info[ucode->id].offset =
1061 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4;
1062 rlc_autoload_info[ucode->id].size =
1063 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 :
1064 ucode->size * 4;
1065 ucode++;
1066 }
1067 }
1068
gfx_v12_0_calc_toc_total_size(struct amdgpu_device * adev)1069 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev)
1070 {
1071 uint32_t total_size = 0;
1072 SOC24_FIRMWARE_ID id;
1073
1074 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr);
1075
1076 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++)
1077 total_size += rlc_autoload_info[id].size;
1078
1079 /* In case the offset in rlc toc ucode is aligned */
1080 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset)
1081 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset +
1082 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size;
1083 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20))
1084 total_size = RLC_TOC_UMF_SIZE_inM << 20;
1085
1086 return total_size;
1087 }
1088
gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device * adev)1089 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev)
1090 {
1091 int r;
1092 uint32_t total_size;
1093
1094 total_size = gfx_v12_0_calc_toc_total_size(adev);
1095
1096 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
1097 AMDGPU_GEM_DOMAIN_VRAM,
1098 &adev->gfx.rlc.rlc_autoload_bo,
1099 &adev->gfx.rlc.rlc_autoload_gpu_addr,
1100 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1101
1102 if (r) {
1103 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1104 return r;
1105 }
1106
1107 return 0;
1108 }
1109
gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device * adev,SOC24_FIRMWARE_ID id,const void * fw_data,uint32_t fw_size)1110 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
1111 SOC24_FIRMWARE_ID id,
1112 const void *fw_data,
1113 uint32_t fw_size)
1114 {
1115 uint32_t toc_offset;
1116 uint32_t toc_fw_size;
1117 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1118
1119 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX)
1120 return;
1121
1122 toc_offset = rlc_autoload_info[id].offset;
1123 toc_fw_size = rlc_autoload_info[id].size;
1124
1125 if (fw_size == 0)
1126 fw_size = toc_fw_size;
1127
1128 if (fw_size > toc_fw_size)
1129 fw_size = toc_fw_size;
1130
1131 memcpy(ptr + toc_offset, fw_data, fw_size);
1132
1133 if (fw_size < toc_fw_size)
1134 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
1135 }
1136
1137 static void
gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device * adev)1138 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
1139 {
1140 void *data;
1141 uint32_t size;
1142 uint32_t *toc_ptr;
1143
1144 data = adev->psp.toc.start_addr;
1145 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size;
1146
1147 toc_ptr = (uint32_t *)data + size / 4 - 2;
1148 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1;
1149
1150 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC,
1151 data, size);
1152 }
1153
1154 static void
gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device * adev)1155 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
1156 {
1157 const __le32 *fw_data;
1158 uint32_t fw_size;
1159 const struct gfx_firmware_header_v2_0 *cpv2_hdr;
1160 const struct rlc_firmware_header_v2_0 *rlc_hdr;
1161 const struct rlc_firmware_header_v2_1 *rlcv21_hdr;
1162 const struct rlc_firmware_header_v2_2 *rlcv22_hdr;
1163 uint16_t version_major, version_minor;
1164
1165 /* pfp ucode */
1166 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1167 adev->gfx.pfp_fw->data;
1168 /* instruction */
1169 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1170 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1171 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1172 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP,
1173 fw_data, fw_size);
1174 /* data */
1175 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1176 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1177 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1178 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK,
1179 fw_data, fw_size);
1180 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK,
1181 fw_data, fw_size);
1182 /* me ucode */
1183 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1184 adev->gfx.me_fw->data;
1185 /* instruction */
1186 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1187 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1188 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1189 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME,
1190 fw_data, fw_size);
1191 /* data */
1192 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1193 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1194 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1195 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK,
1196 fw_data, fw_size);
1197 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK,
1198 fw_data, fw_size);
1199 /* mec ucode */
1200 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1201 adev->gfx.mec_fw->data;
1202 /* instruction */
1203 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1204 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1205 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1206 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC,
1207 fw_data, fw_size);
1208 /* data */
1209 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1210 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1211 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1212 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK,
1213 fw_data, fw_size);
1214 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK,
1215 fw_data, fw_size);
1216 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK,
1217 fw_data, fw_size);
1218 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK,
1219 fw_data, fw_size);
1220
1221 /* rlc ucode */
1222 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
1223 adev->gfx.rlc_fw->data;
1224 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1225 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
1226 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
1227 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE,
1228 fw_data, fw_size);
1229
1230 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1231 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1232 if (version_major == 2) {
1233 if (version_minor >= 1) {
1234 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
1235
1236 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1237 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes));
1238 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes);
1239 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH,
1240 fw_data, fw_size);
1241
1242 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1243 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes));
1244 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes);
1245 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM,
1246 fw_data, fw_size);
1247 }
1248 if (version_minor >= 2) {
1249 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1250
1251 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1252 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes));
1253 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes);
1254 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE,
1255 fw_data, fw_size);
1256
1257 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1258 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes));
1259 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes);
1260 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT,
1261 fw_data, fw_size);
1262 }
1263 }
1264 }
1265
1266 static void
gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device * adev)1267 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
1268 {
1269 const __le32 *fw_data;
1270 uint32_t fw_size;
1271 const struct sdma_firmware_header_v3_0 *sdma_hdr;
1272
1273 sdma_hdr = (const struct sdma_firmware_header_v3_0 *)
1274 adev->sdma.instance[0].fw->data;
1275 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1276 le32_to_cpu(sdma_hdr->ucode_offset_bytes));
1277 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes);
1278
1279 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0,
1280 fw_data, fw_size);
1281 }
1282
1283 static void
gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device * adev)1284 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev)
1285 {
1286 const __le32 *fw_data;
1287 unsigned fw_size;
1288 const struct mes_firmware_header_v1_0 *mes_hdr;
1289 int pipe, ucode_id, data_id;
1290
1291 for (pipe = 0; pipe < 2; pipe++) {
1292 if (pipe == 0) {
1293 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0;
1294 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK;
1295 } else {
1296 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1;
1297 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK;
1298 }
1299
1300 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1301 adev->mes.fw[pipe]->data;
1302
1303 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1304 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1305 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1306
1307 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size);
1308
1309 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1310 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1311 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1312
1313 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size);
1314 }
1315 }
1316
gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device * adev)1317 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
1318 {
1319 uint32_t rlc_g_offset, rlc_g_size;
1320 uint64_t gpu_addr;
1321 uint32_t data;
1322
1323 /* RLC autoload sequence 2: copy ucode */
1324 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
1325 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
1326 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev);
1327 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
1328
1329 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset;
1330 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size;
1331 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start;
1332
1333 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1334 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1335
1336 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1337
1338 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
1339 /* RLC autoload sequence 3: load IMU fw */
1340 if (adev->gfx.imu.funcs->load_microcode)
1341 adev->gfx.imu.funcs->load_microcode(adev);
1342 /* RLC autoload sequence 4 init IMU fw */
1343 if (adev->gfx.imu.funcs->setup_imu)
1344 adev->gfx.imu.funcs->setup_imu(adev);
1345 if (adev->gfx.imu.funcs->start_imu)
1346 adev->gfx.imu.funcs->start_imu(adev);
1347
1348 /* RLC autoload sequence 5 disable gpa mode */
1349 gfx_v12_0_disable_gpa_mode(adev);
1350 } else {
1351 /* unhalt rlc to start autoload without imu */
1352 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
1353 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1);
1354 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
1355 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data);
1356 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
1357 }
1358
1359 return 0;
1360 }
1361
gfx_v12_0_alloc_ip_dump(struct amdgpu_device * adev)1362 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev)
1363 {
1364 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
1365 uint32_t *ptr;
1366 uint32_t inst;
1367
1368 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
1369 if (!ptr) {
1370 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
1371 adev->gfx.ip_dump_core = NULL;
1372 } else {
1373 adev->gfx.ip_dump_core = ptr;
1374 }
1375
1376 /* Allocate memory for compute queue registers for all the instances */
1377 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
1378 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
1379 adev->gfx.mec.num_queue_per_pipe;
1380
1381 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
1382 if (!ptr) {
1383 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
1384 adev->gfx.ip_dump_compute_queues = NULL;
1385 } else {
1386 adev->gfx.ip_dump_compute_queues = ptr;
1387 }
1388
1389 /* Allocate memory for gfx queue registers for all the instances */
1390 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
1391 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
1392 adev->gfx.me.num_queue_per_pipe;
1393
1394 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
1395 if (!ptr) {
1396 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
1397 adev->gfx.ip_dump_gfx_queues = NULL;
1398 } else {
1399 adev->gfx.ip_dump_gfx_queues = ptr;
1400 }
1401 }
1402
gfx_v12_0_sw_init(struct amdgpu_ip_block * ip_block)1403 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
1404 {
1405 int i, j, k, r, ring_id = 0;
1406 unsigned num_compute_rings;
1407 int xcc_id = 0;
1408 struct amdgpu_device *adev = ip_block->adev;
1409 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */
1410
1411 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
1412
1413 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1414 case IP_VERSION(12, 0, 0):
1415 case IP_VERSION(12, 0, 1):
1416 adev->gfx.me.num_me = 1;
1417 adev->gfx.me.num_pipe_per_me = 1;
1418 adev->gfx.me.num_queue_per_pipe = 8;
1419 adev->gfx.mec.num_mec = 1;
1420 adev->gfx.mec.num_pipe_per_mec = 2;
1421 adev->gfx.mec.num_queue_per_pipe = 4;
1422 break;
1423 default:
1424 adev->gfx.me.num_me = 1;
1425 adev->gfx.me.num_pipe_per_me = 1;
1426 adev->gfx.me.num_queue_per_pipe = 1;
1427 adev->gfx.mec.num_mec = 1;
1428 adev->gfx.mec.num_pipe_per_mec = 4;
1429 adev->gfx.mec.num_queue_per_pipe = 8;
1430 break;
1431 }
1432
1433 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1434 case IP_VERSION(12, 0, 0):
1435 case IP_VERSION(12, 0, 1):
1436 if (!adev->gfx.disable_uq &&
1437 adev->gfx.me_fw_version >= 2780 &&
1438 adev->gfx.pfp_fw_version >= 2840 &&
1439 adev->gfx.mec_fw_version >= 3050 &&
1440 adev->mes.fw_version[0] >= 123) {
1441 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
1442 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
1443 }
1444 break;
1445 default:
1446 break;
1447 }
1448
1449 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1450 case IP_VERSION(12, 0, 0):
1451 case IP_VERSION(12, 0, 1):
1452 if (adev->gfx.me_fw_version >= 2480 &&
1453 adev->gfx.pfp_fw_version >= 2530 &&
1454 adev->gfx.mec_fw_version >= 2680 &&
1455 adev->mes.fw_version[0] >= 100)
1456 adev->gfx.enable_cleaner_shader = true;
1457 break;
1458 default:
1459 adev->gfx.enable_cleaner_shader = false;
1460 break;
1461 }
1462
1463 if (adev->gfx.num_compute_rings) {
1464 /* recalculate compute rings to use based on hardware configuration */
1465 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *
1466 adev->gfx.mec.num_queue_per_pipe) / 2;
1467 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,
1468 num_compute_rings);
1469 }
1470
1471 /* EOP Event */
1472 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1473 GFX_12_0_0__SRCID__CP_EOP_INTERRUPT,
1474 &adev->gfx.eop_irq);
1475 if (r)
1476 return r;
1477
1478 /* Bad opcode Event */
1479 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1480 GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR,
1481 &adev->gfx.bad_op_irq);
1482 if (r)
1483 return r;
1484
1485 /* Privileged reg */
1486 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1487 GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT,
1488 &adev->gfx.priv_reg_irq);
1489 if (r)
1490 return r;
1491
1492 /* Privileged inst */
1493 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1494 GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT,
1495 &adev->gfx.priv_inst_irq);
1496 if (r)
1497 return r;
1498
1499 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1500
1501 gfx_v12_0_me_init(adev);
1502
1503 r = gfx_v12_0_rlc_init(adev);
1504 if (r) {
1505 dev_err(adev->dev, "Failed to init rlc BOs!\n");
1506 return r;
1507 }
1508
1509 r = gfx_v12_0_mec_init(adev);
1510 if (r) {
1511 dev_err(adev->dev, "Failed to init MEC BOs!\n");
1512 return r;
1513 }
1514
1515 if (adev->gfx.num_gfx_rings) {
1516 /* set up the gfx ring */
1517 for (i = 0; i < adev->gfx.me.num_me; i++) {
1518 for (j = 0; j < num_queue_per_pipe; j++) {
1519 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1520 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1521 continue;
1522
1523 r = gfx_v12_0_gfx_ring_init(adev, ring_id,
1524 i, k, j);
1525 if (r)
1526 return r;
1527 ring_id++;
1528 }
1529 }
1530 }
1531 }
1532
1533 if (adev->gfx.num_compute_rings) {
1534 ring_id = 0;
1535 /* set up the compute queues - allocate horizontally across pipes */
1536 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1537 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1538 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1539 if (!amdgpu_gfx_is_mec_queue_enabled(adev,
1540 0, i, k, j))
1541 continue;
1542
1543 r = gfx_v12_0_compute_ring_init(adev, ring_id,
1544 i, k, j);
1545 if (r)
1546 return r;
1547
1548 ring_id++;
1549 }
1550 }
1551 }
1552 }
1553
1554 adev->gfx.gfx_supported_reset =
1555 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
1556 adev->gfx.compute_supported_reset =
1557 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
1558 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1559 case IP_VERSION(12, 0, 0):
1560 case IP_VERSION(12, 0, 1):
1561 if ((adev->gfx.me_fw_version >= 2660) &&
1562 (adev->gfx.mec_fw_version >= 2920) &&
1563 !amdgpu_sriov_vf(adev) &&
1564 !adev->debug_disable_gpu_ring_reset) {
1565 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1566 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1567 }
1568 break;
1569 default:
1570 break;
1571 }
1572
1573 if (!adev->enable_mes_kiq) {
1574 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0);
1575 if (r) {
1576 dev_err(adev->dev, "Failed to init KIQ BOs!\n");
1577 return r;
1578 }
1579
1580 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
1581 if (r)
1582 return r;
1583 }
1584
1585 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0);
1586 if (r)
1587 return r;
1588
1589 /* allocate visible FB for rlc auto-loading fw */
1590 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1591 r = gfx_v12_0_rlc_autoload_buffer_init(adev);
1592 if (r)
1593 return r;
1594 }
1595
1596 r = gfx_v12_0_gpu_early_init(adev);
1597 if (r)
1598 return r;
1599
1600 gfx_v12_0_alloc_ip_dump(adev);
1601
1602 r = amdgpu_gfx_sysfs_init(adev);
1603 if (r)
1604 return r;
1605
1606 return 0;
1607 }
1608
gfx_v12_0_pfp_fini(struct amdgpu_device * adev)1609 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev)
1610 {
1611 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1612 &adev->gfx.pfp.pfp_fw_gpu_addr,
1613 (void **)&adev->gfx.pfp.pfp_fw_ptr);
1614
1615 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj,
1616 &adev->gfx.pfp.pfp_fw_data_gpu_addr,
1617 (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
1618 }
1619
gfx_v12_0_me_fini(struct amdgpu_device * adev)1620 static void gfx_v12_0_me_fini(struct amdgpu_device *adev)
1621 {
1622 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1623 &adev->gfx.me.me_fw_gpu_addr,
1624 (void **)&adev->gfx.me.me_fw_ptr);
1625
1626 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj,
1627 &adev->gfx.me.me_fw_data_gpu_addr,
1628 (void **)&adev->gfx.me.me_fw_data_ptr);
1629 }
1630
gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device * adev)1631 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)
1632 {
1633 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1634 &adev->gfx.rlc.rlc_autoload_gpu_addr,
1635 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1636 }
1637
gfx_v12_0_sw_fini(struct amdgpu_ip_block * ip_block)1638 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block)
1639 {
1640 int i;
1641 struct amdgpu_device *adev = ip_block->adev;
1642
1643 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1644 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1645 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1646 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1647
1648 amdgpu_gfx_mqd_sw_fini(adev, 0);
1649
1650 if (!adev->enable_mes_kiq) {
1651 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
1652 amdgpu_gfx_kiq_fini(adev, 0);
1653 }
1654
1655 gfx_v12_0_pfp_fini(adev);
1656 gfx_v12_0_me_fini(adev);
1657 gfx_v12_0_rlc_fini(adev);
1658 gfx_v12_0_mec_fini(adev);
1659
1660 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1661 gfx_v12_0_rlc_autoload_buffer_fini(adev);
1662
1663 gfx_v12_0_free_microcode(adev);
1664
1665 amdgpu_gfx_sysfs_fini(adev);
1666
1667 kfree(adev->gfx.ip_dump_core);
1668 kfree(adev->gfx.ip_dump_compute_queues);
1669 kfree(adev->gfx.ip_dump_gfx_queues);
1670
1671 return 0;
1672 }
1673
gfx_v12_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id)1674 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1675 u32 sh_num, u32 instance, int xcc_id)
1676 {
1677 u32 data;
1678
1679 if (instance == 0xffffffff)
1680 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1681 INSTANCE_BROADCAST_WRITES, 1);
1682 else
1683 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1684 instance);
1685
1686 if (se_num == 0xffffffff)
1687 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1688 1);
1689 else
1690 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1691
1692 if (sh_num == 0xffffffff)
1693 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1694 1);
1695 else
1696 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1697
1698 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
1699 }
1700
gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device * adev)1701 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev)
1702 {
1703 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask;
1704
1705 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE);
1706 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask,
1707 GRBM_CC_GC_SA_UNIT_DISABLE,
1708 SA_DISABLE);
1709 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE);
1710 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask,
1711 GRBM_GC_USER_SA_UNIT_DISABLE,
1712 SA_DISABLE);
1713 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
1714 adev->gfx.config.max_shader_engines);
1715
1716 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask));
1717 }
1718
gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device * adev)1719 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1720 {
1721 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask;
1722 u32 rb_mask;
1723
1724 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
1725 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask,
1726 CC_RB_BACKEND_DISABLE,
1727 BACKEND_DISABLE);
1728 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
1729 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask,
1730 GC_USER_RB_BACKEND_DISABLE,
1731 BACKEND_DISABLE);
1732 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se *
1733 adev->gfx.config.max_shader_engines);
1734
1735 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask));
1736 }
1737
gfx_v12_0_setup_rb(struct amdgpu_device * adev)1738 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev)
1739 {
1740 u32 rb_bitmap_per_sa;
1741 u32 rb_bitmap_width_per_sa;
1742 u32 max_sa;
1743 u32 active_sa_bitmap;
1744 u32 global_active_rb_bitmap;
1745 u32 active_rb_bitmap = 0;
1746 u32 i;
1747
1748 /* query sa bitmap from SA_UNIT_DISABLE registers */
1749 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev);
1750 /* query rb bitmap from RB_BACKEND_DISABLE registers */
1751 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev);
1752
1753 /* generate active rb bitmap according to active sa bitmap */
1754 max_sa = adev->gfx.config.max_shader_engines *
1755 adev->gfx.config.max_sh_per_se;
1756 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se /
1757 adev->gfx.config.max_sh_per_se;
1758 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa);
1759
1760 for (i = 0; i < max_sa; i++) {
1761 if (active_sa_bitmap & (1 << i))
1762 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa));
1763 }
1764
1765 active_rb_bitmap &= global_active_rb_bitmap;
1766 adev->gfx.config.backend_enable_mask = active_rb_bitmap;
1767 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);
1768 }
1769
1770 #define LDS_APP_BASE 0x1
1771 #define SCRATCH_APP_BASE 0x2
1772
gfx_v12_0_init_compute_vmid(struct amdgpu_device * adev)1773 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev)
1774 {
1775 int i;
1776 uint32_t sh_mem_bases;
1777 uint32_t data;
1778
1779 /*
1780 * Configure apertures:
1781 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1782 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1783 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1784 */
1785 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) |
1786 SCRATCH_APP_BASE;
1787
1788 mutex_lock(&adev->srbm_mutex);
1789 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1790 soc24_grbm_select(adev, 0, 0, 0, i);
1791 /* CP and shaders */
1792 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1793 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
1794
1795 /* Enable trap for each kfd vmid. */
1796 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
1797 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1798 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data);
1799 }
1800 soc24_grbm_select(adev, 0, 0, 0, 0);
1801 mutex_unlock(&adev->srbm_mutex);
1802 }
1803
gfx_v12_0_tcp_harvest(struct amdgpu_device * adev)1804 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev)
1805 {
1806 /* TODO: harvest feature to be added later. */
1807 }
1808
gfx_v12_0_get_tcc_info(struct amdgpu_device * adev)1809 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev)
1810 {
1811 }
1812
gfx_v12_0_constants_init(struct amdgpu_device * adev)1813 static void gfx_v12_0_constants_init(struct amdgpu_device *adev)
1814 {
1815 u32 tmp;
1816 int i;
1817
1818 if (!amdgpu_sriov_vf(adev))
1819 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1820
1821 gfx_v12_0_setup_rb(adev);
1822 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info);
1823 gfx_v12_0_get_tcc_info(adev);
1824 adev->gfx.config.pa_sc_tile_steering_override = 0;
1825
1826 /* XXX SH_MEM regs */
1827 /* where to put LDS, scratch, GPUVM in FSA64 space */
1828 mutex_lock(&adev->srbm_mutex);
1829 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
1830 soc24_grbm_select(adev, 0, 0, 0, i);
1831 /* CP and shaders */
1832 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1833 if (i != 0) {
1834 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1835 (adev->gmc.private_aperture_start >> 48));
1836 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1837 (adev->gmc.shared_aperture_start >> 48));
1838 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
1839 }
1840 }
1841 soc24_grbm_select(adev, 0, 0, 0, 0);
1842
1843 mutex_unlock(&adev->srbm_mutex);
1844
1845 gfx_v12_0_init_compute_vmid(adev);
1846 }
1847
gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device * adev,int me,int pipe)1848 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev,
1849 int me, int pipe)
1850 {
1851 if (me != 0)
1852 return 0;
1853
1854 switch (pipe) {
1855 case 0:
1856 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
1857 default:
1858 return 0;
1859 }
1860 }
1861
gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device * adev,int me,int pipe)1862 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev,
1863 int me, int pipe)
1864 {
1865 /*
1866 * amdgpu controls only the first MEC. That's why this function only
1867 * handles the setting of interrupts for this specific MEC. All other
1868 * pipes' interrupts are set by amdkfd.
1869 */
1870 if (me != 1)
1871 return 0;
1872
1873 switch (pipe) {
1874 case 0:
1875 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
1876 case 1:
1877 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
1878 default:
1879 return 0;
1880 }
1881 }
1882
gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)1883 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1884 bool enable)
1885 {
1886 u32 tmp, cp_int_cntl_reg;
1887 int i, j;
1888
1889 if (amdgpu_sriov_vf(adev))
1890 return;
1891
1892 for (i = 0; i < adev->gfx.me.num_me; i++) {
1893 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
1894 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
1895
1896 if (cp_int_cntl_reg) {
1897 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
1898 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1899 enable ? 1 : 0);
1900 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1901 enable ? 1 : 0);
1902 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1903 enable ? 1 : 0);
1904 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1905 enable ? 1 : 0);
1906 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
1907 }
1908 }
1909 }
1910 }
1911
gfx_v12_0_init_csb(struct amdgpu_device * adev)1912 static int gfx_v12_0_init_csb(struct amdgpu_device *adev)
1913 {
1914 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1915
1916 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,
1917 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1918 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,
1919 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1920 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1921
1922 return 0;
1923 }
1924
gfx_v12_0_rlc_stop(struct amdgpu_device * adev)1925 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev)
1926 {
1927 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
1928
1929 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1930 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
1931 }
1932
gfx_v12_0_rlc_reset(struct amdgpu_device * adev)1933 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev)
1934 {
1935 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1936 udelay(50);
1937 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1938 udelay(50);
1939 }
1940
gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device * adev,bool enable)1941 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1942 bool enable)
1943 {
1944 uint32_t rlc_pg_cntl;
1945
1946 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
1947
1948 if (!enable) {
1949 /* RLC_PG_CNTL[23] = 0 (default)
1950 * RLC will wait for handshake acks with SMU
1951 * GFXOFF will be enabled
1952 * RLC_PG_CNTL[23] = 1
1953 * RLC will not issue any message to SMU
1954 * hence no handshake between SMU & RLC
1955 * GFXOFF will be disabled
1956 */
1957 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1958 } else
1959 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1960 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);
1961 }
1962
gfx_v12_0_rlc_start(struct amdgpu_device * adev)1963 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev)
1964 {
1965 /* TODO: enable rlc & smu handshake until smu
1966 * and gfxoff feature works as expected */
1967 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1968 gfx_v12_0_rlc_smu_handshake_cntl(adev, false);
1969
1970 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1971 udelay(50);
1972 }
1973
gfx_v12_0_rlc_enable_srm(struct amdgpu_device * adev)1974 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev)
1975 {
1976 uint32_t tmp;
1977
1978 /* enable Save Restore Machine */
1979 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
1980 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1981 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1982 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
1983 }
1984
gfx_v12_0_load_rlcg_microcode(struct amdgpu_device * adev)1985 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev)
1986 {
1987 const struct rlc_firmware_header_v2_0 *hdr;
1988 const __le32 *fw_data;
1989 unsigned i, fw_size;
1990
1991 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1992 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1993 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1994 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1995
1996 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,
1997 RLCG_UCODE_LOADING_START_ADDRESS);
1998
1999 for (i = 0; i < fw_size; i++)
2000 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,
2001 le32_to_cpup(fw_data++));
2002
2003 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2004 }
2005
gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device * adev)2006 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev)
2007 {
2008 const struct rlc_firmware_header_v2_2 *hdr;
2009 const __le32 *fw_data;
2010 unsigned i, fw_size;
2011 u32 tmp;
2012
2013 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
2014
2015 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2016 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes));
2017 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4;
2018
2019 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);
2020
2021 for (i = 0; i < fw_size; i++) {
2022 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
2023 msleep(1);
2024 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,
2025 le32_to_cpup(fw_data++));
2026 }
2027
2028 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
2029
2030 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2031 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes));
2032 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4;
2033
2034 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);
2035 for (i = 0; i < fw_size; i++) {
2036 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
2037 msleep(1);
2038 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,
2039 le32_to_cpup(fw_data++));
2040 }
2041
2042 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
2043
2044 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
2045 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
2046 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
2047 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
2048 }
2049
gfx_v12_0_rlc_load_microcode(struct amdgpu_device * adev)2050 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev)
2051 {
2052 const struct rlc_firmware_header_v2_0 *hdr;
2053 uint16_t version_major;
2054 uint16_t version_minor;
2055
2056 if (!adev->gfx.rlc_fw)
2057 return -EINVAL;
2058
2059 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2060 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2061
2062 version_major = le16_to_cpu(hdr->header.header_version_major);
2063 version_minor = le16_to_cpu(hdr->header.header_version_minor);
2064
2065 if (version_major == 2) {
2066 gfx_v12_0_load_rlcg_microcode(adev);
2067 if (amdgpu_dpm == 1) {
2068 if (version_minor >= 2)
2069 gfx_v12_0_load_rlc_iram_dram_microcode(adev);
2070 }
2071
2072 return 0;
2073 }
2074
2075 return -EINVAL;
2076 }
2077
gfx_v12_0_rlc_resume(struct amdgpu_device * adev)2078 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev)
2079 {
2080 int r;
2081
2082 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2083 gfx_v12_0_init_csb(adev);
2084
2085 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
2086 gfx_v12_0_rlc_enable_srm(adev);
2087 } else {
2088 if (amdgpu_sriov_vf(adev)) {
2089 gfx_v12_0_init_csb(adev);
2090 return 0;
2091 }
2092
2093 adev->gfx.rlc.funcs->stop(adev);
2094
2095 /* disable CG */
2096 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
2097
2098 /* disable PG */
2099 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);
2100
2101 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
2102 /* legacy rlc firmware loading */
2103 r = gfx_v12_0_rlc_load_microcode(adev);
2104 if (r)
2105 return r;
2106 }
2107
2108 gfx_v12_0_init_csb(adev);
2109
2110 adev->gfx.rlc.funcs->start(adev);
2111 }
2112
2113 return 0;
2114 }
2115
gfx_v12_0_config_gfx_rs64(struct amdgpu_device * adev)2116 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev)
2117 {
2118 const struct gfx_firmware_header_v2_0 *pfp_hdr;
2119 const struct gfx_firmware_header_v2_0 *me_hdr;
2120 const struct gfx_firmware_header_v2_0 *mec_hdr;
2121 uint32_t pipe_id, tmp;
2122
2123 mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2124 adev->gfx.mec_fw->data;
2125 me_hdr = (const struct gfx_firmware_header_v2_0 *)
2126 adev->gfx.me_fw->data;
2127 pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2128 adev->gfx.pfp_fw->data;
2129
2130 /* config pfp program start addr */
2131 for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2132 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2133 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2134 (pfp_hdr->ucode_start_addr_hi << 30) |
2135 (pfp_hdr->ucode_start_addr_lo >> 2));
2136 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2137 pfp_hdr->ucode_start_addr_hi >> 2);
2138 }
2139 soc24_grbm_select(adev, 0, 0, 0, 0);
2140
2141 /* reset pfp pipe */
2142 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2143 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
2144 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
2145 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2146
2147 /* clear pfp pipe reset */
2148 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
2149 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
2150 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2151
2152 /* config me program start addr */
2153 for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2154 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2155 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2156 (me_hdr->ucode_start_addr_hi << 30) |
2157 (me_hdr->ucode_start_addr_lo >> 2));
2158 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2159 me_hdr->ucode_start_addr_hi>>2);
2160 }
2161 soc24_grbm_select(adev, 0, 0, 0, 0);
2162
2163 /* reset me pipe */
2164 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2165 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
2166 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
2167 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2168
2169 /* clear me pipe reset */
2170 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
2171 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
2172 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2173
2174 /* config mec program start addr */
2175 for (pipe_id = 0; pipe_id < 4; pipe_id++) {
2176 soc24_grbm_select(adev, 1, pipe_id, 0, 0);
2177 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2178 mec_hdr->ucode_start_addr_lo >> 2 |
2179 mec_hdr->ucode_start_addr_hi << 30);
2180 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2181 mec_hdr->ucode_start_addr_hi >> 2);
2182 }
2183 soc24_grbm_select(adev, 0, 0, 0, 0);
2184
2185 /* reset mec pipe */
2186 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2187 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
2188 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
2189 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
2190 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
2191 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2192
2193 /* clear mec pipe reset */
2194 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
2195 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
2196 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
2197 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
2198 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2199 }
2200
gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device * adev)2201 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev)
2202 {
2203 const struct gfx_firmware_header_v2_0 *cp_hdr;
2204 unsigned pipe_id, tmp;
2205
2206 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2207 adev->gfx.pfp_fw->data;
2208 mutex_lock(&adev->srbm_mutex);
2209 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2210 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2211 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2212 (cp_hdr->ucode_start_addr_hi << 30) |
2213 (cp_hdr->ucode_start_addr_lo >> 2));
2214 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2215 cp_hdr->ucode_start_addr_hi>>2);
2216
2217 /*
2218 * Program CP_ME_CNTL to reset given PIPE to take
2219 * effect of CP_PFP_PRGRM_CNTR_START.
2220 */
2221 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2222 if (pipe_id == 0)
2223 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2224 PFP_PIPE0_RESET, 1);
2225 else
2226 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2227 PFP_PIPE1_RESET, 1);
2228 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2229
2230 /* Clear pfp pipe0 reset bit. */
2231 if (pipe_id == 0)
2232 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2233 PFP_PIPE0_RESET, 0);
2234 else
2235 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2236 PFP_PIPE1_RESET, 0);
2237 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2238 }
2239 soc24_grbm_select(adev, 0, 0, 0, 0);
2240 mutex_unlock(&adev->srbm_mutex);
2241 }
2242
gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device * adev)2243 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev)
2244 {
2245 const struct gfx_firmware_header_v2_0 *cp_hdr;
2246 unsigned pipe_id, tmp;
2247
2248 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2249 adev->gfx.me_fw->data;
2250 mutex_lock(&adev->srbm_mutex);
2251 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2252 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2253 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2254 (cp_hdr->ucode_start_addr_hi << 30) |
2255 (cp_hdr->ucode_start_addr_lo >> 2) );
2256 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2257 cp_hdr->ucode_start_addr_hi>>2);
2258
2259 /*
2260 * Program CP_ME_CNTL to reset given PIPE to take
2261 * effect of CP_ME_PRGRM_CNTR_START.
2262 */
2263 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2264 if (pipe_id == 0)
2265 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2266 ME_PIPE0_RESET, 1);
2267 else
2268 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2269 ME_PIPE1_RESET, 1);
2270 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2271
2272 /* Clear pfp pipe0 reset bit. */
2273 if (pipe_id == 0)
2274 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2275 ME_PIPE0_RESET, 0);
2276 else
2277 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2278 ME_PIPE1_RESET, 0);
2279 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2280 }
2281 soc24_grbm_select(adev, 0, 0, 0, 0);
2282 mutex_unlock(&adev->srbm_mutex);
2283 }
2284
gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device * adev)2285 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev)
2286 {
2287 const struct gfx_firmware_header_v2_0 *cp_hdr;
2288 unsigned pipe_id;
2289
2290 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2291 adev->gfx.mec_fw->data;
2292 mutex_lock(&adev->srbm_mutex);
2293 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) {
2294 soc24_grbm_select(adev, 1, pipe_id, 0, 0);
2295 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2296 cp_hdr->ucode_start_addr_lo >> 2 |
2297 cp_hdr->ucode_start_addr_hi << 30);
2298 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2299 cp_hdr->ucode_start_addr_hi >> 2);
2300 }
2301 soc24_grbm_select(adev, 0, 0, 0, 0);
2302 mutex_unlock(&adev->srbm_mutex);
2303 }
2304
gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device * adev)2305 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2306 {
2307 uint32_t cp_status;
2308 uint32_t bootload_status;
2309 int i;
2310
2311 for (i = 0; i < adev->usec_timeout; i++) {
2312 cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
2313 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
2314
2315 if ((cp_status == 0) &&
2316 (REG_GET_FIELD(bootload_status,
2317 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2318 break;
2319 }
2320 udelay(1);
2321 if (amdgpu_emu_mode)
2322 msleep(10);
2323 }
2324
2325 if (i >= adev->usec_timeout) {
2326 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2327 return -ETIMEDOUT;
2328 }
2329
2330 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2331 gfx_v12_0_set_pfp_ucode_start_addr(adev);
2332 gfx_v12_0_set_me_ucode_start_addr(adev);
2333 gfx_v12_0_set_mec_ucode_start_addr(adev);
2334 }
2335
2336 return 0;
2337 }
2338
gfx_v12_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)2339 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2340 {
2341 int i;
2342 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2343
2344 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2345 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2346 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2347
2348 for (i = 0; i < adev->usec_timeout; i++) {
2349 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)
2350 break;
2351 udelay(1);
2352 }
2353
2354 if (i >= adev->usec_timeout)
2355 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2356
2357 return 0;
2358 }
2359
gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device * adev)2360 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
2361 {
2362 int r;
2363 const struct gfx_firmware_header_v2_0 *pfp_hdr;
2364 const __le32 *fw_ucode, *fw_data;
2365 unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2366 uint32_t tmp;
2367 uint32_t usec_timeout = 50000; /* wait for 50ms */
2368
2369 pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2370 adev->gfx.pfp_fw->data;
2371
2372 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2373
2374 /* instruction */
2375 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data +
2376 le32_to_cpu(pfp_hdr->ucode_offset_bytes));
2377 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes);
2378 /* data */
2379 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2380 le32_to_cpu(pfp_hdr->data_offset_bytes));
2381 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes);
2382
2383 /* 64kb align */
2384 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2385 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2386 &adev->gfx.pfp.pfp_fw_obj,
2387 &adev->gfx.pfp.pfp_fw_gpu_addr,
2388 (void **)&adev->gfx.pfp.pfp_fw_ptr);
2389 if (r) {
2390 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r);
2391 gfx_v12_0_pfp_fini(adev);
2392 return r;
2393 }
2394
2395 r = amdgpu_bo_create_reserved(adev, fw_data_size,
2396 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2397 &adev->gfx.pfp.pfp_fw_data_obj,
2398 &adev->gfx.pfp.pfp_fw_data_gpu_addr,
2399 (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
2400 if (r) {
2401 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r);
2402 gfx_v12_0_pfp_fini(adev);
2403 return r;
2404 }
2405
2406 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);
2407 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);
2408
2409 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2410 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj);
2411 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2412 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
2413
2414 if (amdgpu_emu_mode == 1)
2415 amdgpu_device_flush_hdp(adev, NULL);
2416
2417 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2418 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2419 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2420 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2421
2422 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2423 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2424 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2425 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2426 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2427
2428 /*
2429 * Programming any of the CP_PFP_IC_BASE registers
2430 * forces invalidation of the ME L1 I$. Wait for the
2431 * invalidation complete
2432 */
2433 for (i = 0; i < usec_timeout; i++) {
2434 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2435 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2436 INVALIDATE_CACHE_COMPLETE))
2437 break;
2438 udelay(1);
2439 }
2440
2441 if (i >= usec_timeout) {
2442 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2443 return -EINVAL;
2444 }
2445
2446 /* Prime the L1 instruction caches */
2447 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2448 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2449 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2450 /* Waiting for cache primed*/
2451 for (i = 0; i < usec_timeout; i++) {
2452 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2453 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2454 ICACHE_PRIMED))
2455 break;
2456 udelay(1);
2457 }
2458
2459 if (i >= usec_timeout) {
2460 dev_err(adev->dev, "failed to prime instruction cache\n");
2461 return -EINVAL;
2462 }
2463
2464 mutex_lock(&adev->srbm_mutex);
2465 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2466 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2467
2468 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2469 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2470 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2471 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2472 }
2473 soc24_grbm_select(adev, 0, 0, 0, 0);
2474 mutex_unlock(&adev->srbm_mutex);
2475
2476 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2477 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2478 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2479 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2480
2481 /* Invalidate the data caches */
2482 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2483 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2484 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2485
2486 for (i = 0; i < usec_timeout; i++) {
2487 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2488 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2489 INVALIDATE_DCACHE_COMPLETE))
2490 break;
2491 udelay(1);
2492 }
2493
2494 if (i >= usec_timeout) {
2495 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2496 return -EINVAL;
2497 }
2498
2499 gfx_v12_0_set_pfp_ucode_start_addr(adev);
2500
2501 return 0;
2502 }
2503
gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device * adev)2504 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
2505 {
2506 int r;
2507 const struct gfx_firmware_header_v2_0 *me_hdr;
2508 const __le32 *fw_ucode, *fw_data;
2509 unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2510 uint32_t tmp;
2511 uint32_t usec_timeout = 50000; /* wait for 50ms */
2512
2513 me_hdr = (const struct gfx_firmware_header_v2_0 *)
2514 adev->gfx.me_fw->data;
2515
2516 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2517
2518 /* instruction */
2519 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data +
2520 le32_to_cpu(me_hdr->ucode_offset_bytes));
2521 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes);
2522 /* data */
2523 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2524 le32_to_cpu(me_hdr->data_offset_bytes));
2525 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes);
2526
2527 /* 64kb align*/
2528 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2529 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2530 &adev->gfx.me.me_fw_obj,
2531 &adev->gfx.me.me_fw_gpu_addr,
2532 (void **)&adev->gfx.me.me_fw_ptr);
2533 if (r) {
2534 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r);
2535 gfx_v12_0_me_fini(adev);
2536 return r;
2537 }
2538
2539 r = amdgpu_bo_create_reserved(adev, fw_data_size,
2540 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2541 &adev->gfx.me.me_fw_data_obj,
2542 &adev->gfx.me.me_fw_data_gpu_addr,
2543 (void **)&adev->gfx.me.me_fw_data_ptr);
2544 if (r) {
2545 dev_err(adev->dev, "(%d) failed to create me data bo\n", r);
2546 gfx_v12_0_me_fini(adev);
2547 return r;
2548 }
2549
2550 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);
2551 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size);
2552
2553 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2554 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj);
2555 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2556 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
2557
2558 if (amdgpu_emu_mode == 1)
2559 amdgpu_device_flush_hdp(adev, NULL);
2560
2561 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2562 lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
2563 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2564 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2565
2566 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2567 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2568 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2569 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2570 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2571
2572 /*
2573 * Programming any of the CP_ME_IC_BASE registers
2574 * forces invalidation of the ME L1 I$. Wait for the
2575 * invalidation complete
2576 */
2577 for (i = 0; i < usec_timeout; i++) {
2578 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2579 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2580 INVALIDATE_CACHE_COMPLETE))
2581 break;
2582 udelay(1);
2583 }
2584
2585 if (i >= usec_timeout) {
2586 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2587 return -EINVAL;
2588 }
2589
2590 /* Prime the instruction caches */
2591 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2592 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2593 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2594
2595 /* Waiting for instruction cache primed*/
2596 for (i = 0; i < usec_timeout; i++) {
2597 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2598 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2599 ICACHE_PRIMED))
2600 break;
2601 udelay(1);
2602 }
2603
2604 if (i >= usec_timeout) {
2605 dev_err(adev->dev, "failed to prime instruction cache\n");
2606 return -EINVAL;
2607 }
2608
2609 mutex_lock(&adev->srbm_mutex);
2610 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2611 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2612
2613 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2614 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2615 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2616 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2617 }
2618 soc24_grbm_select(adev, 0, 0, 0, 0);
2619 mutex_unlock(&adev->srbm_mutex);
2620
2621 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2622 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2623 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2624 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2625
2626 /* Invalidate the data caches */
2627 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2628 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2629 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2630
2631 for (i = 0; i < usec_timeout; i++) {
2632 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2633 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2634 INVALIDATE_DCACHE_COMPLETE))
2635 break;
2636 udelay(1);
2637 }
2638
2639 if (i >= usec_timeout) {
2640 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2641 return -EINVAL;
2642 }
2643
2644 gfx_v12_0_set_me_ucode_start_addr(adev);
2645
2646 return 0;
2647 }
2648
gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device * adev)2649 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2650 {
2651 int r;
2652
2653 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw)
2654 return -EINVAL;
2655
2656 gfx_v12_0_cp_gfx_enable(adev, false);
2657
2658 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev);
2659 if (r) {
2660 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2661 return r;
2662 }
2663
2664 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev);
2665 if (r) {
2666 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2667 return r;
2668 }
2669
2670 return 0;
2671 }
2672
gfx_v12_0_cp_gfx_start(struct amdgpu_device * adev)2673 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev)
2674 {
2675 /* init the CP */
2676 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,
2677 adev->gfx.config.max_hw_contexts - 1);
2678 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);
2679
2680 if (!amdgpu_async_gfx_ring)
2681 gfx_v12_0_cp_gfx_enable(adev, true);
2682
2683 return 0;
2684 }
2685
gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device * adev,CP_PIPE_ID pipe)2686 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2687 CP_PIPE_ID pipe)
2688 {
2689 u32 tmp;
2690
2691 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
2692 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2693
2694 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
2695 }
2696
gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device * adev,struct amdgpu_ring * ring)2697 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2698 struct amdgpu_ring *ring)
2699 {
2700 u32 tmp;
2701
2702 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
2703 if (ring->use_doorbell) {
2704 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2705 DOORBELL_OFFSET, ring->doorbell_index);
2706 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2707 DOORBELL_EN, 1);
2708 } else {
2709 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2710 DOORBELL_EN, 0);
2711 }
2712 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
2713
2714 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2715 DOORBELL_RANGE_LOWER, ring->doorbell_index);
2716 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
2717
2718 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
2719 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2720 }
2721
gfx_v12_0_cp_gfx_resume(struct amdgpu_device * adev)2722 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev)
2723 {
2724 struct amdgpu_ring *ring;
2725 u32 tmp;
2726 u32 rb_bufsz;
2727 u64 rb_addr, rptr_addr, wptr_gpu_addr;
2728
2729 /* Set the write pointer delay */
2730 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
2731
2732 /* set the RB to use vmid 0 */
2733 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);
2734
2735 /* Init gfx ring 0 for pipe 0 */
2736 mutex_lock(&adev->srbm_mutex);
2737 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2738
2739 /* Set ring buffer size */
2740 ring = &adev->gfx.gfx_ring[0];
2741 rb_bufsz = order_base_2(ring->ring_size / 8);
2742 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2743 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2744 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
2745
2746 /* Initialize the ring buffer's write pointers */
2747 ring->wptr = 0;
2748 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
2749 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2750
2751 /* set the wb address whether it's enabled or not */
2752 rptr_addr = ring->rptr_gpu_addr;
2753 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2754 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2755 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2756
2757 wptr_gpu_addr = ring->wptr_gpu_addr;
2758 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
2759 lower_32_bits(wptr_gpu_addr));
2760 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
2761 upper_32_bits(wptr_gpu_addr));
2762
2763 mdelay(1);
2764 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
2765
2766 rb_addr = ring->gpu_addr >> 8;
2767 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);
2768 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2769
2770 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);
2771
2772 gfx_v12_0_cp_gfx_set_doorbell(adev, ring);
2773 mutex_unlock(&adev->srbm_mutex);
2774
2775 /* Switch to pipe 0 */
2776 mutex_lock(&adev->srbm_mutex);
2777 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2778 mutex_unlock(&adev->srbm_mutex);
2779
2780 /* start the ring */
2781 gfx_v12_0_cp_gfx_start(adev);
2782 return 0;
2783 }
2784
gfx_v12_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)2785 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2786 {
2787 u32 data;
2788
2789 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2790 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,
2791 enable ? 0 : 1);
2792 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,
2793 enable ? 0 : 1);
2794 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,
2795 enable ? 0 : 1);
2796 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,
2797 enable ? 0 : 1);
2798 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,
2799 enable ? 0 : 1);
2800 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,
2801 enable ? 1 : 0);
2802 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,
2803 enable ? 1 : 0);
2804 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,
2805 enable ? 1 : 0);
2806 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,
2807 enable ? 1 : 0);
2808 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,
2809 enable ? 0 : 1);
2810 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);
2811
2812 adev->gfx.kiq[0].ring.sched.ready = enable;
2813
2814 udelay(50);
2815 }
2816
gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device * adev)2817 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev)
2818 {
2819 const struct gfx_firmware_header_v2_0 *mec_hdr;
2820 const __le32 *fw_ucode, *fw_data;
2821 u32 tmp, fw_ucode_size, fw_data_size;
2822 u32 i, usec_timeout = 50000; /* Wait for 50 ms */
2823 u32 *fw_ucode_ptr, *fw_data_ptr;
2824 int r;
2825
2826 if (!adev->gfx.mec_fw)
2827 return -EINVAL;
2828
2829 gfx_v12_0_cp_compute_enable(adev, false);
2830
2831 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
2832 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2833
2834 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data +
2835 le32_to_cpu(mec_hdr->ucode_offset_bytes));
2836 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes);
2837
2838 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2839 le32_to_cpu(mec_hdr->data_offset_bytes));
2840 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
2841
2842 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2843 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2844 &adev->gfx.mec.mec_fw_obj,
2845 &adev->gfx.mec.mec_fw_gpu_addr,
2846 (void **)&fw_ucode_ptr);
2847 if (r) {
2848 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
2849 gfx_v12_0_mec_fini(adev);
2850 return r;
2851 }
2852
2853 r = amdgpu_bo_create_reserved(adev,
2854 ALIGN(fw_data_size, 64 * 1024) *
2855 adev->gfx.mec.num_pipe_per_mec,
2856 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2857 &adev->gfx.mec.mec_fw_data_obj,
2858 &adev->gfx.mec.mec_fw_data_gpu_addr,
2859 (void **)&fw_data_ptr);
2860 if (r) {
2861 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
2862 gfx_v12_0_mec_fini(adev);
2863 return r;
2864 }
2865
2866 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);
2867 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2868 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size);
2869 }
2870
2871 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
2872 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj);
2873 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
2874 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
2875
2876 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2877 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2878 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2879 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2880 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2881
2882 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
2883 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
2884 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
2885 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
2886
2887 mutex_lock(&adev->srbm_mutex);
2888 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2889 soc24_grbm_select(adev, 1, i, 0, 0);
2890
2891 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO,
2892 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr +
2893 i * ALIGN(fw_data_size, 64 * 1024)));
2894 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
2895 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr +
2896 i * ALIGN(fw_data_size, 64 * 1024)));
2897
2898 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
2899 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2900 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2901 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2902 }
2903 mutex_unlock(&adev->srbm_mutex);
2904 soc24_grbm_select(adev, 0, 0, 0, 0);
2905
2906 /* Trigger an invalidation of the L1 instruction caches */
2907 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2908 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2909 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
2910
2911 /* Wait for invalidation complete */
2912 for (i = 0; i < usec_timeout; i++) {
2913 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2914 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
2915 INVALIDATE_DCACHE_COMPLETE))
2916 break;
2917 udelay(1);
2918 }
2919
2920 if (i >= usec_timeout) {
2921 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2922 return -EINVAL;
2923 }
2924
2925 /* Trigger an invalidation of the L1 instruction caches */
2926 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2927 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2928 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2929
2930 /* Wait for invalidation complete */
2931 for (i = 0; i < usec_timeout; i++) {
2932 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2933 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2934 INVALIDATE_CACHE_COMPLETE))
2935 break;
2936 udelay(1);
2937 }
2938
2939 if (i >= usec_timeout) {
2940 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2941 return -EINVAL;
2942 }
2943
2944 gfx_v12_0_set_mec_ucode_start_addr(adev);
2945
2946 return 0;
2947 }
2948
gfx_v12_0_kiq_setting(struct amdgpu_ring * ring)2949 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring)
2950 {
2951 uint32_t tmp;
2952 struct amdgpu_device *adev = ring->adev;
2953
2954 /* tell RLC which is KIQ queue */
2955 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
2956 tmp &= 0xffffff00;
2957 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2958 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
2959 }
2960
gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device * adev)2961 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev)
2962 {
2963 /* set graphics engine doorbell range */
2964 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,
2965 (adev->doorbell_index.gfx_ring0 * 2) << 2);
2966 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
2967 (adev->doorbell_index.gfx_userqueue_end * 2) << 2);
2968
2969 /* set compute engine doorbell range */
2970 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
2971 (adev->doorbell_index.kiq * 2) << 2);
2972 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
2973 (adev->doorbell_index.userqueue_end * 2) << 2);
2974 }
2975
gfx_v12_0_gfx_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)2976 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
2977 struct amdgpu_mqd_prop *prop)
2978 {
2979 struct v12_gfx_mqd *mqd = m;
2980 uint64_t hqd_gpu_addr, wb_gpu_addr;
2981 uint32_t tmp;
2982 uint32_t rb_bufsz;
2983
2984 /* set up gfx hqd wptr */
2985 mqd->cp_gfx_hqd_wptr = 0;
2986 mqd->cp_gfx_hqd_wptr_hi = 0;
2987
2988 /* set the pointer to the MQD */
2989 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
2990 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
2991
2992 /* set up mqd control */
2993 tmp = regCP_GFX_MQD_CONTROL_DEFAULT;
2994 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2995 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2996 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2997 mqd->cp_gfx_mqd_control = tmp;
2998
2999 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
3000 tmp = regCP_GFX_HQD_VMID_DEFAULT;
3001 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
3002 mqd->cp_gfx_hqd_vmid = 0;
3003
3004 /* set up default queue priority level
3005 * 0x0 = low priority, 0x1 = high priority */
3006 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT;
3007 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
3008 mqd->cp_gfx_hqd_queue_priority = tmp;
3009
3010 /* set up time quantum */
3011 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT;
3012 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3013 mqd->cp_gfx_hqd_quantum = tmp;
3014
3015 /* set up gfx hqd base. this is similar as CP_RB_BASE */
3016 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3017 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3018 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3019
3020 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3021 wb_gpu_addr = prop->rptr_gpu_addr;
3022 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3023 mqd->cp_gfx_hqd_rptr_addr_hi =
3024 upper_32_bits(wb_gpu_addr) & 0xffff;
3025
3026 /* set up rb_wptr_poll addr */
3027 wb_gpu_addr = prop->wptr_gpu_addr;
3028 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3029 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3030
3031 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3032 rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
3033 tmp = regCP_GFX_HQD_CNTL_DEFAULT;
3034 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3035 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3036 #ifdef __BIG_ENDIAN
3037 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3038 #endif
3039 if (prop->tmz_queue)
3040 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);
3041 if (!prop->kernel_queue)
3042 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1);
3043 mqd->cp_gfx_hqd_cntl = tmp;
3044
3045 /* set up cp_doorbell_control */
3046 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT;
3047 if (prop->use_doorbell) {
3048 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3049 DOORBELL_OFFSET, prop->doorbell_index);
3050 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3051 DOORBELL_EN, 1);
3052 } else
3053 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3054 DOORBELL_EN, 0);
3055 mqd->cp_rb_doorbell_control = tmp;
3056
3057 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3058 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT;
3059
3060 /* active the queue */
3061 mqd->cp_gfx_hqd_active = 1;
3062
3063 /* set gfx UQ items */
3064 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr);
3065 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr);
3066 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr);
3067 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr);
3068 mqd->fence_address_lo = lower_32_bits(prop->fence_address);
3069 mqd->fence_address_hi = upper_32_bits(prop->fence_address);
3070
3071 return 0;
3072 }
3073
gfx_v12_0_kgq_init_queue(struct amdgpu_ring * ring,bool reset)3074 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
3075 {
3076 struct amdgpu_device *adev = ring->adev;
3077 struct v12_gfx_mqd *mqd = ring->mqd_ptr;
3078 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3079
3080 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
3081 memset((void *)mqd, 0, sizeof(*mqd));
3082 mutex_lock(&adev->srbm_mutex);
3083 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3084 amdgpu_ring_init_mqd(ring);
3085 soc24_grbm_select(adev, 0, 0, 0, 0);
3086 mutex_unlock(&adev->srbm_mutex);
3087 if (adev->gfx.me.mqd_backup[mqd_idx])
3088 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3089 } else {
3090 /* restore mqd with the backup copy */
3091 if (adev->gfx.me.mqd_backup[mqd_idx])
3092 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3093 /* reset the ring */
3094 ring->wptr = 0;
3095 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
3096 amdgpu_ring_clear_ring(ring);
3097 }
3098
3099 return 0;
3100 }
3101
gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device * adev)3102 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3103 {
3104 int i, r;
3105
3106 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3107 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
3108 if (r)
3109 return r;
3110 }
3111
3112 r = amdgpu_gfx_enable_kgq(adev, 0);
3113 if (r)
3114 return r;
3115
3116 return gfx_v12_0_cp_gfx_start(adev);
3117 }
3118
gfx_v12_0_compute_mqd_set_cu_mask(struct amdgpu_device * adev,struct v12_compute_mqd * mqd,struct amdgpu_mqd_prop * prop)3119 static void gfx_v12_0_compute_mqd_set_cu_mask(struct amdgpu_device *adev,
3120 struct v12_compute_mqd *mqd,
3121 struct amdgpu_mqd_prop *prop)
3122 {
3123 uint32_t se_mask[8] = {0};
3124 uint32_t wa_mask;
3125 bool has_wa_flag = prop->cu_flags & (AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE |
3126 AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE);
3127
3128 if (!has_wa_flag && (!prop->cu_mask || !prop->cu_mask_count))
3129 return;
3130
3131 if (has_wa_flag) {
3132 wa_mask = (prop->cu_flags & AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE) ?
3133 0xffff : 0xffffffff;
3134 mqd->compute_static_thread_mgmt_se0 = wa_mask;
3135 mqd->compute_static_thread_mgmt_se1 = wa_mask;
3136 mqd->compute_static_thread_mgmt_se2 = wa_mask;
3137 mqd->compute_static_thread_mgmt_se3 = wa_mask;
3138 return;
3139 }
3140
3141 amdgpu_gfx_mqd_symmetrically_map_cu_mask(adev, prop->cu_mask,
3142 prop->cu_mask_count, se_mask);
3143
3144 mqd->compute_static_thread_mgmt_se0 = se_mask[0];
3145 mqd->compute_static_thread_mgmt_se1 = se_mask[1];
3146 mqd->compute_static_thread_mgmt_se2 = se_mask[2];
3147 mqd->compute_static_thread_mgmt_se3 = se_mask[3];
3148 }
3149
gfx_v12_0_compute_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)3150 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
3151 struct amdgpu_mqd_prop *prop)
3152 {
3153 struct v12_compute_mqd *mqd = m;
3154 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3155 uint32_t tmp;
3156
3157 mqd->header = 0xC0310800;
3158 mqd->compute_pipelinestat_enable = 0x00000001;
3159 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3160 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3161 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3162 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3163 mqd->compute_misc_reserved = 0x00000007;
3164
3165 eop_base_addr = prop->eop_gpu_addr >> 8;
3166 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3167 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3168
3169 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3170 tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
3171 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3172 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1));
3173
3174 mqd->cp_hqd_eop_control = tmp;
3175
3176 /* enable doorbell? */
3177 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
3178
3179 if (prop->use_doorbell) {
3180 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3181 DOORBELL_OFFSET, prop->doorbell_index);
3182 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3183 DOORBELL_EN, 1);
3184 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3185 DOORBELL_SOURCE, 0);
3186 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3187 DOORBELL_HIT, 0);
3188 } else {
3189 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3190 DOORBELL_EN, 0);
3191 }
3192
3193 mqd->cp_hqd_pq_doorbell_control = tmp;
3194
3195 /* disable the queue if it's active */
3196 mqd->cp_hqd_dequeue_request = 0;
3197 mqd->cp_hqd_pq_rptr = 0;
3198 mqd->cp_hqd_pq_wptr_lo = 0;
3199 mqd->cp_hqd_pq_wptr_hi = 0;
3200
3201 /* set the pointer to the MQD */
3202 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
3203 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3204
3205 /* set MQD vmid to 0 */
3206 tmp = regCP_MQD_CONTROL_DEFAULT;
3207 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3208 mqd->cp_mqd_control = tmp;
3209
3210 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3211 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3212 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3213 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3214
3215 /* set up the HQD, this is similar to CP_RB0_CNTL */
3216 tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
3217 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3218 (order_base_2(prop->queue_size / 4) - 1));
3219 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3220 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3221 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
3222 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3223 if (prop->kernel_queue) {
3224 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3225 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3226 }
3227 if (prop->tmz_queue)
3228 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);
3229 mqd->cp_hqd_pq_control = tmp;
3230
3231 /* set the wb address whether it's enabled or not */
3232 wb_gpu_addr = prop->rptr_gpu_addr;
3233 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3234 mqd->cp_hqd_pq_rptr_report_addr_hi =
3235 upper_32_bits(wb_gpu_addr) & 0xffff;
3236
3237 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3238 wb_gpu_addr = prop->wptr_gpu_addr;
3239 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3240 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3241
3242 tmp = 0;
3243 /* enable the doorbell if requested */
3244 if (prop->use_doorbell) {
3245 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
3246 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3247 DOORBELL_OFFSET, prop->doorbell_index);
3248
3249 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3250 DOORBELL_EN, 1);
3251 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3252 DOORBELL_SOURCE, 0);
3253 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3254 DOORBELL_HIT, 0);
3255 }
3256
3257 mqd->cp_hqd_pq_doorbell_control = tmp;
3258
3259 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3260 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT;
3261
3262 /* set the vmid for the queue */
3263 mqd->cp_hqd_vmid = 0;
3264
3265 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
3266 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
3267 mqd->cp_hqd_persistent_state = tmp;
3268
3269 /* set MIN_IB_AVAIL_SIZE */
3270 tmp = regCP_HQD_IB_CONTROL_DEFAULT;
3271 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3272 mqd->cp_hqd_ib_control = tmp;
3273
3274 /* set static priority for a compute queue/ring */
3275 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
3276 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
3277
3278 mqd->cp_hqd_active = prop->hqd_active;
3279
3280 /* set UQ fenceaddress */
3281 mqd->fence_address_lo = lower_32_bits(prop->fence_address);
3282 mqd->fence_address_hi = upper_32_bits(prop->fence_address);
3283 /* set CU mask */
3284 gfx_v12_0_compute_mqd_set_cu_mask(adev, mqd, prop);
3285
3286 return 0;
3287 }
3288
gfx_v12_0_kiq_init_register(struct amdgpu_ring * ring)3289 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring)
3290 {
3291 struct amdgpu_device *adev = ring->adev;
3292 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3293 int j;
3294
3295 /* inactivate the queue */
3296 if (amdgpu_sriov_vf(adev))
3297 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
3298
3299 /* disable wptr polling */
3300 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3301
3302 /* write the EOP addr */
3303 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,
3304 mqd->cp_hqd_eop_base_addr_lo);
3305 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
3306 mqd->cp_hqd_eop_base_addr_hi);
3307
3308 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3309 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,
3310 mqd->cp_hqd_eop_control);
3311
3312 /* enable doorbell? */
3313 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3314 mqd->cp_hqd_pq_doorbell_control);
3315
3316 /* disable the queue if it's active */
3317 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
3318 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
3319 for (j = 0; j < adev->usec_timeout; j++) {
3320 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
3321 break;
3322 udelay(1);
3323 }
3324 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
3325 mqd->cp_hqd_dequeue_request);
3326 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,
3327 mqd->cp_hqd_pq_rptr);
3328 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3329 mqd->cp_hqd_pq_wptr_lo);
3330 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3331 mqd->cp_hqd_pq_wptr_hi);
3332 }
3333
3334 /* set the pointer to the MQD */
3335 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,
3336 mqd->cp_mqd_base_addr_lo);
3337 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,
3338 mqd->cp_mqd_base_addr_hi);
3339
3340 /* set MQD vmid to 0 */
3341 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,
3342 mqd->cp_mqd_control);
3343
3344 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3345 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,
3346 mqd->cp_hqd_pq_base_lo);
3347 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,
3348 mqd->cp_hqd_pq_base_hi);
3349
3350 /* set up the HQD, this is similar to CP_RB0_CNTL */
3351 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,
3352 mqd->cp_hqd_pq_control);
3353
3354 /* set the wb address whether it's enabled or not */
3355 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
3356 mqd->cp_hqd_pq_rptr_report_addr_lo);
3357 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3358 mqd->cp_hqd_pq_rptr_report_addr_hi);
3359
3360 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3361 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
3362 mqd->cp_hqd_pq_wptr_poll_addr_lo);
3363 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3364 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3365
3366 /* enable the doorbell if requested */
3367 if (ring->use_doorbell) {
3368 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3369 (adev->doorbell_index.kiq * 2) << 2);
3370 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3371 (adev->doorbell_index.userqueue_end * 2) << 2);
3372 }
3373
3374 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3375 mqd->cp_hqd_pq_doorbell_control);
3376
3377 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3378 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3379 mqd->cp_hqd_pq_wptr_lo);
3380 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3381 mqd->cp_hqd_pq_wptr_hi);
3382
3383 /* set the vmid for the queue */
3384 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
3385
3386 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,
3387 mqd->cp_hqd_persistent_state);
3388
3389 /* activate the queue */
3390 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,
3391 mqd->cp_hqd_active);
3392
3393 if (ring->use_doorbell)
3394 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3395
3396 return 0;
3397 }
3398
gfx_v12_0_kiq_init_queue(struct amdgpu_ring * ring)3399 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring)
3400 {
3401 struct amdgpu_device *adev = ring->adev;
3402 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3403 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3404
3405 gfx_v12_0_kiq_setting(ring);
3406
3407 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
3408 /* reset MQD to a clean status */
3409 if (adev->gfx.mec.mqd_backup[mqd_idx])
3410 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3411
3412 /* reset ring buffer */
3413 ring->wptr = 0;
3414 amdgpu_ring_clear_ring(ring);
3415
3416 mutex_lock(&adev->srbm_mutex);
3417 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3418 gfx_v12_0_kiq_init_register(ring);
3419 soc24_grbm_select(adev, 0, 0, 0, 0);
3420 mutex_unlock(&adev->srbm_mutex);
3421 } else {
3422 memset((void *)mqd, 0, sizeof(*mqd));
3423 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
3424 amdgpu_ring_clear_ring(ring);
3425 mutex_lock(&adev->srbm_mutex);
3426 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3427 amdgpu_ring_init_mqd(ring);
3428 gfx_v12_0_kiq_init_register(ring);
3429 soc24_grbm_select(adev, 0, 0, 0, 0);
3430 mutex_unlock(&adev->srbm_mutex);
3431
3432 if (adev->gfx.mec.mqd_backup[mqd_idx])
3433 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3434 }
3435
3436 return 0;
3437 }
3438
gfx_v12_0_kcq_init_queue(struct amdgpu_ring * ring,bool reset)3439 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset)
3440 {
3441 struct amdgpu_device *adev = ring->adev;
3442 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3443 int mqd_idx = ring - &adev->gfx.compute_ring[0];
3444
3445 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
3446 memset((void *)mqd, 0, sizeof(*mqd));
3447 mutex_lock(&adev->srbm_mutex);
3448 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3449 amdgpu_ring_init_mqd(ring);
3450 soc24_grbm_select(adev, 0, 0, 0, 0);
3451 mutex_unlock(&adev->srbm_mutex);
3452
3453 if (adev->gfx.mec.mqd_backup[mqd_idx])
3454 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3455 } else {
3456 /* restore MQD to a clean status */
3457 if (adev->gfx.mec.mqd_backup[mqd_idx])
3458 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3459 /* reset ring buffer */
3460 ring->wptr = 0;
3461 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
3462 amdgpu_ring_clear_ring(ring);
3463 }
3464
3465 return 0;
3466 }
3467
gfx_v12_0_kiq_resume(struct amdgpu_device * adev)3468 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev)
3469 {
3470 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
3471 adev->gfx.kiq[0].ring.sched.ready = true;
3472 return 0;
3473 }
3474
gfx_v12_0_kcq_resume(struct amdgpu_device * adev)3475 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev)
3476 {
3477 int i, r;
3478
3479 if (!amdgpu_async_gfx_ring)
3480 gfx_v12_0_cp_compute_enable(adev, true);
3481
3482 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3483 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false);
3484 if (r)
3485 return r;
3486 }
3487
3488 return amdgpu_gfx_enable_kcq(adev, 0);
3489 }
3490
gfx_v12_0_cp_resume(struct amdgpu_device * adev)3491 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev)
3492 {
3493 int r, i;
3494 struct amdgpu_ring *ring;
3495
3496 if (!(adev->flags & AMD_IS_APU))
3497 gfx_v12_0_enable_gui_idle_interrupt(adev, false);
3498
3499 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3500 /* legacy firmware loading */
3501 r = gfx_v12_0_cp_gfx_load_microcode(adev);
3502 if (r)
3503 return r;
3504
3505 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev);
3506 if (r)
3507 return r;
3508 }
3509
3510 gfx_v12_0_cp_set_doorbell_range(adev);
3511
3512 if (amdgpu_async_gfx_ring) {
3513 gfx_v12_0_cp_compute_enable(adev, true);
3514 gfx_v12_0_cp_gfx_enable(adev, true);
3515 }
3516
3517 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
3518 r = amdgpu_mes_kiq_hw_init(adev, 0);
3519 else
3520 r = gfx_v12_0_kiq_resume(adev);
3521 if (r)
3522 return r;
3523
3524 r = gfx_v12_0_kcq_resume(adev);
3525 if (r)
3526 return r;
3527
3528 if (!amdgpu_async_gfx_ring) {
3529 r = gfx_v12_0_cp_gfx_resume(adev);
3530 if (r)
3531 return r;
3532 } else {
3533 r = gfx_v12_0_cp_async_gfx_ring_resume(adev);
3534 if (r)
3535 return r;
3536 }
3537
3538 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3539 ring = &adev->gfx.gfx_ring[i];
3540 r = amdgpu_ring_test_helper(ring);
3541 if (r)
3542 return r;
3543 }
3544
3545 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3546 ring = &adev->gfx.compute_ring[i];
3547 r = amdgpu_ring_test_helper(ring);
3548 if (r)
3549 return r;
3550 }
3551
3552 return 0;
3553 }
3554
gfx_v12_0_cp_enable(struct amdgpu_device * adev,bool enable)3555 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable)
3556 {
3557 gfx_v12_0_cp_gfx_enable(adev, enable);
3558 gfx_v12_0_cp_compute_enable(adev, enable);
3559 }
3560
gfx_v12_0_gfxhub_enable(struct amdgpu_device * adev)3561 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev)
3562 {
3563 int r;
3564 bool value;
3565
3566 r = adev->gfxhub.funcs->gart_enable(adev);
3567 if (r)
3568 return r;
3569
3570 amdgpu_device_flush_hdp(adev, NULL);
3571
3572 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS;
3573
3574 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
3575 /* TODO investigate why this and the hdp flush above is needed,
3576 * are we missing a flush somewhere else? */
3577 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
3578
3579 return 0;
3580 }
3581
get_gb_addr_config(struct amdgpu_device * adev)3582 static int get_gb_addr_config(struct amdgpu_device *adev)
3583 {
3584 u32 gb_addr_config;
3585
3586 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
3587 if (gb_addr_config == 0)
3588 return -EINVAL;
3589
3590 adev->gfx.config.gb_addr_config_fields.num_pkrs =
3591 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
3592
3593 adev->gfx.config.gb_addr_config = gb_addr_config;
3594
3595 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
3596 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3597 GB_ADDR_CONFIG, NUM_PIPES);
3598
3599 adev->gfx.config.max_tile_pipes =
3600 adev->gfx.config.gb_addr_config_fields.num_pipes;
3601
3602 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
3603 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3604 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
3605 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
3606 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3607 GB_ADDR_CONFIG, NUM_RB_PER_SE);
3608 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
3609 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3610 GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
3611 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
3612 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3613 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
3614
3615 return 0;
3616 }
3617
gfx_v12_0_disable_gpa_mode(struct amdgpu_device * adev)3618 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev)
3619 {
3620 uint32_t data;
3621
3622 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
3623 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
3624 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
3625
3626 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);
3627 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
3628 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
3629 }
3630
gfx_v12_0_init_golden_registers(struct amdgpu_device * adev)3631 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev)
3632 {
3633 if (amdgpu_sriov_vf(adev))
3634 return;
3635
3636 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3637 case IP_VERSION(12, 0, 0):
3638 case IP_VERSION(12, 0, 1):
3639 soc15_program_register_sequence(adev,
3640 golden_settings_gc_12_0,
3641 (const u32)ARRAY_SIZE(golden_settings_gc_12_0));
3642
3643 if (adev->rev_id == 0)
3644 soc15_program_register_sequence(adev,
3645 golden_settings_gc_12_0_rev0,
3646 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0));
3647 break;
3648 default:
3649 break;
3650 }
3651 }
3652
gfx_v12_0_hw_init(struct amdgpu_ip_block * ip_block)3653 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
3654 {
3655 int r;
3656 struct amdgpu_device *adev = ip_block->adev;
3657
3658 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
3659 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
3660 /* RLC autoload sequence 1: Program rlc ram */
3661 if (adev->gfx.imu.funcs->program_rlc_ram)
3662 adev->gfx.imu.funcs->program_rlc_ram(adev);
3663 }
3664 /* rlc autoload firmware */
3665 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev);
3666 if (r)
3667 return r;
3668 } else {
3669 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3670 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
3671 if (adev->gfx.imu.funcs->load_microcode)
3672 adev->gfx.imu.funcs->load_microcode(adev);
3673 if (adev->gfx.imu.funcs->setup_imu)
3674 adev->gfx.imu.funcs->setup_imu(adev);
3675 if (adev->gfx.imu.funcs->start_imu)
3676 adev->gfx.imu.funcs->start_imu(adev);
3677 }
3678
3679 /* disable gpa mode in backdoor loading */
3680 gfx_v12_0_disable_gpa_mode(adev);
3681 }
3682 }
3683
3684 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) ||
3685 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3686 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev);
3687 if (r) {
3688 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r);
3689 return r;
3690 }
3691 }
3692
3693 if (!amdgpu_emu_mode)
3694 gfx_v12_0_init_golden_registers(adev);
3695
3696 adev->gfx.is_poweron = true;
3697
3698 if (get_gb_addr_config(adev))
3699 drm_warn(adev_to_drm(adev), "Invalid gb_addr_config !\n");
3700
3701 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
3702 gfx_v12_0_config_gfx_rs64(adev);
3703
3704 r = gfx_v12_0_gfxhub_enable(adev);
3705 if (r)
3706 return r;
3707
3708 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT ||
3709 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) &&
3710 (amdgpu_dpm == 1)) {
3711 /**
3712 * For gfx 12, rlc firmware loading relies on smu firmware is
3713 * loaded firstly, so in direct type, it has to load smc ucode
3714 * here before rlc.
3715 */
3716 r = amdgpu_pm_load_smu_firmware(adev, NULL);
3717 if (r)
3718 return r;
3719 }
3720
3721 gfx_v12_0_constants_init(adev);
3722
3723 if (adev->nbio.funcs->gc_doorbell_init)
3724 adev->nbio.funcs->gc_doorbell_init(adev);
3725
3726 r = gfx_v12_0_rlc_resume(adev);
3727 if (r)
3728 return r;
3729
3730 /*
3731 * init golden registers and rlc resume may override some registers,
3732 * reconfig them here
3733 */
3734 gfx_v12_0_tcp_harvest(adev);
3735
3736 r = gfx_v12_0_cp_resume(adev);
3737 if (r)
3738 return r;
3739
3740 return r;
3741 }
3742
gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device * adev,bool enable)3743 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
3744 bool enable)
3745 {
3746 unsigned int irq_type;
3747 int m, p, r;
3748
3749 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
3750 for (m = 0; m < adev->gfx.me.num_me; m++) {
3751 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
3752 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
3753 if (enable)
3754 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,
3755 irq_type);
3756 else
3757 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,
3758 irq_type);
3759 if (r)
3760 return r;
3761 }
3762 }
3763 }
3764
3765 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
3766 for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
3767 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
3768 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
3769 + (m * adev->gfx.mec.num_pipe_per_mec)
3770 + p;
3771 if (enable)
3772 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,
3773 irq_type);
3774 else
3775 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,
3776 irq_type);
3777 if (r)
3778 return r;
3779 }
3780 }
3781 }
3782
3783 return 0;
3784 }
3785
gfx_v12_0_hw_fini(struct amdgpu_ip_block * ip_block)3786 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
3787 {
3788 struct amdgpu_device *adev = ip_block->adev;
3789 uint32_t tmp;
3790
3791 cancel_delayed_work_sync(&adev->gfx.idle_work);
3792
3793 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3794 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3795 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
3796 gfx_v12_0_set_userq_eop_interrupts(adev, false);
3797
3798 if (!adev->no_hw_access) {
3799 if (amdgpu_async_gfx_ring) {
3800 if (amdgpu_gfx_disable_kgq(adev, 0))
3801 DRM_ERROR("KGQ disable failed\n");
3802 }
3803
3804 if (amdgpu_gfx_disable_kcq(adev, 0))
3805 DRM_ERROR("KCQ disable failed\n");
3806
3807 amdgpu_mes_kiq_hw_fini(adev, 0);
3808 }
3809
3810 if (amdgpu_sriov_vf(adev)) {
3811 gfx_v12_0_cp_gfx_enable(adev, false);
3812 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
3813 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
3814 tmp &= 0xffffff00;
3815 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3816
3817 return 0;
3818 }
3819 gfx_v12_0_cp_enable(adev, false);
3820 gfx_v12_0_enable_gui_idle_interrupt(adev, false);
3821
3822 adev->gfxhub.funcs->gart_disable(adev);
3823
3824 adev->gfx.is_poweron = false;
3825
3826 return 0;
3827 }
3828
gfx_v12_0_suspend(struct amdgpu_ip_block * ip_block)3829 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block)
3830 {
3831 return gfx_v12_0_hw_fini(ip_block);
3832 }
3833
gfx_v12_0_resume(struct amdgpu_ip_block * ip_block)3834 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block)
3835 {
3836 return gfx_v12_0_hw_init(ip_block);
3837 }
3838
gfx_v12_0_is_idle(struct amdgpu_ip_block * ip_block)3839 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
3840 {
3841 struct amdgpu_device *adev = ip_block->adev;
3842
3843 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
3844 GRBM_STATUS, GUI_ACTIVE))
3845 return false;
3846 else
3847 return true;
3848 }
3849
gfx_v12_0_wait_for_idle(struct amdgpu_ip_block * ip_block)3850 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
3851 {
3852 unsigned i;
3853 u32 tmp;
3854 struct amdgpu_device *adev = ip_block->adev;
3855
3856 for (i = 0; i < adev->usec_timeout; i++) {
3857 /* read MC_STATUS */
3858 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
3859 GRBM_STATUS__GUI_ACTIVE_MASK;
3860
3861 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3862 return 0;
3863 udelay(1);
3864 }
3865 return -ETIMEDOUT;
3866 }
3867
gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device * adev)3868 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3869 {
3870 uint64_t clock = 0;
3871
3872 if (adev->smuio.funcs &&
3873 adev->smuio.funcs->get_gpu_clock_counter)
3874 clock = adev->smuio.funcs->get_gpu_clock_counter(adev);
3875 else
3876 dev_warn(adev->dev, "query gpu clock counter is not supported\n");
3877
3878 return clock;
3879 }
3880
gfx_v12_0_early_init(struct amdgpu_ip_block * ip_block)3881 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block)
3882 {
3883 struct amdgpu_device *adev = ip_block->adev;
3884
3885 switch (amdgpu_user_queue) {
3886 case -1:
3887 case 0:
3888 default:
3889 adev->gfx.disable_kq = false;
3890 adev->gfx.disable_uq = true;
3891 break;
3892 case 1:
3893 adev->gfx.disable_kq = false;
3894 adev->gfx.disable_uq = false;
3895 break;
3896 case 2:
3897 adev->gfx.disable_kq = true;
3898 adev->gfx.disable_uq = false;
3899 break;
3900 }
3901
3902 adev->gfx.funcs = &gfx_v12_0_gfx_funcs;
3903
3904 if (adev->gfx.disable_kq) {
3905 adev->gfx.num_gfx_rings = 0;
3906 adev->gfx.num_compute_rings = 0;
3907 } else {
3908 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS;
3909 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
3910 AMDGPU_MAX_COMPUTE_RINGS);
3911 }
3912
3913 gfx_v12_0_set_kiq_pm4_funcs(adev);
3914 gfx_v12_0_set_ring_funcs(adev);
3915 gfx_v12_0_set_irq_funcs(adev);
3916 gfx_v12_0_set_rlc_funcs(adev);
3917 gfx_v12_0_set_mqd_funcs(adev);
3918 gfx_v12_0_set_imu_funcs(adev);
3919
3920 gfx_v12_0_init_rlcg_reg_access_ctrl(adev);
3921
3922 return gfx_v12_0_init_microcode(adev);
3923 }
3924
gfx_v12_0_late_init(struct amdgpu_ip_block * ip_block)3925 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block)
3926 {
3927 struct amdgpu_device *adev = ip_block->adev;
3928 int r;
3929
3930 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3931 if (r)
3932 return r;
3933
3934 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3935 if (r)
3936 return r;
3937
3938 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
3939 if (r)
3940 return r;
3941
3942 r = gfx_v12_0_set_userq_eop_interrupts(adev, true);
3943 if (r)
3944 return r;
3945
3946 return 0;
3947 }
3948
gfx_v12_0_is_rlc_enabled(struct amdgpu_device * adev)3949 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev)
3950 {
3951 uint32_t rlc_cntl;
3952
3953 /* if RLC is not enabled, do nothing */
3954 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);
3955 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
3956 }
3957
gfx_v12_0_set_safe_mode(struct amdgpu_device * adev,int xcc_id)3958 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev,
3959 int xcc_id)
3960 {
3961 uint32_t data;
3962 unsigned i;
3963
3964 data = RLC_SAFE_MODE__CMD_MASK;
3965 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3966
3967 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
3968
3969 /* wait for RLC_SAFE_MODE */
3970 for (i = 0; i < adev->usec_timeout; i++) {
3971 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
3972 RLC_SAFE_MODE, CMD))
3973 break;
3974 udelay(1);
3975 }
3976 }
3977
gfx_v12_0_unset_safe_mode(struct amdgpu_device * adev,int xcc_id)3978 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev,
3979 int xcc_id)
3980 {
3981 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
3982 }
3983
gfx_v12_0_update_perf_clk(struct amdgpu_device * adev,bool enable)3984 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
3985 bool enable)
3986 {
3987 uint32_t def, data;
3988
3989 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
3990 return;
3991
3992 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
3993
3994 if (enable)
3995 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
3996 else
3997 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
3998
3999 if (def != data)
4000 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4001 }
4002
gfx_v12_0_update_spm_vmid(struct amdgpu_device * adev,int xcc_id,struct amdgpu_ring * ring,unsigned vmid)4003 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev,
4004 int xcc_id,
4005 struct amdgpu_ring *ring,
4006 unsigned vmid)
4007 {
4008 u32 reg, data;
4009
4010 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
4011 if (amdgpu_sriov_is_pp_one_vf(adev))
4012 data = RREG32_NO_KIQ(reg);
4013 else
4014 data = RREG32(reg);
4015
4016 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
4017 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
4018
4019 if (amdgpu_sriov_is_pp_one_vf(adev))
4020 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
4021 else
4022 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
4023
4024 if (ring
4025 && amdgpu_sriov_is_pp_one_vf(adev)
4026 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX)
4027 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
4028 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
4029 amdgpu_ring_emit_wreg(ring, reg, data);
4030 }
4031 }
4032
4033 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = {
4034 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled,
4035 .set_safe_mode = gfx_v12_0_set_safe_mode,
4036 .unset_safe_mode = gfx_v12_0_unset_safe_mode,
4037 .init = gfx_v12_0_rlc_init,
4038 .get_csb_size = gfx_v12_0_get_csb_size,
4039 .get_csb_buffer = gfx_v12_0_get_csb_buffer,
4040 .resume = gfx_v12_0_rlc_resume,
4041 .stop = gfx_v12_0_rlc_stop,
4042 .reset = gfx_v12_0_rlc_reset,
4043 .start = gfx_v12_0_rlc_start,
4044 .update_spm_vmid = gfx_v12_0_update_spm_vmid,
4045 };
4046
4047 #if 0
4048 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable)
4049 {
4050 /* TODO */
4051 }
4052
4053 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable)
4054 {
4055 /* TODO */
4056 }
4057 #endif
4058
gfx_v12_0_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)4059 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
4060 enum amd_powergating_state state)
4061 {
4062 struct amdgpu_device *adev = ip_block->adev;
4063 bool enable = (state == AMD_PG_STATE_GATE);
4064
4065 if (amdgpu_sriov_vf(adev))
4066 return 0;
4067
4068 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4069 case IP_VERSION(12, 0, 0):
4070 case IP_VERSION(12, 0, 1):
4071 amdgpu_gfx_off_ctrl(adev, enable);
4072 break;
4073 default:
4074 break;
4075 }
4076
4077 return 0;
4078 }
4079
gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)4080 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4081 bool enable)
4082 {
4083 uint32_t def, data;
4084
4085 if (!(adev->cg_flags &
4086 (AMD_CG_SUPPORT_GFX_CGCG |
4087 AMD_CG_SUPPORT_GFX_CGLS |
4088 AMD_CG_SUPPORT_GFX_3D_CGCG |
4089 AMD_CG_SUPPORT_GFX_3D_CGLS)))
4090 return;
4091
4092 if (enable) {
4093 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4094
4095 /* unset CGCG override */
4096 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4097 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4098 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4099 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4100 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG ||
4101 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4102 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4103
4104 /* update CGCG override bits */
4105 if (def != data)
4106 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4107
4108 /* enable cgcg FSM(0x0000363F) */
4109 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4110
4111 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
4112 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK;
4113 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4114 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4115 }
4116
4117 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
4118 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK;
4119 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4120 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4121 }
4122
4123 if (def != data)
4124 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4125
4126 /* Program RLC_CGCG_CGLS_CTRL_3D */
4127 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4128
4129 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
4130 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK;
4131 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4132 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4133 }
4134
4135 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
4136 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK;
4137 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4138 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4139 }
4140
4141 if (def != data)
4142 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4143
4144 /* set IDLE_POLL_COUNT(0x00900100) */
4145 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
4146
4147 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK);
4148 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4149 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4150
4151 if (def != data)
4152 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
4153
4154 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4155 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4156 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4157 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4158 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4159 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);
4160
4161 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4162 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4163 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4164
4165 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4166 if (adev->sdma.num_instances > 1) {
4167 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4168 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4169 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4170 }
4171 } else {
4172 /* Program RLC_CGCG_CGLS_CTRL */
4173 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4174
4175 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4176 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4177
4178 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4179 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4180
4181 if (def != data)
4182 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4183
4184 /* Program RLC_CGCG_CGLS_CTRL_3D */
4185 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4186
4187 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
4188 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4189 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4190 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4191
4192 if (def != data)
4193 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4194 }
4195 }
4196
gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)4197 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4198 bool enable)
4199 {
4200 uint32_t data, def;
4201 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
4202 return;
4203
4204 /* It is disabled by HW by default */
4205 if (enable) {
4206 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4207 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4208 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4209
4210 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4211 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4212 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4213
4214 if (def != data)
4215 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4216 }
4217 } else {
4218 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4219 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4220
4221 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4222 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4223 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4224
4225 if (def != data)
4226 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4227 }
4228 }
4229 }
4230
gfx_v12_0_update_repeater_fgcg(struct amdgpu_device * adev,bool enable)4231 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev,
4232 bool enable)
4233 {
4234 uint32_t def, data;
4235
4236 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
4237 return;
4238
4239 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4240
4241 if (enable)
4242 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |
4243 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK);
4244 else
4245 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |
4246 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK;
4247
4248 if (def != data)
4249 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4250 }
4251
gfx_v12_0_update_sram_fgcg(struct amdgpu_device * adev,bool enable)4252 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev,
4253 bool enable)
4254 {
4255 uint32_t def, data;
4256
4257 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
4258 return;
4259
4260 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4261
4262 if (enable)
4263 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4264 else
4265 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4266
4267 if (def != data)
4268 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4269 }
4270
gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)4271 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4272 bool enable)
4273 {
4274 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4275
4276 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable);
4277
4278 gfx_v12_0_update_medium_grain_clock_gating(adev, enable);
4279
4280 gfx_v12_0_update_repeater_fgcg(adev, enable);
4281
4282 gfx_v12_0_update_sram_fgcg(adev, enable);
4283
4284 gfx_v12_0_update_perf_clk(adev, enable);
4285
4286 if (adev->cg_flags &
4287 (AMD_CG_SUPPORT_GFX_MGCG |
4288 AMD_CG_SUPPORT_GFX_CGLS |
4289 AMD_CG_SUPPORT_GFX_CGCG |
4290 AMD_CG_SUPPORT_GFX_3D_CGCG |
4291 AMD_CG_SUPPORT_GFX_3D_CGLS))
4292 gfx_v12_0_enable_gui_idle_interrupt(adev, enable);
4293
4294 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4295
4296 return 0;
4297 }
4298
gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)4299 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
4300 enum amd_clockgating_state state)
4301 {
4302 struct amdgpu_device *adev = ip_block->adev;
4303
4304 if (amdgpu_sriov_vf(adev))
4305 return 0;
4306
4307 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4308 case IP_VERSION(12, 0, 0):
4309 case IP_VERSION(12, 0, 1):
4310 gfx_v12_0_update_gfx_clock_gating(adev,
4311 state == AMD_CG_STATE_GATE);
4312 break;
4313 default:
4314 break;
4315 }
4316
4317 return 0;
4318 }
4319
gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)4320 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
4321 {
4322 struct amdgpu_device *adev = ip_block->adev;
4323 int data;
4324
4325 /* AMD_CG_SUPPORT_GFX_MGCG */
4326 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4327 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4328 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
4329
4330 /* AMD_CG_SUPPORT_REPEATER_FGCG */
4331 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))
4332 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG;
4333
4334 /* AMD_CG_SUPPORT_GFX_FGCG */
4335 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
4336 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
4337
4338 /* AMD_CG_SUPPORT_GFX_PERF_CLK */
4339 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))
4340 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;
4341
4342 /* AMD_CG_SUPPORT_GFX_CGCG */
4343 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4344 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4345 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
4346
4347 /* AMD_CG_SUPPORT_GFX_CGLS */
4348 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4349 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
4350
4351 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
4352 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4353 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4354 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4355
4356 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
4357 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4358 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4359 }
4360
gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring * ring)4361 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4362 {
4363 /* gfx12 is 32bit rptr*/
4364 return *(uint32_t *)ring->rptr_cpu_addr;
4365 }
4366
gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)4367 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4368 {
4369 struct amdgpu_device *adev = ring->adev;
4370 u64 wptr;
4371
4372 /* XXX check if swapping is necessary on BE */
4373 if (ring->use_doorbell) {
4374 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
4375 } else {
4376 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);
4377 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;
4378 }
4379
4380 return wptr;
4381 }
4382
gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)4383 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4384 {
4385 struct amdgpu_device *adev = ring->adev;
4386
4387 if (ring->use_doorbell) {
4388 /* XXX check if swapping is necessary on BE */
4389 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
4390 ring->wptr);
4391 WDOORBELL64(ring->doorbell_index, ring->wptr);
4392 } else {
4393 WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
4394 lower_32_bits(ring->wptr));
4395 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
4396 upper_32_bits(ring->wptr));
4397 }
4398 }
4399
gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring * ring)4400 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4401 {
4402 /* gfx12 hardware is 32bit rptr */
4403 return *(uint32_t *)ring->rptr_cpu_addr;
4404 }
4405
gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring * ring)4406 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4407 {
4408 u64 wptr;
4409
4410 /* XXX check if swapping is necessary on BE */
4411 if (ring->use_doorbell)
4412 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
4413 else
4414 BUG();
4415 return wptr;
4416 }
4417
gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring * ring)4418 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4419 {
4420 struct amdgpu_device *adev = ring->adev;
4421
4422 /* XXX check if swapping is necessary on BE */
4423 if (ring->use_doorbell) {
4424 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
4425 ring->wptr);
4426 WDOORBELL64(ring->doorbell_index, ring->wptr);
4427 } else {
4428 BUG(); /* only DOORBELL method supported on gfx12 now */
4429 }
4430 }
4431
gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)4432 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4433 {
4434 struct amdgpu_device *adev = ring->adev;
4435 u32 ref_and_mask, reg_mem_engine;
4436
4437 if (!adev->gfx.funcs->get_hdp_flush_mask) {
4438 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__);
4439 return;
4440 }
4441
4442 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine);
4443 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4444 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4445 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
4446 ref_and_mask, ref_and_mask, 0x20);
4447 }
4448
gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)4449 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4450 struct amdgpu_job *job,
4451 struct amdgpu_ib *ib,
4452 uint32_t flags)
4453 {
4454 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4455 u32 header, control = 0;
4456
4457 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4458
4459 control |= ib->length_dw | (vmid << 24);
4460
4461 amdgpu_ring_write(ring, header);
4462 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4463 amdgpu_ring_write(ring,
4464 #ifdef __BIG_ENDIAN
4465 (2 << 0) |
4466 #endif
4467 lower_32_bits(ib->gpu_addr));
4468 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4469 amdgpu_ring_write(ring, control);
4470 }
4471
gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)4472 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4473 struct amdgpu_job *job,
4474 struct amdgpu_ib *ib,
4475 uint32_t flags)
4476 {
4477 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4478 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4479
4480 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4481 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4482 amdgpu_ring_write(ring,
4483 #ifdef __BIG_ENDIAN
4484 (2 << 0) |
4485 #endif
4486 lower_32_bits(ib->gpu_addr));
4487 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4488 amdgpu_ring_write(ring, control);
4489 }
4490
gfx_v12_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)4491 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4492 u64 seq, unsigned flags)
4493 {
4494 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4495 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4496
4497 /* RELEASE_MEM - flush caches, send int */
4498 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4499 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4500 PACKET3_RELEASE_MEM_GCR_GL2_WB |
4501 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4502 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4503 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
4504 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
4505 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
4506
4507 /*
4508 * the address should be Qword aligned if 64bit write, Dword
4509 * aligned if only send 32bit data low (discard data high)
4510 */
4511 if (write64bit)
4512 BUG_ON(addr & 0x7);
4513 else
4514 BUG_ON(addr & 0x3);
4515 amdgpu_ring_write(ring, lower_32_bits(addr));
4516 amdgpu_ring_write(ring, upper_32_bits(addr));
4517 amdgpu_ring_write(ring, lower_32_bits(seq));
4518 amdgpu_ring_write(ring, upper_32_bits(seq));
4519 amdgpu_ring_write(ring, 0);
4520 }
4521
gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)4522 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4523 {
4524 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4525 uint32_t seq = ring->fence_drv.sync_seq;
4526 uint64_t addr = ring->fence_drv.gpu_addr;
4527
4528 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
4529 upper_32_bits(addr), seq, 0xffffffff, 4);
4530 }
4531
gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring * ring,uint16_t pasid,uint32_t flush_type,bool all_hub,uint8_t dst_sel)4532 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
4533 uint16_t pasid, uint32_t flush_type,
4534 bool all_hub, uint8_t dst_sel)
4535 {
4536 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
4537 amdgpu_ring_write(ring,
4538 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
4539 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
4540 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
4541 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
4542 }
4543
gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)4544 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4545 unsigned vmid, uint64_t pd_addr)
4546 {
4547 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4548
4549 /* compute doesn't have PFP */
4550 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4551 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4552 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4553 amdgpu_ring_write(ring, 0x0);
4554 }
4555 }
4556
gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)4557 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4558 u64 seq, unsigned int flags)
4559 {
4560 struct amdgpu_device *adev = ring->adev;
4561
4562 /* we only allocate 32bit for each seq wb address */
4563 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4564
4565 /* write fence seq to the "addr" */
4566 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4567 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4568 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4569 amdgpu_ring_write(ring, lower_32_bits(addr));
4570 amdgpu_ring_write(ring, upper_32_bits(addr));
4571 amdgpu_ring_write(ring, lower_32_bits(seq));
4572
4573 if (flags & AMDGPU_FENCE_FLAG_INT) {
4574 /* set register to trigger INT */
4575 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4576 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4577 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4578 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
4579 amdgpu_ring_write(ring, 0);
4580 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4581 }
4582 }
4583
gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)4584 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
4585 uint32_t flags)
4586 {
4587 uint32_t dw2 = 0;
4588
4589 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4590 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4591 /* set load_global_config & load_global_uconfig */
4592 dw2 |= 0x8001;
4593 /* set load_cs_sh_regs */
4594 dw2 |= 0x01000000;
4595 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4596 dw2 |= 0x10002;
4597 }
4598
4599 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4600 amdgpu_ring_write(ring, dw2);
4601 amdgpu_ring_write(ring, 0);
4602 }
4603
gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)4604 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
4605 uint64_t addr)
4606 {
4607 unsigned ret;
4608
4609 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4610 amdgpu_ring_write(ring, lower_32_bits(addr));
4611 amdgpu_ring_write(ring, upper_32_bits(addr));
4612 /* discard following DWs if *cond_exec_gpu_addr==0 */
4613 amdgpu_ring_write(ring, 0);
4614 ret = ring->wptr & ring->buf_mask;
4615 /* patch dummy value later */
4616 amdgpu_ring_write(ring, 0);
4617
4618 return ret;
4619 }
4620
gfx_v12_0_ring_preempt_ib(struct amdgpu_ring * ring)4621 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring)
4622 {
4623 int i, r = 0;
4624 struct amdgpu_device *adev = ring->adev;
4625 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
4626 struct amdgpu_ring *kiq_ring = &kiq->ring;
4627 unsigned long flags;
4628
4629 if (adev->enable_mes)
4630 return -EINVAL;
4631
4632 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4633 return -EINVAL;
4634
4635 spin_lock_irqsave(&kiq->ring_lock, flags);
4636
4637 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
4638 spin_unlock_irqrestore(&kiq->ring_lock, flags);
4639 return -ENOMEM;
4640 }
4641
4642 /* assert preemption condition */
4643 amdgpu_ring_set_preempt_cond_exec(ring, false);
4644
4645 /* assert IB preemption, emit the trailing fence */
4646 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
4647 ring->trail_fence_gpu_addr,
4648 ++ring->trail_seq);
4649 amdgpu_ring_commit(kiq_ring);
4650
4651 spin_unlock_irqrestore(&kiq->ring_lock, flags);
4652
4653 /* poll the trailing fence */
4654 for (i = 0; i < adev->usec_timeout; i++) {
4655 if (ring->trail_seq ==
4656 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
4657 break;
4658 udelay(1);
4659 }
4660
4661 if (i >= adev->usec_timeout) {
4662 r = -EINVAL;
4663 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
4664 }
4665
4666 /* deassert preemption condition */
4667 amdgpu_ring_set_preempt_cond_exec(ring, true);
4668 return r;
4669 }
4670
gfx_v12_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t reg_val_offs)4671 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
4672 uint32_t reg_val_offs)
4673 {
4674 struct amdgpu_device *adev = ring->adev;
4675
4676 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4677 amdgpu_ring_write(ring, 0 | /* src: register*/
4678 (5 << 8) | /* dst: memory */
4679 (1 << 20)); /* write confirm */
4680 amdgpu_ring_write(ring, reg);
4681 amdgpu_ring_write(ring, 0);
4682 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4683 reg_val_offs * 4));
4684 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4685 reg_val_offs * 4));
4686 }
4687
gfx_v12_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)4688 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring,
4689 uint32_t reg,
4690 uint32_t val)
4691 {
4692 uint32_t cmd = 0;
4693
4694 switch (ring->funcs->type) {
4695 case AMDGPU_RING_TYPE_GFX:
4696 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4697 break;
4698 case AMDGPU_RING_TYPE_KIQ:
4699 cmd = (1 << 16); /* no inc addr */
4700 break;
4701 default:
4702 cmd = WR_CONFIRM;
4703 break;
4704 }
4705 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4706 amdgpu_ring_write(ring, cmd);
4707 amdgpu_ring_write(ring, reg);
4708 amdgpu_ring_write(ring, 0);
4709 amdgpu_ring_write(ring, val);
4710 }
4711
gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)4712 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4713 uint32_t val, uint32_t mask)
4714 {
4715 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4716 }
4717
gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)4718 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4719 uint32_t reg0, uint32_t reg1,
4720 uint32_t ref, uint32_t mask)
4721 {
4722 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4723
4724 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4725 ref, mask, 0x20);
4726 }
4727
4728 static void
gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,uint32_t me,uint32_t pipe,enum amdgpu_interrupt_state state)4729 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4730 uint32_t me, uint32_t pipe,
4731 enum amdgpu_interrupt_state state)
4732 {
4733 uint32_t cp_int_cntl, cp_int_cntl_reg;
4734
4735 if (!me) {
4736 switch (pipe) {
4737 case 0:
4738 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
4739 break;
4740 default:
4741 DRM_DEBUG("invalid pipe %d\n", pipe);
4742 return;
4743 }
4744 } else {
4745 DRM_DEBUG("invalid me %d\n", me);
4746 return;
4747 }
4748
4749 switch (state) {
4750 case AMDGPU_IRQ_STATE_DISABLE:
4751 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4752 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4753 TIME_STAMP_INT_ENABLE, 0);
4754 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4755 GENERIC0_INT_ENABLE, 0);
4756 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4757 break;
4758 case AMDGPU_IRQ_STATE_ENABLE:
4759 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4760 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4761 TIME_STAMP_INT_ENABLE, 1);
4762 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4763 GENERIC0_INT_ENABLE, 1);
4764 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4765 break;
4766 default:
4767 break;
4768 }
4769 }
4770
gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)4771 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4772 int me, int pipe,
4773 enum amdgpu_interrupt_state state)
4774 {
4775 u32 mec_int_cntl, mec_int_cntl_reg;
4776
4777 /*
4778 * amdgpu controls only the first MEC. That's why this function only
4779 * handles the setting of interrupts for this specific MEC. All other
4780 * pipes' interrupts are set by amdkfd.
4781 */
4782
4783 if (me == 1) {
4784 switch (pipe) {
4785 case 0:
4786 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
4787 break;
4788 case 1:
4789 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
4790 break;
4791 default:
4792 DRM_DEBUG("invalid pipe %d\n", pipe);
4793 return;
4794 }
4795 } else {
4796 DRM_DEBUG("invalid me %d\n", me);
4797 return;
4798 }
4799
4800 switch (state) {
4801 case AMDGPU_IRQ_STATE_DISABLE:
4802 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
4803 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4804 TIME_STAMP_INT_ENABLE, 0);
4805 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4806 GENERIC0_INT_ENABLE, 0);
4807 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
4808 break;
4809 case AMDGPU_IRQ_STATE_ENABLE:
4810 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
4811 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4812 TIME_STAMP_INT_ENABLE, 1);
4813 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4814 GENERIC0_INT_ENABLE, 1);
4815 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
4816 break;
4817 default:
4818 break;
4819 }
4820 }
4821
gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)4822 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4823 struct amdgpu_irq_src *src,
4824 unsigned type,
4825 enum amdgpu_interrupt_state state)
4826 {
4827 switch (type) {
4828 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4829 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
4830 break;
4831 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
4832 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
4833 break;
4834 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4835 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4836 break;
4837 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4838 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4839 break;
4840 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4841 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4842 break;
4843 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4844 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4845 break;
4846 default:
4847 break;
4848 }
4849 return 0;
4850 }
4851
gfx_v12_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4852 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev,
4853 struct amdgpu_irq_src *source,
4854 struct amdgpu_iv_entry *entry)
4855 {
4856 u32 doorbell_offset = entry->src_data[0];
4857 u8 me_id, pipe_id, queue_id;
4858 struct amdgpu_ring *ring;
4859 int i;
4860
4861 DRM_DEBUG("IH: CP EOP\n");
4862
4863 if (adev->enable_mes && doorbell_offset) {
4864 amdgpu_userq_process_fence_irq(adev, doorbell_offset);
4865 } else {
4866 me_id = (entry->ring_id & 0x0c) >> 2;
4867 pipe_id = (entry->ring_id & 0x03) >> 0;
4868 queue_id = (entry->ring_id & 0x70) >> 4;
4869
4870 switch (me_id) {
4871 case 0:
4872 if (pipe_id == 0)
4873 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4874 else
4875 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
4876 break;
4877 case 1:
4878 case 2:
4879 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4880 ring = &adev->gfx.compute_ring[i];
4881 /* Per-queue interrupt is supported for MEC starting from VI.
4882 * The interrupt can only be enabled/disabled per pipe instead
4883 * of per queue.
4884 */
4885 if ((ring->me == me_id) &&
4886 (ring->pipe == pipe_id) &&
4887 (ring->queue == queue_id))
4888 amdgpu_fence_process(ring);
4889 }
4890 break;
4891 }
4892 }
4893
4894 return 0;
4895 }
4896
gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)4897 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4898 struct amdgpu_irq_src *source,
4899 unsigned int type,
4900 enum amdgpu_interrupt_state state)
4901 {
4902 u32 cp_int_cntl_reg, cp_int_cntl;
4903 int i, j;
4904
4905 switch (state) {
4906 case AMDGPU_IRQ_STATE_DISABLE:
4907 case AMDGPU_IRQ_STATE_ENABLE:
4908 for (i = 0; i < adev->gfx.me.num_me; i++) {
4909 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4910 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4911
4912 if (cp_int_cntl_reg) {
4913 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4914 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4915 PRIV_REG_INT_ENABLE,
4916 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4917 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4918 }
4919 }
4920 }
4921 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
4922 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
4923 /* MECs start at 1 */
4924 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);
4925
4926 if (cp_int_cntl_reg) {
4927 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4928 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4929 PRIV_REG_INT_ENABLE,
4930 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4931 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4932 }
4933 }
4934 }
4935 break;
4936 default:
4937 break;
4938 }
4939
4940 return 0;
4941 }
4942
gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)4943 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev,
4944 struct amdgpu_irq_src *source,
4945 unsigned type,
4946 enum amdgpu_interrupt_state state)
4947 {
4948 u32 cp_int_cntl_reg, cp_int_cntl;
4949 int i, j;
4950
4951 switch (state) {
4952 case AMDGPU_IRQ_STATE_DISABLE:
4953 case AMDGPU_IRQ_STATE_ENABLE:
4954 for (i = 0; i < adev->gfx.me.num_me; i++) {
4955 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4956 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4957
4958 if (cp_int_cntl_reg) {
4959 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4960 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4961 OPCODE_ERROR_INT_ENABLE,
4962 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4963 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4964 }
4965 }
4966 }
4967 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
4968 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
4969 /* MECs start at 1 */
4970 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);
4971
4972 if (cp_int_cntl_reg) {
4973 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4974 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4975 OPCODE_ERROR_INT_ENABLE,
4976 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4977 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4978 }
4979 }
4980 }
4981 break;
4982 default:
4983 break;
4984 }
4985 return 0;
4986 }
4987
gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)4988 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4989 struct amdgpu_irq_src *source,
4990 unsigned int type,
4991 enum amdgpu_interrupt_state state)
4992 {
4993 u32 cp_int_cntl_reg, cp_int_cntl;
4994 int i, j;
4995
4996 switch (state) {
4997 case AMDGPU_IRQ_STATE_DISABLE:
4998 case AMDGPU_IRQ_STATE_ENABLE:
4999 for (i = 0; i < adev->gfx.me.num_me; i++) {
5000 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5001 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
5002
5003 if (cp_int_cntl_reg) {
5004 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5005 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5006 PRIV_INSTR_INT_ENABLE,
5007 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5008 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5009 }
5010 }
5011 }
5012 break;
5013 default:
5014 break;
5015 }
5016
5017 return 0;
5018 }
5019
gfx_v12_0_handle_priv_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)5020 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev,
5021 struct amdgpu_iv_entry *entry)
5022 {
5023 u8 me_id, pipe_id, queue_id;
5024 struct amdgpu_ring *ring;
5025 int i;
5026
5027 me_id = (entry->ring_id & 0x0c) >> 2;
5028 pipe_id = (entry->ring_id & 0x03) >> 0;
5029 queue_id = (entry->ring_id & 0x70) >> 4;
5030
5031 if (!adev->gfx.disable_kq) {
5032 switch (me_id) {
5033 case 0:
5034 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5035 ring = &adev->gfx.gfx_ring[i];
5036 if (ring->me == me_id && ring->pipe == pipe_id &&
5037 ring->queue == queue_id)
5038 drm_sched_fault(&ring->sched);
5039 }
5040 break;
5041 case 1:
5042 case 2:
5043 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5044 ring = &adev->gfx.compute_ring[i];
5045 if (ring->me == me_id && ring->pipe == pipe_id &&
5046 ring->queue == queue_id)
5047 drm_sched_fault(&ring->sched);
5048 }
5049 break;
5050 default:
5051 BUG();
5052 break;
5053 }
5054 }
5055 }
5056
gfx_v12_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5057 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev,
5058 struct amdgpu_irq_src *source,
5059 struct amdgpu_iv_entry *entry)
5060 {
5061 DRM_ERROR("Illegal register access in command stream\n");
5062 gfx_v12_0_handle_priv_fault(adev, entry);
5063 return 0;
5064 }
5065
gfx_v12_0_bad_op_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5066 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev,
5067 struct amdgpu_irq_src *source,
5068 struct amdgpu_iv_entry *entry)
5069 {
5070 DRM_ERROR("Illegal opcode in command stream\n");
5071 gfx_v12_0_handle_priv_fault(adev, entry);
5072 return 0;
5073 }
5074
gfx_v12_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5075 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev,
5076 struct amdgpu_irq_src *source,
5077 struct amdgpu_iv_entry *entry)
5078 {
5079 DRM_ERROR("Illegal instruction in command stream\n");
5080 gfx_v12_0_handle_priv_fault(adev, entry);
5081 return 0;
5082 }
5083
gfx_v12_0_emit_mem_sync(struct amdgpu_ring * ring)5084 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring)
5085 {
5086 const unsigned int gcr_cntl =
5087 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
5088 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
5089 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
5090 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
5091 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
5092 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
5093 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
5094 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
5095
5096 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
5097 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
5098 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
5099 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
5100 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
5101 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
5102 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
5103 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
5104 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
5105 }
5106
gfx_v12_ring_insert_nop(struct amdgpu_ring * ring,uint32_t num_nop)5107 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
5108 {
5109 /* Header itself is a NOP packet */
5110 if (num_nop == 1) {
5111 amdgpu_ring_write(ring, ring->funcs->nop);
5112 return;
5113 }
5114
5115 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/
5116 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));
5117
5118 /* Header is at index 0, followed by num_nops - 1 NOP packet's */
5119 amdgpu_ring_insert_nop(ring, num_nop - 1);
5120 }
5121
gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring * ring)5122 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
5123 {
5124 /* Emit the cleaner shader */
5125 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
5126 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */
5127 }
5128
gfx_v12_ip_print(struct amdgpu_ip_block * ip_block,struct drm_printer * p)5129 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
5130 {
5131 struct amdgpu_device *adev = ip_block->adev;
5132 uint32_t i, j, k, reg, index = 0;
5133 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
5134
5135 if (!adev->gfx.ip_dump_core)
5136 return;
5137
5138 for (i = 0; i < reg_count; i++)
5139 drm_printf(p, "%-50s \t 0x%08x\n",
5140 gc_reg_list_12_0[i].reg_name,
5141 adev->gfx.ip_dump_core[i]);
5142
5143 /* print compute queue registers for all instances */
5144 if (!adev->gfx.ip_dump_compute_queues)
5145 return;
5146
5147 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
5148 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
5149 adev->gfx.mec.num_mec,
5150 adev->gfx.mec.num_pipe_per_mec,
5151 adev->gfx.mec.num_queue_per_pipe);
5152
5153 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
5154 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
5155 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
5156 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
5157 for (reg = 0; reg < reg_count; reg++) {
5158 drm_printf(p, "%-50s \t 0x%08x\n",
5159 gc_cp_reg_list_12[reg].reg_name,
5160 adev->gfx.ip_dump_compute_queues[index + reg]);
5161 }
5162 index += reg_count;
5163 }
5164 }
5165 }
5166
5167 /* print gfx queue registers for all instances */
5168 if (!adev->gfx.ip_dump_gfx_queues)
5169 return;
5170
5171 index = 0;
5172 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
5173 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
5174 adev->gfx.me.num_me,
5175 adev->gfx.me.num_pipe_per_me,
5176 adev->gfx.me.num_queue_per_pipe);
5177
5178 for (i = 0; i < adev->gfx.me.num_me; i++) {
5179 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5180 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
5181 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
5182 for (reg = 0; reg < reg_count; reg++) {
5183 drm_printf(p, "%-50s \t 0x%08x\n",
5184 gc_gfx_queue_reg_list_12[reg].reg_name,
5185 adev->gfx.ip_dump_gfx_queues[index + reg]);
5186 }
5187 index += reg_count;
5188 }
5189 }
5190 }
5191 }
5192
gfx_v12_ip_dump(struct amdgpu_ip_block * ip_block)5193 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block)
5194 {
5195 struct amdgpu_device *adev = ip_block->adev;
5196 uint32_t i, j, k, reg, index = 0;
5197 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
5198
5199 if (!adev->gfx.ip_dump_core)
5200 return;
5201
5202 amdgpu_gfx_off_ctrl(adev, false);
5203 for (i = 0; i < reg_count; i++)
5204 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i]));
5205 amdgpu_gfx_off_ctrl(adev, true);
5206
5207 /* dump compute queue registers for all instances */
5208 if (!adev->gfx.ip_dump_compute_queues)
5209 return;
5210
5211 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
5212 amdgpu_gfx_off_ctrl(adev, false);
5213 mutex_lock(&adev->srbm_mutex);
5214 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
5215 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
5216 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
5217 /* ME0 is for GFX so start from 1 for CP */
5218 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
5219 for (reg = 0; reg < reg_count; reg++) {
5220 adev->gfx.ip_dump_compute_queues[index + reg] =
5221 RREG32(SOC15_REG_ENTRY_OFFSET(
5222 gc_cp_reg_list_12[reg]));
5223 }
5224 index += reg_count;
5225 }
5226 }
5227 }
5228 soc24_grbm_select(adev, 0, 0, 0, 0);
5229 mutex_unlock(&adev->srbm_mutex);
5230 amdgpu_gfx_off_ctrl(adev, true);
5231
5232 /* dump gfx queue registers for all instances */
5233 if (!adev->gfx.ip_dump_gfx_queues)
5234 return;
5235
5236 index = 0;
5237 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
5238 amdgpu_gfx_off_ctrl(adev, false);
5239 mutex_lock(&adev->srbm_mutex);
5240 for (i = 0; i < adev->gfx.me.num_me; i++) {
5241 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5242 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
5243 soc24_grbm_select(adev, i, j, k, 0);
5244
5245 for (reg = 0; reg < reg_count; reg++) {
5246 adev->gfx.ip_dump_gfx_queues[index + reg] =
5247 RREG32(SOC15_REG_ENTRY_OFFSET(
5248 gc_gfx_queue_reg_list_12[reg]));
5249 }
5250 index += reg_count;
5251 }
5252 }
5253 }
5254 soc24_grbm_select(adev, 0, 0, 0, 0);
5255 mutex_unlock(&adev->srbm_mutex);
5256 amdgpu_gfx_off_ctrl(adev, true);
5257 }
5258
gfx_v12_pipe_reset_support(struct amdgpu_device * adev)5259 static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev)
5260 {
5261 /* Disable the pipe reset until the CPFW fully support it.*/
5262 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n");
5263 return false;
5264 }
5265
gfx_v12_reset_gfx_pipe(struct amdgpu_ring * ring)5266 static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring)
5267 {
5268 struct amdgpu_device *adev = ring->adev;
5269 uint32_t reset_pipe = 0, clean_pipe = 0;
5270 int r;
5271
5272 if (!gfx_v12_pipe_reset_support(adev))
5273 return -EOPNOTSUPP;
5274
5275 gfx_v12_0_set_safe_mode(adev, 0);
5276 mutex_lock(&adev->srbm_mutex);
5277 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5278
5279 switch (ring->pipe) {
5280 case 0:
5281 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5282 PFP_PIPE0_RESET, 1);
5283 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5284 ME_PIPE0_RESET, 1);
5285 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5286 PFP_PIPE0_RESET, 0);
5287 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5288 ME_PIPE0_RESET, 0);
5289 break;
5290 case 1:
5291 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5292 PFP_PIPE1_RESET, 1);
5293 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5294 ME_PIPE1_RESET, 1);
5295 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5296 PFP_PIPE1_RESET, 0);
5297 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5298 ME_PIPE1_RESET, 0);
5299 break;
5300 default:
5301 break;
5302 }
5303
5304 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe);
5305 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe);
5306
5307 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -
5308 RS64_FW_UC_START_ADDR_LO;
5309 soc24_grbm_select(adev, 0, 0, 0, 0);
5310 mutex_unlock(&adev->srbm_mutex);
5311 gfx_v12_0_unset_safe_mode(adev, 0);
5312
5313 dev_info(adev->dev, "The ring %s pipe reset: %s\n", ring->name,
5314 r == 0 ? "successfully" : "failed");
5315 /* Sometimes the ME start pc counter can't cache correctly, so the
5316 * PC check only as a reference and pipe reset result rely on the
5317 * later ring test.
5318 */
5319 return 0;
5320 }
5321
gfx_v12_0_reset_kgq(struct amdgpu_ring * ring,unsigned int vmid,struct amdgpu_fence * timedout_fence)5322 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring,
5323 unsigned int vmid,
5324 struct amdgpu_fence *timedout_fence)
5325 {
5326 struct amdgpu_device *adev = ring->adev;
5327 bool use_mmio = false;
5328 int r;
5329
5330 amdgpu_ring_reset_helper_begin(ring, timedout_fence);
5331
5332 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0);
5333 if (r) {
5334 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r);
5335 r = gfx_v12_reset_gfx_pipe(ring);
5336 if (r)
5337 return r;
5338 }
5339
5340 if (use_mmio) {
5341 r = gfx_v12_0_kgq_init_queue(ring, true);
5342 if (r) {
5343 dev_err(adev->dev, "failed to init kgq\n");
5344 return r;
5345 }
5346
5347 r = amdgpu_mes_map_legacy_queue(adev, ring, 0);
5348 if (r) {
5349 dev_err(adev->dev, "failed to remap kgq\n");
5350 return r;
5351 }
5352 }
5353
5354 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
5355 }
5356
gfx_v12_0_reset_compute_pipe(struct amdgpu_ring * ring)5357 static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring)
5358 {
5359 struct amdgpu_device *adev = ring->adev;
5360 uint32_t reset_pipe = 0, clean_pipe = 0;
5361 int r = 0;
5362
5363 if (!gfx_v12_pipe_reset_support(adev))
5364 return -EOPNOTSUPP;
5365
5366 gfx_v12_0_set_safe_mode(adev, 0);
5367 mutex_lock(&adev->srbm_mutex);
5368 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5369
5370 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
5371 clean_pipe = reset_pipe;
5372
5373 if (adev->gfx.rs64_enable) {
5374 switch (ring->pipe) {
5375 case 0:
5376 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5377 MEC_PIPE0_RESET, 1);
5378 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5379 MEC_PIPE0_RESET, 0);
5380 break;
5381 case 1:
5382 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5383 MEC_PIPE1_RESET, 1);
5384 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5385 MEC_PIPE1_RESET, 0);
5386 break;
5387 case 2:
5388 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5389 MEC_PIPE2_RESET, 1);
5390 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5391 MEC_PIPE2_RESET, 0);
5392 break;
5393 case 3:
5394 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5395 MEC_PIPE3_RESET, 1);
5396 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5397 MEC_PIPE3_RESET, 0);
5398 break;
5399 default:
5400 break;
5401 }
5402 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe);
5403 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe);
5404 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) -
5405 RS64_FW_UC_START_ADDR_LO;
5406 } else {
5407 switch (ring->pipe) {
5408 case 0:
5409 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,
5410 MEC_ME1_PIPE0_RESET, 1);
5411 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,
5412 MEC_ME1_PIPE0_RESET, 0);
5413 break;
5414 case 1:
5415 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,
5416 MEC_ME1_PIPE1_RESET, 1);
5417 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,
5418 MEC_ME1_PIPE1_RESET, 0);
5419 break;
5420 default:
5421 break;
5422 }
5423 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe);
5424 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe);
5425 /* Doesn't find the F32 MEC instruction pointer register, and suppose
5426 * the driver won't run into the F32 mode.
5427 */
5428 }
5429
5430 soc24_grbm_select(adev, 0, 0, 0, 0);
5431 mutex_unlock(&adev->srbm_mutex);
5432 gfx_v12_0_unset_safe_mode(adev, 0);
5433
5434 dev_info(adev->dev, "The ring %s pipe resets: %s\n", ring->name,
5435 r == 0 ? "successfully" : "failed");
5436 /* Need the ring test to verify the pipe reset result.*/
5437 return 0;
5438 }
5439
gfx_v12_0_reset_kcq(struct amdgpu_ring * ring,unsigned int vmid,struct amdgpu_fence * timedout_fence)5440 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring,
5441 unsigned int vmid,
5442 struct amdgpu_fence *timedout_fence)
5443 {
5444 struct amdgpu_device *adev = ring->adev;
5445 int r;
5446
5447 amdgpu_ring_reset_helper_begin(ring, timedout_fence);
5448
5449 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true, 0);
5450 if (r) {
5451 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r);
5452 r = gfx_v12_0_reset_compute_pipe(ring);
5453 if (r)
5454 return r;
5455 }
5456
5457 r = gfx_v12_0_kcq_init_queue(ring, true);
5458 if (r) {
5459 dev_err(adev->dev, "failed to init kcq\n");
5460 return r;
5461 }
5462 r = amdgpu_mes_map_legacy_queue(adev, ring, 0);
5463 if (r) {
5464 dev_err(adev->dev, "failed to remap kcq\n");
5465 return r;
5466 }
5467
5468 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
5469 }
5470
gfx_v12_0_ring_begin_use(struct amdgpu_ring * ring)5471 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring)
5472 {
5473 amdgpu_gfx_profile_ring_begin_use(ring);
5474
5475 amdgpu_gfx_enforce_isolation_ring_begin_use(ring);
5476 }
5477
gfx_v12_0_ring_end_use(struct amdgpu_ring * ring)5478 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring)
5479 {
5480 amdgpu_gfx_profile_ring_end_use(ring);
5481
5482 amdgpu_gfx_enforce_isolation_ring_end_use(ring);
5483 }
5484
5485 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = {
5486 .name = "gfx_v12_0",
5487 .early_init = gfx_v12_0_early_init,
5488 .late_init = gfx_v12_0_late_init,
5489 .sw_init = gfx_v12_0_sw_init,
5490 .sw_fini = gfx_v12_0_sw_fini,
5491 .hw_init = gfx_v12_0_hw_init,
5492 .hw_fini = gfx_v12_0_hw_fini,
5493 .suspend = gfx_v12_0_suspend,
5494 .resume = gfx_v12_0_resume,
5495 .is_idle = gfx_v12_0_is_idle,
5496 .wait_for_idle = gfx_v12_0_wait_for_idle,
5497 .set_clockgating_state = gfx_v12_0_set_clockgating_state,
5498 .set_powergating_state = gfx_v12_0_set_powergating_state,
5499 .get_clockgating_state = gfx_v12_0_get_clockgating_state,
5500 .dump_ip_state = gfx_v12_ip_dump,
5501 .print_ip_state = gfx_v12_ip_print,
5502 };
5503
5504 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = {
5505 .type = AMDGPU_RING_TYPE_GFX,
5506 .align_mask = 0xff,
5507 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5508 .support_64bit_ptrs = true,
5509 .secure_submission_supported = true,
5510 .get_rptr = gfx_v12_0_ring_get_rptr_gfx,
5511 .get_wptr = gfx_v12_0_ring_get_wptr_gfx,
5512 .set_wptr = gfx_v12_0_ring_set_wptr_gfx,
5513 .emit_frame_size = /* totally 242 maximum if 16 IBs */
5514 5 + /* COND_EXEC */
5515 7 + /* PIPELINE_SYNC */
5516 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5517 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5518 2 + /* VM_FLUSH */
5519 8 + /* FENCE for VM_FLUSH */
5520 5 + /* COND_EXEC */
5521 7 + /* HDP_flush */
5522 4 + /* VGT_flush */
5523 31 + /* DE_META */
5524 3 + /* CNTX_CTRL */
5525 5 + /* HDP_INVL */
5526 8 + 8 + /* FENCE x2 */
5527 8 + /* gfx_v12_0_emit_mem_sync */
5528 2, /* gfx_v12_0_ring_emit_cleaner_shader */
5529 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */
5530 .emit_ib = gfx_v12_0_ring_emit_ib_gfx,
5531 .emit_fence = gfx_v12_0_ring_emit_fence,
5532 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync,
5533 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush,
5534 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,
5535 .test_ring = gfx_v12_0_ring_test_ring,
5536 .test_ib = gfx_v12_0_ring_test_ib,
5537 .insert_nop = gfx_v12_ring_insert_nop,
5538 .pad_ib = amdgpu_ring_generic_pad_ib,
5539 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl,
5540 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec,
5541 .preempt_ib = gfx_v12_0_ring_preempt_ib,
5542 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5543 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5544 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5545 .emit_mem_sync = gfx_v12_0_emit_mem_sync,
5546 .reset = gfx_v12_0_reset_kgq,
5547 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
5548 .begin_use = gfx_v12_0_ring_begin_use,
5549 .end_use = gfx_v12_0_ring_end_use,
5550 };
5551
5552 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = {
5553 .type = AMDGPU_RING_TYPE_COMPUTE,
5554 .align_mask = 0xff,
5555 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5556 .support_64bit_ptrs = true,
5557 .get_rptr = gfx_v12_0_ring_get_rptr_compute,
5558 .get_wptr = gfx_v12_0_ring_get_wptr_compute,
5559 .set_wptr = gfx_v12_0_ring_set_wptr_compute,
5560 .emit_frame_size =
5561 7 + /* gfx_v12_0_ring_emit_hdp_flush */
5562 5 + /* hdp invalidate */
5563 7 + /* gfx_v12_0_ring_emit_pipeline_sync */
5564 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5565 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5566 2 + /* gfx_v12_0_ring_emit_vm_flush */
5567 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */
5568 8 + /* gfx_v12_0_emit_mem_sync */
5569 2, /* gfx_v12_0_ring_emit_cleaner_shader */
5570 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */
5571 .emit_ib = gfx_v12_0_ring_emit_ib_compute,
5572 .emit_fence = gfx_v12_0_ring_emit_fence,
5573 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync,
5574 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush,
5575 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,
5576 .test_ring = gfx_v12_0_ring_test_ring,
5577 .test_ib = gfx_v12_0_ring_test_ib,
5578 .insert_nop = gfx_v12_ring_insert_nop,
5579 .pad_ib = amdgpu_ring_generic_pad_ib,
5580 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5581 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5582 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5583 .emit_mem_sync = gfx_v12_0_emit_mem_sync,
5584 .reset = gfx_v12_0_reset_kcq,
5585 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
5586 .begin_use = gfx_v12_0_ring_begin_use,
5587 .end_use = gfx_v12_0_ring_end_use,
5588 };
5589
5590 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = {
5591 .type = AMDGPU_RING_TYPE_KIQ,
5592 .align_mask = 0xff,
5593 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5594 .support_64bit_ptrs = true,
5595 .get_rptr = gfx_v12_0_ring_get_rptr_compute,
5596 .get_wptr = gfx_v12_0_ring_get_wptr_compute,
5597 .set_wptr = gfx_v12_0_ring_set_wptr_compute,
5598 .emit_frame_size =
5599 7 + /* gfx_v12_0_ring_emit_hdp_flush */
5600 5 + /*hdp invalidate */
5601 7 + /* gfx_v12_0_ring_emit_pipeline_sync */
5602 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5603 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5604 2 + /* gfx_v12_0_ring_emit_vm_flush */
5605 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */
5606 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */
5607 .emit_ib = gfx_v12_0_ring_emit_ib_compute,
5608 .emit_fence = gfx_v12_0_ring_emit_fence_kiq,
5609 .test_ring = gfx_v12_0_ring_test_ring,
5610 .test_ib = gfx_v12_0_ring_test_ib,
5611 .insert_nop = amdgpu_ring_insert_nop,
5612 .pad_ib = amdgpu_ring_generic_pad_ib,
5613 .emit_rreg = gfx_v12_0_ring_emit_rreg,
5614 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5615 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5616 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5617 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,
5618 };
5619
gfx_v12_0_set_ring_funcs(struct amdgpu_device * adev)5620 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev)
5621 {
5622 int i;
5623
5624 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq;
5625
5626 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5627 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx;
5628
5629 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5630 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute;
5631 }
5632
5633 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = {
5634 .set = gfx_v12_0_set_eop_interrupt_state,
5635 .process = gfx_v12_0_eop_irq,
5636 };
5637
5638 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = {
5639 .set = gfx_v12_0_set_priv_reg_fault_state,
5640 .process = gfx_v12_0_priv_reg_irq,
5641 };
5642
5643 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = {
5644 .set = gfx_v12_0_set_bad_op_fault_state,
5645 .process = gfx_v12_0_bad_op_irq,
5646 };
5647
5648 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = {
5649 .set = gfx_v12_0_set_priv_inst_fault_state,
5650 .process = gfx_v12_0_priv_inst_irq,
5651 };
5652
gfx_v12_0_set_irq_funcs(struct amdgpu_device * adev)5653 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev)
5654 {
5655 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5656 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs;
5657
5658 adev->gfx.priv_reg_irq.num_types = 1;
5659 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs;
5660
5661 adev->gfx.bad_op_irq.num_types = 1;
5662 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs;
5663
5664 adev->gfx.priv_inst_irq.num_types = 1;
5665 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs;
5666 }
5667
gfx_v12_0_set_imu_funcs(struct amdgpu_device * adev)5668 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev)
5669 {
5670 if (adev->flags & AMD_IS_APU)
5671 adev->gfx.imu.mode = MISSION_MODE;
5672 else
5673 adev->gfx.imu.mode = DEBUG_MODE;
5674
5675 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs;
5676 }
5677
gfx_v12_0_set_rlc_funcs(struct amdgpu_device * adev)5678 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev)
5679 {
5680 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs;
5681 }
5682
gfx_v12_0_set_mqd_funcs(struct amdgpu_device * adev)5683 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev)
5684 {
5685 /* set gfx eng mqd */
5686 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
5687 sizeof(struct v12_gfx_mqd);
5688 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
5689 gfx_v12_0_gfx_mqd_init;
5690 /* set compute eng mqd */
5691 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
5692 sizeof(struct v12_compute_mqd);
5693 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
5694 gfx_v12_0_compute_mqd_init;
5695 }
5696
gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device * adev,u32 bitmap)5697 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
5698 u32 bitmap)
5699 {
5700 u32 data;
5701
5702 if (!bitmap)
5703 return;
5704
5705 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5706 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5707
5708 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
5709 }
5710
gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device * adev)5711 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
5712 {
5713 u32 data, wgp_bitmask;
5714 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
5715 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);
5716
5717 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5718 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5719
5720 wgp_bitmask =
5721 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
5722
5723 return (~data) & wgp_bitmask;
5724 }
5725
gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device * adev)5726 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
5727 {
5728 u32 wgp_idx, wgp_active_bitmap;
5729 u32 cu_bitmap_per_wgp, cu_active_bitmap;
5730
5731 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev);
5732 cu_active_bitmap = 0;
5733
5734 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
5735 /* if there is one WGP enabled, it means 2 CUs will be enabled */
5736 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
5737 if (wgp_active_bitmap & (1 << wgp_idx))
5738 cu_active_bitmap |= cu_bitmap_per_wgp;
5739 }
5740
5741 return cu_active_bitmap;
5742 }
5743
gfx_v12_0_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)5744 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,
5745 struct amdgpu_cu_info *cu_info)
5746 {
5747 int i, j, k, counter, active_cu_number = 0;
5748 u32 mask, bitmap;
5749 unsigned disable_masks[8 * 2];
5750
5751 if (!adev || !cu_info)
5752 return -EINVAL;
5753
5754 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2);
5755
5756 mutex_lock(&adev->grbm_idx_mutex);
5757 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5758 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5759 bitmap = i * adev->gfx.config.max_sh_per_se + j;
5760 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1))
5761 continue;
5762 mask = 1;
5763 counter = 0;
5764 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5765 if (i < 8 && j < 2)
5766 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(
5767 adev, disable_masks[i * 2 + j]);
5768 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev);
5769
5770 /**
5771 * GFX12 could support more than 4 SEs, while the bitmap
5772 * in cu_info struct is 4x4 and ioctl interface struct
5773 * drm_amdgpu_info_device should keep stable.
5774 * So we use last two columns of bitmap to store cu mask for
5775 * SEs 4 to 7, the layout of the bitmap is as below:
5776 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}
5777 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}
5778 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}
5779 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}
5780 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}
5781 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]}
5782 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]}
5783 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]}
5784 */
5785 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap;
5786
5787 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5788 if (bitmap & mask)
5789 counter++;
5790
5791 mask <<= 1;
5792 }
5793 active_cu_number += counter;
5794 }
5795 }
5796 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5797 mutex_unlock(&adev->grbm_idx_mutex);
5798
5799 cu_info->number = active_cu_number;
5800 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5801
5802 return 0;
5803 }
5804
5805 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = {
5806 .type = AMD_IP_BLOCK_TYPE_GFX,
5807 .major = 12,
5808 .minor = 0,
5809 .rev = 0,
5810 .funcs = &gfx_v12_0_ip_funcs,
5811 };
5812