1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/delay.h>
24 #include <linux/kernel.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include "amdgpu.h"
29 #include "amdgpu_gfx.h"
30 #include "amdgpu_psp.h"
31 #include "amdgpu_smu.h"
32 #include "imu_v12_0.h"
33 #include "soc24.h"
34 #include "nvd.h"
35
36 #include "gc/gc_12_0_0_offset.h"
37 #include "gc/gc_12_0_0_sh_mask.h"
38 #include "soc24_enum.h"
39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h"
40
41 #include "soc15.h"
42 #include "clearstate_gfx12.h"
43 #include "v12_structs.h"
44 #include "gfx_v12_0.h"
45 #include "nbif_v6_3_1.h"
46 #include "mes_v12_0.h"
47 #include "mes_userqueue.h"
48 #include "amdgpu_userq_fence.h"
49
50 #define GFX12_NUM_GFX_RINGS 1
51 #define GFX12_MEC_HPD_SIZE 2048
52
53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
54
55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100
56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000
57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01
59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000
60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000
61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000
62
63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006
64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100
66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509
67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000
69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501
70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000
71
72
73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin");
74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin");
75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin");
76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin");
77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin");
78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin");
79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin");
80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin");
81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin");
82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc_kicker.bin");
83 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin");
84
85 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = {
86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
88 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
91 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
94 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
99 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
101 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
115 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
116 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
117 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
118 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
120 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
121 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
122 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
125 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32),
128 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
133 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
134 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),
137 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),
138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),
139 /* cp header registers */
140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
147 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
148 /* SE status registers */
149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
152 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)
153 };
154
155 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = {
156 /* compute registers */
157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),
196 /* cp header registers */
197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
204 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
205 };
206
207 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = {
208 /* gfx queue registers */
209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
229 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
233 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
234 /* cp header registers */
235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
242 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
250 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
251 };
252
253 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = {
254 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f),
255 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000),
256 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020)
257 };
258
259 static const struct soc15_reg_golden golden_settings_gc_12_0[] = {
260 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000),
261 };
262
263 #define DEFAULT_SH_MEM_CONFIG \
264 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
265 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
266 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
267
268 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev);
269 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev);
270 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev);
271 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev);
272 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev);
273 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev);
274 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,
275 struct amdgpu_cu_info *cu_info);
276 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev);
277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
278 u32 sh_num, u32 instance, int xcc_id);
279 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
280
281 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
282 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
283 uint32_t val);
284 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
285 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
286 uint16_t pasid, uint32_t flush_type,
287 bool all_hub, uint8_t dst_sel);
288 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
289 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
290 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
291 bool enable);
292
gfx_v12_0_kiq_set_resources(struct amdgpu_ring * kiq_ring,uint64_t queue_mask)293 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
294 uint64_t queue_mask)
295 {
296 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
297 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
298 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
299 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
300 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
301 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
302 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
303 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
304 amdgpu_ring_write(kiq_ring, 0);
305 }
306
gfx_v12_0_kiq_map_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring)307 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring,
308 struct amdgpu_ring *ring)
309 {
310 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
311 uint64_t wptr_addr = ring->wptr_gpu_addr;
312 uint32_t me = 0, eng_sel = 0;
313
314 switch (ring->funcs->type) {
315 case AMDGPU_RING_TYPE_COMPUTE:
316 me = 1;
317 eng_sel = 0;
318 break;
319 case AMDGPU_RING_TYPE_GFX:
320 me = 0;
321 eng_sel = 4;
322 break;
323 case AMDGPU_RING_TYPE_MES:
324 me = 2;
325 eng_sel = 5;
326 break;
327 default:
328 WARN_ON(1);
329 }
330
331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
332 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
333 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
334 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
335 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
336 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
337 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
338 PACKET3_MAP_QUEUES_ME((me)) |
339 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
340 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
341 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
342 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
343 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
344 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
345 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
346 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
347 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
348 }
349
gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq)350 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
351 struct amdgpu_ring *ring,
352 enum amdgpu_unmap_queues_action action,
353 u64 gpu_addr, u64 seq)
354 {
355 struct amdgpu_device *adev = kiq_ring->adev;
356 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
357
358 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
359 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
360 return;
361 }
362
363 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
364 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
365 PACKET3_UNMAP_QUEUES_ACTION(action) |
366 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
367 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
368 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
369 amdgpu_ring_write(kiq_ring,
370 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
371
372 if (action == PREEMPT_QUEUES_NO_UNMAP) {
373 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
374 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
375 amdgpu_ring_write(kiq_ring, seq);
376 } else {
377 amdgpu_ring_write(kiq_ring, 0);
378 amdgpu_ring_write(kiq_ring, 0);
379 amdgpu_ring_write(kiq_ring, 0);
380 }
381 }
382
gfx_v12_0_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq)383 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring,
384 struct amdgpu_ring *ring,
385 u64 addr, u64 seq)
386 {
387 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
388
389 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
390 amdgpu_ring_write(kiq_ring,
391 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
392 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
393 PACKET3_QUERY_STATUS_COMMAND(2));
394 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
395 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
396 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
397 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
398 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
399 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
400 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
401 }
402
gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub)403 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
404 uint16_t pasid,
405 uint32_t flush_type,
406 bool all_hub)
407 {
408 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
409 }
410
411 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = {
412 .kiq_set_resources = gfx_v12_0_kiq_set_resources,
413 .kiq_map_queues = gfx_v12_0_kiq_map_queues,
414 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues,
415 .kiq_query_status = gfx_v12_0_kiq_query_status,
416 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs,
417 .set_resources_size = 8,
418 .map_queues_size = 7,
419 .unmap_queues_size = 6,
420 .query_status_size = 7,
421 .invalidate_tlbs_size = 2,
422 };
423
gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device * adev)424 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
425 {
426 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs;
427 }
428
gfx_v12_0_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)429 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
430 int mem_space, int opt, uint32_t addr0,
431 uint32_t addr1, uint32_t ref,
432 uint32_t mask, uint32_t inv)
433 {
434 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
435 amdgpu_ring_write(ring,
436 /* memory (1) or register (0) */
437 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
438 WAIT_REG_MEM_OPERATION(opt) | /* wait */
439 WAIT_REG_MEM_FUNCTION(3) | /* equal */
440 WAIT_REG_MEM_ENGINE(eng_sel)));
441
442 if (mem_space)
443 BUG_ON(addr0 & 0x3); /* Dword align */
444 amdgpu_ring_write(ring, addr0);
445 amdgpu_ring_write(ring, addr1);
446 amdgpu_ring_write(ring, ref);
447 amdgpu_ring_write(ring, mask);
448 amdgpu_ring_write(ring, inv); /* poll interval */
449 }
450
gfx_v12_0_ring_test_ring(struct amdgpu_ring * ring)451 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring)
452 {
453 struct amdgpu_device *adev = ring->adev;
454 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
455 uint32_t tmp = 0;
456 unsigned i;
457 int r;
458
459 WREG32(scratch, 0xCAFEDEAD);
460 r = amdgpu_ring_alloc(ring, 5);
461 if (r) {
462 dev_err(adev->dev,
463 "amdgpu: cp failed to lock ring %d (%d).\n",
464 ring->idx, r);
465 return r;
466 }
467
468 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {
469 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
470 } else {
471 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
472 amdgpu_ring_write(ring, scratch -
473 PACKET3_SET_UCONFIG_REG_START);
474 amdgpu_ring_write(ring, 0xDEADBEEF);
475 }
476 amdgpu_ring_commit(ring);
477
478 for (i = 0; i < adev->usec_timeout; i++) {
479 tmp = RREG32(scratch);
480 if (tmp == 0xDEADBEEF)
481 break;
482 if (amdgpu_emu_mode == 1)
483 msleep(1);
484 else
485 udelay(1);
486 }
487
488 if (i >= adev->usec_timeout)
489 r = -ETIMEDOUT;
490 return r;
491 }
492
gfx_v12_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)493 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
494 {
495 struct amdgpu_device *adev = ring->adev;
496 struct amdgpu_ib ib;
497 struct dma_fence *f = NULL;
498 unsigned index;
499 uint64_t gpu_addr;
500 volatile uint32_t *cpu_ptr;
501 long r;
502
503 /* MES KIQ fw hasn't indirect buffer support for now */
504 if (adev->enable_mes_kiq &&
505 ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
506 return 0;
507
508 memset(&ib, 0, sizeof(ib));
509
510 r = amdgpu_device_wb_get(adev, &index);
511 if (r)
512 return r;
513
514 gpu_addr = adev->wb.gpu_addr + (index * 4);
515 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
516 cpu_ptr = &adev->wb.wb[index];
517
518 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
519 if (r) {
520 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r);
521 goto err1;
522 }
523
524 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
526 ib.ptr[2] = lower_32_bits(gpu_addr);
527 ib.ptr[3] = upper_32_bits(gpu_addr);
528 ib.ptr[4] = 0xDEADBEEF;
529 ib.length_dw = 5;
530
531 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
532 if (r)
533 goto err2;
534
535 r = dma_fence_wait_timeout(f, false, timeout);
536 if (r == 0) {
537 r = -ETIMEDOUT;
538 goto err2;
539 } else if (r < 0) {
540 goto err2;
541 }
542
543 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
544 r = 0;
545 else
546 r = -EINVAL;
547 err2:
548 amdgpu_ib_free(&ib, NULL);
549 dma_fence_put(f);
550 err1:
551 amdgpu_device_wb_free(adev, index);
552 return r;
553 }
554
gfx_v12_0_free_microcode(struct amdgpu_device * adev)555 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev)
556 {
557 amdgpu_ucode_release(&adev->gfx.pfp_fw);
558 amdgpu_ucode_release(&adev->gfx.me_fw);
559 amdgpu_ucode_release(&adev->gfx.rlc_fw);
560 amdgpu_ucode_release(&adev->gfx.mec_fw);
561
562 kfree(adev->gfx.rlc.register_list_format);
563 }
564
gfx_v12_0_init_toc_microcode(struct amdgpu_device * adev,const char * ucode_prefix)565 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix)
566 {
567 const struct psp_firmware_header_v1_0 *toc_hdr;
568 int err = 0;
569
570 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw,
571 AMDGPU_UCODE_REQUIRED,
572 "amdgpu/%s_toc.bin", ucode_prefix);
573 if (err)
574 goto out;
575
576 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
577 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
578 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
579 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
580 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
581 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
582 return 0;
583 out:
584 amdgpu_ucode_release(&adev->psp.toc_fw);
585 return err;
586 }
587
gfx_v12_0_init_microcode(struct amdgpu_device * adev)588 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev)
589 {
590 char ucode_prefix[30];
591 int err;
592 const struct rlc_firmware_header_v2_0 *rlc_hdr;
593 uint16_t version_major;
594 uint16_t version_minor;
595
596 DRM_DEBUG("\n");
597
598 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
599
600 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
601 AMDGPU_UCODE_REQUIRED,
602 "amdgpu/%s_pfp.bin", ucode_prefix);
603 if (err)
604 goto out;
605 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);
606 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
607
608 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
609 AMDGPU_UCODE_REQUIRED,
610 "amdgpu/%s_me.bin", ucode_prefix);
611 if (err)
612 goto out;
613 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);
614 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
615
616 if (!amdgpu_sriov_vf(adev)) {
617 if (amdgpu_is_kicker_fw(adev))
618 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
619 AMDGPU_UCODE_REQUIRED,
620 "amdgpu/%s_rlc_kicker.bin", ucode_prefix);
621 else
622 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
623 AMDGPU_UCODE_REQUIRED,
624 "amdgpu/%s_rlc.bin", ucode_prefix);
625 if (err)
626 goto out;
627 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
628 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
629 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
630 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
631 if (err)
632 goto out;
633 }
634
635 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
636 AMDGPU_UCODE_REQUIRED,
637 "amdgpu/%s_mec.bin", ucode_prefix);
638 if (err)
639 goto out;
640 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);
641 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);
642 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);
643
644 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
645 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix);
646
647 /* only one MEC for gfx 12 */
648 adev->gfx.mec2_fw = NULL;
649
650 if (adev->gfx.imu.funcs) {
651 if (adev->gfx.imu.funcs->init_microcode) {
652 err = adev->gfx.imu.funcs->init_microcode(adev);
653 if (err)
654 dev_err(adev->dev, "Failed to load imu firmware!\n");
655 }
656 }
657
658 out:
659 if (err) {
660 amdgpu_ucode_release(&adev->gfx.pfp_fw);
661 amdgpu_ucode_release(&adev->gfx.me_fw);
662 amdgpu_ucode_release(&adev->gfx.rlc_fw);
663 amdgpu_ucode_release(&adev->gfx.mec_fw);
664 }
665
666 return err;
667 }
668
gfx_v12_0_get_csb_size(struct amdgpu_device * adev)669 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev)
670 {
671 u32 count = 0;
672 const struct cs_section_def *sect = NULL;
673 const struct cs_extent_def *ext = NULL;
674
675 count += 1;
676
677 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) {
678 if (sect->id == SECT_CONTEXT) {
679 for (ext = sect->section; ext->extent != NULL; ++ext)
680 count += 2 + ext->reg_count;
681 } else
682 return 0;
683 }
684
685 return count;
686 }
687
gfx_v12_0_get_csb_buffer(struct amdgpu_device * adev,volatile u32 * buffer)688 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev,
689 volatile u32 *buffer)
690 {
691 u32 count = 0, clustercount = 0, i;
692 const struct cs_section_def *sect = NULL;
693 const struct cs_extent_def *ext = NULL;
694
695 if (adev->gfx.rlc.cs_data == NULL)
696 return;
697 if (buffer == NULL)
698 return;
699
700 count += 1;
701
702 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
703 if (sect->id == SECT_CONTEXT) {
704 for (ext = sect->section; ext->extent != NULL; ++ext) {
705 clustercount++;
706 buffer[count++] = ext->reg_count;
707 buffer[count++] = ext->reg_index;
708
709 for (i = 0; i < ext->reg_count; i++)
710 buffer[count++] = cpu_to_le32(ext->extent[i]);
711 }
712 } else
713 return;
714 }
715
716 buffer[0] = clustercount;
717 }
718
gfx_v12_0_rlc_fini(struct amdgpu_device * adev)719 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev)
720 {
721 /* clear state block */
722 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
723 &adev->gfx.rlc.clear_state_gpu_addr,
724 (void **)&adev->gfx.rlc.cs_ptr);
725
726 /* jump table block */
727 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
728 &adev->gfx.rlc.cp_table_gpu_addr,
729 (void **)&adev->gfx.rlc.cp_table_ptr);
730 }
731
gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device * adev)732 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
733 {
734 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
735
736 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
737 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
738 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
739 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
740 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
741 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
742 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
743 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
744 adev->gfx.rlc.rlcg_reg_access_supported = true;
745 }
746
gfx_v12_0_rlc_init(struct amdgpu_device * adev)747 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev)
748 {
749 const struct cs_section_def *cs_data;
750 int r;
751
752 adev->gfx.rlc.cs_data = gfx12_cs_data;
753
754 cs_data = adev->gfx.rlc.cs_data;
755
756 if (cs_data) {
757 /* init clear state block */
758 r = amdgpu_gfx_rlc_init_csb(adev);
759 if (r)
760 return r;
761 }
762
763 /* init spm vmid with 0xf */
764 if (adev->gfx.rlc.funcs->update_spm_vmid)
765 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
766
767 return 0;
768 }
769
gfx_v12_0_mec_fini(struct amdgpu_device * adev)770 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev)
771 {
772 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
773 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
774 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL);
775 }
776
gfx_v12_0_me_init(struct amdgpu_device * adev)777 static void gfx_v12_0_me_init(struct amdgpu_device *adev)
778 {
779 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
780
781 amdgpu_gfx_graphics_queue_acquire(adev);
782 }
783
gfx_v12_0_mec_init(struct amdgpu_device * adev)784 static int gfx_v12_0_mec_init(struct amdgpu_device *adev)
785 {
786 int r;
787 u32 *hpd;
788 size_t mec_hpd_size;
789
790 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
791
792 /* take ownership of the relevant compute queues */
793 amdgpu_gfx_compute_queue_acquire(adev);
794 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE;
795
796 if (mec_hpd_size) {
797 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
798 AMDGPU_GEM_DOMAIN_GTT,
799 &adev->gfx.mec.hpd_eop_obj,
800 &adev->gfx.mec.hpd_eop_gpu_addr,
801 (void **)&hpd);
802 if (r) {
803 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
804 gfx_v12_0_mec_fini(adev);
805 return r;
806 }
807
808 memset(hpd, 0, mec_hpd_size);
809
810 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
811 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
812 }
813
814 return 0;
815 }
816
wave_read_ind(struct amdgpu_device * adev,uint32_t wave,uint32_t address)817 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
818 {
819 WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
820 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
821 (address << SQ_IND_INDEX__INDEX__SHIFT));
822 return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
823 }
824
wave_read_regs(struct amdgpu_device * adev,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)825 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
826 uint32_t thread, uint32_t regno,
827 uint32_t num, uint32_t *out)
828 {
829 WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
830 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
831 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
832 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
833 (SQ_IND_INDEX__AUTO_INCR_MASK));
834 while (num--)
835 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
836 }
837
gfx_v12_0_read_wave_data(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)838 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev,
839 uint32_t xcc_id,
840 uint32_t simd, uint32_t wave,
841 uint32_t *dst, int *no_fields)
842 {
843 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE
844 * field when performing a select_se_sh so it should be
845 * zero here */
846 WARN_ON(simd != 0);
847
848 /* type 4 wave data */
849 dst[(*no_fields)++] = 4;
850 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
851 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
852 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
853 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
854 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
855 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
856 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV);
865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV);
866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER);
867 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL);
868 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE);
869 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE);
870 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO);
871 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI);
872 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE);
873 }
874
gfx_v12_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)875 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev,
876 uint32_t xcc_id, uint32_t simd,
877 uint32_t wave, uint32_t start,
878 uint32_t size, uint32_t *dst)
879 {
880 WARN_ON(simd != 0);
881
882 wave_read_regs(
883 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
884 dst);
885 }
886
gfx_v12_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst)887 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev,
888 uint32_t xcc_id, uint32_t simd,
889 uint32_t wave, uint32_t thread,
890 uint32_t start, uint32_t size,
891 uint32_t *dst)
892 {
893 wave_read_regs(
894 adev, wave, thread,
895 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
896 }
897
gfx_v12_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm,u32 xcc_id)898 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev,
899 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
900 {
901 soc24_grbm_select(adev, me, pipe, q, vm);
902 }
903
904 /* all sizes are in bytes */
905 #define MQD_SHADOW_BASE_SIZE 73728
906 #define MQD_SHADOW_BASE_ALIGNMENT 256
907 #define MQD_FWWORKAREA_SIZE 484
908 #define MQD_FWWORKAREA_ALIGNMENT 256
909
gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device * adev,struct amdgpu_gfx_shadow_info * shadow_info)910 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev,
911 struct amdgpu_gfx_shadow_info *shadow_info)
912 {
913 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;
914 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;
915 shadow_info->csa_size = MQD_FWWORKAREA_SIZE;
916 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;
917 }
918
gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device * adev,struct amdgpu_gfx_shadow_info * shadow_info,bool skip_check)919 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev,
920 struct amdgpu_gfx_shadow_info *shadow_info,
921 bool skip_check)
922 {
923 if (adev->gfx.cp_gfx_shadow || skip_check) {
924 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info);
925 return 0;
926 }
927
928 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));
929 return -EINVAL;
930 }
931
932 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = {
933 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter,
934 .select_se_sh = &gfx_v12_0_select_se_sh,
935 .read_wave_data = &gfx_v12_0_read_wave_data,
936 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs,
937 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs,
938 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q,
939 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk,
940 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info,
941 };
942
gfx_v12_0_gpu_early_init(struct amdgpu_device * adev)943 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev)
944 {
945
946 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
947 case IP_VERSION(12, 0, 0):
948 case IP_VERSION(12, 0, 1):
949 adev->gfx.config.max_hw_contexts = 8;
950 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
951 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
952 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
953 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
954 break;
955 default:
956 BUG();
957 break;
958 }
959
960 return 0;
961 }
962
gfx_v12_0_gfx_ring_init(struct amdgpu_device * adev,int ring_id,int me,int pipe,int queue)963 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
964 int me, int pipe, int queue)
965 {
966 int r;
967 struct amdgpu_ring *ring;
968 unsigned int irq_type;
969
970 ring = &adev->gfx.gfx_ring[ring_id];
971
972 ring->me = me;
973 ring->pipe = pipe;
974 ring->queue = queue;
975
976 ring->ring_obj = NULL;
977 ring->use_doorbell = true;
978
979 if (!ring_id)
980 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
981 else
982 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
983 ring->vm_hub = AMDGPU_GFXHUB(0);
984 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
985
986 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
987 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
988 AMDGPU_RING_PRIO_DEFAULT, NULL);
989 if (r)
990 return r;
991 return 0;
992 }
993
gfx_v12_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)994 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
995 int mec, int pipe, int queue)
996 {
997 int r;
998 unsigned irq_type;
999 struct amdgpu_ring *ring;
1000 unsigned int hw_prio;
1001
1002 ring = &adev->gfx.compute_ring[ring_id];
1003
1004 /* mec0 is me1 */
1005 ring->me = mec + 1;
1006 ring->pipe = pipe;
1007 ring->queue = queue;
1008
1009 ring->ring_obj = NULL;
1010 ring->use_doorbell = true;
1011 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1012 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1013 + (ring_id * GFX12_MEC_HPD_SIZE);
1014 ring->vm_hub = AMDGPU_GFXHUB(0);
1015 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1016
1017 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1018 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1019 + ring->pipe;
1020 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
1021 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
1022 /* type-2 packets are deprecated on MEC, use type-3 instead */
1023 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1024 hw_prio, NULL);
1025 if (r)
1026 return r;
1027
1028 return 0;
1029 }
1030
1031 static struct {
1032 SOC24_FIRMWARE_ID id;
1033 unsigned int offset;
1034 unsigned int size;
1035 unsigned int size_x16;
1036 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX];
1037
1038 #define RLC_TOC_OFFSET_DWUNIT 8
1039 #define RLC_SIZE_MULTIPLE 1024
1040 #define RLC_TOC_UMF_SIZE_inM 23ULL
1041 #define RLC_TOC_FORMAT_API 165ULL
1042
gfx_v12_0_parse_rlc_toc(struct amdgpu_device * adev,void * rlc_toc)1043 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc)
1044 {
1045 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc;
1046
1047 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) {
1048 rlc_autoload_info[ucode->id].id = ucode->id;
1049 rlc_autoload_info[ucode->id].offset =
1050 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4;
1051 rlc_autoload_info[ucode->id].size =
1052 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 :
1053 ucode->size * 4;
1054 ucode++;
1055 }
1056 }
1057
gfx_v12_0_calc_toc_total_size(struct amdgpu_device * adev)1058 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev)
1059 {
1060 uint32_t total_size = 0;
1061 SOC24_FIRMWARE_ID id;
1062
1063 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr);
1064
1065 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++)
1066 total_size += rlc_autoload_info[id].size;
1067
1068 /* In case the offset in rlc toc ucode is aligned */
1069 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset)
1070 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset +
1071 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size;
1072 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20))
1073 total_size = RLC_TOC_UMF_SIZE_inM << 20;
1074
1075 return total_size;
1076 }
1077
gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device * adev)1078 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev)
1079 {
1080 int r;
1081 uint32_t total_size;
1082
1083 total_size = gfx_v12_0_calc_toc_total_size(adev);
1084
1085 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
1086 AMDGPU_GEM_DOMAIN_VRAM,
1087 &adev->gfx.rlc.rlc_autoload_bo,
1088 &adev->gfx.rlc.rlc_autoload_gpu_addr,
1089 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1090
1091 if (r) {
1092 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1093 return r;
1094 }
1095
1096 return 0;
1097 }
1098
gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device * adev,SOC24_FIRMWARE_ID id,const void * fw_data,uint32_t fw_size)1099 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
1100 SOC24_FIRMWARE_ID id,
1101 const void *fw_data,
1102 uint32_t fw_size)
1103 {
1104 uint32_t toc_offset;
1105 uint32_t toc_fw_size;
1106 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1107
1108 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX)
1109 return;
1110
1111 toc_offset = rlc_autoload_info[id].offset;
1112 toc_fw_size = rlc_autoload_info[id].size;
1113
1114 if (fw_size == 0)
1115 fw_size = toc_fw_size;
1116
1117 if (fw_size > toc_fw_size)
1118 fw_size = toc_fw_size;
1119
1120 memcpy(ptr + toc_offset, fw_data, fw_size);
1121
1122 if (fw_size < toc_fw_size)
1123 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
1124 }
1125
1126 static void
gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device * adev)1127 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
1128 {
1129 void *data;
1130 uint32_t size;
1131 uint32_t *toc_ptr;
1132
1133 data = adev->psp.toc.start_addr;
1134 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size;
1135
1136 toc_ptr = (uint32_t *)data + size / 4 - 2;
1137 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1;
1138
1139 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC,
1140 data, size);
1141 }
1142
1143 static void
gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device * adev)1144 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
1145 {
1146 const __le32 *fw_data;
1147 uint32_t fw_size;
1148 const struct gfx_firmware_header_v2_0 *cpv2_hdr;
1149 const struct rlc_firmware_header_v2_0 *rlc_hdr;
1150 const struct rlc_firmware_header_v2_1 *rlcv21_hdr;
1151 const struct rlc_firmware_header_v2_2 *rlcv22_hdr;
1152 uint16_t version_major, version_minor;
1153
1154 /* pfp ucode */
1155 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1156 adev->gfx.pfp_fw->data;
1157 /* instruction */
1158 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1159 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1160 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1161 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP,
1162 fw_data, fw_size);
1163 /* data */
1164 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1165 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1166 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1167 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK,
1168 fw_data, fw_size);
1169 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK,
1170 fw_data, fw_size);
1171 /* me ucode */
1172 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1173 adev->gfx.me_fw->data;
1174 /* instruction */
1175 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1176 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1177 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1178 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME,
1179 fw_data, fw_size);
1180 /* data */
1181 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1182 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1183 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1184 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK,
1185 fw_data, fw_size);
1186 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK,
1187 fw_data, fw_size);
1188 /* mec ucode */
1189 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1190 adev->gfx.mec_fw->data;
1191 /* instruction */
1192 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1193 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1194 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1195 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC,
1196 fw_data, fw_size);
1197 /* data */
1198 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1199 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1200 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1201 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK,
1202 fw_data, fw_size);
1203 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK,
1204 fw_data, fw_size);
1205 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK,
1206 fw_data, fw_size);
1207 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK,
1208 fw_data, fw_size);
1209
1210 /* rlc ucode */
1211 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
1212 adev->gfx.rlc_fw->data;
1213 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1214 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
1215 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
1216 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE,
1217 fw_data, fw_size);
1218
1219 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1220 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1221 if (version_major == 2) {
1222 if (version_minor >= 1) {
1223 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
1224
1225 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1226 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes));
1227 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes);
1228 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH,
1229 fw_data, fw_size);
1230
1231 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1232 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes));
1233 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes);
1234 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM,
1235 fw_data, fw_size);
1236 }
1237 if (version_minor >= 2) {
1238 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1239
1240 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1241 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes));
1242 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes);
1243 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE,
1244 fw_data, fw_size);
1245
1246 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1247 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes));
1248 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes);
1249 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT,
1250 fw_data, fw_size);
1251 }
1252 }
1253 }
1254
1255 static void
gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device * adev)1256 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
1257 {
1258 const __le32 *fw_data;
1259 uint32_t fw_size;
1260 const struct sdma_firmware_header_v3_0 *sdma_hdr;
1261
1262 sdma_hdr = (const struct sdma_firmware_header_v3_0 *)
1263 adev->sdma.instance[0].fw->data;
1264 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1265 le32_to_cpu(sdma_hdr->ucode_offset_bytes));
1266 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes);
1267
1268 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0,
1269 fw_data, fw_size);
1270 }
1271
1272 static void
gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device * adev)1273 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev)
1274 {
1275 const __le32 *fw_data;
1276 unsigned fw_size;
1277 const struct mes_firmware_header_v1_0 *mes_hdr;
1278 int pipe, ucode_id, data_id;
1279
1280 for (pipe = 0; pipe < 2; pipe++) {
1281 if (pipe == 0) {
1282 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0;
1283 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK;
1284 } else {
1285 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1;
1286 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK;
1287 }
1288
1289 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1290 adev->mes.fw[pipe]->data;
1291
1292 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1293 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1294 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1295
1296 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size);
1297
1298 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1299 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1300 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1301
1302 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size);
1303 }
1304 }
1305
gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device * adev)1306 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
1307 {
1308 uint32_t rlc_g_offset, rlc_g_size;
1309 uint64_t gpu_addr;
1310 uint32_t data;
1311
1312 /* RLC autoload sequence 2: copy ucode */
1313 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
1314 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
1315 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev);
1316 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
1317
1318 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset;
1319 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size;
1320 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start;
1321
1322 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1323 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1324
1325 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1326
1327 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
1328 /* RLC autoload sequence 3: load IMU fw */
1329 if (adev->gfx.imu.funcs->load_microcode)
1330 adev->gfx.imu.funcs->load_microcode(adev);
1331 /* RLC autoload sequence 4 init IMU fw */
1332 if (adev->gfx.imu.funcs->setup_imu)
1333 adev->gfx.imu.funcs->setup_imu(adev);
1334 if (adev->gfx.imu.funcs->start_imu)
1335 adev->gfx.imu.funcs->start_imu(adev);
1336
1337 /* RLC autoload sequence 5 disable gpa mode */
1338 gfx_v12_0_disable_gpa_mode(adev);
1339 } else {
1340 /* unhalt rlc to start autoload without imu */
1341 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
1342 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1);
1343 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
1344 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data);
1345 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
1346 }
1347
1348 return 0;
1349 }
1350
gfx_v12_0_alloc_ip_dump(struct amdgpu_device * adev)1351 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev)
1352 {
1353 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
1354 uint32_t *ptr;
1355 uint32_t inst;
1356
1357 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
1358 if (!ptr) {
1359 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
1360 adev->gfx.ip_dump_core = NULL;
1361 } else {
1362 adev->gfx.ip_dump_core = ptr;
1363 }
1364
1365 /* Allocate memory for compute queue registers for all the instances */
1366 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
1367 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
1368 adev->gfx.mec.num_queue_per_pipe;
1369
1370 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
1371 if (!ptr) {
1372 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
1373 adev->gfx.ip_dump_compute_queues = NULL;
1374 } else {
1375 adev->gfx.ip_dump_compute_queues = ptr;
1376 }
1377
1378 /* Allocate memory for gfx queue registers for all the instances */
1379 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
1380 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
1381 adev->gfx.me.num_queue_per_pipe;
1382
1383 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
1384 if (!ptr) {
1385 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
1386 adev->gfx.ip_dump_gfx_queues = NULL;
1387 } else {
1388 adev->gfx.ip_dump_gfx_queues = ptr;
1389 }
1390 }
1391
gfx_v12_0_sw_init(struct amdgpu_ip_block * ip_block)1392 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
1393 {
1394 int i, j, k, r, ring_id = 0;
1395 unsigned num_compute_rings;
1396 int xcc_id = 0;
1397 struct amdgpu_device *adev = ip_block->adev;
1398 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */
1399
1400 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
1401
1402 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1403 case IP_VERSION(12, 0, 0):
1404 case IP_VERSION(12, 0, 1):
1405 adev->gfx.me.num_me = 1;
1406 adev->gfx.me.num_pipe_per_me = 1;
1407 adev->gfx.me.num_queue_per_pipe = 8;
1408 adev->gfx.mec.num_mec = 1;
1409 adev->gfx.mec.num_pipe_per_mec = 2;
1410 adev->gfx.mec.num_queue_per_pipe = 4;
1411 break;
1412 default:
1413 adev->gfx.me.num_me = 1;
1414 adev->gfx.me.num_pipe_per_me = 1;
1415 adev->gfx.me.num_queue_per_pipe = 1;
1416 adev->gfx.mec.num_mec = 1;
1417 adev->gfx.mec.num_pipe_per_mec = 4;
1418 adev->gfx.mec.num_queue_per_pipe = 8;
1419 break;
1420 }
1421
1422 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1423 case IP_VERSION(12, 0, 0):
1424 case IP_VERSION(12, 0, 1):
1425 if (!adev->gfx.disable_uq &&
1426 adev->gfx.me_fw_version >= 2780 &&
1427 adev->gfx.pfp_fw_version >= 2840 &&
1428 adev->gfx.mec_fw_version >= 3050 &&
1429 adev->mes.fw_version[0] >= 123) {
1430 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
1431 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
1432 }
1433 break;
1434 default:
1435 break;
1436 }
1437
1438 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1439 case IP_VERSION(12, 0, 0):
1440 case IP_VERSION(12, 0, 1):
1441 if (adev->gfx.me_fw_version >= 2480 &&
1442 adev->gfx.pfp_fw_version >= 2530 &&
1443 adev->gfx.mec_fw_version >= 2680 &&
1444 adev->mes.fw_version[0] >= 100)
1445 adev->gfx.enable_cleaner_shader = true;
1446 break;
1447 default:
1448 adev->gfx.enable_cleaner_shader = false;
1449 break;
1450 }
1451
1452 if (adev->gfx.num_compute_rings) {
1453 /* recalculate compute rings to use based on hardware configuration */
1454 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *
1455 adev->gfx.mec.num_queue_per_pipe) / 2;
1456 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,
1457 num_compute_rings);
1458 }
1459
1460 /* EOP Event */
1461 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1462 GFX_12_0_0__SRCID__CP_EOP_INTERRUPT,
1463 &adev->gfx.eop_irq);
1464 if (r)
1465 return r;
1466
1467 /* Bad opcode Event */
1468 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1469 GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR,
1470 &adev->gfx.bad_op_irq);
1471 if (r)
1472 return r;
1473
1474 /* Privileged reg */
1475 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1476 GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT,
1477 &adev->gfx.priv_reg_irq);
1478 if (r)
1479 return r;
1480
1481 /* Privileged inst */
1482 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1483 GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT,
1484 &adev->gfx.priv_inst_irq);
1485 if (r)
1486 return r;
1487
1488 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1489
1490 gfx_v12_0_me_init(adev);
1491
1492 r = gfx_v12_0_rlc_init(adev);
1493 if (r) {
1494 dev_err(adev->dev, "Failed to init rlc BOs!\n");
1495 return r;
1496 }
1497
1498 r = gfx_v12_0_mec_init(adev);
1499 if (r) {
1500 dev_err(adev->dev, "Failed to init MEC BOs!\n");
1501 return r;
1502 }
1503
1504 if (adev->gfx.num_gfx_rings) {
1505 /* set up the gfx ring */
1506 for (i = 0; i < adev->gfx.me.num_me; i++) {
1507 for (j = 0; j < num_queue_per_pipe; j++) {
1508 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1509 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1510 continue;
1511
1512 r = gfx_v12_0_gfx_ring_init(adev, ring_id,
1513 i, k, j);
1514 if (r)
1515 return r;
1516 ring_id++;
1517 }
1518 }
1519 }
1520 }
1521
1522 if (adev->gfx.num_compute_rings) {
1523 ring_id = 0;
1524 /* set up the compute queues - allocate horizontally across pipes */
1525 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1526 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1527 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1528 if (!amdgpu_gfx_is_mec_queue_enabled(adev,
1529 0, i, k, j))
1530 continue;
1531
1532 r = gfx_v12_0_compute_ring_init(adev, ring_id,
1533 i, k, j);
1534 if (r)
1535 return r;
1536
1537 ring_id++;
1538 }
1539 }
1540 }
1541 }
1542
1543 adev->gfx.gfx_supported_reset =
1544 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
1545 adev->gfx.compute_supported_reset =
1546 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
1547 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1548 case IP_VERSION(12, 0, 0):
1549 case IP_VERSION(12, 0, 1):
1550 if ((adev->gfx.me_fw_version >= 2660) &&
1551 (adev->gfx.mec_fw_version >= 2920) &&
1552 !amdgpu_sriov_vf(adev)) {
1553 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1554 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1555 }
1556 break;
1557 default:
1558 break;
1559 }
1560
1561 if (!adev->enable_mes_kiq) {
1562 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0);
1563 if (r) {
1564 dev_err(adev->dev, "Failed to init KIQ BOs!\n");
1565 return r;
1566 }
1567
1568 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
1569 if (r)
1570 return r;
1571 }
1572
1573 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0);
1574 if (r)
1575 return r;
1576
1577 /* allocate visible FB for rlc auto-loading fw */
1578 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1579 r = gfx_v12_0_rlc_autoload_buffer_init(adev);
1580 if (r)
1581 return r;
1582 }
1583
1584 r = gfx_v12_0_gpu_early_init(adev);
1585 if (r)
1586 return r;
1587
1588 gfx_v12_0_alloc_ip_dump(adev);
1589
1590 r = amdgpu_gfx_sysfs_init(adev);
1591 if (r)
1592 return r;
1593
1594 return 0;
1595 }
1596
gfx_v12_0_pfp_fini(struct amdgpu_device * adev)1597 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev)
1598 {
1599 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1600 &adev->gfx.pfp.pfp_fw_gpu_addr,
1601 (void **)&adev->gfx.pfp.pfp_fw_ptr);
1602
1603 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj,
1604 &adev->gfx.pfp.pfp_fw_data_gpu_addr,
1605 (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
1606 }
1607
gfx_v12_0_me_fini(struct amdgpu_device * adev)1608 static void gfx_v12_0_me_fini(struct amdgpu_device *adev)
1609 {
1610 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1611 &adev->gfx.me.me_fw_gpu_addr,
1612 (void **)&adev->gfx.me.me_fw_ptr);
1613
1614 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj,
1615 &adev->gfx.me.me_fw_data_gpu_addr,
1616 (void **)&adev->gfx.me.me_fw_data_ptr);
1617 }
1618
gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device * adev)1619 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)
1620 {
1621 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1622 &adev->gfx.rlc.rlc_autoload_gpu_addr,
1623 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1624 }
1625
gfx_v12_0_sw_fini(struct amdgpu_ip_block * ip_block)1626 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block)
1627 {
1628 int i;
1629 struct amdgpu_device *adev = ip_block->adev;
1630
1631 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1632 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1633 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1634 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1635
1636 amdgpu_gfx_mqd_sw_fini(adev, 0);
1637
1638 if (!adev->enable_mes_kiq) {
1639 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
1640 amdgpu_gfx_kiq_fini(adev, 0);
1641 }
1642
1643 gfx_v12_0_pfp_fini(adev);
1644 gfx_v12_0_me_fini(adev);
1645 gfx_v12_0_rlc_fini(adev);
1646 gfx_v12_0_mec_fini(adev);
1647
1648 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1649 gfx_v12_0_rlc_autoload_buffer_fini(adev);
1650
1651 gfx_v12_0_free_microcode(adev);
1652
1653 amdgpu_gfx_sysfs_fini(adev);
1654
1655 kfree(adev->gfx.ip_dump_core);
1656 kfree(adev->gfx.ip_dump_compute_queues);
1657 kfree(adev->gfx.ip_dump_gfx_queues);
1658
1659 return 0;
1660 }
1661
gfx_v12_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id)1662 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1663 u32 sh_num, u32 instance, int xcc_id)
1664 {
1665 u32 data;
1666
1667 if (instance == 0xffffffff)
1668 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1669 INSTANCE_BROADCAST_WRITES, 1);
1670 else
1671 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1672 instance);
1673
1674 if (se_num == 0xffffffff)
1675 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1676 1);
1677 else
1678 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1679
1680 if (sh_num == 0xffffffff)
1681 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1682 1);
1683 else
1684 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1685
1686 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
1687 }
1688
gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device * adev)1689 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev)
1690 {
1691 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask;
1692
1693 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE);
1694 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask,
1695 GRBM_CC_GC_SA_UNIT_DISABLE,
1696 SA_DISABLE);
1697 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE);
1698 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask,
1699 GRBM_GC_USER_SA_UNIT_DISABLE,
1700 SA_DISABLE);
1701 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
1702 adev->gfx.config.max_shader_engines);
1703
1704 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask));
1705 }
1706
gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device * adev)1707 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1708 {
1709 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask;
1710 u32 rb_mask;
1711
1712 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
1713 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask,
1714 CC_RB_BACKEND_DISABLE,
1715 BACKEND_DISABLE);
1716 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
1717 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask,
1718 GC_USER_RB_BACKEND_DISABLE,
1719 BACKEND_DISABLE);
1720 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se *
1721 adev->gfx.config.max_shader_engines);
1722
1723 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask));
1724 }
1725
gfx_v12_0_setup_rb(struct amdgpu_device * adev)1726 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev)
1727 {
1728 u32 rb_bitmap_per_sa;
1729 u32 rb_bitmap_width_per_sa;
1730 u32 max_sa;
1731 u32 active_sa_bitmap;
1732 u32 global_active_rb_bitmap;
1733 u32 active_rb_bitmap = 0;
1734 u32 i;
1735
1736 /* query sa bitmap from SA_UNIT_DISABLE registers */
1737 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev);
1738 /* query rb bitmap from RB_BACKEND_DISABLE registers */
1739 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev);
1740
1741 /* generate active rb bitmap according to active sa bitmap */
1742 max_sa = adev->gfx.config.max_shader_engines *
1743 adev->gfx.config.max_sh_per_se;
1744 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se /
1745 adev->gfx.config.max_sh_per_se;
1746 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa);
1747
1748 for (i = 0; i < max_sa; i++) {
1749 if (active_sa_bitmap & (1 << i))
1750 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa));
1751 }
1752
1753 active_rb_bitmap &= global_active_rb_bitmap;
1754 adev->gfx.config.backend_enable_mask = active_rb_bitmap;
1755 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);
1756 }
1757
1758 #define LDS_APP_BASE 0x1
1759 #define SCRATCH_APP_BASE 0x2
1760
gfx_v12_0_init_compute_vmid(struct amdgpu_device * adev)1761 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev)
1762 {
1763 int i;
1764 uint32_t sh_mem_bases;
1765 uint32_t data;
1766
1767 /*
1768 * Configure apertures:
1769 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1770 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1771 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1772 */
1773 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) |
1774 SCRATCH_APP_BASE;
1775
1776 mutex_lock(&adev->srbm_mutex);
1777 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1778 soc24_grbm_select(adev, 0, 0, 0, i);
1779 /* CP and shaders */
1780 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1781 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
1782
1783 /* Enable trap for each kfd vmid. */
1784 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
1785 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1786 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data);
1787 }
1788 soc24_grbm_select(adev, 0, 0, 0, 0);
1789 mutex_unlock(&adev->srbm_mutex);
1790 }
1791
gfx_v12_0_tcp_harvest(struct amdgpu_device * adev)1792 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev)
1793 {
1794 /* TODO: harvest feature to be added later. */
1795 }
1796
gfx_v12_0_get_tcc_info(struct amdgpu_device * adev)1797 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev)
1798 {
1799 }
1800
gfx_v12_0_constants_init(struct amdgpu_device * adev)1801 static void gfx_v12_0_constants_init(struct amdgpu_device *adev)
1802 {
1803 u32 tmp;
1804 int i;
1805
1806 if (!amdgpu_sriov_vf(adev))
1807 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1808
1809 gfx_v12_0_setup_rb(adev);
1810 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info);
1811 gfx_v12_0_get_tcc_info(adev);
1812 adev->gfx.config.pa_sc_tile_steering_override = 0;
1813
1814 /* XXX SH_MEM regs */
1815 /* where to put LDS, scratch, GPUVM in FSA64 space */
1816 mutex_lock(&adev->srbm_mutex);
1817 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
1818 soc24_grbm_select(adev, 0, 0, 0, i);
1819 /* CP and shaders */
1820 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1821 if (i != 0) {
1822 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1823 (adev->gmc.private_aperture_start >> 48));
1824 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1825 (adev->gmc.shared_aperture_start >> 48));
1826 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
1827 }
1828 }
1829 soc24_grbm_select(adev, 0, 0, 0, 0);
1830
1831 mutex_unlock(&adev->srbm_mutex);
1832
1833 gfx_v12_0_init_compute_vmid(adev);
1834 }
1835
gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device * adev,int me,int pipe)1836 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev,
1837 int me, int pipe)
1838 {
1839 if (me != 0)
1840 return 0;
1841
1842 switch (pipe) {
1843 case 0:
1844 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
1845 default:
1846 return 0;
1847 }
1848 }
1849
gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device * adev,int me,int pipe)1850 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev,
1851 int me, int pipe)
1852 {
1853 /*
1854 * amdgpu controls only the first MEC. That's why this function only
1855 * handles the setting of interrupts for this specific MEC. All other
1856 * pipes' interrupts are set by amdkfd.
1857 */
1858 if (me != 1)
1859 return 0;
1860
1861 switch (pipe) {
1862 case 0:
1863 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
1864 case 1:
1865 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
1866 default:
1867 return 0;
1868 }
1869 }
1870
gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)1871 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1872 bool enable)
1873 {
1874 u32 tmp, cp_int_cntl_reg;
1875 int i, j;
1876
1877 if (amdgpu_sriov_vf(adev))
1878 return;
1879
1880 for (i = 0; i < adev->gfx.me.num_me; i++) {
1881 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
1882 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
1883
1884 if (cp_int_cntl_reg) {
1885 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
1886 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1887 enable ? 1 : 0);
1888 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1889 enable ? 1 : 0);
1890 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1891 enable ? 1 : 0);
1892 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1893 enable ? 1 : 0);
1894 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
1895 }
1896 }
1897 }
1898 }
1899
gfx_v12_0_init_csb(struct amdgpu_device * adev)1900 static int gfx_v12_0_init_csb(struct amdgpu_device *adev)
1901 {
1902 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1903
1904 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,
1905 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1906 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,
1907 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1908 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1909
1910 return 0;
1911 }
1912
gfx_v12_0_rlc_stop(struct amdgpu_device * adev)1913 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev)
1914 {
1915 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
1916
1917 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1918 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
1919 }
1920
gfx_v12_0_rlc_reset(struct amdgpu_device * adev)1921 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev)
1922 {
1923 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1924 udelay(50);
1925 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1926 udelay(50);
1927 }
1928
gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device * adev,bool enable)1929 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1930 bool enable)
1931 {
1932 uint32_t rlc_pg_cntl;
1933
1934 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
1935
1936 if (!enable) {
1937 /* RLC_PG_CNTL[23] = 0 (default)
1938 * RLC will wait for handshake acks with SMU
1939 * GFXOFF will be enabled
1940 * RLC_PG_CNTL[23] = 1
1941 * RLC will not issue any message to SMU
1942 * hence no handshake between SMU & RLC
1943 * GFXOFF will be disabled
1944 */
1945 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1946 } else
1947 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1948 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);
1949 }
1950
gfx_v12_0_rlc_start(struct amdgpu_device * adev)1951 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev)
1952 {
1953 /* TODO: enable rlc & smu handshake until smu
1954 * and gfxoff feature works as expected */
1955 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1956 gfx_v12_0_rlc_smu_handshake_cntl(adev, false);
1957
1958 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1959 udelay(50);
1960 }
1961
gfx_v12_0_rlc_enable_srm(struct amdgpu_device * adev)1962 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev)
1963 {
1964 uint32_t tmp;
1965
1966 /* enable Save Restore Machine */
1967 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
1968 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1969 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1970 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
1971 }
1972
gfx_v12_0_load_rlcg_microcode(struct amdgpu_device * adev)1973 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev)
1974 {
1975 const struct rlc_firmware_header_v2_0 *hdr;
1976 const __le32 *fw_data;
1977 unsigned i, fw_size;
1978
1979 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1980 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1981 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1982 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1983
1984 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,
1985 RLCG_UCODE_LOADING_START_ADDRESS);
1986
1987 for (i = 0; i < fw_size; i++)
1988 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,
1989 le32_to_cpup(fw_data++));
1990
1991 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1992 }
1993
gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device * adev)1994 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev)
1995 {
1996 const struct rlc_firmware_header_v2_2 *hdr;
1997 const __le32 *fw_data;
1998 unsigned i, fw_size;
1999 u32 tmp;
2000
2001 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
2002
2003 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2004 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes));
2005 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4;
2006
2007 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);
2008
2009 for (i = 0; i < fw_size; i++) {
2010 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
2011 msleep(1);
2012 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,
2013 le32_to_cpup(fw_data++));
2014 }
2015
2016 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
2017
2018 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2019 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes));
2020 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4;
2021
2022 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);
2023 for (i = 0; i < fw_size; i++) {
2024 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
2025 msleep(1);
2026 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,
2027 le32_to_cpup(fw_data++));
2028 }
2029
2030 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
2031
2032 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
2033 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
2034 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
2035 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
2036 }
2037
gfx_v12_0_rlc_load_microcode(struct amdgpu_device * adev)2038 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev)
2039 {
2040 const struct rlc_firmware_header_v2_0 *hdr;
2041 uint16_t version_major;
2042 uint16_t version_minor;
2043
2044 if (!adev->gfx.rlc_fw)
2045 return -EINVAL;
2046
2047 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2048 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2049
2050 version_major = le16_to_cpu(hdr->header.header_version_major);
2051 version_minor = le16_to_cpu(hdr->header.header_version_minor);
2052
2053 if (version_major == 2) {
2054 gfx_v12_0_load_rlcg_microcode(adev);
2055 if (amdgpu_dpm == 1) {
2056 if (version_minor >= 2)
2057 gfx_v12_0_load_rlc_iram_dram_microcode(adev);
2058 }
2059
2060 return 0;
2061 }
2062
2063 return -EINVAL;
2064 }
2065
gfx_v12_0_rlc_resume(struct amdgpu_device * adev)2066 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev)
2067 {
2068 int r;
2069
2070 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2071 gfx_v12_0_init_csb(adev);
2072
2073 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
2074 gfx_v12_0_rlc_enable_srm(adev);
2075 } else {
2076 if (amdgpu_sriov_vf(adev)) {
2077 gfx_v12_0_init_csb(adev);
2078 return 0;
2079 }
2080
2081 adev->gfx.rlc.funcs->stop(adev);
2082
2083 /* disable CG */
2084 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
2085
2086 /* disable PG */
2087 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);
2088
2089 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
2090 /* legacy rlc firmware loading */
2091 r = gfx_v12_0_rlc_load_microcode(adev);
2092 if (r)
2093 return r;
2094 }
2095
2096 gfx_v12_0_init_csb(adev);
2097
2098 adev->gfx.rlc.funcs->start(adev);
2099 }
2100
2101 return 0;
2102 }
2103
gfx_v12_0_config_gfx_rs64(struct amdgpu_device * adev)2104 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev)
2105 {
2106 const struct gfx_firmware_header_v2_0 *pfp_hdr;
2107 const struct gfx_firmware_header_v2_0 *me_hdr;
2108 const struct gfx_firmware_header_v2_0 *mec_hdr;
2109 uint32_t pipe_id, tmp;
2110
2111 mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2112 adev->gfx.mec_fw->data;
2113 me_hdr = (const struct gfx_firmware_header_v2_0 *)
2114 adev->gfx.me_fw->data;
2115 pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2116 adev->gfx.pfp_fw->data;
2117
2118 /* config pfp program start addr */
2119 for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2120 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2121 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2122 (pfp_hdr->ucode_start_addr_hi << 30) |
2123 (pfp_hdr->ucode_start_addr_lo >> 2));
2124 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2125 pfp_hdr->ucode_start_addr_hi >> 2);
2126 }
2127 soc24_grbm_select(adev, 0, 0, 0, 0);
2128
2129 /* reset pfp pipe */
2130 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2131 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
2132 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
2133 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2134
2135 /* clear pfp pipe reset */
2136 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
2137 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
2138 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2139
2140 /* config me program start addr */
2141 for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2142 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2143 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2144 (me_hdr->ucode_start_addr_hi << 30) |
2145 (me_hdr->ucode_start_addr_lo >> 2));
2146 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2147 me_hdr->ucode_start_addr_hi>>2);
2148 }
2149 soc24_grbm_select(adev, 0, 0, 0, 0);
2150
2151 /* reset me pipe */
2152 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2153 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
2154 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
2155 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2156
2157 /* clear me pipe reset */
2158 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
2159 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
2160 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2161
2162 /* config mec program start addr */
2163 for (pipe_id = 0; pipe_id < 4; pipe_id++) {
2164 soc24_grbm_select(adev, 1, pipe_id, 0, 0);
2165 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2166 mec_hdr->ucode_start_addr_lo >> 2 |
2167 mec_hdr->ucode_start_addr_hi << 30);
2168 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2169 mec_hdr->ucode_start_addr_hi >> 2);
2170 }
2171 soc24_grbm_select(adev, 0, 0, 0, 0);
2172
2173 /* reset mec pipe */
2174 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2175 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
2176 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
2177 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
2178 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
2179 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2180
2181 /* clear mec pipe reset */
2182 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
2183 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
2184 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
2185 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
2186 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2187 }
2188
gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device * adev)2189 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev)
2190 {
2191 const struct gfx_firmware_header_v2_0 *cp_hdr;
2192 unsigned pipe_id, tmp;
2193
2194 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2195 adev->gfx.pfp_fw->data;
2196 mutex_lock(&adev->srbm_mutex);
2197 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2198 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2199 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2200 (cp_hdr->ucode_start_addr_hi << 30) |
2201 (cp_hdr->ucode_start_addr_lo >> 2));
2202 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2203 cp_hdr->ucode_start_addr_hi>>2);
2204
2205 /*
2206 * Program CP_ME_CNTL to reset given PIPE to take
2207 * effect of CP_PFP_PRGRM_CNTR_START.
2208 */
2209 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2210 if (pipe_id == 0)
2211 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2212 PFP_PIPE0_RESET, 1);
2213 else
2214 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2215 PFP_PIPE1_RESET, 1);
2216 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2217
2218 /* Clear pfp pipe0 reset bit. */
2219 if (pipe_id == 0)
2220 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2221 PFP_PIPE0_RESET, 0);
2222 else
2223 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2224 PFP_PIPE1_RESET, 0);
2225 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2226 }
2227 soc24_grbm_select(adev, 0, 0, 0, 0);
2228 mutex_unlock(&adev->srbm_mutex);
2229 }
2230
gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device * adev)2231 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev)
2232 {
2233 const struct gfx_firmware_header_v2_0 *cp_hdr;
2234 unsigned pipe_id, tmp;
2235
2236 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2237 adev->gfx.me_fw->data;
2238 mutex_lock(&adev->srbm_mutex);
2239 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2240 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2241 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2242 (cp_hdr->ucode_start_addr_hi << 30) |
2243 (cp_hdr->ucode_start_addr_lo >> 2) );
2244 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2245 cp_hdr->ucode_start_addr_hi>>2);
2246
2247 /*
2248 * Program CP_ME_CNTL to reset given PIPE to take
2249 * effect of CP_ME_PRGRM_CNTR_START.
2250 */
2251 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2252 if (pipe_id == 0)
2253 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2254 ME_PIPE0_RESET, 1);
2255 else
2256 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2257 ME_PIPE1_RESET, 1);
2258 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2259
2260 /* Clear pfp pipe0 reset bit. */
2261 if (pipe_id == 0)
2262 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2263 ME_PIPE0_RESET, 0);
2264 else
2265 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2266 ME_PIPE1_RESET, 0);
2267 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2268 }
2269 soc24_grbm_select(adev, 0, 0, 0, 0);
2270 mutex_unlock(&adev->srbm_mutex);
2271 }
2272
gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device * adev)2273 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev)
2274 {
2275 const struct gfx_firmware_header_v2_0 *cp_hdr;
2276 unsigned pipe_id;
2277
2278 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2279 adev->gfx.mec_fw->data;
2280 mutex_lock(&adev->srbm_mutex);
2281 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) {
2282 soc24_grbm_select(adev, 1, pipe_id, 0, 0);
2283 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2284 cp_hdr->ucode_start_addr_lo >> 2 |
2285 cp_hdr->ucode_start_addr_hi << 30);
2286 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2287 cp_hdr->ucode_start_addr_hi >> 2);
2288 }
2289 soc24_grbm_select(adev, 0, 0, 0, 0);
2290 mutex_unlock(&adev->srbm_mutex);
2291 }
2292
gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device * adev)2293 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2294 {
2295 uint32_t cp_status;
2296 uint32_t bootload_status;
2297 int i;
2298
2299 for (i = 0; i < adev->usec_timeout; i++) {
2300 cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
2301 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
2302
2303 if ((cp_status == 0) &&
2304 (REG_GET_FIELD(bootload_status,
2305 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2306 break;
2307 }
2308 udelay(1);
2309 if (amdgpu_emu_mode)
2310 msleep(10);
2311 }
2312
2313 if (i >= adev->usec_timeout) {
2314 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2315 return -ETIMEDOUT;
2316 }
2317
2318 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2319 gfx_v12_0_set_pfp_ucode_start_addr(adev);
2320 gfx_v12_0_set_me_ucode_start_addr(adev);
2321 gfx_v12_0_set_mec_ucode_start_addr(adev);
2322 }
2323
2324 return 0;
2325 }
2326
gfx_v12_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)2327 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2328 {
2329 int i;
2330 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2331
2332 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2333 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2334 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2335
2336 for (i = 0; i < adev->usec_timeout; i++) {
2337 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)
2338 break;
2339 udelay(1);
2340 }
2341
2342 if (i >= adev->usec_timeout)
2343 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2344
2345 return 0;
2346 }
2347
gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device * adev)2348 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
2349 {
2350 int r;
2351 const struct gfx_firmware_header_v2_0 *pfp_hdr;
2352 const __le32 *fw_ucode, *fw_data;
2353 unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2354 uint32_t tmp;
2355 uint32_t usec_timeout = 50000; /* wait for 50ms */
2356
2357 pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2358 adev->gfx.pfp_fw->data;
2359
2360 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2361
2362 /* instruction */
2363 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data +
2364 le32_to_cpu(pfp_hdr->ucode_offset_bytes));
2365 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes);
2366 /* data */
2367 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2368 le32_to_cpu(pfp_hdr->data_offset_bytes));
2369 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes);
2370
2371 /* 64kb align */
2372 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2373 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2374 &adev->gfx.pfp.pfp_fw_obj,
2375 &adev->gfx.pfp.pfp_fw_gpu_addr,
2376 (void **)&adev->gfx.pfp.pfp_fw_ptr);
2377 if (r) {
2378 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r);
2379 gfx_v12_0_pfp_fini(adev);
2380 return r;
2381 }
2382
2383 r = amdgpu_bo_create_reserved(adev, fw_data_size,
2384 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2385 &adev->gfx.pfp.pfp_fw_data_obj,
2386 &adev->gfx.pfp.pfp_fw_data_gpu_addr,
2387 (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
2388 if (r) {
2389 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r);
2390 gfx_v12_0_pfp_fini(adev);
2391 return r;
2392 }
2393
2394 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);
2395 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);
2396
2397 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2398 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj);
2399 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2400 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
2401
2402 if (amdgpu_emu_mode == 1)
2403 amdgpu_device_flush_hdp(adev, NULL);
2404
2405 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2406 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2407 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2408 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2409
2410 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2411 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2412 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2413 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2414 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2415
2416 /*
2417 * Programming any of the CP_PFP_IC_BASE registers
2418 * forces invalidation of the ME L1 I$. Wait for the
2419 * invalidation complete
2420 */
2421 for (i = 0; i < usec_timeout; i++) {
2422 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2423 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2424 INVALIDATE_CACHE_COMPLETE))
2425 break;
2426 udelay(1);
2427 }
2428
2429 if (i >= usec_timeout) {
2430 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2431 return -EINVAL;
2432 }
2433
2434 /* Prime the L1 instruction caches */
2435 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2436 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2437 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2438 /* Waiting for cache primed*/
2439 for (i = 0; i < usec_timeout; i++) {
2440 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2441 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2442 ICACHE_PRIMED))
2443 break;
2444 udelay(1);
2445 }
2446
2447 if (i >= usec_timeout) {
2448 dev_err(adev->dev, "failed to prime instruction cache\n");
2449 return -EINVAL;
2450 }
2451
2452 mutex_lock(&adev->srbm_mutex);
2453 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2454 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2455
2456 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2457 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2458 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2459 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2460 }
2461 soc24_grbm_select(adev, 0, 0, 0, 0);
2462 mutex_unlock(&adev->srbm_mutex);
2463
2464 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2465 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2466 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2467 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2468
2469 /* Invalidate the data caches */
2470 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2471 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2472 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2473
2474 for (i = 0; i < usec_timeout; i++) {
2475 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2476 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2477 INVALIDATE_DCACHE_COMPLETE))
2478 break;
2479 udelay(1);
2480 }
2481
2482 if (i >= usec_timeout) {
2483 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2484 return -EINVAL;
2485 }
2486
2487 gfx_v12_0_set_pfp_ucode_start_addr(adev);
2488
2489 return 0;
2490 }
2491
gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device * adev)2492 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
2493 {
2494 int r;
2495 const struct gfx_firmware_header_v2_0 *me_hdr;
2496 const __le32 *fw_ucode, *fw_data;
2497 unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2498 uint32_t tmp;
2499 uint32_t usec_timeout = 50000; /* wait for 50ms */
2500
2501 me_hdr = (const struct gfx_firmware_header_v2_0 *)
2502 adev->gfx.me_fw->data;
2503
2504 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2505
2506 /* instruction */
2507 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data +
2508 le32_to_cpu(me_hdr->ucode_offset_bytes));
2509 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes);
2510 /* data */
2511 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2512 le32_to_cpu(me_hdr->data_offset_bytes));
2513 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes);
2514
2515 /* 64kb align*/
2516 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2517 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2518 &adev->gfx.me.me_fw_obj,
2519 &adev->gfx.me.me_fw_gpu_addr,
2520 (void **)&adev->gfx.me.me_fw_ptr);
2521 if (r) {
2522 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r);
2523 gfx_v12_0_me_fini(adev);
2524 return r;
2525 }
2526
2527 r = amdgpu_bo_create_reserved(adev, fw_data_size,
2528 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2529 &adev->gfx.me.me_fw_data_obj,
2530 &adev->gfx.me.me_fw_data_gpu_addr,
2531 (void **)&adev->gfx.me.me_fw_data_ptr);
2532 if (r) {
2533 dev_err(adev->dev, "(%d) failed to create me data bo\n", r);
2534 gfx_v12_0_me_fini(adev);
2535 return r;
2536 }
2537
2538 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);
2539 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size);
2540
2541 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2542 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj);
2543 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2544 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
2545
2546 if (amdgpu_emu_mode == 1)
2547 amdgpu_device_flush_hdp(adev, NULL);
2548
2549 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2550 lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
2551 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2552 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2553
2554 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2555 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2556 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2557 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2558 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2559
2560 /*
2561 * Programming any of the CP_ME_IC_BASE registers
2562 * forces invalidation of the ME L1 I$. Wait for the
2563 * invalidation complete
2564 */
2565 for (i = 0; i < usec_timeout; i++) {
2566 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2567 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2568 INVALIDATE_CACHE_COMPLETE))
2569 break;
2570 udelay(1);
2571 }
2572
2573 if (i >= usec_timeout) {
2574 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2575 return -EINVAL;
2576 }
2577
2578 /* Prime the instruction caches */
2579 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2580 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2581 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2582
2583 /* Waiting for instruction cache primed*/
2584 for (i = 0; i < usec_timeout; i++) {
2585 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2586 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2587 ICACHE_PRIMED))
2588 break;
2589 udelay(1);
2590 }
2591
2592 if (i >= usec_timeout) {
2593 dev_err(adev->dev, "failed to prime instruction cache\n");
2594 return -EINVAL;
2595 }
2596
2597 mutex_lock(&adev->srbm_mutex);
2598 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2599 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2600
2601 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2602 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2603 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2604 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2605 }
2606 soc24_grbm_select(adev, 0, 0, 0, 0);
2607 mutex_unlock(&adev->srbm_mutex);
2608
2609 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2610 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2611 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2612 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2613
2614 /* Invalidate the data caches */
2615 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2616 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2617 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2618
2619 for (i = 0; i < usec_timeout; i++) {
2620 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2621 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2622 INVALIDATE_DCACHE_COMPLETE))
2623 break;
2624 udelay(1);
2625 }
2626
2627 if (i >= usec_timeout) {
2628 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2629 return -EINVAL;
2630 }
2631
2632 gfx_v12_0_set_me_ucode_start_addr(adev);
2633
2634 return 0;
2635 }
2636
gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device * adev)2637 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2638 {
2639 int r;
2640
2641 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw)
2642 return -EINVAL;
2643
2644 gfx_v12_0_cp_gfx_enable(adev, false);
2645
2646 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev);
2647 if (r) {
2648 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2649 return r;
2650 }
2651
2652 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev);
2653 if (r) {
2654 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2655 return r;
2656 }
2657
2658 return 0;
2659 }
2660
gfx_v12_0_cp_gfx_start(struct amdgpu_device * adev)2661 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev)
2662 {
2663 /* init the CP */
2664 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,
2665 adev->gfx.config.max_hw_contexts - 1);
2666 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);
2667
2668 if (!amdgpu_async_gfx_ring)
2669 gfx_v12_0_cp_gfx_enable(adev, true);
2670
2671 return 0;
2672 }
2673
gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device * adev,CP_PIPE_ID pipe)2674 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2675 CP_PIPE_ID pipe)
2676 {
2677 u32 tmp;
2678
2679 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
2680 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2681
2682 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
2683 }
2684
gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device * adev,struct amdgpu_ring * ring)2685 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2686 struct amdgpu_ring *ring)
2687 {
2688 u32 tmp;
2689
2690 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
2691 if (ring->use_doorbell) {
2692 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2693 DOORBELL_OFFSET, ring->doorbell_index);
2694 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2695 DOORBELL_EN, 1);
2696 } else {
2697 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2698 DOORBELL_EN, 0);
2699 }
2700 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
2701
2702 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2703 DOORBELL_RANGE_LOWER, ring->doorbell_index);
2704 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
2705
2706 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
2707 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2708 }
2709
gfx_v12_0_cp_gfx_resume(struct amdgpu_device * adev)2710 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev)
2711 {
2712 struct amdgpu_ring *ring;
2713 u32 tmp;
2714 u32 rb_bufsz;
2715 u64 rb_addr, rptr_addr, wptr_gpu_addr;
2716
2717 /* Set the write pointer delay */
2718 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
2719
2720 /* set the RB to use vmid 0 */
2721 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);
2722
2723 /* Init gfx ring 0 for pipe 0 */
2724 mutex_lock(&adev->srbm_mutex);
2725 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2726
2727 /* Set ring buffer size */
2728 ring = &adev->gfx.gfx_ring[0];
2729 rb_bufsz = order_base_2(ring->ring_size / 8);
2730 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2731 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2732 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
2733
2734 /* Initialize the ring buffer's write pointers */
2735 ring->wptr = 0;
2736 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
2737 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2738
2739 /* set the wb address whether it's enabled or not */
2740 rptr_addr = ring->rptr_gpu_addr;
2741 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2742 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2743 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2744
2745 wptr_gpu_addr = ring->wptr_gpu_addr;
2746 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
2747 lower_32_bits(wptr_gpu_addr));
2748 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
2749 upper_32_bits(wptr_gpu_addr));
2750
2751 mdelay(1);
2752 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
2753
2754 rb_addr = ring->gpu_addr >> 8;
2755 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);
2756 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2757
2758 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);
2759
2760 gfx_v12_0_cp_gfx_set_doorbell(adev, ring);
2761 mutex_unlock(&adev->srbm_mutex);
2762
2763 /* Switch to pipe 0 */
2764 mutex_lock(&adev->srbm_mutex);
2765 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2766 mutex_unlock(&adev->srbm_mutex);
2767
2768 /* start the ring */
2769 gfx_v12_0_cp_gfx_start(adev);
2770 return 0;
2771 }
2772
gfx_v12_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)2773 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2774 {
2775 u32 data;
2776
2777 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2778 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,
2779 enable ? 0 : 1);
2780 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,
2781 enable ? 0 : 1);
2782 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,
2783 enable ? 0 : 1);
2784 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,
2785 enable ? 0 : 1);
2786 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,
2787 enable ? 0 : 1);
2788 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,
2789 enable ? 1 : 0);
2790 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,
2791 enable ? 1 : 0);
2792 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,
2793 enable ? 1 : 0);
2794 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,
2795 enable ? 1 : 0);
2796 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,
2797 enable ? 0 : 1);
2798 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);
2799
2800 adev->gfx.kiq[0].ring.sched.ready = enable;
2801
2802 udelay(50);
2803 }
2804
gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device * adev)2805 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev)
2806 {
2807 const struct gfx_firmware_header_v2_0 *mec_hdr;
2808 const __le32 *fw_ucode, *fw_data;
2809 u32 tmp, fw_ucode_size, fw_data_size;
2810 u32 i, usec_timeout = 50000; /* Wait for 50 ms */
2811 u32 *fw_ucode_ptr, *fw_data_ptr;
2812 int r;
2813
2814 if (!adev->gfx.mec_fw)
2815 return -EINVAL;
2816
2817 gfx_v12_0_cp_compute_enable(adev, false);
2818
2819 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
2820 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2821
2822 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data +
2823 le32_to_cpu(mec_hdr->ucode_offset_bytes));
2824 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes);
2825
2826 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2827 le32_to_cpu(mec_hdr->data_offset_bytes));
2828 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
2829
2830 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2831 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2832 &adev->gfx.mec.mec_fw_obj,
2833 &adev->gfx.mec.mec_fw_gpu_addr,
2834 (void **)&fw_ucode_ptr);
2835 if (r) {
2836 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
2837 gfx_v12_0_mec_fini(adev);
2838 return r;
2839 }
2840
2841 r = amdgpu_bo_create_reserved(adev,
2842 ALIGN(fw_data_size, 64 * 1024) *
2843 adev->gfx.mec.num_pipe_per_mec,
2844 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2845 &adev->gfx.mec.mec_fw_data_obj,
2846 &adev->gfx.mec.mec_fw_data_gpu_addr,
2847 (void **)&fw_data_ptr);
2848 if (r) {
2849 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
2850 gfx_v12_0_mec_fini(adev);
2851 return r;
2852 }
2853
2854 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);
2855 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2856 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size);
2857 }
2858
2859 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
2860 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj);
2861 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
2862 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
2863
2864 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2865 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2866 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2867 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2868 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2869
2870 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
2871 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
2872 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
2873 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
2874
2875 mutex_lock(&adev->srbm_mutex);
2876 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2877 soc24_grbm_select(adev, 1, i, 0, 0);
2878
2879 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO,
2880 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr +
2881 i * ALIGN(fw_data_size, 64 * 1024)));
2882 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
2883 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr +
2884 i * ALIGN(fw_data_size, 64 * 1024)));
2885
2886 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
2887 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2888 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2889 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2890 }
2891 mutex_unlock(&adev->srbm_mutex);
2892 soc24_grbm_select(adev, 0, 0, 0, 0);
2893
2894 /* Trigger an invalidation of the L1 instruction caches */
2895 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2896 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2897 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
2898
2899 /* Wait for invalidation complete */
2900 for (i = 0; i < usec_timeout; i++) {
2901 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2902 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
2903 INVALIDATE_DCACHE_COMPLETE))
2904 break;
2905 udelay(1);
2906 }
2907
2908 if (i >= usec_timeout) {
2909 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2910 return -EINVAL;
2911 }
2912
2913 /* Trigger an invalidation of the L1 instruction caches */
2914 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2915 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2916 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2917
2918 /* Wait for invalidation complete */
2919 for (i = 0; i < usec_timeout; i++) {
2920 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2921 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2922 INVALIDATE_CACHE_COMPLETE))
2923 break;
2924 udelay(1);
2925 }
2926
2927 if (i >= usec_timeout) {
2928 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2929 return -EINVAL;
2930 }
2931
2932 gfx_v12_0_set_mec_ucode_start_addr(adev);
2933
2934 return 0;
2935 }
2936
gfx_v12_0_kiq_setting(struct amdgpu_ring * ring)2937 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring)
2938 {
2939 uint32_t tmp;
2940 struct amdgpu_device *adev = ring->adev;
2941
2942 /* tell RLC which is KIQ queue */
2943 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
2944 tmp &= 0xffffff00;
2945 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2946 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
2947 }
2948
gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device * adev)2949 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev)
2950 {
2951 /* set graphics engine doorbell range */
2952 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,
2953 (adev->doorbell_index.gfx_ring0 * 2) << 2);
2954 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
2955 (adev->doorbell_index.gfx_userqueue_end * 2) << 2);
2956
2957 /* set compute engine doorbell range */
2958 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
2959 (adev->doorbell_index.kiq * 2) << 2);
2960 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
2961 (adev->doorbell_index.userqueue_end * 2) << 2);
2962 }
2963
gfx_v12_0_gfx_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)2964 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
2965 struct amdgpu_mqd_prop *prop)
2966 {
2967 struct v12_gfx_mqd *mqd = m;
2968 uint64_t hqd_gpu_addr, wb_gpu_addr;
2969 uint32_t tmp;
2970 uint32_t rb_bufsz;
2971
2972 /* set up gfx hqd wptr */
2973 mqd->cp_gfx_hqd_wptr = 0;
2974 mqd->cp_gfx_hqd_wptr_hi = 0;
2975
2976 /* set the pointer to the MQD */
2977 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
2978 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
2979
2980 /* set up mqd control */
2981 tmp = regCP_GFX_MQD_CONTROL_DEFAULT;
2982 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2983 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2984 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2985 mqd->cp_gfx_mqd_control = tmp;
2986
2987 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
2988 tmp = regCP_GFX_HQD_VMID_DEFAULT;
2989 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
2990 mqd->cp_gfx_hqd_vmid = 0;
2991
2992 /* set up default queue priority level
2993 * 0x0 = low priority, 0x1 = high priority */
2994 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT;
2995 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
2996 mqd->cp_gfx_hqd_queue_priority = tmp;
2997
2998 /* set up time quantum */
2999 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT;
3000 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3001 mqd->cp_gfx_hqd_quantum = tmp;
3002
3003 /* set up gfx hqd base. this is similar as CP_RB_BASE */
3004 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3005 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3006 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3007
3008 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3009 wb_gpu_addr = prop->rptr_gpu_addr;
3010 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3011 mqd->cp_gfx_hqd_rptr_addr_hi =
3012 upper_32_bits(wb_gpu_addr) & 0xffff;
3013
3014 /* set up rb_wptr_poll addr */
3015 wb_gpu_addr = prop->wptr_gpu_addr;
3016 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3017 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3018
3019 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3020 rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
3021 tmp = regCP_GFX_HQD_CNTL_DEFAULT;
3022 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3023 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3024 #ifdef __BIG_ENDIAN
3025 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3026 #endif
3027 if (prop->tmz_queue)
3028 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);
3029 mqd->cp_gfx_hqd_cntl = tmp;
3030
3031 /* set up cp_doorbell_control */
3032 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT;
3033 if (prop->use_doorbell) {
3034 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3035 DOORBELL_OFFSET, prop->doorbell_index);
3036 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3037 DOORBELL_EN, 1);
3038 } else
3039 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3040 DOORBELL_EN, 0);
3041 mqd->cp_rb_doorbell_control = tmp;
3042
3043 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3044 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT;
3045
3046 /* active the queue */
3047 mqd->cp_gfx_hqd_active = 1;
3048
3049 /* set gfx UQ items */
3050 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr);
3051 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr);
3052 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr);
3053 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr);
3054 mqd->fence_address_lo = lower_32_bits(prop->fence_address);
3055 mqd->fence_address_hi = upper_32_bits(prop->fence_address);
3056
3057 return 0;
3058 }
3059
gfx_v12_0_kgq_init_queue(struct amdgpu_ring * ring,bool reset)3060 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
3061 {
3062 struct amdgpu_device *adev = ring->adev;
3063 struct v12_gfx_mqd *mqd = ring->mqd_ptr;
3064 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3065
3066 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
3067 memset((void *)mqd, 0, sizeof(*mqd));
3068 mutex_lock(&adev->srbm_mutex);
3069 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3070 amdgpu_ring_init_mqd(ring);
3071 soc24_grbm_select(adev, 0, 0, 0, 0);
3072 mutex_unlock(&adev->srbm_mutex);
3073 if (adev->gfx.me.mqd_backup[mqd_idx])
3074 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3075 } else {
3076 /* restore mqd with the backup copy */
3077 if (adev->gfx.me.mqd_backup[mqd_idx])
3078 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3079 /* reset the ring */
3080 ring->wptr = 0;
3081 *ring->wptr_cpu_addr = 0;
3082 amdgpu_ring_clear_ring(ring);
3083 }
3084
3085 return 0;
3086 }
3087
gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device * adev)3088 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3089 {
3090 int i, r;
3091
3092 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3093 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
3094 if (r)
3095 return r;
3096 }
3097
3098 r = amdgpu_gfx_enable_kgq(adev, 0);
3099 if (r)
3100 return r;
3101
3102 return gfx_v12_0_cp_gfx_start(adev);
3103 }
3104
gfx_v12_0_compute_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)3105 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
3106 struct amdgpu_mqd_prop *prop)
3107 {
3108 struct v12_compute_mqd *mqd = m;
3109 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3110 uint32_t tmp;
3111
3112 mqd->header = 0xC0310800;
3113 mqd->compute_pipelinestat_enable = 0x00000001;
3114 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3115 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3116 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3117 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3118 mqd->compute_misc_reserved = 0x00000007;
3119
3120 eop_base_addr = prop->eop_gpu_addr >> 8;
3121 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3122 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3123
3124 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3125 tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
3126 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3127 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1));
3128
3129 mqd->cp_hqd_eop_control = tmp;
3130
3131 /* enable doorbell? */
3132 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
3133
3134 if (prop->use_doorbell) {
3135 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3136 DOORBELL_OFFSET, prop->doorbell_index);
3137 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3138 DOORBELL_EN, 1);
3139 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3140 DOORBELL_SOURCE, 0);
3141 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3142 DOORBELL_HIT, 0);
3143 } else {
3144 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3145 DOORBELL_EN, 0);
3146 }
3147
3148 mqd->cp_hqd_pq_doorbell_control = tmp;
3149
3150 /* disable the queue if it's active */
3151 mqd->cp_hqd_dequeue_request = 0;
3152 mqd->cp_hqd_pq_rptr = 0;
3153 mqd->cp_hqd_pq_wptr_lo = 0;
3154 mqd->cp_hqd_pq_wptr_hi = 0;
3155
3156 /* set the pointer to the MQD */
3157 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
3158 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3159
3160 /* set MQD vmid to 0 */
3161 tmp = regCP_MQD_CONTROL_DEFAULT;
3162 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3163 mqd->cp_mqd_control = tmp;
3164
3165 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3166 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3167 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3168 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3169
3170 /* set up the HQD, this is similar to CP_RB0_CNTL */
3171 tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
3172 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3173 (order_base_2(prop->queue_size / 4) - 1));
3174 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3175 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3176 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
3177 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3178 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3179 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3180 if (prop->tmz_queue)
3181 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);
3182 mqd->cp_hqd_pq_control = tmp;
3183
3184 /* set the wb address whether it's enabled or not */
3185 wb_gpu_addr = prop->rptr_gpu_addr;
3186 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3187 mqd->cp_hqd_pq_rptr_report_addr_hi =
3188 upper_32_bits(wb_gpu_addr) & 0xffff;
3189
3190 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3191 wb_gpu_addr = prop->wptr_gpu_addr;
3192 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3193 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3194
3195 tmp = 0;
3196 /* enable the doorbell if requested */
3197 if (prop->use_doorbell) {
3198 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
3199 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3200 DOORBELL_OFFSET, prop->doorbell_index);
3201
3202 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3203 DOORBELL_EN, 1);
3204 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3205 DOORBELL_SOURCE, 0);
3206 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3207 DOORBELL_HIT, 0);
3208 }
3209
3210 mqd->cp_hqd_pq_doorbell_control = tmp;
3211
3212 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3213 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT;
3214
3215 /* set the vmid for the queue */
3216 mqd->cp_hqd_vmid = 0;
3217
3218 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
3219 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
3220 mqd->cp_hqd_persistent_state = tmp;
3221
3222 /* set MIN_IB_AVAIL_SIZE */
3223 tmp = regCP_HQD_IB_CONTROL_DEFAULT;
3224 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3225 mqd->cp_hqd_ib_control = tmp;
3226
3227 /* set static priority for a compute queue/ring */
3228 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
3229 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
3230
3231 mqd->cp_hqd_active = prop->hqd_active;
3232
3233 /* set UQ fenceaddress */
3234 mqd->fence_address_lo = lower_32_bits(prop->fence_address);
3235 mqd->fence_address_hi = upper_32_bits(prop->fence_address);
3236
3237 return 0;
3238 }
3239
gfx_v12_0_kiq_init_register(struct amdgpu_ring * ring)3240 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring)
3241 {
3242 struct amdgpu_device *adev = ring->adev;
3243 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3244 int j;
3245
3246 /* inactivate the queue */
3247 if (amdgpu_sriov_vf(adev))
3248 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
3249
3250 /* disable wptr polling */
3251 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3252
3253 /* write the EOP addr */
3254 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,
3255 mqd->cp_hqd_eop_base_addr_lo);
3256 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
3257 mqd->cp_hqd_eop_base_addr_hi);
3258
3259 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3260 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,
3261 mqd->cp_hqd_eop_control);
3262
3263 /* enable doorbell? */
3264 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3265 mqd->cp_hqd_pq_doorbell_control);
3266
3267 /* disable the queue if it's active */
3268 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
3269 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
3270 for (j = 0; j < adev->usec_timeout; j++) {
3271 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
3272 break;
3273 udelay(1);
3274 }
3275 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
3276 mqd->cp_hqd_dequeue_request);
3277 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,
3278 mqd->cp_hqd_pq_rptr);
3279 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3280 mqd->cp_hqd_pq_wptr_lo);
3281 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3282 mqd->cp_hqd_pq_wptr_hi);
3283 }
3284
3285 /* set the pointer to the MQD */
3286 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,
3287 mqd->cp_mqd_base_addr_lo);
3288 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,
3289 mqd->cp_mqd_base_addr_hi);
3290
3291 /* set MQD vmid to 0 */
3292 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,
3293 mqd->cp_mqd_control);
3294
3295 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3296 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,
3297 mqd->cp_hqd_pq_base_lo);
3298 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,
3299 mqd->cp_hqd_pq_base_hi);
3300
3301 /* set up the HQD, this is similar to CP_RB0_CNTL */
3302 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,
3303 mqd->cp_hqd_pq_control);
3304
3305 /* set the wb address whether it's enabled or not */
3306 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
3307 mqd->cp_hqd_pq_rptr_report_addr_lo);
3308 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3309 mqd->cp_hqd_pq_rptr_report_addr_hi);
3310
3311 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3312 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
3313 mqd->cp_hqd_pq_wptr_poll_addr_lo);
3314 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3315 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3316
3317 /* enable the doorbell if requested */
3318 if (ring->use_doorbell) {
3319 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3320 (adev->doorbell_index.kiq * 2) << 2);
3321 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3322 (adev->doorbell_index.userqueue_end * 2) << 2);
3323 }
3324
3325 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3326 mqd->cp_hqd_pq_doorbell_control);
3327
3328 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3329 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3330 mqd->cp_hqd_pq_wptr_lo);
3331 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3332 mqd->cp_hqd_pq_wptr_hi);
3333
3334 /* set the vmid for the queue */
3335 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
3336
3337 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,
3338 mqd->cp_hqd_persistent_state);
3339
3340 /* activate the queue */
3341 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,
3342 mqd->cp_hqd_active);
3343
3344 if (ring->use_doorbell)
3345 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3346
3347 return 0;
3348 }
3349
gfx_v12_0_kiq_init_queue(struct amdgpu_ring * ring)3350 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring)
3351 {
3352 struct amdgpu_device *adev = ring->adev;
3353 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3354 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3355
3356 gfx_v12_0_kiq_setting(ring);
3357
3358 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
3359 /* reset MQD to a clean status */
3360 if (adev->gfx.mec.mqd_backup[mqd_idx])
3361 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3362
3363 /* reset ring buffer */
3364 ring->wptr = 0;
3365 amdgpu_ring_clear_ring(ring);
3366
3367 mutex_lock(&adev->srbm_mutex);
3368 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3369 gfx_v12_0_kiq_init_register(ring);
3370 soc24_grbm_select(adev, 0, 0, 0, 0);
3371 mutex_unlock(&adev->srbm_mutex);
3372 } else {
3373 memset((void *)mqd, 0, sizeof(*mqd));
3374 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
3375 amdgpu_ring_clear_ring(ring);
3376 mutex_lock(&adev->srbm_mutex);
3377 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3378 amdgpu_ring_init_mqd(ring);
3379 gfx_v12_0_kiq_init_register(ring);
3380 soc24_grbm_select(adev, 0, 0, 0, 0);
3381 mutex_unlock(&adev->srbm_mutex);
3382
3383 if (adev->gfx.mec.mqd_backup[mqd_idx])
3384 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3385 }
3386
3387 return 0;
3388 }
3389
gfx_v12_0_kcq_init_queue(struct amdgpu_ring * ring,bool reset)3390 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset)
3391 {
3392 struct amdgpu_device *adev = ring->adev;
3393 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3394 int mqd_idx = ring - &adev->gfx.compute_ring[0];
3395
3396 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
3397 memset((void *)mqd, 0, sizeof(*mqd));
3398 mutex_lock(&adev->srbm_mutex);
3399 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3400 amdgpu_ring_init_mqd(ring);
3401 soc24_grbm_select(adev, 0, 0, 0, 0);
3402 mutex_unlock(&adev->srbm_mutex);
3403
3404 if (adev->gfx.mec.mqd_backup[mqd_idx])
3405 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3406 } else {
3407 /* restore MQD to a clean status */
3408 if (adev->gfx.mec.mqd_backup[mqd_idx])
3409 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3410 /* reset ring buffer */
3411 ring->wptr = 0;
3412 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
3413 amdgpu_ring_clear_ring(ring);
3414 }
3415
3416 return 0;
3417 }
3418
gfx_v12_0_kiq_resume(struct amdgpu_device * adev)3419 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev)
3420 {
3421 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
3422 adev->gfx.kiq[0].ring.sched.ready = true;
3423 return 0;
3424 }
3425
gfx_v12_0_kcq_resume(struct amdgpu_device * adev)3426 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev)
3427 {
3428 int i, r;
3429
3430 if (!amdgpu_async_gfx_ring)
3431 gfx_v12_0_cp_compute_enable(adev, true);
3432
3433 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3434 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false);
3435 if (r)
3436 return r;
3437 }
3438
3439 return amdgpu_gfx_enable_kcq(adev, 0);
3440 }
3441
gfx_v12_0_cp_resume(struct amdgpu_device * adev)3442 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev)
3443 {
3444 int r, i;
3445 struct amdgpu_ring *ring;
3446
3447 if (!(adev->flags & AMD_IS_APU))
3448 gfx_v12_0_enable_gui_idle_interrupt(adev, false);
3449
3450 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3451 /* legacy firmware loading */
3452 r = gfx_v12_0_cp_gfx_load_microcode(adev);
3453 if (r)
3454 return r;
3455
3456 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev);
3457 if (r)
3458 return r;
3459 }
3460
3461 gfx_v12_0_cp_set_doorbell_range(adev);
3462
3463 if (amdgpu_async_gfx_ring) {
3464 gfx_v12_0_cp_compute_enable(adev, true);
3465 gfx_v12_0_cp_gfx_enable(adev, true);
3466 }
3467
3468 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
3469 r = amdgpu_mes_kiq_hw_init(adev);
3470 else
3471 r = gfx_v12_0_kiq_resume(adev);
3472 if (r)
3473 return r;
3474
3475 r = gfx_v12_0_kcq_resume(adev);
3476 if (r)
3477 return r;
3478
3479 if (!amdgpu_async_gfx_ring) {
3480 r = gfx_v12_0_cp_gfx_resume(adev);
3481 if (r)
3482 return r;
3483 } else {
3484 r = gfx_v12_0_cp_async_gfx_ring_resume(adev);
3485 if (r)
3486 return r;
3487 }
3488
3489 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3490 ring = &adev->gfx.gfx_ring[i];
3491 r = amdgpu_ring_test_helper(ring);
3492 if (r)
3493 return r;
3494 }
3495
3496 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3497 ring = &adev->gfx.compute_ring[i];
3498 r = amdgpu_ring_test_helper(ring);
3499 if (r)
3500 return r;
3501 }
3502
3503 return 0;
3504 }
3505
gfx_v12_0_cp_enable(struct amdgpu_device * adev,bool enable)3506 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable)
3507 {
3508 gfx_v12_0_cp_gfx_enable(adev, enable);
3509 gfx_v12_0_cp_compute_enable(adev, enable);
3510 }
3511
gfx_v12_0_gfxhub_enable(struct amdgpu_device * adev)3512 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev)
3513 {
3514 int r;
3515 bool value;
3516
3517 r = adev->gfxhub.funcs->gart_enable(adev);
3518 if (r)
3519 return r;
3520
3521 amdgpu_device_flush_hdp(adev, NULL);
3522
3523 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
3524 false : true;
3525
3526 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
3527 /* TODO investigate why this and the hdp flush above is needed,
3528 * are we missing a flush somewhere else? */
3529 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
3530
3531 return 0;
3532 }
3533
get_gb_addr_config(struct amdgpu_device * adev)3534 static int get_gb_addr_config(struct amdgpu_device *adev)
3535 {
3536 u32 gb_addr_config;
3537
3538 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
3539 if (gb_addr_config == 0)
3540 return -EINVAL;
3541
3542 adev->gfx.config.gb_addr_config_fields.num_pkrs =
3543 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
3544
3545 adev->gfx.config.gb_addr_config = gb_addr_config;
3546
3547 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
3548 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3549 GB_ADDR_CONFIG, NUM_PIPES);
3550
3551 adev->gfx.config.max_tile_pipes =
3552 adev->gfx.config.gb_addr_config_fields.num_pipes;
3553
3554 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
3555 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3556 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
3557 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
3558 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3559 GB_ADDR_CONFIG, NUM_RB_PER_SE);
3560 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
3561 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3562 GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
3563 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
3564 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3565 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
3566
3567 return 0;
3568 }
3569
gfx_v12_0_disable_gpa_mode(struct amdgpu_device * adev)3570 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev)
3571 {
3572 uint32_t data;
3573
3574 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
3575 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
3576 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
3577
3578 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);
3579 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
3580 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
3581 }
3582
gfx_v12_0_init_golden_registers(struct amdgpu_device * adev)3583 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev)
3584 {
3585 if (amdgpu_sriov_vf(adev))
3586 return;
3587
3588 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3589 case IP_VERSION(12, 0, 0):
3590 case IP_VERSION(12, 0, 1):
3591 soc15_program_register_sequence(adev,
3592 golden_settings_gc_12_0,
3593 (const u32)ARRAY_SIZE(golden_settings_gc_12_0));
3594
3595 if (adev->rev_id == 0)
3596 soc15_program_register_sequence(adev,
3597 golden_settings_gc_12_0_rev0,
3598 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0));
3599 break;
3600 default:
3601 break;
3602 }
3603 }
3604
gfx_v12_0_hw_init(struct amdgpu_ip_block * ip_block)3605 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
3606 {
3607 int r;
3608 struct amdgpu_device *adev = ip_block->adev;
3609
3610 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
3611 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
3612 /* RLC autoload sequence 1: Program rlc ram */
3613 if (adev->gfx.imu.funcs->program_rlc_ram)
3614 adev->gfx.imu.funcs->program_rlc_ram(adev);
3615 }
3616 /* rlc autoload firmware */
3617 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev);
3618 if (r)
3619 return r;
3620 } else {
3621 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3622 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
3623 if (adev->gfx.imu.funcs->load_microcode)
3624 adev->gfx.imu.funcs->load_microcode(adev);
3625 if (adev->gfx.imu.funcs->setup_imu)
3626 adev->gfx.imu.funcs->setup_imu(adev);
3627 if (adev->gfx.imu.funcs->start_imu)
3628 adev->gfx.imu.funcs->start_imu(adev);
3629 }
3630
3631 /* disable gpa mode in backdoor loading */
3632 gfx_v12_0_disable_gpa_mode(adev);
3633 }
3634 }
3635
3636 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) ||
3637 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3638 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev);
3639 if (r) {
3640 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r);
3641 return r;
3642 }
3643 }
3644
3645 if (!amdgpu_emu_mode)
3646 gfx_v12_0_init_golden_registers(adev);
3647
3648 adev->gfx.is_poweron = true;
3649
3650 if (get_gb_addr_config(adev))
3651 DRM_WARN("Invalid gb_addr_config !\n");
3652
3653 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
3654 gfx_v12_0_config_gfx_rs64(adev);
3655
3656 r = gfx_v12_0_gfxhub_enable(adev);
3657 if (r)
3658 return r;
3659
3660 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT ||
3661 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) &&
3662 (amdgpu_dpm == 1)) {
3663 /**
3664 * For gfx 12, rlc firmware loading relies on smu firmware is
3665 * loaded firstly, so in direct type, it has to load smc ucode
3666 * here before rlc.
3667 */
3668 r = amdgpu_pm_load_smu_firmware(adev, NULL);
3669 if (r)
3670 return r;
3671 }
3672
3673 gfx_v12_0_constants_init(adev);
3674
3675 if (adev->nbio.funcs->gc_doorbell_init)
3676 adev->nbio.funcs->gc_doorbell_init(adev);
3677
3678 r = gfx_v12_0_rlc_resume(adev);
3679 if (r)
3680 return r;
3681
3682 /*
3683 * init golden registers and rlc resume may override some registers,
3684 * reconfig them here
3685 */
3686 gfx_v12_0_tcp_harvest(adev);
3687
3688 r = gfx_v12_0_cp_resume(adev);
3689 if (r)
3690 return r;
3691
3692 return r;
3693 }
3694
gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device * adev,bool enable)3695 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
3696 bool enable)
3697 {
3698 unsigned int irq_type;
3699 int m, p, r;
3700
3701 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
3702 for (m = 0; m < adev->gfx.me.num_me; m++) {
3703 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
3704 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
3705 if (enable)
3706 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,
3707 irq_type);
3708 else
3709 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,
3710 irq_type);
3711 if (r)
3712 return r;
3713 }
3714 }
3715 }
3716
3717 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
3718 for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
3719 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
3720 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
3721 + (m * adev->gfx.mec.num_pipe_per_mec)
3722 + p;
3723 if (enable)
3724 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,
3725 irq_type);
3726 else
3727 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,
3728 irq_type);
3729 if (r)
3730 return r;
3731 }
3732 }
3733 }
3734
3735 return 0;
3736 }
3737
gfx_v12_0_hw_fini(struct amdgpu_ip_block * ip_block)3738 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
3739 {
3740 struct amdgpu_device *adev = ip_block->adev;
3741 uint32_t tmp;
3742
3743 cancel_delayed_work_sync(&adev->gfx.idle_work);
3744
3745 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3746 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3747 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
3748 gfx_v12_0_set_userq_eop_interrupts(adev, false);
3749
3750 if (!adev->no_hw_access) {
3751 if (amdgpu_async_gfx_ring) {
3752 if (amdgpu_gfx_disable_kgq(adev, 0))
3753 DRM_ERROR("KGQ disable failed\n");
3754 }
3755
3756 if (amdgpu_gfx_disable_kcq(adev, 0))
3757 DRM_ERROR("KCQ disable failed\n");
3758
3759 amdgpu_mes_kiq_hw_fini(adev);
3760 }
3761
3762 if (amdgpu_sriov_vf(adev)) {
3763 gfx_v12_0_cp_gfx_enable(adev, false);
3764 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
3765 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
3766 tmp &= 0xffffff00;
3767 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3768
3769 return 0;
3770 }
3771 gfx_v12_0_cp_enable(adev, false);
3772 gfx_v12_0_enable_gui_idle_interrupt(adev, false);
3773
3774 adev->gfxhub.funcs->gart_disable(adev);
3775
3776 adev->gfx.is_poweron = false;
3777
3778 return 0;
3779 }
3780
gfx_v12_0_suspend(struct amdgpu_ip_block * ip_block)3781 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block)
3782 {
3783 return gfx_v12_0_hw_fini(ip_block);
3784 }
3785
gfx_v12_0_resume(struct amdgpu_ip_block * ip_block)3786 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block)
3787 {
3788 return gfx_v12_0_hw_init(ip_block);
3789 }
3790
gfx_v12_0_is_idle(struct amdgpu_ip_block * ip_block)3791 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
3792 {
3793 struct amdgpu_device *adev = ip_block->adev;
3794
3795 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
3796 GRBM_STATUS, GUI_ACTIVE))
3797 return false;
3798 else
3799 return true;
3800 }
3801
gfx_v12_0_wait_for_idle(struct amdgpu_ip_block * ip_block)3802 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
3803 {
3804 unsigned i;
3805 u32 tmp;
3806 struct amdgpu_device *adev = ip_block->adev;
3807
3808 for (i = 0; i < adev->usec_timeout; i++) {
3809 /* read MC_STATUS */
3810 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
3811 GRBM_STATUS__GUI_ACTIVE_MASK;
3812
3813 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3814 return 0;
3815 udelay(1);
3816 }
3817 return -ETIMEDOUT;
3818 }
3819
gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device * adev)3820 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3821 {
3822 uint64_t clock = 0;
3823
3824 if (adev->smuio.funcs &&
3825 adev->smuio.funcs->get_gpu_clock_counter)
3826 clock = adev->smuio.funcs->get_gpu_clock_counter(adev);
3827 else
3828 dev_warn(adev->dev, "query gpu clock counter is not supported\n");
3829
3830 return clock;
3831 }
3832
gfx_v12_0_early_init(struct amdgpu_ip_block * ip_block)3833 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block)
3834 {
3835 struct amdgpu_device *adev = ip_block->adev;
3836
3837 switch (amdgpu_user_queue) {
3838 case -1:
3839 case 0:
3840 default:
3841 adev->gfx.disable_kq = false;
3842 adev->gfx.disable_uq = true;
3843 break;
3844 case 1:
3845 adev->gfx.disable_kq = false;
3846 adev->gfx.disable_uq = false;
3847 break;
3848 case 2:
3849 adev->gfx.disable_kq = true;
3850 adev->gfx.disable_uq = false;
3851 break;
3852 }
3853
3854 adev->gfx.funcs = &gfx_v12_0_gfx_funcs;
3855
3856 if (adev->gfx.disable_kq) {
3857 adev->gfx.num_gfx_rings = 0;
3858 adev->gfx.num_compute_rings = 0;
3859 } else {
3860 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS;
3861 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
3862 AMDGPU_MAX_COMPUTE_RINGS);
3863 }
3864
3865 gfx_v12_0_set_kiq_pm4_funcs(adev);
3866 gfx_v12_0_set_ring_funcs(adev);
3867 gfx_v12_0_set_irq_funcs(adev);
3868 gfx_v12_0_set_rlc_funcs(adev);
3869 gfx_v12_0_set_mqd_funcs(adev);
3870 gfx_v12_0_set_imu_funcs(adev);
3871
3872 gfx_v12_0_init_rlcg_reg_access_ctrl(adev);
3873
3874 return gfx_v12_0_init_microcode(adev);
3875 }
3876
gfx_v12_0_late_init(struct amdgpu_ip_block * ip_block)3877 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block)
3878 {
3879 struct amdgpu_device *adev = ip_block->adev;
3880 int r;
3881
3882 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3883 if (r)
3884 return r;
3885
3886 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3887 if (r)
3888 return r;
3889
3890 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
3891 if (r)
3892 return r;
3893
3894 r = gfx_v12_0_set_userq_eop_interrupts(adev, true);
3895 if (r)
3896 return r;
3897
3898 return 0;
3899 }
3900
gfx_v12_0_is_rlc_enabled(struct amdgpu_device * adev)3901 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev)
3902 {
3903 uint32_t rlc_cntl;
3904
3905 /* if RLC is not enabled, do nothing */
3906 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);
3907 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
3908 }
3909
gfx_v12_0_set_safe_mode(struct amdgpu_device * adev,int xcc_id)3910 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev,
3911 int xcc_id)
3912 {
3913 uint32_t data;
3914 unsigned i;
3915
3916 data = RLC_SAFE_MODE__CMD_MASK;
3917 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3918
3919 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
3920
3921 /* wait for RLC_SAFE_MODE */
3922 for (i = 0; i < adev->usec_timeout; i++) {
3923 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
3924 RLC_SAFE_MODE, CMD))
3925 break;
3926 udelay(1);
3927 }
3928 }
3929
gfx_v12_0_unset_safe_mode(struct amdgpu_device * adev,int xcc_id)3930 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev,
3931 int xcc_id)
3932 {
3933 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
3934 }
3935
gfx_v12_0_update_perf_clk(struct amdgpu_device * adev,bool enable)3936 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
3937 bool enable)
3938 {
3939 uint32_t def, data;
3940
3941 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
3942 return;
3943
3944 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
3945
3946 if (enable)
3947 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
3948 else
3949 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
3950
3951 if (def != data)
3952 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
3953 }
3954
gfx_v12_0_update_spm_vmid(struct amdgpu_device * adev,struct amdgpu_ring * ring,unsigned vmid)3955 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev,
3956 struct amdgpu_ring *ring,
3957 unsigned vmid)
3958 {
3959 u32 reg, data;
3960
3961 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
3962 if (amdgpu_sriov_is_pp_one_vf(adev))
3963 data = RREG32_NO_KIQ(reg);
3964 else
3965 data = RREG32(reg);
3966
3967 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
3968 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
3969
3970 if (amdgpu_sriov_is_pp_one_vf(adev))
3971 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
3972 else
3973 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
3974
3975 if (ring
3976 && amdgpu_sriov_is_pp_one_vf(adev)
3977 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX)
3978 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
3979 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
3980 amdgpu_ring_emit_wreg(ring, reg, data);
3981 }
3982 }
3983
3984 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = {
3985 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled,
3986 .set_safe_mode = gfx_v12_0_set_safe_mode,
3987 .unset_safe_mode = gfx_v12_0_unset_safe_mode,
3988 .init = gfx_v12_0_rlc_init,
3989 .get_csb_size = gfx_v12_0_get_csb_size,
3990 .get_csb_buffer = gfx_v12_0_get_csb_buffer,
3991 .resume = gfx_v12_0_rlc_resume,
3992 .stop = gfx_v12_0_rlc_stop,
3993 .reset = gfx_v12_0_rlc_reset,
3994 .start = gfx_v12_0_rlc_start,
3995 .update_spm_vmid = gfx_v12_0_update_spm_vmid,
3996 };
3997
3998 #if 0
3999 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable)
4000 {
4001 /* TODO */
4002 }
4003
4004 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable)
4005 {
4006 /* TODO */
4007 }
4008 #endif
4009
gfx_v12_0_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)4010 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
4011 enum amd_powergating_state state)
4012 {
4013 struct amdgpu_device *adev = ip_block->adev;
4014 bool enable = (state == AMD_PG_STATE_GATE);
4015
4016 if (amdgpu_sriov_vf(adev))
4017 return 0;
4018
4019 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4020 case IP_VERSION(12, 0, 0):
4021 case IP_VERSION(12, 0, 1):
4022 amdgpu_gfx_off_ctrl(adev, enable);
4023 break;
4024 default:
4025 break;
4026 }
4027
4028 return 0;
4029 }
4030
gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)4031 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4032 bool enable)
4033 {
4034 uint32_t def, data;
4035
4036 if (!(adev->cg_flags &
4037 (AMD_CG_SUPPORT_GFX_CGCG |
4038 AMD_CG_SUPPORT_GFX_CGLS |
4039 AMD_CG_SUPPORT_GFX_3D_CGCG |
4040 AMD_CG_SUPPORT_GFX_3D_CGLS)))
4041 return;
4042
4043 if (enable) {
4044 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4045
4046 /* unset CGCG override */
4047 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4048 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4049 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4050 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4051 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG ||
4052 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4053 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4054
4055 /* update CGCG override bits */
4056 if (def != data)
4057 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4058
4059 /* enable cgcg FSM(0x0000363F) */
4060 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4061
4062 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
4063 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK;
4064 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4065 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4066 }
4067
4068 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
4069 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK;
4070 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4071 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4072 }
4073
4074 if (def != data)
4075 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4076
4077 /* Program RLC_CGCG_CGLS_CTRL_3D */
4078 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4079
4080 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
4081 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK;
4082 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4083 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4084 }
4085
4086 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
4087 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK;
4088 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4089 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4090 }
4091
4092 if (def != data)
4093 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4094
4095 /* set IDLE_POLL_COUNT(0x00900100) */
4096 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
4097
4098 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK);
4099 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4100 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4101
4102 if (def != data)
4103 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
4104
4105 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4106 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4107 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4108 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4109 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4110 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);
4111
4112 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4113 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4114 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4115
4116 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4117 if (adev->sdma.num_instances > 1) {
4118 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4119 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4120 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4121 }
4122 } else {
4123 /* Program RLC_CGCG_CGLS_CTRL */
4124 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4125
4126 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4127 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4128
4129 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4130 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4131
4132 if (def != data)
4133 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4134
4135 /* Program RLC_CGCG_CGLS_CTRL_3D */
4136 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4137
4138 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
4139 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4140 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4141 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4142
4143 if (def != data)
4144 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4145 }
4146 }
4147
gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)4148 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4149 bool enable)
4150 {
4151 uint32_t data, def;
4152 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
4153 return;
4154
4155 /* It is disabled by HW by default */
4156 if (enable) {
4157 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4158 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4159 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4160
4161 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4162 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4163 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4164
4165 if (def != data)
4166 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4167 }
4168 } else {
4169 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4170 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4171
4172 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4173 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4174 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4175
4176 if (def != data)
4177 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4178 }
4179 }
4180 }
4181
gfx_v12_0_update_repeater_fgcg(struct amdgpu_device * adev,bool enable)4182 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev,
4183 bool enable)
4184 {
4185 uint32_t def, data;
4186
4187 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
4188 return;
4189
4190 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4191
4192 if (enable)
4193 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |
4194 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK);
4195 else
4196 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |
4197 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK;
4198
4199 if (def != data)
4200 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4201 }
4202
gfx_v12_0_update_sram_fgcg(struct amdgpu_device * adev,bool enable)4203 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev,
4204 bool enable)
4205 {
4206 uint32_t def, data;
4207
4208 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
4209 return;
4210
4211 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4212
4213 if (enable)
4214 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4215 else
4216 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4217
4218 if (def != data)
4219 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4220 }
4221
gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)4222 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4223 bool enable)
4224 {
4225 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4226
4227 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable);
4228
4229 gfx_v12_0_update_medium_grain_clock_gating(adev, enable);
4230
4231 gfx_v12_0_update_repeater_fgcg(adev, enable);
4232
4233 gfx_v12_0_update_sram_fgcg(adev, enable);
4234
4235 gfx_v12_0_update_perf_clk(adev, enable);
4236
4237 if (adev->cg_flags &
4238 (AMD_CG_SUPPORT_GFX_MGCG |
4239 AMD_CG_SUPPORT_GFX_CGLS |
4240 AMD_CG_SUPPORT_GFX_CGCG |
4241 AMD_CG_SUPPORT_GFX_3D_CGCG |
4242 AMD_CG_SUPPORT_GFX_3D_CGLS))
4243 gfx_v12_0_enable_gui_idle_interrupt(adev, enable);
4244
4245 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4246
4247 return 0;
4248 }
4249
gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)4250 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
4251 enum amd_clockgating_state state)
4252 {
4253 struct amdgpu_device *adev = ip_block->adev;
4254
4255 if (amdgpu_sriov_vf(adev))
4256 return 0;
4257
4258 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4259 case IP_VERSION(12, 0, 0):
4260 case IP_VERSION(12, 0, 1):
4261 gfx_v12_0_update_gfx_clock_gating(adev,
4262 state == AMD_CG_STATE_GATE);
4263 break;
4264 default:
4265 break;
4266 }
4267
4268 return 0;
4269 }
4270
gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)4271 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
4272 {
4273 struct amdgpu_device *adev = ip_block->adev;
4274 int data;
4275
4276 /* AMD_CG_SUPPORT_GFX_MGCG */
4277 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4278 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4279 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
4280
4281 /* AMD_CG_SUPPORT_REPEATER_FGCG */
4282 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))
4283 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG;
4284
4285 /* AMD_CG_SUPPORT_GFX_FGCG */
4286 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
4287 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
4288
4289 /* AMD_CG_SUPPORT_GFX_PERF_CLK */
4290 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))
4291 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;
4292
4293 /* AMD_CG_SUPPORT_GFX_CGCG */
4294 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4295 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4296 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
4297
4298 /* AMD_CG_SUPPORT_GFX_CGLS */
4299 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4300 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
4301
4302 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
4303 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4304 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4305 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4306
4307 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
4308 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4309 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4310 }
4311
gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring * ring)4312 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4313 {
4314 /* gfx12 is 32bit rptr*/
4315 return *(uint32_t *)ring->rptr_cpu_addr;
4316 }
4317
gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)4318 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4319 {
4320 struct amdgpu_device *adev = ring->adev;
4321 u64 wptr;
4322
4323 /* XXX check if swapping is necessary on BE */
4324 if (ring->use_doorbell) {
4325 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
4326 } else {
4327 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);
4328 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;
4329 }
4330
4331 return wptr;
4332 }
4333
gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)4334 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4335 {
4336 struct amdgpu_device *adev = ring->adev;
4337
4338 if (ring->use_doorbell) {
4339 /* XXX check if swapping is necessary on BE */
4340 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
4341 ring->wptr);
4342 WDOORBELL64(ring->doorbell_index, ring->wptr);
4343 } else {
4344 WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
4345 lower_32_bits(ring->wptr));
4346 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
4347 upper_32_bits(ring->wptr));
4348 }
4349 }
4350
gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring * ring)4351 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4352 {
4353 /* gfx12 hardware is 32bit rptr */
4354 return *(uint32_t *)ring->rptr_cpu_addr;
4355 }
4356
gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring * ring)4357 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4358 {
4359 u64 wptr;
4360
4361 /* XXX check if swapping is necessary on BE */
4362 if (ring->use_doorbell)
4363 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
4364 else
4365 BUG();
4366 return wptr;
4367 }
4368
gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring * ring)4369 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4370 {
4371 struct amdgpu_device *adev = ring->adev;
4372
4373 /* XXX check if swapping is necessary on BE */
4374 if (ring->use_doorbell) {
4375 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
4376 ring->wptr);
4377 WDOORBELL64(ring->doorbell_index, ring->wptr);
4378 } else {
4379 BUG(); /* only DOORBELL method supported on gfx12 now */
4380 }
4381 }
4382
gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)4383 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4384 {
4385 struct amdgpu_device *adev = ring->adev;
4386 u32 ref_and_mask, reg_mem_engine;
4387 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
4388
4389 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4390 switch (ring->me) {
4391 case 1:
4392 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4393 break;
4394 case 2:
4395 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4396 break;
4397 default:
4398 return;
4399 }
4400 reg_mem_engine = 0;
4401 } else {
4402 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4403 reg_mem_engine = 1; /* pfp */
4404 }
4405
4406 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4407 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4408 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
4409 ref_and_mask, ref_and_mask, 0x20);
4410 }
4411
gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)4412 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4413 struct amdgpu_job *job,
4414 struct amdgpu_ib *ib,
4415 uint32_t flags)
4416 {
4417 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4418 u32 header, control = 0;
4419
4420 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE);
4421
4422 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4423
4424 control |= ib->length_dw | (vmid << 24);
4425
4426 amdgpu_ring_write(ring, header);
4427 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4428 amdgpu_ring_write(ring,
4429 #ifdef __BIG_ENDIAN
4430 (2 << 0) |
4431 #endif
4432 lower_32_bits(ib->gpu_addr));
4433 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4434 amdgpu_ring_write(ring, control);
4435 }
4436
gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)4437 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4438 struct amdgpu_job *job,
4439 struct amdgpu_ib *ib,
4440 uint32_t flags)
4441 {
4442 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4443 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4444
4445 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4446 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4447 amdgpu_ring_write(ring,
4448 #ifdef __BIG_ENDIAN
4449 (2 << 0) |
4450 #endif
4451 lower_32_bits(ib->gpu_addr));
4452 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4453 amdgpu_ring_write(ring, control);
4454 }
4455
gfx_v12_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)4456 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4457 u64 seq, unsigned flags)
4458 {
4459 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4460 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4461
4462 /* RELEASE_MEM - flush caches, send int */
4463 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4464 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4465 PACKET3_RELEASE_MEM_GCR_GL2_WB |
4466 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4467 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4468 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
4469 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
4470 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
4471
4472 /*
4473 * the address should be Qword aligned if 64bit write, Dword
4474 * aligned if only send 32bit data low (discard data high)
4475 */
4476 if (write64bit)
4477 BUG_ON(addr & 0x7);
4478 else
4479 BUG_ON(addr & 0x3);
4480 amdgpu_ring_write(ring, lower_32_bits(addr));
4481 amdgpu_ring_write(ring, upper_32_bits(addr));
4482 amdgpu_ring_write(ring, lower_32_bits(seq));
4483 amdgpu_ring_write(ring, upper_32_bits(seq));
4484 amdgpu_ring_write(ring, 0);
4485 }
4486
gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)4487 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4488 {
4489 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4490 uint32_t seq = ring->fence_drv.sync_seq;
4491 uint64_t addr = ring->fence_drv.gpu_addr;
4492
4493 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
4494 upper_32_bits(addr), seq, 0xffffffff, 4);
4495 }
4496
gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring * ring,uint16_t pasid,uint32_t flush_type,bool all_hub,uint8_t dst_sel)4497 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
4498 uint16_t pasid, uint32_t flush_type,
4499 bool all_hub, uint8_t dst_sel)
4500 {
4501 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
4502 amdgpu_ring_write(ring,
4503 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
4504 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
4505 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
4506 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
4507 }
4508
gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)4509 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4510 unsigned vmid, uint64_t pd_addr)
4511 {
4512 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4513
4514 /* compute doesn't have PFP */
4515 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4516 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4517 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4518 amdgpu_ring_write(ring, 0x0);
4519 }
4520 }
4521
gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)4522 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4523 u64 seq, unsigned int flags)
4524 {
4525 struct amdgpu_device *adev = ring->adev;
4526
4527 /* we only allocate 32bit for each seq wb address */
4528 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4529
4530 /* write fence seq to the "addr" */
4531 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4532 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4533 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4534 amdgpu_ring_write(ring, lower_32_bits(addr));
4535 amdgpu_ring_write(ring, upper_32_bits(addr));
4536 amdgpu_ring_write(ring, lower_32_bits(seq));
4537
4538 if (flags & AMDGPU_FENCE_FLAG_INT) {
4539 /* set register to trigger INT */
4540 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4541 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4542 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4543 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
4544 amdgpu_ring_write(ring, 0);
4545 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4546 }
4547 }
4548
gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)4549 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
4550 uint32_t flags)
4551 {
4552 uint32_t dw2 = 0;
4553
4554 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4555 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4556 /* set load_global_config & load_global_uconfig */
4557 dw2 |= 0x8001;
4558 /* set load_cs_sh_regs */
4559 dw2 |= 0x01000000;
4560 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4561 dw2 |= 0x10002;
4562 }
4563
4564 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4565 amdgpu_ring_write(ring, dw2);
4566 amdgpu_ring_write(ring, 0);
4567 }
4568
gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)4569 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
4570 uint64_t addr)
4571 {
4572 unsigned ret;
4573
4574 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4575 amdgpu_ring_write(ring, lower_32_bits(addr));
4576 amdgpu_ring_write(ring, upper_32_bits(addr));
4577 /* discard following DWs if *cond_exec_gpu_addr==0 */
4578 amdgpu_ring_write(ring, 0);
4579 ret = ring->wptr & ring->buf_mask;
4580 /* patch dummy value later */
4581 amdgpu_ring_write(ring, 0);
4582
4583 return ret;
4584 }
4585
gfx_v12_0_ring_preempt_ib(struct amdgpu_ring * ring)4586 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring)
4587 {
4588 int i, r = 0;
4589 struct amdgpu_device *adev = ring->adev;
4590 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
4591 struct amdgpu_ring *kiq_ring = &kiq->ring;
4592 unsigned long flags;
4593
4594 if (adev->enable_mes)
4595 return -EINVAL;
4596
4597 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4598 return -EINVAL;
4599
4600 spin_lock_irqsave(&kiq->ring_lock, flags);
4601
4602 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
4603 spin_unlock_irqrestore(&kiq->ring_lock, flags);
4604 return -ENOMEM;
4605 }
4606
4607 /* assert preemption condition */
4608 amdgpu_ring_set_preempt_cond_exec(ring, false);
4609
4610 /* assert IB preemption, emit the trailing fence */
4611 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
4612 ring->trail_fence_gpu_addr,
4613 ++ring->trail_seq);
4614 amdgpu_ring_commit(kiq_ring);
4615
4616 spin_unlock_irqrestore(&kiq->ring_lock, flags);
4617
4618 /* poll the trailing fence */
4619 for (i = 0; i < adev->usec_timeout; i++) {
4620 if (ring->trail_seq ==
4621 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
4622 break;
4623 udelay(1);
4624 }
4625
4626 if (i >= adev->usec_timeout) {
4627 r = -EINVAL;
4628 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
4629 }
4630
4631 /* deassert preemption condition */
4632 amdgpu_ring_set_preempt_cond_exec(ring, true);
4633 return r;
4634 }
4635
gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring * ring,bool start,bool secure)4636 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring,
4637 bool start,
4638 bool secure)
4639 {
4640 uint32_t v = secure ? FRAME_TMZ : 0;
4641
4642 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4643 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
4644 }
4645
gfx_v12_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t reg_val_offs)4646 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
4647 uint32_t reg_val_offs)
4648 {
4649 struct amdgpu_device *adev = ring->adev;
4650
4651 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4652 amdgpu_ring_write(ring, 0 | /* src: register*/
4653 (5 << 8) | /* dst: memory */
4654 (1 << 20)); /* write confirm */
4655 amdgpu_ring_write(ring, reg);
4656 amdgpu_ring_write(ring, 0);
4657 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4658 reg_val_offs * 4));
4659 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4660 reg_val_offs * 4));
4661 }
4662
gfx_v12_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)4663 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring,
4664 uint32_t reg,
4665 uint32_t val)
4666 {
4667 uint32_t cmd = 0;
4668
4669 switch (ring->funcs->type) {
4670 case AMDGPU_RING_TYPE_GFX:
4671 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4672 break;
4673 case AMDGPU_RING_TYPE_KIQ:
4674 cmd = (1 << 16); /* no inc addr */
4675 break;
4676 default:
4677 cmd = WR_CONFIRM;
4678 break;
4679 }
4680 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4681 amdgpu_ring_write(ring, cmd);
4682 amdgpu_ring_write(ring, reg);
4683 amdgpu_ring_write(ring, 0);
4684 amdgpu_ring_write(ring, val);
4685 }
4686
gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)4687 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4688 uint32_t val, uint32_t mask)
4689 {
4690 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4691 }
4692
gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)4693 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4694 uint32_t reg0, uint32_t reg1,
4695 uint32_t ref, uint32_t mask)
4696 {
4697 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4698
4699 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4700 ref, mask, 0x20);
4701 }
4702
4703 static void
gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,uint32_t me,uint32_t pipe,enum amdgpu_interrupt_state state)4704 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4705 uint32_t me, uint32_t pipe,
4706 enum amdgpu_interrupt_state state)
4707 {
4708 uint32_t cp_int_cntl, cp_int_cntl_reg;
4709
4710 if (!me) {
4711 switch (pipe) {
4712 case 0:
4713 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
4714 break;
4715 default:
4716 DRM_DEBUG("invalid pipe %d\n", pipe);
4717 return;
4718 }
4719 } else {
4720 DRM_DEBUG("invalid me %d\n", me);
4721 return;
4722 }
4723
4724 switch (state) {
4725 case AMDGPU_IRQ_STATE_DISABLE:
4726 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4727 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4728 TIME_STAMP_INT_ENABLE, 0);
4729 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4730 GENERIC0_INT_ENABLE, 0);
4731 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4732 break;
4733 case AMDGPU_IRQ_STATE_ENABLE:
4734 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4735 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4736 TIME_STAMP_INT_ENABLE, 1);
4737 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4738 GENERIC0_INT_ENABLE, 1);
4739 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4740 break;
4741 default:
4742 break;
4743 }
4744 }
4745
gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)4746 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4747 int me, int pipe,
4748 enum amdgpu_interrupt_state state)
4749 {
4750 u32 mec_int_cntl, mec_int_cntl_reg;
4751
4752 /*
4753 * amdgpu controls only the first MEC. That's why this function only
4754 * handles the setting of interrupts for this specific MEC. All other
4755 * pipes' interrupts are set by amdkfd.
4756 */
4757
4758 if (me == 1) {
4759 switch (pipe) {
4760 case 0:
4761 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
4762 break;
4763 case 1:
4764 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
4765 break;
4766 default:
4767 DRM_DEBUG("invalid pipe %d\n", pipe);
4768 return;
4769 }
4770 } else {
4771 DRM_DEBUG("invalid me %d\n", me);
4772 return;
4773 }
4774
4775 switch (state) {
4776 case AMDGPU_IRQ_STATE_DISABLE:
4777 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
4778 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4779 TIME_STAMP_INT_ENABLE, 0);
4780 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4781 GENERIC0_INT_ENABLE, 0);
4782 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
4783 break;
4784 case AMDGPU_IRQ_STATE_ENABLE:
4785 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
4786 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4787 TIME_STAMP_INT_ENABLE, 1);
4788 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4789 GENERIC0_INT_ENABLE, 1);
4790 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
4791 break;
4792 default:
4793 break;
4794 }
4795 }
4796
gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)4797 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4798 struct amdgpu_irq_src *src,
4799 unsigned type,
4800 enum amdgpu_interrupt_state state)
4801 {
4802 switch (type) {
4803 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4804 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
4805 break;
4806 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
4807 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
4808 break;
4809 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4810 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4811 break;
4812 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4813 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4814 break;
4815 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4816 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4817 break;
4818 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4819 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4820 break;
4821 default:
4822 break;
4823 }
4824 return 0;
4825 }
4826
gfx_v12_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4827 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev,
4828 struct amdgpu_irq_src *source,
4829 struct amdgpu_iv_entry *entry)
4830 {
4831 u32 doorbell_offset = entry->src_data[0];
4832 u8 me_id, pipe_id, queue_id;
4833 struct amdgpu_ring *ring;
4834 int i;
4835
4836 DRM_DEBUG("IH: CP EOP\n");
4837
4838 if (adev->enable_mes && doorbell_offset) {
4839 struct amdgpu_userq_fence_driver *fence_drv = NULL;
4840 struct xarray *xa = &adev->userq_xa;
4841 unsigned long flags;
4842
4843 xa_lock_irqsave(xa, flags);
4844 fence_drv = xa_load(xa, doorbell_offset);
4845 if (fence_drv)
4846 amdgpu_userq_fence_driver_process(fence_drv);
4847 xa_unlock_irqrestore(xa, flags);
4848 } else {
4849 me_id = (entry->ring_id & 0x0c) >> 2;
4850 pipe_id = (entry->ring_id & 0x03) >> 0;
4851 queue_id = (entry->ring_id & 0x70) >> 4;
4852
4853 switch (me_id) {
4854 case 0:
4855 if (pipe_id == 0)
4856 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4857 else
4858 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
4859 break;
4860 case 1:
4861 case 2:
4862 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4863 ring = &adev->gfx.compute_ring[i];
4864 /* Per-queue interrupt is supported for MEC starting from VI.
4865 * The interrupt can only be enabled/disabled per pipe instead
4866 * of per queue.
4867 */
4868 if ((ring->me == me_id) &&
4869 (ring->pipe == pipe_id) &&
4870 (ring->queue == queue_id))
4871 amdgpu_fence_process(ring);
4872 }
4873 break;
4874 }
4875 }
4876
4877 return 0;
4878 }
4879
gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)4880 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4881 struct amdgpu_irq_src *source,
4882 unsigned int type,
4883 enum amdgpu_interrupt_state state)
4884 {
4885 u32 cp_int_cntl_reg, cp_int_cntl;
4886 int i, j;
4887
4888 switch (state) {
4889 case AMDGPU_IRQ_STATE_DISABLE:
4890 case AMDGPU_IRQ_STATE_ENABLE:
4891 for (i = 0; i < adev->gfx.me.num_me; i++) {
4892 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4893 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4894
4895 if (cp_int_cntl_reg) {
4896 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4897 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4898 PRIV_REG_INT_ENABLE,
4899 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4900 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4901 }
4902 }
4903 }
4904 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
4905 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
4906 /* MECs start at 1 */
4907 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);
4908
4909 if (cp_int_cntl_reg) {
4910 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4911 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4912 PRIV_REG_INT_ENABLE,
4913 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4914 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4915 }
4916 }
4917 }
4918 break;
4919 default:
4920 break;
4921 }
4922
4923 return 0;
4924 }
4925
gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)4926 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev,
4927 struct amdgpu_irq_src *source,
4928 unsigned type,
4929 enum amdgpu_interrupt_state state)
4930 {
4931 u32 cp_int_cntl_reg, cp_int_cntl;
4932 int i, j;
4933
4934 switch (state) {
4935 case AMDGPU_IRQ_STATE_DISABLE:
4936 case AMDGPU_IRQ_STATE_ENABLE:
4937 for (i = 0; i < adev->gfx.me.num_me; i++) {
4938 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4939 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4940
4941 if (cp_int_cntl_reg) {
4942 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4943 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4944 OPCODE_ERROR_INT_ENABLE,
4945 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4946 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4947 }
4948 }
4949 }
4950 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
4951 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
4952 /* MECs start at 1 */
4953 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);
4954
4955 if (cp_int_cntl_reg) {
4956 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4957 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4958 OPCODE_ERROR_INT_ENABLE,
4959 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4960 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4961 }
4962 }
4963 }
4964 break;
4965 default:
4966 break;
4967 }
4968 return 0;
4969 }
4970
gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)4971 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4972 struct amdgpu_irq_src *source,
4973 unsigned int type,
4974 enum amdgpu_interrupt_state state)
4975 {
4976 u32 cp_int_cntl_reg, cp_int_cntl;
4977 int i, j;
4978
4979 switch (state) {
4980 case AMDGPU_IRQ_STATE_DISABLE:
4981 case AMDGPU_IRQ_STATE_ENABLE:
4982 for (i = 0; i < adev->gfx.me.num_me; i++) {
4983 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4984 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4985
4986 if (cp_int_cntl_reg) {
4987 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4988 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4989 PRIV_INSTR_INT_ENABLE,
4990 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4991 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4992 }
4993 }
4994 }
4995 break;
4996 default:
4997 break;
4998 }
4999
5000 return 0;
5001 }
5002
gfx_v12_0_handle_priv_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)5003 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev,
5004 struct amdgpu_iv_entry *entry)
5005 {
5006 u8 me_id, pipe_id, queue_id;
5007 struct amdgpu_ring *ring;
5008 int i;
5009
5010 me_id = (entry->ring_id & 0x0c) >> 2;
5011 pipe_id = (entry->ring_id & 0x03) >> 0;
5012 queue_id = (entry->ring_id & 0x70) >> 4;
5013
5014 if (!adev->gfx.disable_kq) {
5015 switch (me_id) {
5016 case 0:
5017 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5018 ring = &adev->gfx.gfx_ring[i];
5019 if (ring->me == me_id && ring->pipe == pipe_id &&
5020 ring->queue == queue_id)
5021 drm_sched_fault(&ring->sched);
5022 }
5023 break;
5024 case 1:
5025 case 2:
5026 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5027 ring = &adev->gfx.compute_ring[i];
5028 if (ring->me == me_id && ring->pipe == pipe_id &&
5029 ring->queue == queue_id)
5030 drm_sched_fault(&ring->sched);
5031 }
5032 break;
5033 default:
5034 BUG();
5035 break;
5036 }
5037 }
5038 }
5039
gfx_v12_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5040 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev,
5041 struct amdgpu_irq_src *source,
5042 struct amdgpu_iv_entry *entry)
5043 {
5044 DRM_ERROR("Illegal register access in command stream\n");
5045 gfx_v12_0_handle_priv_fault(adev, entry);
5046 return 0;
5047 }
5048
gfx_v12_0_bad_op_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5049 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev,
5050 struct amdgpu_irq_src *source,
5051 struct amdgpu_iv_entry *entry)
5052 {
5053 DRM_ERROR("Illegal opcode in command stream \n");
5054 gfx_v12_0_handle_priv_fault(adev, entry);
5055 return 0;
5056 }
5057
gfx_v12_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5058 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev,
5059 struct amdgpu_irq_src *source,
5060 struct amdgpu_iv_entry *entry)
5061 {
5062 DRM_ERROR("Illegal instruction in command stream\n");
5063 gfx_v12_0_handle_priv_fault(adev, entry);
5064 return 0;
5065 }
5066
gfx_v12_0_emit_mem_sync(struct amdgpu_ring * ring)5067 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring)
5068 {
5069 const unsigned int gcr_cntl =
5070 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
5071 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
5072 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
5073 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
5074 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
5075 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
5076 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
5077 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
5078
5079 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
5080 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
5081 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
5082 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
5083 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
5084 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
5085 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
5086 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
5087 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
5088 }
5089
gfx_v12_ring_insert_nop(struct amdgpu_ring * ring,uint32_t num_nop)5090 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
5091 {
5092 /* Header itself is a NOP packet */
5093 if (num_nop == 1) {
5094 amdgpu_ring_write(ring, ring->funcs->nop);
5095 return;
5096 }
5097
5098 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/
5099 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));
5100
5101 /* Header is at index 0, followed by num_nops - 1 NOP packet's */
5102 amdgpu_ring_insert_nop(ring, num_nop - 1);
5103 }
5104
gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring * ring)5105 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
5106 {
5107 /* Emit the cleaner shader */
5108 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
5109 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */
5110 }
5111
gfx_v12_ip_print(struct amdgpu_ip_block * ip_block,struct drm_printer * p)5112 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
5113 {
5114 struct amdgpu_device *adev = ip_block->adev;
5115 uint32_t i, j, k, reg, index = 0;
5116 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
5117
5118 if (!adev->gfx.ip_dump_core)
5119 return;
5120
5121 for (i = 0; i < reg_count; i++)
5122 drm_printf(p, "%-50s \t 0x%08x\n",
5123 gc_reg_list_12_0[i].reg_name,
5124 adev->gfx.ip_dump_core[i]);
5125
5126 /* print compute queue registers for all instances */
5127 if (!adev->gfx.ip_dump_compute_queues)
5128 return;
5129
5130 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
5131 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
5132 adev->gfx.mec.num_mec,
5133 adev->gfx.mec.num_pipe_per_mec,
5134 adev->gfx.mec.num_queue_per_pipe);
5135
5136 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
5137 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
5138 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
5139 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
5140 for (reg = 0; reg < reg_count; reg++) {
5141 drm_printf(p, "%-50s \t 0x%08x\n",
5142 gc_cp_reg_list_12[reg].reg_name,
5143 adev->gfx.ip_dump_compute_queues[index + reg]);
5144 }
5145 index += reg_count;
5146 }
5147 }
5148 }
5149
5150 /* print gfx queue registers for all instances */
5151 if (!adev->gfx.ip_dump_gfx_queues)
5152 return;
5153
5154 index = 0;
5155 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
5156 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
5157 adev->gfx.me.num_me,
5158 adev->gfx.me.num_pipe_per_me,
5159 adev->gfx.me.num_queue_per_pipe);
5160
5161 for (i = 0; i < adev->gfx.me.num_me; i++) {
5162 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5163 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
5164 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
5165 for (reg = 0; reg < reg_count; reg++) {
5166 drm_printf(p, "%-50s \t 0x%08x\n",
5167 gc_gfx_queue_reg_list_12[reg].reg_name,
5168 adev->gfx.ip_dump_gfx_queues[index + reg]);
5169 }
5170 index += reg_count;
5171 }
5172 }
5173 }
5174 }
5175
gfx_v12_ip_dump(struct amdgpu_ip_block * ip_block)5176 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block)
5177 {
5178 struct amdgpu_device *adev = ip_block->adev;
5179 uint32_t i, j, k, reg, index = 0;
5180 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
5181
5182 if (!adev->gfx.ip_dump_core)
5183 return;
5184
5185 amdgpu_gfx_off_ctrl(adev, false);
5186 for (i = 0; i < reg_count; i++)
5187 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i]));
5188 amdgpu_gfx_off_ctrl(adev, true);
5189
5190 /* dump compute queue registers for all instances */
5191 if (!adev->gfx.ip_dump_compute_queues)
5192 return;
5193
5194 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
5195 amdgpu_gfx_off_ctrl(adev, false);
5196 mutex_lock(&adev->srbm_mutex);
5197 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
5198 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
5199 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
5200 /* ME0 is for GFX so start from 1 for CP */
5201 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
5202 for (reg = 0; reg < reg_count; reg++) {
5203 adev->gfx.ip_dump_compute_queues[index + reg] =
5204 RREG32(SOC15_REG_ENTRY_OFFSET(
5205 gc_cp_reg_list_12[reg]));
5206 }
5207 index += reg_count;
5208 }
5209 }
5210 }
5211 soc24_grbm_select(adev, 0, 0, 0, 0);
5212 mutex_unlock(&adev->srbm_mutex);
5213 amdgpu_gfx_off_ctrl(adev, true);
5214
5215 /* dump gfx queue registers for all instances */
5216 if (!adev->gfx.ip_dump_gfx_queues)
5217 return;
5218
5219 index = 0;
5220 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
5221 amdgpu_gfx_off_ctrl(adev, false);
5222 mutex_lock(&adev->srbm_mutex);
5223 for (i = 0; i < adev->gfx.me.num_me; i++) {
5224 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5225 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
5226 soc24_grbm_select(adev, i, j, k, 0);
5227
5228 for (reg = 0; reg < reg_count; reg++) {
5229 adev->gfx.ip_dump_gfx_queues[index + reg] =
5230 RREG32(SOC15_REG_ENTRY_OFFSET(
5231 gc_gfx_queue_reg_list_12[reg]));
5232 }
5233 index += reg_count;
5234 }
5235 }
5236 }
5237 soc24_grbm_select(adev, 0, 0, 0, 0);
5238 mutex_unlock(&adev->srbm_mutex);
5239 amdgpu_gfx_off_ctrl(adev, true);
5240 }
5241
gfx_v12_pipe_reset_support(struct amdgpu_device * adev)5242 static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev)
5243 {
5244 /* Disable the pipe reset until the CPFW fully support it.*/
5245 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n");
5246 return false;
5247 }
5248
gfx_v12_reset_gfx_pipe(struct amdgpu_ring * ring)5249 static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring)
5250 {
5251 struct amdgpu_device *adev = ring->adev;
5252 uint32_t reset_pipe = 0, clean_pipe = 0;
5253 int r;
5254
5255 if (!gfx_v12_pipe_reset_support(adev))
5256 return -EOPNOTSUPP;
5257
5258 gfx_v12_0_set_safe_mode(adev, 0);
5259 mutex_lock(&adev->srbm_mutex);
5260 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5261
5262 switch (ring->pipe) {
5263 case 0:
5264 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5265 PFP_PIPE0_RESET, 1);
5266 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5267 ME_PIPE0_RESET, 1);
5268 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5269 PFP_PIPE0_RESET, 0);
5270 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5271 ME_PIPE0_RESET, 0);
5272 break;
5273 case 1:
5274 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5275 PFP_PIPE1_RESET, 1);
5276 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5277 ME_PIPE1_RESET, 1);
5278 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5279 PFP_PIPE1_RESET, 0);
5280 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5281 ME_PIPE1_RESET, 0);
5282 break;
5283 default:
5284 break;
5285 }
5286
5287 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe);
5288 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe);
5289
5290 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -
5291 RS64_FW_UC_START_ADDR_LO;
5292 soc24_grbm_select(adev, 0, 0, 0, 0);
5293 mutex_unlock(&adev->srbm_mutex);
5294 gfx_v12_0_unset_safe_mode(adev, 0);
5295
5296 dev_info(adev->dev, "The ring %s pipe reset: %s\n", ring->name,
5297 r == 0 ? "successfully" : "failed");
5298 /* Sometimes the ME start pc counter can't cache correctly, so the
5299 * PC check only as a reference and pipe reset result rely on the
5300 * later ring test.
5301 */
5302 return 0;
5303 }
5304
gfx_v12_0_reset_kgq(struct amdgpu_ring * ring,unsigned int vmid,struct amdgpu_fence * timedout_fence)5305 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring,
5306 unsigned int vmid,
5307 struct amdgpu_fence *timedout_fence)
5308 {
5309 struct amdgpu_device *adev = ring->adev;
5310 int r;
5311
5312 amdgpu_ring_reset_helper_begin(ring, timedout_fence);
5313
5314 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false);
5315 if (r) {
5316 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r);
5317 r = gfx_v12_reset_gfx_pipe(ring);
5318 if (r)
5319 return r;
5320 }
5321
5322 r = gfx_v12_0_kgq_init_queue(ring, true);
5323 if (r) {
5324 dev_err(adev->dev, "failed to init kgq\n");
5325 return r;
5326 }
5327
5328 r = amdgpu_mes_map_legacy_queue(adev, ring);
5329 if (r) {
5330 dev_err(adev->dev, "failed to remap kgq\n");
5331 return r;
5332 }
5333
5334 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
5335 }
5336
gfx_v12_0_reset_compute_pipe(struct amdgpu_ring * ring)5337 static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring)
5338 {
5339 struct amdgpu_device *adev = ring->adev;
5340 uint32_t reset_pipe = 0, clean_pipe = 0;
5341 int r = 0;
5342
5343 if (!gfx_v12_pipe_reset_support(adev))
5344 return -EOPNOTSUPP;
5345
5346 gfx_v12_0_set_safe_mode(adev, 0);
5347 mutex_lock(&adev->srbm_mutex);
5348 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5349
5350 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
5351 clean_pipe = reset_pipe;
5352
5353 if (adev->gfx.rs64_enable) {
5354 switch (ring->pipe) {
5355 case 0:
5356 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5357 MEC_PIPE0_RESET, 1);
5358 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5359 MEC_PIPE0_RESET, 0);
5360 break;
5361 case 1:
5362 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5363 MEC_PIPE1_RESET, 1);
5364 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5365 MEC_PIPE1_RESET, 0);
5366 break;
5367 case 2:
5368 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5369 MEC_PIPE2_RESET, 1);
5370 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5371 MEC_PIPE2_RESET, 0);
5372 break;
5373 case 3:
5374 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5375 MEC_PIPE3_RESET, 1);
5376 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5377 MEC_PIPE3_RESET, 0);
5378 break;
5379 default:
5380 break;
5381 }
5382 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe);
5383 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe);
5384 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) -
5385 RS64_FW_UC_START_ADDR_LO;
5386 } else {
5387 switch (ring->pipe) {
5388 case 0:
5389 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,
5390 MEC_ME1_PIPE0_RESET, 1);
5391 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,
5392 MEC_ME1_PIPE0_RESET, 0);
5393 break;
5394 case 1:
5395 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,
5396 MEC_ME1_PIPE1_RESET, 1);
5397 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,
5398 MEC_ME1_PIPE1_RESET, 0);
5399 break;
5400 default:
5401 break;
5402 }
5403 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe);
5404 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe);
5405 /* Doesn't find the F32 MEC instruction pointer register, and suppose
5406 * the driver won't run into the F32 mode.
5407 */
5408 }
5409
5410 soc24_grbm_select(adev, 0, 0, 0, 0);
5411 mutex_unlock(&adev->srbm_mutex);
5412 gfx_v12_0_unset_safe_mode(adev, 0);
5413
5414 dev_info(adev->dev, "The ring %s pipe resets: %s\n", ring->name,
5415 r == 0 ? "successfully" : "failed");
5416 /* Need the ring test to verify the pipe reset result.*/
5417 return 0;
5418 }
5419
gfx_v12_0_reset_kcq(struct amdgpu_ring * ring,unsigned int vmid,struct amdgpu_fence * timedout_fence)5420 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring,
5421 unsigned int vmid,
5422 struct amdgpu_fence *timedout_fence)
5423 {
5424 struct amdgpu_device *adev = ring->adev;
5425 int r;
5426
5427 amdgpu_ring_reset_helper_begin(ring, timedout_fence);
5428
5429 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true);
5430 if (r) {
5431 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r);
5432 r = gfx_v12_0_reset_compute_pipe(ring);
5433 if (r)
5434 return r;
5435 }
5436
5437 r = gfx_v12_0_kcq_init_queue(ring, true);
5438 if (r) {
5439 dev_err(adev->dev, "failed to init kcq\n");
5440 return r;
5441 }
5442 r = amdgpu_mes_map_legacy_queue(adev, ring);
5443 if (r) {
5444 dev_err(adev->dev, "failed to remap kcq\n");
5445 return r;
5446 }
5447
5448 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
5449 }
5450
gfx_v12_0_ring_begin_use(struct amdgpu_ring * ring)5451 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring)
5452 {
5453 amdgpu_gfx_profile_ring_begin_use(ring);
5454
5455 amdgpu_gfx_enforce_isolation_ring_begin_use(ring);
5456 }
5457
gfx_v12_0_ring_end_use(struct amdgpu_ring * ring)5458 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring)
5459 {
5460 amdgpu_gfx_profile_ring_end_use(ring);
5461
5462 amdgpu_gfx_enforce_isolation_ring_end_use(ring);
5463 }
5464
5465 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = {
5466 .name = "gfx_v12_0",
5467 .early_init = gfx_v12_0_early_init,
5468 .late_init = gfx_v12_0_late_init,
5469 .sw_init = gfx_v12_0_sw_init,
5470 .sw_fini = gfx_v12_0_sw_fini,
5471 .hw_init = gfx_v12_0_hw_init,
5472 .hw_fini = gfx_v12_0_hw_fini,
5473 .suspend = gfx_v12_0_suspend,
5474 .resume = gfx_v12_0_resume,
5475 .is_idle = gfx_v12_0_is_idle,
5476 .wait_for_idle = gfx_v12_0_wait_for_idle,
5477 .set_clockgating_state = gfx_v12_0_set_clockgating_state,
5478 .set_powergating_state = gfx_v12_0_set_powergating_state,
5479 .get_clockgating_state = gfx_v12_0_get_clockgating_state,
5480 .dump_ip_state = gfx_v12_ip_dump,
5481 .print_ip_state = gfx_v12_ip_print,
5482 };
5483
5484 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = {
5485 .type = AMDGPU_RING_TYPE_GFX,
5486 .align_mask = 0xff,
5487 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5488 .support_64bit_ptrs = true,
5489 .secure_submission_supported = true,
5490 .get_rptr = gfx_v12_0_ring_get_rptr_gfx,
5491 .get_wptr = gfx_v12_0_ring_get_wptr_gfx,
5492 .set_wptr = gfx_v12_0_ring_set_wptr_gfx,
5493 .emit_frame_size = /* totally 242 maximum if 16 IBs */
5494 5 + /* COND_EXEC */
5495 7 + /* PIPELINE_SYNC */
5496 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5497 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5498 2 + /* VM_FLUSH */
5499 8 + /* FENCE for VM_FLUSH */
5500 5 + /* COND_EXEC */
5501 7 + /* HDP_flush */
5502 4 + /* VGT_flush */
5503 31 + /* DE_META */
5504 3 + /* CNTX_CTRL */
5505 5 + /* HDP_INVL */
5506 8 + 8 + /* FENCE x2 */
5507 8 + /* gfx_v12_0_emit_mem_sync */
5508 2, /* gfx_v12_0_ring_emit_cleaner_shader */
5509 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */
5510 .emit_ib = gfx_v12_0_ring_emit_ib_gfx,
5511 .emit_fence = gfx_v12_0_ring_emit_fence,
5512 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync,
5513 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush,
5514 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,
5515 .test_ring = gfx_v12_0_ring_test_ring,
5516 .test_ib = gfx_v12_0_ring_test_ib,
5517 .insert_nop = gfx_v12_ring_insert_nop,
5518 .pad_ib = amdgpu_ring_generic_pad_ib,
5519 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl,
5520 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec,
5521 .preempt_ib = gfx_v12_0_ring_preempt_ib,
5522 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl,
5523 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5524 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5525 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5526 .emit_mem_sync = gfx_v12_0_emit_mem_sync,
5527 .reset = gfx_v12_0_reset_kgq,
5528 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
5529 .begin_use = gfx_v12_0_ring_begin_use,
5530 .end_use = gfx_v12_0_ring_end_use,
5531 };
5532
5533 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = {
5534 .type = AMDGPU_RING_TYPE_COMPUTE,
5535 .align_mask = 0xff,
5536 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5537 .support_64bit_ptrs = true,
5538 .get_rptr = gfx_v12_0_ring_get_rptr_compute,
5539 .get_wptr = gfx_v12_0_ring_get_wptr_compute,
5540 .set_wptr = gfx_v12_0_ring_set_wptr_compute,
5541 .emit_frame_size =
5542 7 + /* gfx_v12_0_ring_emit_hdp_flush */
5543 5 + /* hdp invalidate */
5544 7 + /* gfx_v12_0_ring_emit_pipeline_sync */
5545 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5546 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5547 2 + /* gfx_v12_0_ring_emit_vm_flush */
5548 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */
5549 8 + /* gfx_v12_0_emit_mem_sync */
5550 2, /* gfx_v12_0_ring_emit_cleaner_shader */
5551 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */
5552 .emit_ib = gfx_v12_0_ring_emit_ib_compute,
5553 .emit_fence = gfx_v12_0_ring_emit_fence,
5554 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync,
5555 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush,
5556 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,
5557 .test_ring = gfx_v12_0_ring_test_ring,
5558 .test_ib = gfx_v12_0_ring_test_ib,
5559 .insert_nop = gfx_v12_ring_insert_nop,
5560 .pad_ib = amdgpu_ring_generic_pad_ib,
5561 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5562 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5563 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5564 .emit_mem_sync = gfx_v12_0_emit_mem_sync,
5565 .reset = gfx_v12_0_reset_kcq,
5566 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
5567 .begin_use = gfx_v12_0_ring_begin_use,
5568 .end_use = gfx_v12_0_ring_end_use,
5569 };
5570
5571 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = {
5572 .type = AMDGPU_RING_TYPE_KIQ,
5573 .align_mask = 0xff,
5574 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5575 .support_64bit_ptrs = true,
5576 .get_rptr = gfx_v12_0_ring_get_rptr_compute,
5577 .get_wptr = gfx_v12_0_ring_get_wptr_compute,
5578 .set_wptr = gfx_v12_0_ring_set_wptr_compute,
5579 .emit_frame_size =
5580 7 + /* gfx_v12_0_ring_emit_hdp_flush */
5581 5 + /*hdp invalidate */
5582 7 + /* gfx_v12_0_ring_emit_pipeline_sync */
5583 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5584 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5585 2 + /* gfx_v12_0_ring_emit_vm_flush */
5586 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */
5587 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */
5588 .emit_ib = gfx_v12_0_ring_emit_ib_compute,
5589 .emit_fence = gfx_v12_0_ring_emit_fence_kiq,
5590 .test_ring = gfx_v12_0_ring_test_ring,
5591 .test_ib = gfx_v12_0_ring_test_ib,
5592 .insert_nop = amdgpu_ring_insert_nop,
5593 .pad_ib = amdgpu_ring_generic_pad_ib,
5594 .emit_rreg = gfx_v12_0_ring_emit_rreg,
5595 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5596 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5597 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5598 };
5599
gfx_v12_0_set_ring_funcs(struct amdgpu_device * adev)5600 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev)
5601 {
5602 int i;
5603
5604 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq;
5605
5606 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5607 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx;
5608
5609 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5610 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute;
5611 }
5612
5613 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = {
5614 .set = gfx_v12_0_set_eop_interrupt_state,
5615 .process = gfx_v12_0_eop_irq,
5616 };
5617
5618 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = {
5619 .set = gfx_v12_0_set_priv_reg_fault_state,
5620 .process = gfx_v12_0_priv_reg_irq,
5621 };
5622
5623 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = {
5624 .set = gfx_v12_0_set_bad_op_fault_state,
5625 .process = gfx_v12_0_bad_op_irq,
5626 };
5627
5628 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = {
5629 .set = gfx_v12_0_set_priv_inst_fault_state,
5630 .process = gfx_v12_0_priv_inst_irq,
5631 };
5632
gfx_v12_0_set_irq_funcs(struct amdgpu_device * adev)5633 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev)
5634 {
5635 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5636 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs;
5637
5638 adev->gfx.priv_reg_irq.num_types = 1;
5639 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs;
5640
5641 adev->gfx.bad_op_irq.num_types = 1;
5642 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs;
5643
5644 adev->gfx.priv_inst_irq.num_types = 1;
5645 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs;
5646 }
5647
gfx_v12_0_set_imu_funcs(struct amdgpu_device * adev)5648 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev)
5649 {
5650 if (adev->flags & AMD_IS_APU)
5651 adev->gfx.imu.mode = MISSION_MODE;
5652 else
5653 adev->gfx.imu.mode = DEBUG_MODE;
5654
5655 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs;
5656 }
5657
gfx_v12_0_set_rlc_funcs(struct amdgpu_device * adev)5658 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev)
5659 {
5660 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs;
5661 }
5662
gfx_v12_0_set_mqd_funcs(struct amdgpu_device * adev)5663 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev)
5664 {
5665 /* set gfx eng mqd */
5666 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
5667 sizeof(struct v12_gfx_mqd);
5668 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
5669 gfx_v12_0_gfx_mqd_init;
5670 /* set compute eng mqd */
5671 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
5672 sizeof(struct v12_compute_mqd);
5673 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
5674 gfx_v12_0_compute_mqd_init;
5675 }
5676
gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device * adev,u32 bitmap)5677 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
5678 u32 bitmap)
5679 {
5680 u32 data;
5681
5682 if (!bitmap)
5683 return;
5684
5685 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5686 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5687
5688 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
5689 }
5690
gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device * adev)5691 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
5692 {
5693 u32 data, wgp_bitmask;
5694 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
5695 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);
5696
5697 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5698 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5699
5700 wgp_bitmask =
5701 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
5702
5703 return (~data) & wgp_bitmask;
5704 }
5705
gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device * adev)5706 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
5707 {
5708 u32 wgp_idx, wgp_active_bitmap;
5709 u32 cu_bitmap_per_wgp, cu_active_bitmap;
5710
5711 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev);
5712 cu_active_bitmap = 0;
5713
5714 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
5715 /* if there is one WGP enabled, it means 2 CUs will be enabled */
5716 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
5717 if (wgp_active_bitmap & (1 << wgp_idx))
5718 cu_active_bitmap |= cu_bitmap_per_wgp;
5719 }
5720
5721 return cu_active_bitmap;
5722 }
5723
gfx_v12_0_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)5724 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,
5725 struct amdgpu_cu_info *cu_info)
5726 {
5727 int i, j, k, counter, active_cu_number = 0;
5728 u32 mask, bitmap;
5729 unsigned disable_masks[8 * 2];
5730
5731 if (!adev || !cu_info)
5732 return -EINVAL;
5733
5734 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
5735
5736 mutex_lock(&adev->grbm_idx_mutex);
5737 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5738 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5739 bitmap = i * adev->gfx.config.max_sh_per_se + j;
5740 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1))
5741 continue;
5742 mask = 1;
5743 counter = 0;
5744 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5745 if (i < 8 && j < 2)
5746 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(
5747 adev, disable_masks[i * 2 + j]);
5748 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev);
5749
5750 /**
5751 * GFX12 could support more than 4 SEs, while the bitmap
5752 * in cu_info struct is 4x4 and ioctl interface struct
5753 * drm_amdgpu_info_device should keep stable.
5754 * So we use last two columns of bitmap to store cu mask for
5755 * SEs 4 to 7, the layout of the bitmap is as below:
5756 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}
5757 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}
5758 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}
5759 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}
5760 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}
5761 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]}
5762 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]}
5763 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]}
5764 */
5765 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap;
5766
5767 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5768 if (bitmap & mask)
5769 counter++;
5770
5771 mask <<= 1;
5772 }
5773 active_cu_number += counter;
5774 }
5775 }
5776 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5777 mutex_unlock(&adev->grbm_idx_mutex);
5778
5779 cu_info->number = active_cu_number;
5780 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5781
5782 return 0;
5783 }
5784
5785 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = {
5786 .type = AMD_IP_BLOCK_TYPE_GFX,
5787 .major = 12,
5788 .minor = 0,
5789 .rev = 0,
5790 .funcs = &gfx_v12_0_ip_funcs,
5791 };
5792