1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/delay.h>
24 #include <linux/kernel.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include "amdgpu.h"
29 #include "amdgpu_gfx.h"
30 #include "amdgpu_psp.h"
31 #include "amdgpu_smu.h"
32 #include "imu_v12_0.h"
33 #include "soc24.h"
34 #include "nvd.h"
35
36 #include "gc/gc_12_0_0_offset.h"
37 #include "gc/gc_12_0_0_sh_mask.h"
38 #include "soc24_enum.h"
39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h"
40
41 #include "soc15.h"
42 #include "clearstate_gfx12.h"
43 #include "v12_structs.h"
44 #include "gfx_v12_0.h"
45 #include "nbif_v6_3_1.h"
46 #include "mes_v12_0.h"
47 #include "mes_userqueue.h"
48 #include "amdgpu_userq_fence.h"
49
50 #define GFX12_NUM_GFX_RINGS 1
51 #define GFX12_MEC_HPD_SIZE 2048
52
53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
54
55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100
56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000
57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01
59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000
60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000
61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000
62
63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006
64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100
66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509
67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000
69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501
70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000
71
72
73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin");
74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin");
75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin");
76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin");
77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin");
78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin");
79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin");
80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin");
81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin");
82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc_kicker.bin");
83 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin");
84
85 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = {
86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
88 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
91 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
94 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
99 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
101 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
115 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
116 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
117 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
118 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
120 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
121 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
122 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
125 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32),
128 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
133 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
134 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),
137 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),
138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),
139 /* cp header registers */
140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
147 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
148 /* SE status registers */
149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
152 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)
153 };
154
155 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = {
156 /* compute registers */
157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),
196 /* cp header registers */
197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
204 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
205 };
206
207 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = {
208 /* gfx queue registers */
209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
229 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
233 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
234 /* cp header registers */
235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
242 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
250 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
251 };
252
253 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = {
254 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f),
255 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000),
256 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020)
257 };
258
259 static const struct soc15_reg_golden golden_settings_gc_12_0[] = {
260 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000),
261 };
262
263 #define DEFAULT_SH_MEM_CONFIG \
264 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
265 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
266 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
267
268 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev);
269 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev);
270 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev);
271 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev);
272 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev);
273 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev);
274 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,
275 struct amdgpu_cu_info *cu_info);
276 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev);
277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
278 u32 sh_num, u32 instance, int xcc_id);
279 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
280
281 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
282 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
283 uint32_t val);
284 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
285 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
286 uint16_t pasid, uint32_t flush_type,
287 bool all_hub, uint8_t dst_sel);
288 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
289 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
290 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
291 bool enable);
292
gfx_v12_0_kiq_set_resources(struct amdgpu_ring * kiq_ring,uint64_t queue_mask)293 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
294 uint64_t queue_mask)
295 {
296 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
297 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
298 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
299 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
300 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
301 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
302 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
303 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
304 amdgpu_ring_write(kiq_ring, 0);
305 }
306
gfx_v12_0_kiq_map_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring)307 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring,
308 struct amdgpu_ring *ring)
309 {
310 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
311 uint64_t wptr_addr = ring->wptr_gpu_addr;
312 uint32_t me = 0, eng_sel = 0;
313
314 switch (ring->funcs->type) {
315 case AMDGPU_RING_TYPE_COMPUTE:
316 me = 1;
317 eng_sel = 0;
318 break;
319 case AMDGPU_RING_TYPE_GFX:
320 me = 0;
321 eng_sel = 4;
322 break;
323 case AMDGPU_RING_TYPE_MES:
324 me = 2;
325 eng_sel = 5;
326 break;
327 default:
328 WARN_ON(1);
329 }
330
331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
332 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
333 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
334 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
335 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
336 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
337 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
338 PACKET3_MAP_QUEUES_ME((me)) |
339 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
340 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
341 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
342 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
343 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
344 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
345 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
346 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
347 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
348 }
349
gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq)350 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
351 struct amdgpu_ring *ring,
352 enum amdgpu_unmap_queues_action action,
353 u64 gpu_addr, u64 seq)
354 {
355 struct amdgpu_device *adev = kiq_ring->adev;
356 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
357
358 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
359 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
360 return;
361 }
362
363 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
364 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
365 PACKET3_UNMAP_QUEUES_ACTION(action) |
366 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
367 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
368 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
369 amdgpu_ring_write(kiq_ring,
370 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
371
372 if (action == PREEMPT_QUEUES_NO_UNMAP) {
373 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
374 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
375 amdgpu_ring_write(kiq_ring, seq);
376 } else {
377 amdgpu_ring_write(kiq_ring, 0);
378 amdgpu_ring_write(kiq_ring, 0);
379 amdgpu_ring_write(kiq_ring, 0);
380 }
381 }
382
gfx_v12_0_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq)383 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring,
384 struct amdgpu_ring *ring,
385 u64 addr, u64 seq)
386 {
387 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
388
389 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
390 amdgpu_ring_write(kiq_ring,
391 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
392 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
393 PACKET3_QUERY_STATUS_COMMAND(2));
394 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
395 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
396 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
397 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
398 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
399 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
400 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
401 }
402
gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub)403 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
404 uint16_t pasid,
405 uint32_t flush_type,
406 bool all_hub)
407 {
408 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
409 }
410
411 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = {
412 .kiq_set_resources = gfx_v12_0_kiq_set_resources,
413 .kiq_map_queues = gfx_v12_0_kiq_map_queues,
414 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues,
415 .kiq_query_status = gfx_v12_0_kiq_query_status,
416 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs,
417 .set_resources_size = 8,
418 .map_queues_size = 7,
419 .unmap_queues_size = 6,
420 .query_status_size = 7,
421 .invalidate_tlbs_size = 2,
422 };
423
gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device * adev)424 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
425 {
426 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs;
427 }
428
gfx_v12_0_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)429 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
430 int mem_space, int opt, uint32_t addr0,
431 uint32_t addr1, uint32_t ref,
432 uint32_t mask, uint32_t inv)
433 {
434 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
435 amdgpu_ring_write(ring,
436 /* memory (1) or register (0) */
437 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
438 WAIT_REG_MEM_OPERATION(opt) | /* wait */
439 WAIT_REG_MEM_FUNCTION(3) | /* equal */
440 WAIT_REG_MEM_ENGINE(eng_sel)));
441
442 if (mem_space)
443 BUG_ON(addr0 & 0x3); /* Dword align */
444 amdgpu_ring_write(ring, addr0);
445 amdgpu_ring_write(ring, addr1);
446 amdgpu_ring_write(ring, ref);
447 amdgpu_ring_write(ring, mask);
448 amdgpu_ring_write(ring, inv); /* poll interval */
449 }
450
gfx_v12_0_ring_test_ring(struct amdgpu_ring * ring)451 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring)
452 {
453 struct amdgpu_device *adev = ring->adev;
454 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
455 uint32_t tmp = 0;
456 unsigned i;
457 int r;
458
459 WREG32(scratch, 0xCAFEDEAD);
460 r = amdgpu_ring_alloc(ring, 5);
461 if (r) {
462 dev_err(adev->dev,
463 "amdgpu: cp failed to lock ring %d (%d).\n",
464 ring->idx, r);
465 return r;
466 }
467
468 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {
469 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
470 } else {
471 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
472 amdgpu_ring_write(ring, scratch -
473 PACKET3_SET_UCONFIG_REG_START);
474 amdgpu_ring_write(ring, 0xDEADBEEF);
475 }
476 amdgpu_ring_commit(ring);
477
478 for (i = 0; i < adev->usec_timeout; i++) {
479 tmp = RREG32(scratch);
480 if (tmp == 0xDEADBEEF)
481 break;
482 if (amdgpu_emu_mode == 1)
483 msleep(1);
484 else
485 udelay(1);
486 }
487
488 if (i >= adev->usec_timeout)
489 r = -ETIMEDOUT;
490 return r;
491 }
492
gfx_v12_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)493 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
494 {
495 struct amdgpu_device *adev = ring->adev;
496 struct amdgpu_ib ib;
497 struct dma_fence *f = NULL;
498 unsigned index;
499 uint64_t gpu_addr;
500 uint32_t *cpu_ptr;
501 long r;
502
503 /* MES KIQ fw hasn't indirect buffer support for now */
504 if (adev->enable_mes_kiq &&
505 ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
506 return 0;
507
508 memset(&ib, 0, sizeof(ib));
509
510 r = amdgpu_device_wb_get(adev, &index);
511 if (r)
512 return r;
513
514 gpu_addr = adev->wb.gpu_addr + (index * 4);
515 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
516 cpu_ptr = &adev->wb.wb[index];
517
518 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
519 if (r) {
520 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r);
521 goto err1;
522 }
523
524 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
526 ib.ptr[2] = lower_32_bits(gpu_addr);
527 ib.ptr[3] = upper_32_bits(gpu_addr);
528 ib.ptr[4] = 0xDEADBEEF;
529 ib.length_dw = 5;
530
531 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
532 if (r)
533 goto err2;
534
535 r = dma_fence_wait_timeout(f, false, timeout);
536 if (r == 0) {
537 r = -ETIMEDOUT;
538 goto err2;
539 } else if (r < 0) {
540 goto err2;
541 }
542
543 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
544 r = 0;
545 else
546 r = -EINVAL;
547 err2:
548 amdgpu_ib_free(&ib, NULL);
549 dma_fence_put(f);
550 err1:
551 amdgpu_device_wb_free(adev, index);
552 return r;
553 }
554
gfx_v12_0_free_microcode(struct amdgpu_device * adev)555 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev)
556 {
557 amdgpu_ucode_release(&adev->gfx.pfp_fw);
558 amdgpu_ucode_release(&adev->gfx.me_fw);
559 amdgpu_ucode_release(&adev->gfx.rlc_fw);
560 amdgpu_ucode_release(&adev->gfx.mec_fw);
561
562 kfree(adev->gfx.rlc.register_list_format);
563 }
564
gfx_v12_0_init_toc_microcode(struct amdgpu_device * adev,const char * ucode_prefix)565 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix)
566 {
567 const struct psp_firmware_header_v1_0 *toc_hdr;
568 int err = 0;
569
570 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw,
571 AMDGPU_UCODE_REQUIRED,
572 "amdgpu/%s_toc.bin", ucode_prefix);
573 if (err)
574 goto out;
575
576 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
577 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
578 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
579 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
580 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
581 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
582 return 0;
583 out:
584 amdgpu_ucode_release(&adev->psp.toc_fw);
585 return err;
586 }
587
gfx_v12_0_init_microcode(struct amdgpu_device * adev)588 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev)
589 {
590 char ucode_prefix[30];
591 int err;
592 const struct rlc_firmware_header_v2_0 *rlc_hdr;
593 uint16_t version_major;
594 uint16_t version_minor;
595
596 DRM_DEBUG("\n");
597
598 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
599
600 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
601 AMDGPU_UCODE_REQUIRED,
602 "amdgpu/%s_pfp.bin", ucode_prefix);
603 if (err)
604 goto out;
605 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);
606 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
607
608 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
609 AMDGPU_UCODE_REQUIRED,
610 "amdgpu/%s_me.bin", ucode_prefix);
611 if (err)
612 goto out;
613 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);
614 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
615
616 if (!amdgpu_sriov_vf(adev)) {
617 if (amdgpu_is_kicker_fw(adev))
618 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
619 AMDGPU_UCODE_REQUIRED,
620 "amdgpu/%s_rlc_kicker.bin", ucode_prefix);
621 else
622 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
623 AMDGPU_UCODE_REQUIRED,
624 "amdgpu/%s_rlc.bin", ucode_prefix);
625 if (err)
626 goto out;
627 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
628 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
629 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
630 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
631 if (err)
632 goto out;
633 }
634
635 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
636 AMDGPU_UCODE_REQUIRED,
637 "amdgpu/%s_mec.bin", ucode_prefix);
638 if (err)
639 goto out;
640 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);
641 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);
642 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);
643
644 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
645 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix);
646
647 /* only one MEC for gfx 12 */
648 adev->gfx.mec2_fw = NULL;
649
650 if (adev->gfx.imu.funcs) {
651 if (adev->gfx.imu.funcs->init_microcode) {
652 err = adev->gfx.imu.funcs->init_microcode(adev);
653 if (err)
654 dev_err(adev->dev, "Failed to load imu firmware!\n");
655 }
656 }
657
658 out:
659 if (err) {
660 amdgpu_ucode_release(&adev->gfx.pfp_fw);
661 amdgpu_ucode_release(&adev->gfx.me_fw);
662 amdgpu_ucode_release(&adev->gfx.rlc_fw);
663 amdgpu_ucode_release(&adev->gfx.mec_fw);
664 }
665
666 return err;
667 }
668
gfx_v12_0_get_csb_size(struct amdgpu_device * adev)669 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev)
670 {
671 u32 count = 0;
672 const struct cs_section_def *sect = NULL;
673 const struct cs_extent_def *ext = NULL;
674
675 count += 1;
676
677 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) {
678 if (sect->id == SECT_CONTEXT) {
679 for (ext = sect->section; ext->extent != NULL; ++ext)
680 count += 2 + ext->reg_count;
681 } else
682 return 0;
683 }
684
685 return count;
686 }
687
gfx_v12_0_get_csb_buffer(struct amdgpu_device * adev,u32 * buffer)688 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)
689 {
690 u32 count = 0, clustercount = 0, i;
691 const struct cs_section_def *sect = NULL;
692 const struct cs_extent_def *ext = NULL;
693
694 if (adev->gfx.rlc.cs_data == NULL)
695 return;
696 if (buffer == NULL)
697 return;
698
699 count += 1;
700
701 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
702 if (sect->id == SECT_CONTEXT) {
703 for (ext = sect->section; ext->extent != NULL; ++ext) {
704 clustercount++;
705 buffer[count++] = ext->reg_count;
706 buffer[count++] = ext->reg_index;
707
708 for (i = 0; i < ext->reg_count; i++)
709 buffer[count++] = cpu_to_le32(ext->extent[i]);
710 }
711 } else
712 return;
713 }
714
715 buffer[0] = clustercount;
716 }
717
gfx_v12_0_rlc_fini(struct amdgpu_device * adev)718 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev)
719 {
720 /* clear state block */
721 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
722 &adev->gfx.rlc.clear_state_gpu_addr,
723 (void **)&adev->gfx.rlc.cs_ptr);
724
725 /* jump table block */
726 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
727 &adev->gfx.rlc.cp_table_gpu_addr,
728 (void **)&adev->gfx.rlc.cp_table_ptr);
729 }
730
gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device * adev)731 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
732 {
733 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
734
735 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
736 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
737 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
738 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
739 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
740 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
741 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
742 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
743 adev->gfx.rlc.rlcg_reg_access_supported = true;
744 }
745
gfx_v12_0_rlc_init(struct amdgpu_device * adev)746 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev)
747 {
748 const struct cs_section_def *cs_data;
749 int r;
750
751 adev->gfx.rlc.cs_data = gfx12_cs_data;
752
753 cs_data = adev->gfx.rlc.cs_data;
754
755 if (cs_data) {
756 /* init clear state block */
757 r = amdgpu_gfx_rlc_init_csb(adev);
758 if (r)
759 return r;
760 }
761
762 /* init spm vmid with 0xf */
763 if (adev->gfx.rlc.funcs->update_spm_vmid)
764 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
765
766 return 0;
767 }
768
gfx_v12_0_mec_fini(struct amdgpu_device * adev)769 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev)
770 {
771 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
772 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
773 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL);
774 }
775
gfx_v12_0_me_init(struct amdgpu_device * adev)776 static void gfx_v12_0_me_init(struct amdgpu_device *adev)
777 {
778 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
779
780 amdgpu_gfx_graphics_queue_acquire(adev);
781 }
782
gfx_v12_0_mec_init(struct amdgpu_device * adev)783 static int gfx_v12_0_mec_init(struct amdgpu_device *adev)
784 {
785 int r;
786 u32 *hpd;
787 size_t mec_hpd_size;
788
789 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
790
791 /* take ownership of the relevant compute queues */
792 amdgpu_gfx_compute_queue_acquire(adev);
793 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE;
794
795 if (mec_hpd_size) {
796 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
797 AMDGPU_GEM_DOMAIN_GTT,
798 &adev->gfx.mec.hpd_eop_obj,
799 &adev->gfx.mec.hpd_eop_gpu_addr,
800 (void **)&hpd);
801 if (r) {
802 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
803 gfx_v12_0_mec_fini(adev);
804 return r;
805 }
806
807 memset(hpd, 0, mec_hpd_size);
808
809 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
810 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
811 }
812
813 return 0;
814 }
815
wave_read_ind(struct amdgpu_device * adev,uint32_t wave,uint32_t address)816 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
817 {
818 WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
819 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
820 (address << SQ_IND_INDEX__INDEX__SHIFT));
821 return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
822 }
823
wave_read_regs(struct amdgpu_device * adev,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)824 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
825 uint32_t thread, uint32_t regno,
826 uint32_t num, uint32_t *out)
827 {
828 WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
829 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
830 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
831 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
832 (SQ_IND_INDEX__AUTO_INCR_MASK));
833 while (num--)
834 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
835 }
836
gfx_v12_0_read_wave_data(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)837 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev,
838 uint32_t xcc_id,
839 uint32_t simd, uint32_t wave,
840 uint32_t *dst, int *no_fields)
841 {
842 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE
843 * field when performing a select_se_sh so it should be
844 * zero here */
845 WARN_ON(simd != 0);
846
847 /* type 4 wave data */
848 dst[(*no_fields)++] = 4;
849 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
850 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
851 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
852 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
853 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
854 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
855 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
856 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV);
864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV);
865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER);
866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL);
867 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE);
868 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE);
869 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO);
870 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI);
871 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE);
872 }
873
gfx_v12_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)874 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev,
875 uint32_t xcc_id, uint32_t simd,
876 uint32_t wave, uint32_t start,
877 uint32_t size, uint32_t *dst)
878 {
879 WARN_ON(simd != 0);
880
881 wave_read_regs(
882 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
883 dst);
884 }
885
gfx_v12_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst)886 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev,
887 uint32_t xcc_id, uint32_t simd,
888 uint32_t wave, uint32_t thread,
889 uint32_t start, uint32_t size,
890 uint32_t *dst)
891 {
892 wave_read_regs(
893 adev, wave, thread,
894 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
895 }
896
gfx_v12_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm,u32 xcc_id)897 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev,
898 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
899 {
900 soc24_grbm_select(adev, me, pipe, q, vm);
901 }
902
903 /* all sizes are in bytes */
904 #define MQD_SHADOW_BASE_SIZE 73728
905 #define MQD_SHADOW_BASE_ALIGNMENT 256
906 #define MQD_FWWORKAREA_SIZE 484
907 #define MQD_FWWORKAREA_ALIGNMENT 256
908
gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device * adev,struct amdgpu_gfx_shadow_info * shadow_info)909 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev,
910 struct amdgpu_gfx_shadow_info *shadow_info)
911 {
912 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;
913 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;
914 shadow_info->csa_size = MQD_FWWORKAREA_SIZE;
915 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;
916 }
917
gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device * adev,struct amdgpu_gfx_shadow_info * shadow_info,bool skip_check)918 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev,
919 struct amdgpu_gfx_shadow_info *shadow_info,
920 bool skip_check)
921 {
922 if (adev->gfx.cp_gfx_shadow || skip_check) {
923 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info);
924 return 0;
925 }
926
927 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));
928 return -EINVAL;
929 }
930
931 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = {
932 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter,
933 .select_se_sh = &gfx_v12_0_select_se_sh,
934 .read_wave_data = &gfx_v12_0_read_wave_data,
935 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs,
936 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs,
937 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q,
938 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk,
939 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info,
940 };
941
gfx_v12_0_gpu_early_init(struct amdgpu_device * adev)942 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev)
943 {
944
945 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
946 case IP_VERSION(12, 0, 0):
947 case IP_VERSION(12, 0, 1):
948 adev->gfx.config.max_hw_contexts = 8;
949 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
950 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
951 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
952 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
953 break;
954 default:
955 BUG();
956 break;
957 }
958
959 return 0;
960 }
961
gfx_v12_0_gfx_ring_init(struct amdgpu_device * adev,int ring_id,int me,int pipe,int queue)962 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
963 int me, int pipe, int queue)
964 {
965 int r;
966 struct amdgpu_ring *ring;
967 unsigned int irq_type;
968
969 ring = &adev->gfx.gfx_ring[ring_id];
970
971 ring->me = me;
972 ring->pipe = pipe;
973 ring->queue = queue;
974
975 ring->ring_obj = NULL;
976 ring->use_doorbell = true;
977
978 if (!ring_id)
979 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
980 else
981 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
982 ring->vm_hub = AMDGPU_GFXHUB(0);
983 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
984
985 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
986 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
987 AMDGPU_RING_PRIO_DEFAULT, NULL);
988 if (r)
989 return r;
990 return 0;
991 }
992
gfx_v12_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)993 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
994 int mec, int pipe, int queue)
995 {
996 int r;
997 unsigned irq_type;
998 struct amdgpu_ring *ring;
999 unsigned int hw_prio;
1000
1001 ring = &adev->gfx.compute_ring[ring_id];
1002
1003 /* mec0 is me1 */
1004 ring->me = mec + 1;
1005 ring->pipe = pipe;
1006 ring->queue = queue;
1007
1008 ring->ring_obj = NULL;
1009 ring->use_doorbell = true;
1010 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1011 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1012 + (ring_id * GFX12_MEC_HPD_SIZE);
1013 ring->vm_hub = AMDGPU_GFXHUB(0);
1014 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1015
1016 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1017 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1018 + ring->pipe;
1019 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
1020 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
1021 /* type-2 packets are deprecated on MEC, use type-3 instead */
1022 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1023 hw_prio, NULL);
1024 if (r)
1025 return r;
1026
1027 return 0;
1028 }
1029
1030 static struct {
1031 SOC24_FIRMWARE_ID id;
1032 unsigned int offset;
1033 unsigned int size;
1034 unsigned int size_x16;
1035 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX];
1036
1037 #define RLC_TOC_OFFSET_DWUNIT 8
1038 #define RLC_SIZE_MULTIPLE 1024
1039 #define RLC_TOC_UMF_SIZE_inM 23ULL
1040 #define RLC_TOC_FORMAT_API 165ULL
1041
gfx_v12_0_parse_rlc_toc(struct amdgpu_device * adev,void * rlc_toc)1042 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc)
1043 {
1044 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc;
1045
1046 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) {
1047 rlc_autoload_info[ucode->id].id = ucode->id;
1048 rlc_autoload_info[ucode->id].offset =
1049 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4;
1050 rlc_autoload_info[ucode->id].size =
1051 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 :
1052 ucode->size * 4;
1053 ucode++;
1054 }
1055 }
1056
gfx_v12_0_calc_toc_total_size(struct amdgpu_device * adev)1057 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev)
1058 {
1059 uint32_t total_size = 0;
1060 SOC24_FIRMWARE_ID id;
1061
1062 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr);
1063
1064 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++)
1065 total_size += rlc_autoload_info[id].size;
1066
1067 /* In case the offset in rlc toc ucode is aligned */
1068 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset)
1069 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset +
1070 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size;
1071 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20))
1072 total_size = RLC_TOC_UMF_SIZE_inM << 20;
1073
1074 return total_size;
1075 }
1076
gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device * adev)1077 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev)
1078 {
1079 int r;
1080 uint32_t total_size;
1081
1082 total_size = gfx_v12_0_calc_toc_total_size(adev);
1083
1084 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
1085 AMDGPU_GEM_DOMAIN_VRAM,
1086 &adev->gfx.rlc.rlc_autoload_bo,
1087 &adev->gfx.rlc.rlc_autoload_gpu_addr,
1088 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1089
1090 if (r) {
1091 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1092 return r;
1093 }
1094
1095 return 0;
1096 }
1097
gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device * adev,SOC24_FIRMWARE_ID id,const void * fw_data,uint32_t fw_size)1098 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
1099 SOC24_FIRMWARE_ID id,
1100 const void *fw_data,
1101 uint32_t fw_size)
1102 {
1103 uint32_t toc_offset;
1104 uint32_t toc_fw_size;
1105 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1106
1107 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX)
1108 return;
1109
1110 toc_offset = rlc_autoload_info[id].offset;
1111 toc_fw_size = rlc_autoload_info[id].size;
1112
1113 if (fw_size == 0)
1114 fw_size = toc_fw_size;
1115
1116 if (fw_size > toc_fw_size)
1117 fw_size = toc_fw_size;
1118
1119 memcpy(ptr + toc_offset, fw_data, fw_size);
1120
1121 if (fw_size < toc_fw_size)
1122 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
1123 }
1124
1125 static void
gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device * adev)1126 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
1127 {
1128 void *data;
1129 uint32_t size;
1130 uint32_t *toc_ptr;
1131
1132 data = adev->psp.toc.start_addr;
1133 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size;
1134
1135 toc_ptr = (uint32_t *)data + size / 4 - 2;
1136 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1;
1137
1138 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC,
1139 data, size);
1140 }
1141
1142 static void
gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device * adev)1143 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
1144 {
1145 const __le32 *fw_data;
1146 uint32_t fw_size;
1147 const struct gfx_firmware_header_v2_0 *cpv2_hdr;
1148 const struct rlc_firmware_header_v2_0 *rlc_hdr;
1149 const struct rlc_firmware_header_v2_1 *rlcv21_hdr;
1150 const struct rlc_firmware_header_v2_2 *rlcv22_hdr;
1151 uint16_t version_major, version_minor;
1152
1153 /* pfp ucode */
1154 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1155 adev->gfx.pfp_fw->data;
1156 /* instruction */
1157 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1158 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1159 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1160 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP,
1161 fw_data, fw_size);
1162 /* data */
1163 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1164 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1165 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1166 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK,
1167 fw_data, fw_size);
1168 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK,
1169 fw_data, fw_size);
1170 /* me ucode */
1171 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1172 adev->gfx.me_fw->data;
1173 /* instruction */
1174 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1175 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1176 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1177 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME,
1178 fw_data, fw_size);
1179 /* data */
1180 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1181 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1182 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1183 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK,
1184 fw_data, fw_size);
1185 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK,
1186 fw_data, fw_size);
1187 /* mec ucode */
1188 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1189 adev->gfx.mec_fw->data;
1190 /* instruction */
1191 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1192 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1193 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1194 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC,
1195 fw_data, fw_size);
1196 /* data */
1197 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1198 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1199 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1200 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK,
1201 fw_data, fw_size);
1202 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK,
1203 fw_data, fw_size);
1204 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK,
1205 fw_data, fw_size);
1206 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK,
1207 fw_data, fw_size);
1208
1209 /* rlc ucode */
1210 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
1211 adev->gfx.rlc_fw->data;
1212 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1213 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
1214 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
1215 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE,
1216 fw_data, fw_size);
1217
1218 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1219 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1220 if (version_major == 2) {
1221 if (version_minor >= 1) {
1222 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
1223
1224 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1225 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes));
1226 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes);
1227 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH,
1228 fw_data, fw_size);
1229
1230 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1231 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes));
1232 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes);
1233 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM,
1234 fw_data, fw_size);
1235 }
1236 if (version_minor >= 2) {
1237 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1238
1239 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1240 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes));
1241 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes);
1242 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE,
1243 fw_data, fw_size);
1244
1245 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1246 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes));
1247 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes);
1248 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT,
1249 fw_data, fw_size);
1250 }
1251 }
1252 }
1253
1254 static void
gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device * adev)1255 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
1256 {
1257 const __le32 *fw_data;
1258 uint32_t fw_size;
1259 const struct sdma_firmware_header_v3_0 *sdma_hdr;
1260
1261 sdma_hdr = (const struct sdma_firmware_header_v3_0 *)
1262 adev->sdma.instance[0].fw->data;
1263 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1264 le32_to_cpu(sdma_hdr->ucode_offset_bytes));
1265 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes);
1266
1267 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0,
1268 fw_data, fw_size);
1269 }
1270
1271 static void
gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device * adev)1272 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev)
1273 {
1274 const __le32 *fw_data;
1275 unsigned fw_size;
1276 const struct mes_firmware_header_v1_0 *mes_hdr;
1277 int pipe, ucode_id, data_id;
1278
1279 for (pipe = 0; pipe < 2; pipe++) {
1280 if (pipe == 0) {
1281 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0;
1282 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK;
1283 } else {
1284 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1;
1285 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK;
1286 }
1287
1288 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1289 adev->mes.fw[pipe]->data;
1290
1291 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1292 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1293 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1294
1295 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size);
1296
1297 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1298 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1299 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1300
1301 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size);
1302 }
1303 }
1304
gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device * adev)1305 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
1306 {
1307 uint32_t rlc_g_offset, rlc_g_size;
1308 uint64_t gpu_addr;
1309 uint32_t data;
1310
1311 /* RLC autoload sequence 2: copy ucode */
1312 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
1313 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
1314 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev);
1315 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
1316
1317 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset;
1318 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size;
1319 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start;
1320
1321 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1322 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1323
1324 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1325
1326 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
1327 /* RLC autoload sequence 3: load IMU fw */
1328 if (adev->gfx.imu.funcs->load_microcode)
1329 adev->gfx.imu.funcs->load_microcode(adev);
1330 /* RLC autoload sequence 4 init IMU fw */
1331 if (adev->gfx.imu.funcs->setup_imu)
1332 adev->gfx.imu.funcs->setup_imu(adev);
1333 if (adev->gfx.imu.funcs->start_imu)
1334 adev->gfx.imu.funcs->start_imu(adev);
1335
1336 /* RLC autoload sequence 5 disable gpa mode */
1337 gfx_v12_0_disable_gpa_mode(adev);
1338 } else {
1339 /* unhalt rlc to start autoload without imu */
1340 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
1341 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1);
1342 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
1343 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data);
1344 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
1345 }
1346
1347 return 0;
1348 }
1349
gfx_v12_0_alloc_ip_dump(struct amdgpu_device * adev)1350 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev)
1351 {
1352 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
1353 uint32_t *ptr;
1354 uint32_t inst;
1355
1356 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
1357 if (!ptr) {
1358 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
1359 adev->gfx.ip_dump_core = NULL;
1360 } else {
1361 adev->gfx.ip_dump_core = ptr;
1362 }
1363
1364 /* Allocate memory for compute queue registers for all the instances */
1365 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
1366 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
1367 adev->gfx.mec.num_queue_per_pipe;
1368
1369 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
1370 if (!ptr) {
1371 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
1372 adev->gfx.ip_dump_compute_queues = NULL;
1373 } else {
1374 adev->gfx.ip_dump_compute_queues = ptr;
1375 }
1376
1377 /* Allocate memory for gfx queue registers for all the instances */
1378 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
1379 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
1380 adev->gfx.me.num_queue_per_pipe;
1381
1382 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
1383 if (!ptr) {
1384 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
1385 adev->gfx.ip_dump_gfx_queues = NULL;
1386 } else {
1387 adev->gfx.ip_dump_gfx_queues = ptr;
1388 }
1389 }
1390
gfx_v12_0_sw_init(struct amdgpu_ip_block * ip_block)1391 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
1392 {
1393 int i, j, k, r, ring_id = 0;
1394 unsigned num_compute_rings;
1395 int xcc_id = 0;
1396 struct amdgpu_device *adev = ip_block->adev;
1397 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */
1398
1399 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
1400
1401 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1402 case IP_VERSION(12, 0, 0):
1403 case IP_VERSION(12, 0, 1):
1404 adev->gfx.me.num_me = 1;
1405 adev->gfx.me.num_pipe_per_me = 1;
1406 adev->gfx.me.num_queue_per_pipe = 8;
1407 adev->gfx.mec.num_mec = 1;
1408 adev->gfx.mec.num_pipe_per_mec = 2;
1409 adev->gfx.mec.num_queue_per_pipe = 4;
1410 break;
1411 default:
1412 adev->gfx.me.num_me = 1;
1413 adev->gfx.me.num_pipe_per_me = 1;
1414 adev->gfx.me.num_queue_per_pipe = 1;
1415 adev->gfx.mec.num_mec = 1;
1416 adev->gfx.mec.num_pipe_per_mec = 4;
1417 adev->gfx.mec.num_queue_per_pipe = 8;
1418 break;
1419 }
1420
1421 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1422 case IP_VERSION(12, 0, 0):
1423 case IP_VERSION(12, 0, 1):
1424 if (!adev->gfx.disable_uq &&
1425 adev->gfx.me_fw_version >= 2780 &&
1426 adev->gfx.pfp_fw_version >= 2840 &&
1427 adev->gfx.mec_fw_version >= 3050 &&
1428 adev->mes.fw_version[0] >= 123) {
1429 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
1430 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
1431 }
1432 break;
1433 default:
1434 break;
1435 }
1436
1437 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1438 case IP_VERSION(12, 0, 0):
1439 case IP_VERSION(12, 0, 1):
1440 if (adev->gfx.me_fw_version >= 2480 &&
1441 adev->gfx.pfp_fw_version >= 2530 &&
1442 adev->gfx.mec_fw_version >= 2680 &&
1443 adev->mes.fw_version[0] >= 100)
1444 adev->gfx.enable_cleaner_shader = true;
1445 break;
1446 default:
1447 adev->gfx.enable_cleaner_shader = false;
1448 break;
1449 }
1450
1451 if (adev->gfx.num_compute_rings) {
1452 /* recalculate compute rings to use based on hardware configuration */
1453 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *
1454 adev->gfx.mec.num_queue_per_pipe) / 2;
1455 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,
1456 num_compute_rings);
1457 }
1458
1459 /* EOP Event */
1460 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1461 GFX_12_0_0__SRCID__CP_EOP_INTERRUPT,
1462 &adev->gfx.eop_irq);
1463 if (r)
1464 return r;
1465
1466 /* Bad opcode Event */
1467 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1468 GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR,
1469 &adev->gfx.bad_op_irq);
1470 if (r)
1471 return r;
1472
1473 /* Privileged reg */
1474 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1475 GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT,
1476 &adev->gfx.priv_reg_irq);
1477 if (r)
1478 return r;
1479
1480 /* Privileged inst */
1481 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1482 GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT,
1483 &adev->gfx.priv_inst_irq);
1484 if (r)
1485 return r;
1486
1487 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1488
1489 gfx_v12_0_me_init(adev);
1490
1491 r = gfx_v12_0_rlc_init(adev);
1492 if (r) {
1493 dev_err(adev->dev, "Failed to init rlc BOs!\n");
1494 return r;
1495 }
1496
1497 r = gfx_v12_0_mec_init(adev);
1498 if (r) {
1499 dev_err(adev->dev, "Failed to init MEC BOs!\n");
1500 return r;
1501 }
1502
1503 if (adev->gfx.num_gfx_rings) {
1504 /* set up the gfx ring */
1505 for (i = 0; i < adev->gfx.me.num_me; i++) {
1506 for (j = 0; j < num_queue_per_pipe; j++) {
1507 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1508 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1509 continue;
1510
1511 r = gfx_v12_0_gfx_ring_init(adev, ring_id,
1512 i, k, j);
1513 if (r)
1514 return r;
1515 ring_id++;
1516 }
1517 }
1518 }
1519 }
1520
1521 if (adev->gfx.num_compute_rings) {
1522 ring_id = 0;
1523 /* set up the compute queues - allocate horizontally across pipes */
1524 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1525 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1526 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1527 if (!amdgpu_gfx_is_mec_queue_enabled(adev,
1528 0, i, k, j))
1529 continue;
1530
1531 r = gfx_v12_0_compute_ring_init(adev, ring_id,
1532 i, k, j);
1533 if (r)
1534 return r;
1535
1536 ring_id++;
1537 }
1538 }
1539 }
1540 }
1541
1542 adev->gfx.gfx_supported_reset =
1543 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
1544 adev->gfx.compute_supported_reset =
1545 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
1546 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1547 case IP_VERSION(12, 0, 0):
1548 case IP_VERSION(12, 0, 1):
1549 if ((adev->gfx.me_fw_version >= 2660) &&
1550 (adev->gfx.mec_fw_version >= 2920) &&
1551 !amdgpu_sriov_vf(adev) &&
1552 !adev->debug_disable_gpu_ring_reset) {
1553 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1554 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1555 }
1556 break;
1557 default:
1558 break;
1559 }
1560
1561 if (!adev->enable_mes_kiq) {
1562 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0);
1563 if (r) {
1564 dev_err(adev->dev, "Failed to init KIQ BOs!\n");
1565 return r;
1566 }
1567
1568 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
1569 if (r)
1570 return r;
1571 }
1572
1573 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0);
1574 if (r)
1575 return r;
1576
1577 /* allocate visible FB for rlc auto-loading fw */
1578 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1579 r = gfx_v12_0_rlc_autoload_buffer_init(adev);
1580 if (r)
1581 return r;
1582 }
1583
1584 r = gfx_v12_0_gpu_early_init(adev);
1585 if (r)
1586 return r;
1587
1588 gfx_v12_0_alloc_ip_dump(adev);
1589
1590 r = amdgpu_gfx_sysfs_init(adev);
1591 if (r)
1592 return r;
1593
1594 return 0;
1595 }
1596
gfx_v12_0_pfp_fini(struct amdgpu_device * adev)1597 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev)
1598 {
1599 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1600 &adev->gfx.pfp.pfp_fw_gpu_addr,
1601 (void **)&adev->gfx.pfp.pfp_fw_ptr);
1602
1603 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj,
1604 &adev->gfx.pfp.pfp_fw_data_gpu_addr,
1605 (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
1606 }
1607
gfx_v12_0_me_fini(struct amdgpu_device * adev)1608 static void gfx_v12_0_me_fini(struct amdgpu_device *adev)
1609 {
1610 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1611 &adev->gfx.me.me_fw_gpu_addr,
1612 (void **)&adev->gfx.me.me_fw_ptr);
1613
1614 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj,
1615 &adev->gfx.me.me_fw_data_gpu_addr,
1616 (void **)&adev->gfx.me.me_fw_data_ptr);
1617 }
1618
gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device * adev)1619 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)
1620 {
1621 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1622 &adev->gfx.rlc.rlc_autoload_gpu_addr,
1623 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1624 }
1625
gfx_v12_0_sw_fini(struct amdgpu_ip_block * ip_block)1626 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block)
1627 {
1628 int i;
1629 struct amdgpu_device *adev = ip_block->adev;
1630
1631 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1632 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1633 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1634 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1635
1636 amdgpu_gfx_mqd_sw_fini(adev, 0);
1637
1638 if (!adev->enable_mes_kiq) {
1639 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
1640 amdgpu_gfx_kiq_fini(adev, 0);
1641 }
1642
1643 gfx_v12_0_pfp_fini(adev);
1644 gfx_v12_0_me_fini(adev);
1645 gfx_v12_0_rlc_fini(adev);
1646 gfx_v12_0_mec_fini(adev);
1647
1648 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1649 gfx_v12_0_rlc_autoload_buffer_fini(adev);
1650
1651 gfx_v12_0_free_microcode(adev);
1652
1653 amdgpu_gfx_sysfs_fini(adev);
1654
1655 kfree(adev->gfx.ip_dump_core);
1656 kfree(adev->gfx.ip_dump_compute_queues);
1657 kfree(adev->gfx.ip_dump_gfx_queues);
1658
1659 return 0;
1660 }
1661
gfx_v12_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id)1662 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1663 u32 sh_num, u32 instance, int xcc_id)
1664 {
1665 u32 data;
1666
1667 if (instance == 0xffffffff)
1668 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1669 INSTANCE_BROADCAST_WRITES, 1);
1670 else
1671 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1672 instance);
1673
1674 if (se_num == 0xffffffff)
1675 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1676 1);
1677 else
1678 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1679
1680 if (sh_num == 0xffffffff)
1681 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1682 1);
1683 else
1684 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1685
1686 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
1687 }
1688
gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device * adev)1689 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev)
1690 {
1691 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask;
1692
1693 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE);
1694 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask,
1695 GRBM_CC_GC_SA_UNIT_DISABLE,
1696 SA_DISABLE);
1697 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE);
1698 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask,
1699 GRBM_GC_USER_SA_UNIT_DISABLE,
1700 SA_DISABLE);
1701 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
1702 adev->gfx.config.max_shader_engines);
1703
1704 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask));
1705 }
1706
gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device * adev)1707 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1708 {
1709 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask;
1710 u32 rb_mask;
1711
1712 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
1713 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask,
1714 CC_RB_BACKEND_DISABLE,
1715 BACKEND_DISABLE);
1716 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
1717 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask,
1718 GC_USER_RB_BACKEND_DISABLE,
1719 BACKEND_DISABLE);
1720 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se *
1721 adev->gfx.config.max_shader_engines);
1722
1723 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask));
1724 }
1725
gfx_v12_0_setup_rb(struct amdgpu_device * adev)1726 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev)
1727 {
1728 u32 rb_bitmap_per_sa;
1729 u32 rb_bitmap_width_per_sa;
1730 u32 max_sa;
1731 u32 active_sa_bitmap;
1732 u32 global_active_rb_bitmap;
1733 u32 active_rb_bitmap = 0;
1734 u32 i;
1735
1736 /* query sa bitmap from SA_UNIT_DISABLE registers */
1737 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev);
1738 /* query rb bitmap from RB_BACKEND_DISABLE registers */
1739 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev);
1740
1741 /* generate active rb bitmap according to active sa bitmap */
1742 max_sa = adev->gfx.config.max_shader_engines *
1743 adev->gfx.config.max_sh_per_se;
1744 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se /
1745 adev->gfx.config.max_sh_per_se;
1746 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa);
1747
1748 for (i = 0; i < max_sa; i++) {
1749 if (active_sa_bitmap & (1 << i))
1750 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa));
1751 }
1752
1753 active_rb_bitmap &= global_active_rb_bitmap;
1754 adev->gfx.config.backend_enable_mask = active_rb_bitmap;
1755 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);
1756 }
1757
1758 #define LDS_APP_BASE 0x1
1759 #define SCRATCH_APP_BASE 0x2
1760
gfx_v12_0_init_compute_vmid(struct amdgpu_device * adev)1761 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev)
1762 {
1763 int i;
1764 uint32_t sh_mem_bases;
1765 uint32_t data;
1766
1767 /*
1768 * Configure apertures:
1769 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1770 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1771 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1772 */
1773 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) |
1774 SCRATCH_APP_BASE;
1775
1776 mutex_lock(&adev->srbm_mutex);
1777 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1778 soc24_grbm_select(adev, 0, 0, 0, i);
1779 /* CP and shaders */
1780 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1781 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
1782
1783 /* Enable trap for each kfd vmid. */
1784 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
1785 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1786 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data);
1787 }
1788 soc24_grbm_select(adev, 0, 0, 0, 0);
1789 mutex_unlock(&adev->srbm_mutex);
1790 }
1791
gfx_v12_0_tcp_harvest(struct amdgpu_device * adev)1792 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev)
1793 {
1794 /* TODO: harvest feature to be added later. */
1795 }
1796
gfx_v12_0_get_tcc_info(struct amdgpu_device * adev)1797 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev)
1798 {
1799 }
1800
gfx_v12_0_constants_init(struct amdgpu_device * adev)1801 static void gfx_v12_0_constants_init(struct amdgpu_device *adev)
1802 {
1803 u32 tmp;
1804 int i;
1805
1806 if (!amdgpu_sriov_vf(adev))
1807 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1808
1809 gfx_v12_0_setup_rb(adev);
1810 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info);
1811 gfx_v12_0_get_tcc_info(adev);
1812 adev->gfx.config.pa_sc_tile_steering_override = 0;
1813
1814 /* XXX SH_MEM regs */
1815 /* where to put LDS, scratch, GPUVM in FSA64 space */
1816 mutex_lock(&adev->srbm_mutex);
1817 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
1818 soc24_grbm_select(adev, 0, 0, 0, i);
1819 /* CP and shaders */
1820 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1821 if (i != 0) {
1822 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1823 (adev->gmc.private_aperture_start >> 48));
1824 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1825 (adev->gmc.shared_aperture_start >> 48));
1826 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
1827 }
1828 }
1829 soc24_grbm_select(adev, 0, 0, 0, 0);
1830
1831 mutex_unlock(&adev->srbm_mutex);
1832
1833 gfx_v12_0_init_compute_vmid(adev);
1834 }
1835
gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device * adev,int me,int pipe)1836 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev,
1837 int me, int pipe)
1838 {
1839 if (me != 0)
1840 return 0;
1841
1842 switch (pipe) {
1843 case 0:
1844 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
1845 default:
1846 return 0;
1847 }
1848 }
1849
gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device * adev,int me,int pipe)1850 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev,
1851 int me, int pipe)
1852 {
1853 /*
1854 * amdgpu controls only the first MEC. That's why this function only
1855 * handles the setting of interrupts for this specific MEC. All other
1856 * pipes' interrupts are set by amdkfd.
1857 */
1858 if (me != 1)
1859 return 0;
1860
1861 switch (pipe) {
1862 case 0:
1863 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
1864 case 1:
1865 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
1866 default:
1867 return 0;
1868 }
1869 }
1870
gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)1871 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1872 bool enable)
1873 {
1874 u32 tmp, cp_int_cntl_reg;
1875 int i, j;
1876
1877 if (amdgpu_sriov_vf(adev))
1878 return;
1879
1880 for (i = 0; i < adev->gfx.me.num_me; i++) {
1881 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
1882 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
1883
1884 if (cp_int_cntl_reg) {
1885 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
1886 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1887 enable ? 1 : 0);
1888 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1889 enable ? 1 : 0);
1890 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1891 enable ? 1 : 0);
1892 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1893 enable ? 1 : 0);
1894 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
1895 }
1896 }
1897 }
1898 }
1899
gfx_v12_0_init_csb(struct amdgpu_device * adev)1900 static int gfx_v12_0_init_csb(struct amdgpu_device *adev)
1901 {
1902 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1903
1904 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,
1905 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1906 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,
1907 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1908 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1909
1910 return 0;
1911 }
1912
gfx_v12_0_rlc_stop(struct amdgpu_device * adev)1913 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev)
1914 {
1915 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
1916
1917 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1918 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
1919 }
1920
gfx_v12_0_rlc_reset(struct amdgpu_device * adev)1921 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev)
1922 {
1923 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1924 udelay(50);
1925 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1926 udelay(50);
1927 }
1928
gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device * adev,bool enable)1929 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1930 bool enable)
1931 {
1932 uint32_t rlc_pg_cntl;
1933
1934 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
1935
1936 if (!enable) {
1937 /* RLC_PG_CNTL[23] = 0 (default)
1938 * RLC will wait for handshake acks with SMU
1939 * GFXOFF will be enabled
1940 * RLC_PG_CNTL[23] = 1
1941 * RLC will not issue any message to SMU
1942 * hence no handshake between SMU & RLC
1943 * GFXOFF will be disabled
1944 */
1945 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1946 } else
1947 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1948 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);
1949 }
1950
gfx_v12_0_rlc_start(struct amdgpu_device * adev)1951 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev)
1952 {
1953 /* TODO: enable rlc & smu handshake until smu
1954 * and gfxoff feature works as expected */
1955 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1956 gfx_v12_0_rlc_smu_handshake_cntl(adev, false);
1957
1958 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1959 udelay(50);
1960 }
1961
gfx_v12_0_rlc_enable_srm(struct amdgpu_device * adev)1962 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev)
1963 {
1964 uint32_t tmp;
1965
1966 /* enable Save Restore Machine */
1967 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
1968 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1969 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1970 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
1971 }
1972
gfx_v12_0_load_rlcg_microcode(struct amdgpu_device * adev)1973 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev)
1974 {
1975 const struct rlc_firmware_header_v2_0 *hdr;
1976 const __le32 *fw_data;
1977 unsigned i, fw_size;
1978
1979 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1980 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1981 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1982 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1983
1984 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,
1985 RLCG_UCODE_LOADING_START_ADDRESS);
1986
1987 for (i = 0; i < fw_size; i++)
1988 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,
1989 le32_to_cpup(fw_data++));
1990
1991 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1992 }
1993
gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device * adev)1994 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev)
1995 {
1996 const struct rlc_firmware_header_v2_2 *hdr;
1997 const __le32 *fw_data;
1998 unsigned i, fw_size;
1999 u32 tmp;
2000
2001 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
2002
2003 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2004 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes));
2005 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4;
2006
2007 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);
2008
2009 for (i = 0; i < fw_size; i++) {
2010 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
2011 msleep(1);
2012 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,
2013 le32_to_cpup(fw_data++));
2014 }
2015
2016 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
2017
2018 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2019 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes));
2020 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4;
2021
2022 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);
2023 for (i = 0; i < fw_size; i++) {
2024 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
2025 msleep(1);
2026 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,
2027 le32_to_cpup(fw_data++));
2028 }
2029
2030 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
2031
2032 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
2033 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
2034 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
2035 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
2036 }
2037
gfx_v12_0_rlc_load_microcode(struct amdgpu_device * adev)2038 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev)
2039 {
2040 const struct rlc_firmware_header_v2_0 *hdr;
2041 uint16_t version_major;
2042 uint16_t version_minor;
2043
2044 if (!adev->gfx.rlc_fw)
2045 return -EINVAL;
2046
2047 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2048 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2049
2050 version_major = le16_to_cpu(hdr->header.header_version_major);
2051 version_minor = le16_to_cpu(hdr->header.header_version_minor);
2052
2053 if (version_major == 2) {
2054 gfx_v12_0_load_rlcg_microcode(adev);
2055 if (amdgpu_dpm == 1) {
2056 if (version_minor >= 2)
2057 gfx_v12_0_load_rlc_iram_dram_microcode(adev);
2058 }
2059
2060 return 0;
2061 }
2062
2063 return -EINVAL;
2064 }
2065
gfx_v12_0_rlc_resume(struct amdgpu_device * adev)2066 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev)
2067 {
2068 int r;
2069
2070 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2071 gfx_v12_0_init_csb(adev);
2072
2073 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
2074 gfx_v12_0_rlc_enable_srm(adev);
2075 } else {
2076 if (amdgpu_sriov_vf(adev)) {
2077 gfx_v12_0_init_csb(adev);
2078 return 0;
2079 }
2080
2081 adev->gfx.rlc.funcs->stop(adev);
2082
2083 /* disable CG */
2084 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
2085
2086 /* disable PG */
2087 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);
2088
2089 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
2090 /* legacy rlc firmware loading */
2091 r = gfx_v12_0_rlc_load_microcode(adev);
2092 if (r)
2093 return r;
2094 }
2095
2096 gfx_v12_0_init_csb(adev);
2097
2098 adev->gfx.rlc.funcs->start(adev);
2099 }
2100
2101 return 0;
2102 }
2103
gfx_v12_0_config_gfx_rs64(struct amdgpu_device * adev)2104 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev)
2105 {
2106 const struct gfx_firmware_header_v2_0 *pfp_hdr;
2107 const struct gfx_firmware_header_v2_0 *me_hdr;
2108 const struct gfx_firmware_header_v2_0 *mec_hdr;
2109 uint32_t pipe_id, tmp;
2110
2111 mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2112 adev->gfx.mec_fw->data;
2113 me_hdr = (const struct gfx_firmware_header_v2_0 *)
2114 adev->gfx.me_fw->data;
2115 pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2116 adev->gfx.pfp_fw->data;
2117
2118 /* config pfp program start addr */
2119 for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2120 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2121 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2122 (pfp_hdr->ucode_start_addr_hi << 30) |
2123 (pfp_hdr->ucode_start_addr_lo >> 2));
2124 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2125 pfp_hdr->ucode_start_addr_hi >> 2);
2126 }
2127 soc24_grbm_select(adev, 0, 0, 0, 0);
2128
2129 /* reset pfp pipe */
2130 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2131 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
2132 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
2133 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2134
2135 /* clear pfp pipe reset */
2136 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
2137 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
2138 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2139
2140 /* config me program start addr */
2141 for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2142 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2143 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2144 (me_hdr->ucode_start_addr_hi << 30) |
2145 (me_hdr->ucode_start_addr_lo >> 2));
2146 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2147 me_hdr->ucode_start_addr_hi>>2);
2148 }
2149 soc24_grbm_select(adev, 0, 0, 0, 0);
2150
2151 /* reset me pipe */
2152 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2153 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
2154 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
2155 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2156
2157 /* clear me pipe reset */
2158 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
2159 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
2160 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2161
2162 /* config mec program start addr */
2163 for (pipe_id = 0; pipe_id < 4; pipe_id++) {
2164 soc24_grbm_select(adev, 1, pipe_id, 0, 0);
2165 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2166 mec_hdr->ucode_start_addr_lo >> 2 |
2167 mec_hdr->ucode_start_addr_hi << 30);
2168 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2169 mec_hdr->ucode_start_addr_hi >> 2);
2170 }
2171 soc24_grbm_select(adev, 0, 0, 0, 0);
2172
2173 /* reset mec pipe */
2174 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2175 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
2176 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
2177 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
2178 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
2179 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2180
2181 /* clear mec pipe reset */
2182 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
2183 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
2184 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
2185 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
2186 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2187 }
2188
gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device * adev)2189 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev)
2190 {
2191 const struct gfx_firmware_header_v2_0 *cp_hdr;
2192 unsigned pipe_id, tmp;
2193
2194 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2195 adev->gfx.pfp_fw->data;
2196 mutex_lock(&adev->srbm_mutex);
2197 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2198 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2199 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2200 (cp_hdr->ucode_start_addr_hi << 30) |
2201 (cp_hdr->ucode_start_addr_lo >> 2));
2202 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2203 cp_hdr->ucode_start_addr_hi>>2);
2204
2205 /*
2206 * Program CP_ME_CNTL to reset given PIPE to take
2207 * effect of CP_PFP_PRGRM_CNTR_START.
2208 */
2209 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2210 if (pipe_id == 0)
2211 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2212 PFP_PIPE0_RESET, 1);
2213 else
2214 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2215 PFP_PIPE1_RESET, 1);
2216 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2217
2218 /* Clear pfp pipe0 reset bit. */
2219 if (pipe_id == 0)
2220 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2221 PFP_PIPE0_RESET, 0);
2222 else
2223 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2224 PFP_PIPE1_RESET, 0);
2225 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2226 }
2227 soc24_grbm_select(adev, 0, 0, 0, 0);
2228 mutex_unlock(&adev->srbm_mutex);
2229 }
2230
gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device * adev)2231 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev)
2232 {
2233 const struct gfx_firmware_header_v2_0 *cp_hdr;
2234 unsigned pipe_id, tmp;
2235
2236 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2237 adev->gfx.me_fw->data;
2238 mutex_lock(&adev->srbm_mutex);
2239 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2240 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2241 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2242 (cp_hdr->ucode_start_addr_hi << 30) |
2243 (cp_hdr->ucode_start_addr_lo >> 2) );
2244 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2245 cp_hdr->ucode_start_addr_hi>>2);
2246
2247 /*
2248 * Program CP_ME_CNTL to reset given PIPE to take
2249 * effect of CP_ME_PRGRM_CNTR_START.
2250 */
2251 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2252 if (pipe_id == 0)
2253 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2254 ME_PIPE0_RESET, 1);
2255 else
2256 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2257 ME_PIPE1_RESET, 1);
2258 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2259
2260 /* Clear pfp pipe0 reset bit. */
2261 if (pipe_id == 0)
2262 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2263 ME_PIPE0_RESET, 0);
2264 else
2265 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2266 ME_PIPE1_RESET, 0);
2267 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2268 }
2269 soc24_grbm_select(adev, 0, 0, 0, 0);
2270 mutex_unlock(&adev->srbm_mutex);
2271 }
2272
gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device * adev)2273 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev)
2274 {
2275 const struct gfx_firmware_header_v2_0 *cp_hdr;
2276 unsigned pipe_id;
2277
2278 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2279 adev->gfx.mec_fw->data;
2280 mutex_lock(&adev->srbm_mutex);
2281 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) {
2282 soc24_grbm_select(adev, 1, pipe_id, 0, 0);
2283 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2284 cp_hdr->ucode_start_addr_lo >> 2 |
2285 cp_hdr->ucode_start_addr_hi << 30);
2286 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2287 cp_hdr->ucode_start_addr_hi >> 2);
2288 }
2289 soc24_grbm_select(adev, 0, 0, 0, 0);
2290 mutex_unlock(&adev->srbm_mutex);
2291 }
2292
gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device * adev)2293 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2294 {
2295 uint32_t cp_status;
2296 uint32_t bootload_status;
2297 int i;
2298
2299 for (i = 0; i < adev->usec_timeout; i++) {
2300 cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
2301 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
2302
2303 if ((cp_status == 0) &&
2304 (REG_GET_FIELD(bootload_status,
2305 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2306 break;
2307 }
2308 udelay(1);
2309 if (amdgpu_emu_mode)
2310 msleep(10);
2311 }
2312
2313 if (i >= adev->usec_timeout) {
2314 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2315 return -ETIMEDOUT;
2316 }
2317
2318 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2319 gfx_v12_0_set_pfp_ucode_start_addr(adev);
2320 gfx_v12_0_set_me_ucode_start_addr(adev);
2321 gfx_v12_0_set_mec_ucode_start_addr(adev);
2322 }
2323
2324 return 0;
2325 }
2326
gfx_v12_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)2327 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2328 {
2329 int i;
2330 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2331
2332 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2333 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2334 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2335
2336 for (i = 0; i < adev->usec_timeout; i++) {
2337 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)
2338 break;
2339 udelay(1);
2340 }
2341
2342 if (i >= adev->usec_timeout)
2343 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2344
2345 return 0;
2346 }
2347
gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device * adev)2348 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
2349 {
2350 int r;
2351 const struct gfx_firmware_header_v2_0 *pfp_hdr;
2352 const __le32 *fw_ucode, *fw_data;
2353 unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2354 uint32_t tmp;
2355 uint32_t usec_timeout = 50000; /* wait for 50ms */
2356
2357 pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2358 adev->gfx.pfp_fw->data;
2359
2360 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2361
2362 /* instruction */
2363 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data +
2364 le32_to_cpu(pfp_hdr->ucode_offset_bytes));
2365 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes);
2366 /* data */
2367 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2368 le32_to_cpu(pfp_hdr->data_offset_bytes));
2369 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes);
2370
2371 /* 64kb align */
2372 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2373 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2374 &adev->gfx.pfp.pfp_fw_obj,
2375 &adev->gfx.pfp.pfp_fw_gpu_addr,
2376 (void **)&adev->gfx.pfp.pfp_fw_ptr);
2377 if (r) {
2378 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r);
2379 gfx_v12_0_pfp_fini(adev);
2380 return r;
2381 }
2382
2383 r = amdgpu_bo_create_reserved(adev, fw_data_size,
2384 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2385 &adev->gfx.pfp.pfp_fw_data_obj,
2386 &adev->gfx.pfp.pfp_fw_data_gpu_addr,
2387 (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
2388 if (r) {
2389 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r);
2390 gfx_v12_0_pfp_fini(adev);
2391 return r;
2392 }
2393
2394 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);
2395 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);
2396
2397 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2398 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj);
2399 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2400 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
2401
2402 if (amdgpu_emu_mode == 1)
2403 amdgpu_device_flush_hdp(adev, NULL);
2404
2405 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2406 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2407 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2408 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2409
2410 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2411 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2412 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2413 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2414 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2415
2416 /*
2417 * Programming any of the CP_PFP_IC_BASE registers
2418 * forces invalidation of the ME L1 I$. Wait for the
2419 * invalidation complete
2420 */
2421 for (i = 0; i < usec_timeout; i++) {
2422 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2423 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2424 INVALIDATE_CACHE_COMPLETE))
2425 break;
2426 udelay(1);
2427 }
2428
2429 if (i >= usec_timeout) {
2430 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2431 return -EINVAL;
2432 }
2433
2434 /* Prime the L1 instruction caches */
2435 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2436 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2437 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2438 /* Waiting for cache primed*/
2439 for (i = 0; i < usec_timeout; i++) {
2440 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2441 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2442 ICACHE_PRIMED))
2443 break;
2444 udelay(1);
2445 }
2446
2447 if (i >= usec_timeout) {
2448 dev_err(adev->dev, "failed to prime instruction cache\n");
2449 return -EINVAL;
2450 }
2451
2452 mutex_lock(&adev->srbm_mutex);
2453 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2454 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2455
2456 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2457 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2458 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2459 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2460 }
2461 soc24_grbm_select(adev, 0, 0, 0, 0);
2462 mutex_unlock(&adev->srbm_mutex);
2463
2464 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2465 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2466 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2467 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2468
2469 /* Invalidate the data caches */
2470 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2471 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2472 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2473
2474 for (i = 0; i < usec_timeout; i++) {
2475 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2476 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2477 INVALIDATE_DCACHE_COMPLETE))
2478 break;
2479 udelay(1);
2480 }
2481
2482 if (i >= usec_timeout) {
2483 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2484 return -EINVAL;
2485 }
2486
2487 gfx_v12_0_set_pfp_ucode_start_addr(adev);
2488
2489 return 0;
2490 }
2491
gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device * adev)2492 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
2493 {
2494 int r;
2495 const struct gfx_firmware_header_v2_0 *me_hdr;
2496 const __le32 *fw_ucode, *fw_data;
2497 unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2498 uint32_t tmp;
2499 uint32_t usec_timeout = 50000; /* wait for 50ms */
2500
2501 me_hdr = (const struct gfx_firmware_header_v2_0 *)
2502 adev->gfx.me_fw->data;
2503
2504 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2505
2506 /* instruction */
2507 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data +
2508 le32_to_cpu(me_hdr->ucode_offset_bytes));
2509 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes);
2510 /* data */
2511 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2512 le32_to_cpu(me_hdr->data_offset_bytes));
2513 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes);
2514
2515 /* 64kb align*/
2516 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2517 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2518 &adev->gfx.me.me_fw_obj,
2519 &adev->gfx.me.me_fw_gpu_addr,
2520 (void **)&adev->gfx.me.me_fw_ptr);
2521 if (r) {
2522 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r);
2523 gfx_v12_0_me_fini(adev);
2524 return r;
2525 }
2526
2527 r = amdgpu_bo_create_reserved(adev, fw_data_size,
2528 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2529 &adev->gfx.me.me_fw_data_obj,
2530 &adev->gfx.me.me_fw_data_gpu_addr,
2531 (void **)&adev->gfx.me.me_fw_data_ptr);
2532 if (r) {
2533 dev_err(adev->dev, "(%d) failed to create me data bo\n", r);
2534 gfx_v12_0_me_fini(adev);
2535 return r;
2536 }
2537
2538 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);
2539 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size);
2540
2541 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2542 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj);
2543 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2544 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
2545
2546 if (amdgpu_emu_mode == 1)
2547 amdgpu_device_flush_hdp(adev, NULL);
2548
2549 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2550 lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
2551 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2552 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2553
2554 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2555 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2556 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2557 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2558 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2559
2560 /*
2561 * Programming any of the CP_ME_IC_BASE registers
2562 * forces invalidation of the ME L1 I$. Wait for the
2563 * invalidation complete
2564 */
2565 for (i = 0; i < usec_timeout; i++) {
2566 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2567 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2568 INVALIDATE_CACHE_COMPLETE))
2569 break;
2570 udelay(1);
2571 }
2572
2573 if (i >= usec_timeout) {
2574 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2575 return -EINVAL;
2576 }
2577
2578 /* Prime the instruction caches */
2579 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2580 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2581 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2582
2583 /* Waiting for instruction cache primed*/
2584 for (i = 0; i < usec_timeout; i++) {
2585 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2586 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2587 ICACHE_PRIMED))
2588 break;
2589 udelay(1);
2590 }
2591
2592 if (i >= usec_timeout) {
2593 dev_err(adev->dev, "failed to prime instruction cache\n");
2594 return -EINVAL;
2595 }
2596
2597 mutex_lock(&adev->srbm_mutex);
2598 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2599 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2600
2601 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2602 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2603 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2604 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2605 }
2606 soc24_grbm_select(adev, 0, 0, 0, 0);
2607 mutex_unlock(&adev->srbm_mutex);
2608
2609 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2610 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2611 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2612 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2613
2614 /* Invalidate the data caches */
2615 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2616 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2617 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2618
2619 for (i = 0; i < usec_timeout; i++) {
2620 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2621 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2622 INVALIDATE_DCACHE_COMPLETE))
2623 break;
2624 udelay(1);
2625 }
2626
2627 if (i >= usec_timeout) {
2628 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2629 return -EINVAL;
2630 }
2631
2632 gfx_v12_0_set_me_ucode_start_addr(adev);
2633
2634 return 0;
2635 }
2636
gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device * adev)2637 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2638 {
2639 int r;
2640
2641 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw)
2642 return -EINVAL;
2643
2644 gfx_v12_0_cp_gfx_enable(adev, false);
2645
2646 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev);
2647 if (r) {
2648 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2649 return r;
2650 }
2651
2652 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev);
2653 if (r) {
2654 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2655 return r;
2656 }
2657
2658 return 0;
2659 }
2660
gfx_v12_0_cp_gfx_start(struct amdgpu_device * adev)2661 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev)
2662 {
2663 /* init the CP */
2664 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,
2665 adev->gfx.config.max_hw_contexts - 1);
2666 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);
2667
2668 if (!amdgpu_async_gfx_ring)
2669 gfx_v12_0_cp_gfx_enable(adev, true);
2670
2671 return 0;
2672 }
2673
gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device * adev,CP_PIPE_ID pipe)2674 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2675 CP_PIPE_ID pipe)
2676 {
2677 u32 tmp;
2678
2679 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
2680 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2681
2682 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
2683 }
2684
gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device * adev,struct amdgpu_ring * ring)2685 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2686 struct amdgpu_ring *ring)
2687 {
2688 u32 tmp;
2689
2690 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
2691 if (ring->use_doorbell) {
2692 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2693 DOORBELL_OFFSET, ring->doorbell_index);
2694 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2695 DOORBELL_EN, 1);
2696 } else {
2697 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2698 DOORBELL_EN, 0);
2699 }
2700 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
2701
2702 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2703 DOORBELL_RANGE_LOWER, ring->doorbell_index);
2704 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
2705
2706 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
2707 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2708 }
2709
gfx_v12_0_cp_gfx_resume(struct amdgpu_device * adev)2710 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev)
2711 {
2712 struct amdgpu_ring *ring;
2713 u32 tmp;
2714 u32 rb_bufsz;
2715 u64 rb_addr, rptr_addr, wptr_gpu_addr;
2716
2717 /* Set the write pointer delay */
2718 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
2719
2720 /* set the RB to use vmid 0 */
2721 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);
2722
2723 /* Init gfx ring 0 for pipe 0 */
2724 mutex_lock(&adev->srbm_mutex);
2725 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2726
2727 /* Set ring buffer size */
2728 ring = &adev->gfx.gfx_ring[0];
2729 rb_bufsz = order_base_2(ring->ring_size / 8);
2730 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2731 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2732 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
2733
2734 /* Initialize the ring buffer's write pointers */
2735 ring->wptr = 0;
2736 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
2737 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2738
2739 /* set the wb address whether it's enabled or not */
2740 rptr_addr = ring->rptr_gpu_addr;
2741 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2742 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2743 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2744
2745 wptr_gpu_addr = ring->wptr_gpu_addr;
2746 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
2747 lower_32_bits(wptr_gpu_addr));
2748 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
2749 upper_32_bits(wptr_gpu_addr));
2750
2751 mdelay(1);
2752 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
2753
2754 rb_addr = ring->gpu_addr >> 8;
2755 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);
2756 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2757
2758 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);
2759
2760 gfx_v12_0_cp_gfx_set_doorbell(adev, ring);
2761 mutex_unlock(&adev->srbm_mutex);
2762
2763 /* Switch to pipe 0 */
2764 mutex_lock(&adev->srbm_mutex);
2765 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2766 mutex_unlock(&adev->srbm_mutex);
2767
2768 /* start the ring */
2769 gfx_v12_0_cp_gfx_start(adev);
2770 return 0;
2771 }
2772
gfx_v12_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)2773 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2774 {
2775 u32 data;
2776
2777 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2778 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,
2779 enable ? 0 : 1);
2780 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,
2781 enable ? 0 : 1);
2782 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,
2783 enable ? 0 : 1);
2784 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,
2785 enable ? 0 : 1);
2786 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,
2787 enable ? 0 : 1);
2788 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,
2789 enable ? 1 : 0);
2790 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,
2791 enable ? 1 : 0);
2792 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,
2793 enable ? 1 : 0);
2794 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,
2795 enable ? 1 : 0);
2796 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,
2797 enable ? 0 : 1);
2798 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);
2799
2800 adev->gfx.kiq[0].ring.sched.ready = enable;
2801
2802 udelay(50);
2803 }
2804
gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device * adev)2805 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev)
2806 {
2807 const struct gfx_firmware_header_v2_0 *mec_hdr;
2808 const __le32 *fw_ucode, *fw_data;
2809 u32 tmp, fw_ucode_size, fw_data_size;
2810 u32 i, usec_timeout = 50000; /* Wait for 50 ms */
2811 u32 *fw_ucode_ptr, *fw_data_ptr;
2812 int r;
2813
2814 if (!adev->gfx.mec_fw)
2815 return -EINVAL;
2816
2817 gfx_v12_0_cp_compute_enable(adev, false);
2818
2819 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
2820 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2821
2822 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data +
2823 le32_to_cpu(mec_hdr->ucode_offset_bytes));
2824 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes);
2825
2826 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2827 le32_to_cpu(mec_hdr->data_offset_bytes));
2828 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
2829
2830 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2831 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2832 &adev->gfx.mec.mec_fw_obj,
2833 &adev->gfx.mec.mec_fw_gpu_addr,
2834 (void **)&fw_ucode_ptr);
2835 if (r) {
2836 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
2837 gfx_v12_0_mec_fini(adev);
2838 return r;
2839 }
2840
2841 r = amdgpu_bo_create_reserved(adev,
2842 ALIGN(fw_data_size, 64 * 1024) *
2843 adev->gfx.mec.num_pipe_per_mec,
2844 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2845 &adev->gfx.mec.mec_fw_data_obj,
2846 &adev->gfx.mec.mec_fw_data_gpu_addr,
2847 (void **)&fw_data_ptr);
2848 if (r) {
2849 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
2850 gfx_v12_0_mec_fini(adev);
2851 return r;
2852 }
2853
2854 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);
2855 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2856 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size);
2857 }
2858
2859 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
2860 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj);
2861 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
2862 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
2863
2864 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2865 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2866 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2867 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2868 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2869
2870 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
2871 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
2872 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
2873 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
2874
2875 mutex_lock(&adev->srbm_mutex);
2876 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2877 soc24_grbm_select(adev, 1, i, 0, 0);
2878
2879 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO,
2880 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr +
2881 i * ALIGN(fw_data_size, 64 * 1024)));
2882 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
2883 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr +
2884 i * ALIGN(fw_data_size, 64 * 1024)));
2885
2886 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
2887 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2888 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2889 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2890 }
2891 mutex_unlock(&adev->srbm_mutex);
2892 soc24_grbm_select(adev, 0, 0, 0, 0);
2893
2894 /* Trigger an invalidation of the L1 instruction caches */
2895 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2896 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2897 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
2898
2899 /* Wait for invalidation complete */
2900 for (i = 0; i < usec_timeout; i++) {
2901 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2902 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
2903 INVALIDATE_DCACHE_COMPLETE))
2904 break;
2905 udelay(1);
2906 }
2907
2908 if (i >= usec_timeout) {
2909 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2910 return -EINVAL;
2911 }
2912
2913 /* Trigger an invalidation of the L1 instruction caches */
2914 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2915 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2916 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2917
2918 /* Wait for invalidation complete */
2919 for (i = 0; i < usec_timeout; i++) {
2920 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2921 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2922 INVALIDATE_CACHE_COMPLETE))
2923 break;
2924 udelay(1);
2925 }
2926
2927 if (i >= usec_timeout) {
2928 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2929 return -EINVAL;
2930 }
2931
2932 gfx_v12_0_set_mec_ucode_start_addr(adev);
2933
2934 return 0;
2935 }
2936
gfx_v12_0_kiq_setting(struct amdgpu_ring * ring)2937 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring)
2938 {
2939 uint32_t tmp;
2940 struct amdgpu_device *adev = ring->adev;
2941
2942 /* tell RLC which is KIQ queue */
2943 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
2944 tmp &= 0xffffff00;
2945 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2946 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
2947 }
2948
gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device * adev)2949 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev)
2950 {
2951 /* set graphics engine doorbell range */
2952 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,
2953 (adev->doorbell_index.gfx_ring0 * 2) << 2);
2954 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
2955 (adev->doorbell_index.gfx_userqueue_end * 2) << 2);
2956
2957 /* set compute engine doorbell range */
2958 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
2959 (adev->doorbell_index.kiq * 2) << 2);
2960 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
2961 (adev->doorbell_index.userqueue_end * 2) << 2);
2962 }
2963
gfx_v12_0_gfx_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)2964 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
2965 struct amdgpu_mqd_prop *prop)
2966 {
2967 struct v12_gfx_mqd *mqd = m;
2968 uint64_t hqd_gpu_addr, wb_gpu_addr;
2969 uint32_t tmp;
2970 uint32_t rb_bufsz;
2971
2972 /* set up gfx hqd wptr */
2973 mqd->cp_gfx_hqd_wptr = 0;
2974 mqd->cp_gfx_hqd_wptr_hi = 0;
2975
2976 /* set the pointer to the MQD */
2977 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
2978 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
2979
2980 /* set up mqd control */
2981 tmp = regCP_GFX_MQD_CONTROL_DEFAULT;
2982 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2983 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2984 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2985 mqd->cp_gfx_mqd_control = tmp;
2986
2987 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
2988 tmp = regCP_GFX_HQD_VMID_DEFAULT;
2989 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
2990 mqd->cp_gfx_hqd_vmid = 0;
2991
2992 /* set up default queue priority level
2993 * 0x0 = low priority, 0x1 = high priority */
2994 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT;
2995 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
2996 mqd->cp_gfx_hqd_queue_priority = tmp;
2997
2998 /* set up time quantum */
2999 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT;
3000 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3001 mqd->cp_gfx_hqd_quantum = tmp;
3002
3003 /* set up gfx hqd base. this is similar as CP_RB_BASE */
3004 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3005 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3006 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3007
3008 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3009 wb_gpu_addr = prop->rptr_gpu_addr;
3010 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3011 mqd->cp_gfx_hqd_rptr_addr_hi =
3012 upper_32_bits(wb_gpu_addr) & 0xffff;
3013
3014 /* set up rb_wptr_poll addr */
3015 wb_gpu_addr = prop->wptr_gpu_addr;
3016 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3017 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3018
3019 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3020 rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
3021 tmp = regCP_GFX_HQD_CNTL_DEFAULT;
3022 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3023 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3024 #ifdef __BIG_ENDIAN
3025 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3026 #endif
3027 if (prop->tmz_queue)
3028 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);
3029 if (!prop->kernel_queue)
3030 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1);
3031 mqd->cp_gfx_hqd_cntl = tmp;
3032
3033 /* set up cp_doorbell_control */
3034 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT;
3035 if (prop->use_doorbell) {
3036 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3037 DOORBELL_OFFSET, prop->doorbell_index);
3038 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3039 DOORBELL_EN, 1);
3040 } else
3041 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3042 DOORBELL_EN, 0);
3043 mqd->cp_rb_doorbell_control = tmp;
3044
3045 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3046 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT;
3047
3048 /* active the queue */
3049 mqd->cp_gfx_hqd_active = 1;
3050
3051 /* set gfx UQ items */
3052 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr);
3053 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr);
3054 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr);
3055 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr);
3056 mqd->fence_address_lo = lower_32_bits(prop->fence_address);
3057 mqd->fence_address_hi = upper_32_bits(prop->fence_address);
3058
3059 return 0;
3060 }
3061
gfx_v12_0_kgq_init_queue(struct amdgpu_ring * ring,bool reset)3062 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
3063 {
3064 struct amdgpu_device *adev = ring->adev;
3065 struct v12_gfx_mqd *mqd = ring->mqd_ptr;
3066 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3067
3068 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
3069 memset((void *)mqd, 0, sizeof(*mqd));
3070 mutex_lock(&adev->srbm_mutex);
3071 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3072 amdgpu_ring_init_mqd(ring);
3073 soc24_grbm_select(adev, 0, 0, 0, 0);
3074 mutex_unlock(&adev->srbm_mutex);
3075 if (adev->gfx.me.mqd_backup[mqd_idx])
3076 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3077 } else {
3078 /* restore mqd with the backup copy */
3079 if (adev->gfx.me.mqd_backup[mqd_idx])
3080 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3081 /* reset the ring */
3082 ring->wptr = 0;
3083 *ring->wptr_cpu_addr = 0;
3084 amdgpu_ring_clear_ring(ring);
3085 }
3086
3087 return 0;
3088 }
3089
gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device * adev)3090 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3091 {
3092 int i, r;
3093
3094 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3095 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
3096 if (r)
3097 return r;
3098 }
3099
3100 r = amdgpu_gfx_enable_kgq(adev, 0);
3101 if (r)
3102 return r;
3103
3104 return gfx_v12_0_cp_gfx_start(adev);
3105 }
3106
gfx_v12_0_compute_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)3107 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
3108 struct amdgpu_mqd_prop *prop)
3109 {
3110 struct v12_compute_mqd *mqd = m;
3111 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3112 uint32_t tmp;
3113
3114 mqd->header = 0xC0310800;
3115 mqd->compute_pipelinestat_enable = 0x00000001;
3116 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3117 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3118 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3119 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3120 mqd->compute_misc_reserved = 0x00000007;
3121
3122 eop_base_addr = prop->eop_gpu_addr >> 8;
3123 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3124 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3125
3126 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3127 tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
3128 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3129 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1));
3130
3131 mqd->cp_hqd_eop_control = tmp;
3132
3133 /* enable doorbell? */
3134 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
3135
3136 if (prop->use_doorbell) {
3137 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3138 DOORBELL_OFFSET, prop->doorbell_index);
3139 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3140 DOORBELL_EN, 1);
3141 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3142 DOORBELL_SOURCE, 0);
3143 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3144 DOORBELL_HIT, 0);
3145 } else {
3146 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3147 DOORBELL_EN, 0);
3148 }
3149
3150 mqd->cp_hqd_pq_doorbell_control = tmp;
3151
3152 /* disable the queue if it's active */
3153 mqd->cp_hqd_dequeue_request = 0;
3154 mqd->cp_hqd_pq_rptr = 0;
3155 mqd->cp_hqd_pq_wptr_lo = 0;
3156 mqd->cp_hqd_pq_wptr_hi = 0;
3157
3158 /* set the pointer to the MQD */
3159 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
3160 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3161
3162 /* set MQD vmid to 0 */
3163 tmp = regCP_MQD_CONTROL_DEFAULT;
3164 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3165 mqd->cp_mqd_control = tmp;
3166
3167 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3168 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3169 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3170 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3171
3172 /* set up the HQD, this is similar to CP_RB0_CNTL */
3173 tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
3174 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3175 (order_base_2(prop->queue_size / 4) - 1));
3176 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3177 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3178 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
3179 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3180 if (prop->kernel_queue) {
3181 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3182 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3183 }
3184 if (prop->tmz_queue)
3185 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);
3186 mqd->cp_hqd_pq_control = tmp;
3187
3188 /* set the wb address whether it's enabled or not */
3189 wb_gpu_addr = prop->rptr_gpu_addr;
3190 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3191 mqd->cp_hqd_pq_rptr_report_addr_hi =
3192 upper_32_bits(wb_gpu_addr) & 0xffff;
3193
3194 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3195 wb_gpu_addr = prop->wptr_gpu_addr;
3196 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3197 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3198
3199 tmp = 0;
3200 /* enable the doorbell if requested */
3201 if (prop->use_doorbell) {
3202 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
3203 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3204 DOORBELL_OFFSET, prop->doorbell_index);
3205
3206 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3207 DOORBELL_EN, 1);
3208 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3209 DOORBELL_SOURCE, 0);
3210 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3211 DOORBELL_HIT, 0);
3212 }
3213
3214 mqd->cp_hqd_pq_doorbell_control = tmp;
3215
3216 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3217 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT;
3218
3219 /* set the vmid for the queue */
3220 mqd->cp_hqd_vmid = 0;
3221
3222 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
3223 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
3224 mqd->cp_hqd_persistent_state = tmp;
3225
3226 /* set MIN_IB_AVAIL_SIZE */
3227 tmp = regCP_HQD_IB_CONTROL_DEFAULT;
3228 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3229 mqd->cp_hqd_ib_control = tmp;
3230
3231 /* set static priority for a compute queue/ring */
3232 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
3233 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
3234
3235 mqd->cp_hqd_active = prop->hqd_active;
3236
3237 /* set UQ fenceaddress */
3238 mqd->fence_address_lo = lower_32_bits(prop->fence_address);
3239 mqd->fence_address_hi = upper_32_bits(prop->fence_address);
3240
3241 return 0;
3242 }
3243
gfx_v12_0_kiq_init_register(struct amdgpu_ring * ring)3244 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring)
3245 {
3246 struct amdgpu_device *adev = ring->adev;
3247 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3248 int j;
3249
3250 /* inactivate the queue */
3251 if (amdgpu_sriov_vf(adev))
3252 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
3253
3254 /* disable wptr polling */
3255 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3256
3257 /* write the EOP addr */
3258 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,
3259 mqd->cp_hqd_eop_base_addr_lo);
3260 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
3261 mqd->cp_hqd_eop_base_addr_hi);
3262
3263 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3264 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,
3265 mqd->cp_hqd_eop_control);
3266
3267 /* enable doorbell? */
3268 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3269 mqd->cp_hqd_pq_doorbell_control);
3270
3271 /* disable the queue if it's active */
3272 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
3273 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
3274 for (j = 0; j < adev->usec_timeout; j++) {
3275 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
3276 break;
3277 udelay(1);
3278 }
3279 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
3280 mqd->cp_hqd_dequeue_request);
3281 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,
3282 mqd->cp_hqd_pq_rptr);
3283 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3284 mqd->cp_hqd_pq_wptr_lo);
3285 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3286 mqd->cp_hqd_pq_wptr_hi);
3287 }
3288
3289 /* set the pointer to the MQD */
3290 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,
3291 mqd->cp_mqd_base_addr_lo);
3292 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,
3293 mqd->cp_mqd_base_addr_hi);
3294
3295 /* set MQD vmid to 0 */
3296 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,
3297 mqd->cp_mqd_control);
3298
3299 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3300 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,
3301 mqd->cp_hqd_pq_base_lo);
3302 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,
3303 mqd->cp_hqd_pq_base_hi);
3304
3305 /* set up the HQD, this is similar to CP_RB0_CNTL */
3306 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,
3307 mqd->cp_hqd_pq_control);
3308
3309 /* set the wb address whether it's enabled or not */
3310 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
3311 mqd->cp_hqd_pq_rptr_report_addr_lo);
3312 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3313 mqd->cp_hqd_pq_rptr_report_addr_hi);
3314
3315 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3316 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
3317 mqd->cp_hqd_pq_wptr_poll_addr_lo);
3318 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3319 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3320
3321 /* enable the doorbell if requested */
3322 if (ring->use_doorbell) {
3323 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3324 (adev->doorbell_index.kiq * 2) << 2);
3325 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3326 (adev->doorbell_index.userqueue_end * 2) << 2);
3327 }
3328
3329 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3330 mqd->cp_hqd_pq_doorbell_control);
3331
3332 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3333 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3334 mqd->cp_hqd_pq_wptr_lo);
3335 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3336 mqd->cp_hqd_pq_wptr_hi);
3337
3338 /* set the vmid for the queue */
3339 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
3340
3341 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,
3342 mqd->cp_hqd_persistent_state);
3343
3344 /* activate the queue */
3345 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,
3346 mqd->cp_hqd_active);
3347
3348 if (ring->use_doorbell)
3349 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3350
3351 return 0;
3352 }
3353
gfx_v12_0_kiq_init_queue(struct amdgpu_ring * ring)3354 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring)
3355 {
3356 struct amdgpu_device *adev = ring->adev;
3357 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3358 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3359
3360 gfx_v12_0_kiq_setting(ring);
3361
3362 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
3363 /* reset MQD to a clean status */
3364 if (adev->gfx.mec.mqd_backup[mqd_idx])
3365 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3366
3367 /* reset ring buffer */
3368 ring->wptr = 0;
3369 amdgpu_ring_clear_ring(ring);
3370
3371 mutex_lock(&adev->srbm_mutex);
3372 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3373 gfx_v12_0_kiq_init_register(ring);
3374 soc24_grbm_select(adev, 0, 0, 0, 0);
3375 mutex_unlock(&adev->srbm_mutex);
3376 } else {
3377 memset((void *)mqd, 0, sizeof(*mqd));
3378 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
3379 amdgpu_ring_clear_ring(ring);
3380 mutex_lock(&adev->srbm_mutex);
3381 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3382 amdgpu_ring_init_mqd(ring);
3383 gfx_v12_0_kiq_init_register(ring);
3384 soc24_grbm_select(adev, 0, 0, 0, 0);
3385 mutex_unlock(&adev->srbm_mutex);
3386
3387 if (adev->gfx.mec.mqd_backup[mqd_idx])
3388 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3389 }
3390
3391 return 0;
3392 }
3393
gfx_v12_0_kcq_init_queue(struct amdgpu_ring * ring,bool reset)3394 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset)
3395 {
3396 struct amdgpu_device *adev = ring->adev;
3397 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3398 int mqd_idx = ring - &adev->gfx.compute_ring[0];
3399
3400 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
3401 memset((void *)mqd, 0, sizeof(*mqd));
3402 mutex_lock(&adev->srbm_mutex);
3403 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3404 amdgpu_ring_init_mqd(ring);
3405 soc24_grbm_select(adev, 0, 0, 0, 0);
3406 mutex_unlock(&adev->srbm_mutex);
3407
3408 if (adev->gfx.mec.mqd_backup[mqd_idx])
3409 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3410 } else {
3411 /* restore MQD to a clean status */
3412 if (adev->gfx.mec.mqd_backup[mqd_idx])
3413 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3414 /* reset ring buffer */
3415 ring->wptr = 0;
3416 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
3417 amdgpu_ring_clear_ring(ring);
3418 }
3419
3420 return 0;
3421 }
3422
gfx_v12_0_kiq_resume(struct amdgpu_device * adev)3423 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev)
3424 {
3425 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
3426 adev->gfx.kiq[0].ring.sched.ready = true;
3427 return 0;
3428 }
3429
gfx_v12_0_kcq_resume(struct amdgpu_device * adev)3430 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev)
3431 {
3432 int i, r;
3433
3434 if (!amdgpu_async_gfx_ring)
3435 gfx_v12_0_cp_compute_enable(adev, true);
3436
3437 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3438 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false);
3439 if (r)
3440 return r;
3441 }
3442
3443 return amdgpu_gfx_enable_kcq(adev, 0);
3444 }
3445
gfx_v12_0_cp_resume(struct amdgpu_device * adev)3446 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev)
3447 {
3448 int r, i;
3449 struct amdgpu_ring *ring;
3450
3451 if (!(adev->flags & AMD_IS_APU))
3452 gfx_v12_0_enable_gui_idle_interrupt(adev, false);
3453
3454 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3455 /* legacy firmware loading */
3456 r = gfx_v12_0_cp_gfx_load_microcode(adev);
3457 if (r)
3458 return r;
3459
3460 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev);
3461 if (r)
3462 return r;
3463 }
3464
3465 gfx_v12_0_cp_set_doorbell_range(adev);
3466
3467 if (amdgpu_async_gfx_ring) {
3468 gfx_v12_0_cp_compute_enable(adev, true);
3469 gfx_v12_0_cp_gfx_enable(adev, true);
3470 }
3471
3472 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
3473 r = amdgpu_mes_kiq_hw_init(adev);
3474 else
3475 r = gfx_v12_0_kiq_resume(adev);
3476 if (r)
3477 return r;
3478
3479 r = gfx_v12_0_kcq_resume(adev);
3480 if (r)
3481 return r;
3482
3483 if (!amdgpu_async_gfx_ring) {
3484 r = gfx_v12_0_cp_gfx_resume(adev);
3485 if (r)
3486 return r;
3487 } else {
3488 r = gfx_v12_0_cp_async_gfx_ring_resume(adev);
3489 if (r)
3490 return r;
3491 }
3492
3493 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3494 ring = &adev->gfx.gfx_ring[i];
3495 r = amdgpu_ring_test_helper(ring);
3496 if (r)
3497 return r;
3498 }
3499
3500 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3501 ring = &adev->gfx.compute_ring[i];
3502 r = amdgpu_ring_test_helper(ring);
3503 if (r)
3504 return r;
3505 }
3506
3507 return 0;
3508 }
3509
gfx_v12_0_cp_enable(struct amdgpu_device * adev,bool enable)3510 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable)
3511 {
3512 gfx_v12_0_cp_gfx_enable(adev, enable);
3513 gfx_v12_0_cp_compute_enable(adev, enable);
3514 }
3515
gfx_v12_0_gfxhub_enable(struct amdgpu_device * adev)3516 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev)
3517 {
3518 int r;
3519 bool value;
3520
3521 r = adev->gfxhub.funcs->gart_enable(adev);
3522 if (r)
3523 return r;
3524
3525 amdgpu_device_flush_hdp(adev, NULL);
3526
3527 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS;
3528
3529 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
3530 /* TODO investigate why this and the hdp flush above is needed,
3531 * are we missing a flush somewhere else? */
3532 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
3533
3534 return 0;
3535 }
3536
get_gb_addr_config(struct amdgpu_device * adev)3537 static int get_gb_addr_config(struct amdgpu_device *adev)
3538 {
3539 u32 gb_addr_config;
3540
3541 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
3542 if (gb_addr_config == 0)
3543 return -EINVAL;
3544
3545 adev->gfx.config.gb_addr_config_fields.num_pkrs =
3546 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
3547
3548 adev->gfx.config.gb_addr_config = gb_addr_config;
3549
3550 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
3551 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3552 GB_ADDR_CONFIG, NUM_PIPES);
3553
3554 adev->gfx.config.max_tile_pipes =
3555 adev->gfx.config.gb_addr_config_fields.num_pipes;
3556
3557 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
3558 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3559 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
3560 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
3561 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3562 GB_ADDR_CONFIG, NUM_RB_PER_SE);
3563 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
3564 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3565 GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
3566 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
3567 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3568 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
3569
3570 return 0;
3571 }
3572
gfx_v12_0_disable_gpa_mode(struct amdgpu_device * adev)3573 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev)
3574 {
3575 uint32_t data;
3576
3577 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
3578 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
3579 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
3580
3581 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);
3582 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
3583 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
3584 }
3585
gfx_v12_0_init_golden_registers(struct amdgpu_device * adev)3586 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev)
3587 {
3588 if (amdgpu_sriov_vf(adev))
3589 return;
3590
3591 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3592 case IP_VERSION(12, 0, 0):
3593 case IP_VERSION(12, 0, 1):
3594 soc15_program_register_sequence(adev,
3595 golden_settings_gc_12_0,
3596 (const u32)ARRAY_SIZE(golden_settings_gc_12_0));
3597
3598 if (adev->rev_id == 0)
3599 soc15_program_register_sequence(adev,
3600 golden_settings_gc_12_0_rev0,
3601 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0));
3602 break;
3603 default:
3604 break;
3605 }
3606 }
3607
gfx_v12_0_hw_init(struct amdgpu_ip_block * ip_block)3608 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
3609 {
3610 int r;
3611 struct amdgpu_device *adev = ip_block->adev;
3612
3613 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
3614 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
3615 /* RLC autoload sequence 1: Program rlc ram */
3616 if (adev->gfx.imu.funcs->program_rlc_ram)
3617 adev->gfx.imu.funcs->program_rlc_ram(adev);
3618 }
3619 /* rlc autoload firmware */
3620 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev);
3621 if (r)
3622 return r;
3623 } else {
3624 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3625 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
3626 if (adev->gfx.imu.funcs->load_microcode)
3627 adev->gfx.imu.funcs->load_microcode(adev);
3628 if (adev->gfx.imu.funcs->setup_imu)
3629 adev->gfx.imu.funcs->setup_imu(adev);
3630 if (adev->gfx.imu.funcs->start_imu)
3631 adev->gfx.imu.funcs->start_imu(adev);
3632 }
3633
3634 /* disable gpa mode in backdoor loading */
3635 gfx_v12_0_disable_gpa_mode(adev);
3636 }
3637 }
3638
3639 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) ||
3640 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3641 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev);
3642 if (r) {
3643 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r);
3644 return r;
3645 }
3646 }
3647
3648 if (!amdgpu_emu_mode)
3649 gfx_v12_0_init_golden_registers(adev);
3650
3651 adev->gfx.is_poweron = true;
3652
3653 if (get_gb_addr_config(adev))
3654 DRM_WARN("Invalid gb_addr_config !\n");
3655
3656 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
3657 gfx_v12_0_config_gfx_rs64(adev);
3658
3659 r = gfx_v12_0_gfxhub_enable(adev);
3660 if (r)
3661 return r;
3662
3663 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT ||
3664 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) &&
3665 (amdgpu_dpm == 1)) {
3666 /**
3667 * For gfx 12, rlc firmware loading relies on smu firmware is
3668 * loaded firstly, so in direct type, it has to load smc ucode
3669 * here before rlc.
3670 */
3671 r = amdgpu_pm_load_smu_firmware(adev, NULL);
3672 if (r)
3673 return r;
3674 }
3675
3676 gfx_v12_0_constants_init(adev);
3677
3678 if (adev->nbio.funcs->gc_doorbell_init)
3679 adev->nbio.funcs->gc_doorbell_init(adev);
3680
3681 r = gfx_v12_0_rlc_resume(adev);
3682 if (r)
3683 return r;
3684
3685 /*
3686 * init golden registers and rlc resume may override some registers,
3687 * reconfig them here
3688 */
3689 gfx_v12_0_tcp_harvest(adev);
3690
3691 r = gfx_v12_0_cp_resume(adev);
3692 if (r)
3693 return r;
3694
3695 return r;
3696 }
3697
gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device * adev,bool enable)3698 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,
3699 bool enable)
3700 {
3701 unsigned int irq_type;
3702 int m, p, r;
3703
3704 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) {
3705 for (m = 0; m < adev->gfx.me.num_me; m++) {
3706 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) {
3707 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
3708 if (enable)
3709 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,
3710 irq_type);
3711 else
3712 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,
3713 irq_type);
3714 if (r)
3715 return r;
3716 }
3717 }
3718 }
3719
3720 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) {
3721 for (m = 0; m < adev->gfx.mec.num_mec; ++m) {
3722 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) {
3723 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
3724 + (m * adev->gfx.mec.num_pipe_per_mec)
3725 + p;
3726 if (enable)
3727 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq,
3728 irq_type);
3729 else
3730 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq,
3731 irq_type);
3732 if (r)
3733 return r;
3734 }
3735 }
3736 }
3737
3738 return 0;
3739 }
3740
gfx_v12_0_hw_fini(struct amdgpu_ip_block * ip_block)3741 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
3742 {
3743 struct amdgpu_device *adev = ip_block->adev;
3744 uint32_t tmp;
3745
3746 cancel_delayed_work_sync(&adev->gfx.idle_work);
3747
3748 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3749 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3750 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
3751 gfx_v12_0_set_userq_eop_interrupts(adev, false);
3752
3753 if (!adev->no_hw_access) {
3754 if (amdgpu_async_gfx_ring) {
3755 if (amdgpu_gfx_disable_kgq(adev, 0))
3756 DRM_ERROR("KGQ disable failed\n");
3757 }
3758
3759 if (amdgpu_gfx_disable_kcq(adev, 0))
3760 DRM_ERROR("KCQ disable failed\n");
3761
3762 amdgpu_mes_kiq_hw_fini(adev);
3763 }
3764
3765 if (amdgpu_sriov_vf(adev)) {
3766 gfx_v12_0_cp_gfx_enable(adev, false);
3767 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
3768 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
3769 tmp &= 0xffffff00;
3770 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3771
3772 return 0;
3773 }
3774 gfx_v12_0_cp_enable(adev, false);
3775 gfx_v12_0_enable_gui_idle_interrupt(adev, false);
3776
3777 adev->gfxhub.funcs->gart_disable(adev);
3778
3779 adev->gfx.is_poweron = false;
3780
3781 return 0;
3782 }
3783
gfx_v12_0_suspend(struct amdgpu_ip_block * ip_block)3784 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block)
3785 {
3786 return gfx_v12_0_hw_fini(ip_block);
3787 }
3788
gfx_v12_0_resume(struct amdgpu_ip_block * ip_block)3789 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block)
3790 {
3791 return gfx_v12_0_hw_init(ip_block);
3792 }
3793
gfx_v12_0_is_idle(struct amdgpu_ip_block * ip_block)3794 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
3795 {
3796 struct amdgpu_device *adev = ip_block->adev;
3797
3798 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
3799 GRBM_STATUS, GUI_ACTIVE))
3800 return false;
3801 else
3802 return true;
3803 }
3804
gfx_v12_0_wait_for_idle(struct amdgpu_ip_block * ip_block)3805 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
3806 {
3807 unsigned i;
3808 u32 tmp;
3809 struct amdgpu_device *adev = ip_block->adev;
3810
3811 for (i = 0; i < adev->usec_timeout; i++) {
3812 /* read MC_STATUS */
3813 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
3814 GRBM_STATUS__GUI_ACTIVE_MASK;
3815
3816 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3817 return 0;
3818 udelay(1);
3819 }
3820 return -ETIMEDOUT;
3821 }
3822
gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device * adev)3823 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3824 {
3825 uint64_t clock = 0;
3826
3827 if (adev->smuio.funcs &&
3828 adev->smuio.funcs->get_gpu_clock_counter)
3829 clock = adev->smuio.funcs->get_gpu_clock_counter(adev);
3830 else
3831 dev_warn(adev->dev, "query gpu clock counter is not supported\n");
3832
3833 return clock;
3834 }
3835
gfx_v12_0_early_init(struct amdgpu_ip_block * ip_block)3836 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block)
3837 {
3838 struct amdgpu_device *adev = ip_block->adev;
3839
3840 switch (amdgpu_user_queue) {
3841 case -1:
3842 case 0:
3843 default:
3844 adev->gfx.disable_kq = false;
3845 adev->gfx.disable_uq = true;
3846 break;
3847 case 1:
3848 adev->gfx.disable_kq = false;
3849 adev->gfx.disable_uq = false;
3850 break;
3851 case 2:
3852 adev->gfx.disable_kq = true;
3853 adev->gfx.disable_uq = false;
3854 break;
3855 }
3856
3857 adev->gfx.funcs = &gfx_v12_0_gfx_funcs;
3858
3859 if (adev->gfx.disable_kq) {
3860 adev->gfx.num_gfx_rings = 0;
3861 adev->gfx.num_compute_rings = 0;
3862 } else {
3863 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS;
3864 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
3865 AMDGPU_MAX_COMPUTE_RINGS);
3866 }
3867
3868 gfx_v12_0_set_kiq_pm4_funcs(adev);
3869 gfx_v12_0_set_ring_funcs(adev);
3870 gfx_v12_0_set_irq_funcs(adev);
3871 gfx_v12_0_set_rlc_funcs(adev);
3872 gfx_v12_0_set_mqd_funcs(adev);
3873 gfx_v12_0_set_imu_funcs(adev);
3874
3875 gfx_v12_0_init_rlcg_reg_access_ctrl(adev);
3876
3877 return gfx_v12_0_init_microcode(adev);
3878 }
3879
gfx_v12_0_late_init(struct amdgpu_ip_block * ip_block)3880 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block)
3881 {
3882 struct amdgpu_device *adev = ip_block->adev;
3883 int r;
3884
3885 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3886 if (r)
3887 return r;
3888
3889 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3890 if (r)
3891 return r;
3892
3893 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
3894 if (r)
3895 return r;
3896
3897 r = gfx_v12_0_set_userq_eop_interrupts(adev, true);
3898 if (r)
3899 return r;
3900
3901 return 0;
3902 }
3903
gfx_v12_0_is_rlc_enabled(struct amdgpu_device * adev)3904 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev)
3905 {
3906 uint32_t rlc_cntl;
3907
3908 /* if RLC is not enabled, do nothing */
3909 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);
3910 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
3911 }
3912
gfx_v12_0_set_safe_mode(struct amdgpu_device * adev,int xcc_id)3913 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev,
3914 int xcc_id)
3915 {
3916 uint32_t data;
3917 unsigned i;
3918
3919 data = RLC_SAFE_MODE__CMD_MASK;
3920 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3921
3922 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
3923
3924 /* wait for RLC_SAFE_MODE */
3925 for (i = 0; i < adev->usec_timeout; i++) {
3926 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
3927 RLC_SAFE_MODE, CMD))
3928 break;
3929 udelay(1);
3930 }
3931 }
3932
gfx_v12_0_unset_safe_mode(struct amdgpu_device * adev,int xcc_id)3933 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev,
3934 int xcc_id)
3935 {
3936 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
3937 }
3938
gfx_v12_0_update_perf_clk(struct amdgpu_device * adev,bool enable)3939 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
3940 bool enable)
3941 {
3942 uint32_t def, data;
3943
3944 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
3945 return;
3946
3947 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
3948
3949 if (enable)
3950 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
3951 else
3952 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
3953
3954 if (def != data)
3955 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
3956 }
3957
gfx_v12_0_update_spm_vmid(struct amdgpu_device * adev,struct amdgpu_ring * ring,unsigned vmid)3958 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev,
3959 struct amdgpu_ring *ring,
3960 unsigned vmid)
3961 {
3962 u32 reg, data;
3963
3964 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
3965 if (amdgpu_sriov_is_pp_one_vf(adev))
3966 data = RREG32_NO_KIQ(reg);
3967 else
3968 data = RREG32(reg);
3969
3970 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
3971 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
3972
3973 if (amdgpu_sriov_is_pp_one_vf(adev))
3974 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
3975 else
3976 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
3977
3978 if (ring
3979 && amdgpu_sriov_is_pp_one_vf(adev)
3980 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX)
3981 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
3982 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
3983 amdgpu_ring_emit_wreg(ring, reg, data);
3984 }
3985 }
3986
3987 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = {
3988 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled,
3989 .set_safe_mode = gfx_v12_0_set_safe_mode,
3990 .unset_safe_mode = gfx_v12_0_unset_safe_mode,
3991 .init = gfx_v12_0_rlc_init,
3992 .get_csb_size = gfx_v12_0_get_csb_size,
3993 .get_csb_buffer = gfx_v12_0_get_csb_buffer,
3994 .resume = gfx_v12_0_rlc_resume,
3995 .stop = gfx_v12_0_rlc_stop,
3996 .reset = gfx_v12_0_rlc_reset,
3997 .start = gfx_v12_0_rlc_start,
3998 .update_spm_vmid = gfx_v12_0_update_spm_vmid,
3999 };
4000
4001 #if 0
4002 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable)
4003 {
4004 /* TODO */
4005 }
4006
4007 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable)
4008 {
4009 /* TODO */
4010 }
4011 #endif
4012
gfx_v12_0_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)4013 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
4014 enum amd_powergating_state state)
4015 {
4016 struct amdgpu_device *adev = ip_block->adev;
4017 bool enable = (state == AMD_PG_STATE_GATE);
4018
4019 if (amdgpu_sriov_vf(adev))
4020 return 0;
4021
4022 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4023 case IP_VERSION(12, 0, 0):
4024 case IP_VERSION(12, 0, 1):
4025 amdgpu_gfx_off_ctrl(adev, enable);
4026 break;
4027 default:
4028 break;
4029 }
4030
4031 return 0;
4032 }
4033
gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)4034 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4035 bool enable)
4036 {
4037 uint32_t def, data;
4038
4039 if (!(adev->cg_flags &
4040 (AMD_CG_SUPPORT_GFX_CGCG |
4041 AMD_CG_SUPPORT_GFX_CGLS |
4042 AMD_CG_SUPPORT_GFX_3D_CGCG |
4043 AMD_CG_SUPPORT_GFX_3D_CGLS)))
4044 return;
4045
4046 if (enable) {
4047 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4048
4049 /* unset CGCG override */
4050 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4051 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4052 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4053 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4054 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG ||
4055 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4056 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4057
4058 /* update CGCG override bits */
4059 if (def != data)
4060 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4061
4062 /* enable cgcg FSM(0x0000363F) */
4063 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4064
4065 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
4066 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK;
4067 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4068 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4069 }
4070
4071 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
4072 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK;
4073 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4074 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4075 }
4076
4077 if (def != data)
4078 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4079
4080 /* Program RLC_CGCG_CGLS_CTRL_3D */
4081 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4082
4083 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
4084 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK;
4085 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4086 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4087 }
4088
4089 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
4090 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK;
4091 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4092 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4093 }
4094
4095 if (def != data)
4096 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4097
4098 /* set IDLE_POLL_COUNT(0x00900100) */
4099 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
4100
4101 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK);
4102 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4103 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4104
4105 if (def != data)
4106 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
4107
4108 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4109 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4110 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4111 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4112 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4113 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);
4114
4115 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4116 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4117 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4118
4119 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4120 if (adev->sdma.num_instances > 1) {
4121 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4122 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4123 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4124 }
4125 } else {
4126 /* Program RLC_CGCG_CGLS_CTRL */
4127 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4128
4129 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4130 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4131
4132 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4133 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4134
4135 if (def != data)
4136 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4137
4138 /* Program RLC_CGCG_CGLS_CTRL_3D */
4139 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4140
4141 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
4142 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4143 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4144 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4145
4146 if (def != data)
4147 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4148 }
4149 }
4150
gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)4151 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4152 bool enable)
4153 {
4154 uint32_t data, def;
4155 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
4156 return;
4157
4158 /* It is disabled by HW by default */
4159 if (enable) {
4160 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4161 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4162 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4163
4164 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4165 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4166 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4167
4168 if (def != data)
4169 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4170 }
4171 } else {
4172 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4173 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4174
4175 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4176 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4177 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4178
4179 if (def != data)
4180 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4181 }
4182 }
4183 }
4184
gfx_v12_0_update_repeater_fgcg(struct amdgpu_device * adev,bool enable)4185 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev,
4186 bool enable)
4187 {
4188 uint32_t def, data;
4189
4190 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
4191 return;
4192
4193 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4194
4195 if (enable)
4196 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |
4197 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK);
4198 else
4199 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |
4200 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK;
4201
4202 if (def != data)
4203 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4204 }
4205
gfx_v12_0_update_sram_fgcg(struct amdgpu_device * adev,bool enable)4206 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev,
4207 bool enable)
4208 {
4209 uint32_t def, data;
4210
4211 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
4212 return;
4213
4214 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4215
4216 if (enable)
4217 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4218 else
4219 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4220
4221 if (def != data)
4222 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4223 }
4224
gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)4225 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4226 bool enable)
4227 {
4228 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4229
4230 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable);
4231
4232 gfx_v12_0_update_medium_grain_clock_gating(adev, enable);
4233
4234 gfx_v12_0_update_repeater_fgcg(adev, enable);
4235
4236 gfx_v12_0_update_sram_fgcg(adev, enable);
4237
4238 gfx_v12_0_update_perf_clk(adev, enable);
4239
4240 if (adev->cg_flags &
4241 (AMD_CG_SUPPORT_GFX_MGCG |
4242 AMD_CG_SUPPORT_GFX_CGLS |
4243 AMD_CG_SUPPORT_GFX_CGCG |
4244 AMD_CG_SUPPORT_GFX_3D_CGCG |
4245 AMD_CG_SUPPORT_GFX_3D_CGLS))
4246 gfx_v12_0_enable_gui_idle_interrupt(adev, enable);
4247
4248 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4249
4250 return 0;
4251 }
4252
gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)4253 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
4254 enum amd_clockgating_state state)
4255 {
4256 struct amdgpu_device *adev = ip_block->adev;
4257
4258 if (amdgpu_sriov_vf(adev))
4259 return 0;
4260
4261 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4262 case IP_VERSION(12, 0, 0):
4263 case IP_VERSION(12, 0, 1):
4264 gfx_v12_0_update_gfx_clock_gating(adev,
4265 state == AMD_CG_STATE_GATE);
4266 break;
4267 default:
4268 break;
4269 }
4270
4271 return 0;
4272 }
4273
gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)4274 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
4275 {
4276 struct amdgpu_device *adev = ip_block->adev;
4277 int data;
4278
4279 /* AMD_CG_SUPPORT_GFX_MGCG */
4280 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4281 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4282 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
4283
4284 /* AMD_CG_SUPPORT_REPEATER_FGCG */
4285 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))
4286 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG;
4287
4288 /* AMD_CG_SUPPORT_GFX_FGCG */
4289 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
4290 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
4291
4292 /* AMD_CG_SUPPORT_GFX_PERF_CLK */
4293 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))
4294 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;
4295
4296 /* AMD_CG_SUPPORT_GFX_CGCG */
4297 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4298 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4299 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
4300
4301 /* AMD_CG_SUPPORT_GFX_CGLS */
4302 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4303 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
4304
4305 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
4306 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4307 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4308 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4309
4310 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
4311 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4312 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4313 }
4314
gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring * ring)4315 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4316 {
4317 /* gfx12 is 32bit rptr*/
4318 return *(uint32_t *)ring->rptr_cpu_addr;
4319 }
4320
gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)4321 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4322 {
4323 struct amdgpu_device *adev = ring->adev;
4324 u64 wptr;
4325
4326 /* XXX check if swapping is necessary on BE */
4327 if (ring->use_doorbell) {
4328 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
4329 } else {
4330 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);
4331 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;
4332 }
4333
4334 return wptr;
4335 }
4336
gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)4337 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4338 {
4339 struct amdgpu_device *adev = ring->adev;
4340
4341 if (ring->use_doorbell) {
4342 /* XXX check if swapping is necessary on BE */
4343 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
4344 ring->wptr);
4345 WDOORBELL64(ring->doorbell_index, ring->wptr);
4346 } else {
4347 WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
4348 lower_32_bits(ring->wptr));
4349 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
4350 upper_32_bits(ring->wptr));
4351 }
4352 }
4353
gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring * ring)4354 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4355 {
4356 /* gfx12 hardware is 32bit rptr */
4357 return *(uint32_t *)ring->rptr_cpu_addr;
4358 }
4359
gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring * ring)4360 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4361 {
4362 u64 wptr;
4363
4364 /* XXX check if swapping is necessary on BE */
4365 if (ring->use_doorbell)
4366 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
4367 else
4368 BUG();
4369 return wptr;
4370 }
4371
gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring * ring)4372 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4373 {
4374 struct amdgpu_device *adev = ring->adev;
4375
4376 /* XXX check if swapping is necessary on BE */
4377 if (ring->use_doorbell) {
4378 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
4379 ring->wptr);
4380 WDOORBELL64(ring->doorbell_index, ring->wptr);
4381 } else {
4382 BUG(); /* only DOORBELL method supported on gfx12 now */
4383 }
4384 }
4385
gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)4386 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4387 {
4388 struct amdgpu_device *adev = ring->adev;
4389 u32 ref_and_mask, reg_mem_engine;
4390 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
4391
4392 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4393 switch (ring->me) {
4394 case 1:
4395 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4396 break;
4397 case 2:
4398 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4399 break;
4400 default:
4401 return;
4402 }
4403 reg_mem_engine = 0;
4404 } else {
4405 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4406 reg_mem_engine = 1; /* pfp */
4407 }
4408
4409 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4410 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4411 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
4412 ref_and_mask, ref_and_mask, 0x20);
4413 }
4414
gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)4415 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4416 struct amdgpu_job *job,
4417 struct amdgpu_ib *ib,
4418 uint32_t flags)
4419 {
4420 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4421 u32 header, control = 0;
4422
4423 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4424
4425 control |= ib->length_dw | (vmid << 24);
4426
4427 amdgpu_ring_write(ring, header);
4428 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4429 amdgpu_ring_write(ring,
4430 #ifdef __BIG_ENDIAN
4431 (2 << 0) |
4432 #endif
4433 lower_32_bits(ib->gpu_addr));
4434 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4435 amdgpu_ring_write(ring, control);
4436 }
4437
gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)4438 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4439 struct amdgpu_job *job,
4440 struct amdgpu_ib *ib,
4441 uint32_t flags)
4442 {
4443 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4444 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4445
4446 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4447 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4448 amdgpu_ring_write(ring,
4449 #ifdef __BIG_ENDIAN
4450 (2 << 0) |
4451 #endif
4452 lower_32_bits(ib->gpu_addr));
4453 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4454 amdgpu_ring_write(ring, control);
4455 }
4456
gfx_v12_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)4457 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4458 u64 seq, unsigned flags)
4459 {
4460 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4461 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4462
4463 /* RELEASE_MEM - flush caches, send int */
4464 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4465 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4466 PACKET3_RELEASE_MEM_GCR_GL2_WB |
4467 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4468 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4469 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
4470 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
4471 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
4472
4473 /*
4474 * the address should be Qword aligned if 64bit write, Dword
4475 * aligned if only send 32bit data low (discard data high)
4476 */
4477 if (write64bit)
4478 BUG_ON(addr & 0x7);
4479 else
4480 BUG_ON(addr & 0x3);
4481 amdgpu_ring_write(ring, lower_32_bits(addr));
4482 amdgpu_ring_write(ring, upper_32_bits(addr));
4483 amdgpu_ring_write(ring, lower_32_bits(seq));
4484 amdgpu_ring_write(ring, upper_32_bits(seq));
4485 amdgpu_ring_write(ring, 0);
4486 }
4487
gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)4488 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4489 {
4490 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4491 uint32_t seq = ring->fence_drv.sync_seq;
4492 uint64_t addr = ring->fence_drv.gpu_addr;
4493
4494 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
4495 upper_32_bits(addr), seq, 0xffffffff, 4);
4496 }
4497
gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring * ring,uint16_t pasid,uint32_t flush_type,bool all_hub,uint8_t dst_sel)4498 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
4499 uint16_t pasid, uint32_t flush_type,
4500 bool all_hub, uint8_t dst_sel)
4501 {
4502 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
4503 amdgpu_ring_write(ring,
4504 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
4505 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
4506 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
4507 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
4508 }
4509
gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)4510 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4511 unsigned vmid, uint64_t pd_addr)
4512 {
4513 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4514
4515 /* compute doesn't have PFP */
4516 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4517 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4518 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4519 amdgpu_ring_write(ring, 0x0);
4520 }
4521 }
4522
gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)4523 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4524 u64 seq, unsigned int flags)
4525 {
4526 struct amdgpu_device *adev = ring->adev;
4527
4528 /* we only allocate 32bit for each seq wb address */
4529 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4530
4531 /* write fence seq to the "addr" */
4532 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4533 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4534 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4535 amdgpu_ring_write(ring, lower_32_bits(addr));
4536 amdgpu_ring_write(ring, upper_32_bits(addr));
4537 amdgpu_ring_write(ring, lower_32_bits(seq));
4538
4539 if (flags & AMDGPU_FENCE_FLAG_INT) {
4540 /* set register to trigger INT */
4541 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4542 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4543 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4544 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
4545 amdgpu_ring_write(ring, 0);
4546 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4547 }
4548 }
4549
gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)4550 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
4551 uint32_t flags)
4552 {
4553 uint32_t dw2 = 0;
4554
4555 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4556 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4557 /* set load_global_config & load_global_uconfig */
4558 dw2 |= 0x8001;
4559 /* set load_cs_sh_regs */
4560 dw2 |= 0x01000000;
4561 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4562 dw2 |= 0x10002;
4563 }
4564
4565 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4566 amdgpu_ring_write(ring, dw2);
4567 amdgpu_ring_write(ring, 0);
4568 }
4569
gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)4570 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
4571 uint64_t addr)
4572 {
4573 unsigned ret;
4574
4575 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4576 amdgpu_ring_write(ring, lower_32_bits(addr));
4577 amdgpu_ring_write(ring, upper_32_bits(addr));
4578 /* discard following DWs if *cond_exec_gpu_addr==0 */
4579 amdgpu_ring_write(ring, 0);
4580 ret = ring->wptr & ring->buf_mask;
4581 /* patch dummy value later */
4582 amdgpu_ring_write(ring, 0);
4583
4584 return ret;
4585 }
4586
gfx_v12_0_ring_preempt_ib(struct amdgpu_ring * ring)4587 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring)
4588 {
4589 int i, r = 0;
4590 struct amdgpu_device *adev = ring->adev;
4591 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
4592 struct amdgpu_ring *kiq_ring = &kiq->ring;
4593 unsigned long flags;
4594
4595 if (adev->enable_mes)
4596 return -EINVAL;
4597
4598 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4599 return -EINVAL;
4600
4601 spin_lock_irqsave(&kiq->ring_lock, flags);
4602
4603 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
4604 spin_unlock_irqrestore(&kiq->ring_lock, flags);
4605 return -ENOMEM;
4606 }
4607
4608 /* assert preemption condition */
4609 amdgpu_ring_set_preempt_cond_exec(ring, false);
4610
4611 /* assert IB preemption, emit the trailing fence */
4612 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
4613 ring->trail_fence_gpu_addr,
4614 ++ring->trail_seq);
4615 amdgpu_ring_commit(kiq_ring);
4616
4617 spin_unlock_irqrestore(&kiq->ring_lock, flags);
4618
4619 /* poll the trailing fence */
4620 for (i = 0; i < adev->usec_timeout; i++) {
4621 if (ring->trail_seq ==
4622 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
4623 break;
4624 udelay(1);
4625 }
4626
4627 if (i >= adev->usec_timeout) {
4628 r = -EINVAL;
4629 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
4630 }
4631
4632 /* deassert preemption condition */
4633 amdgpu_ring_set_preempt_cond_exec(ring, true);
4634 return r;
4635 }
4636
gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring * ring,bool start,bool secure)4637 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring,
4638 bool start,
4639 bool secure)
4640 {
4641 uint32_t v = secure ? FRAME_TMZ : 0;
4642
4643 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4644 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
4645 }
4646
gfx_v12_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t reg_val_offs)4647 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
4648 uint32_t reg_val_offs)
4649 {
4650 struct amdgpu_device *adev = ring->adev;
4651
4652 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4653 amdgpu_ring_write(ring, 0 | /* src: register*/
4654 (5 << 8) | /* dst: memory */
4655 (1 << 20)); /* write confirm */
4656 amdgpu_ring_write(ring, reg);
4657 amdgpu_ring_write(ring, 0);
4658 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4659 reg_val_offs * 4));
4660 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4661 reg_val_offs * 4));
4662 }
4663
gfx_v12_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)4664 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring,
4665 uint32_t reg,
4666 uint32_t val)
4667 {
4668 uint32_t cmd = 0;
4669
4670 switch (ring->funcs->type) {
4671 case AMDGPU_RING_TYPE_GFX:
4672 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4673 break;
4674 case AMDGPU_RING_TYPE_KIQ:
4675 cmd = (1 << 16); /* no inc addr */
4676 break;
4677 default:
4678 cmd = WR_CONFIRM;
4679 break;
4680 }
4681 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4682 amdgpu_ring_write(ring, cmd);
4683 amdgpu_ring_write(ring, reg);
4684 amdgpu_ring_write(ring, 0);
4685 amdgpu_ring_write(ring, val);
4686 }
4687
gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)4688 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4689 uint32_t val, uint32_t mask)
4690 {
4691 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4692 }
4693
gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)4694 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4695 uint32_t reg0, uint32_t reg1,
4696 uint32_t ref, uint32_t mask)
4697 {
4698 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4699
4700 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4701 ref, mask, 0x20);
4702 }
4703
4704 static void
gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,uint32_t me,uint32_t pipe,enum amdgpu_interrupt_state state)4705 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4706 uint32_t me, uint32_t pipe,
4707 enum amdgpu_interrupt_state state)
4708 {
4709 uint32_t cp_int_cntl, cp_int_cntl_reg;
4710
4711 if (!me) {
4712 switch (pipe) {
4713 case 0:
4714 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
4715 break;
4716 default:
4717 DRM_DEBUG("invalid pipe %d\n", pipe);
4718 return;
4719 }
4720 } else {
4721 DRM_DEBUG("invalid me %d\n", me);
4722 return;
4723 }
4724
4725 switch (state) {
4726 case AMDGPU_IRQ_STATE_DISABLE:
4727 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4728 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4729 TIME_STAMP_INT_ENABLE, 0);
4730 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4731 GENERIC0_INT_ENABLE, 0);
4732 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4733 break;
4734 case AMDGPU_IRQ_STATE_ENABLE:
4735 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4736 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4737 TIME_STAMP_INT_ENABLE, 1);
4738 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4739 GENERIC0_INT_ENABLE, 1);
4740 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4741 break;
4742 default:
4743 break;
4744 }
4745 }
4746
gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)4747 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4748 int me, int pipe,
4749 enum amdgpu_interrupt_state state)
4750 {
4751 u32 mec_int_cntl, mec_int_cntl_reg;
4752
4753 /*
4754 * amdgpu controls only the first MEC. That's why this function only
4755 * handles the setting of interrupts for this specific MEC. All other
4756 * pipes' interrupts are set by amdkfd.
4757 */
4758
4759 if (me == 1) {
4760 switch (pipe) {
4761 case 0:
4762 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
4763 break;
4764 case 1:
4765 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
4766 break;
4767 default:
4768 DRM_DEBUG("invalid pipe %d\n", pipe);
4769 return;
4770 }
4771 } else {
4772 DRM_DEBUG("invalid me %d\n", me);
4773 return;
4774 }
4775
4776 switch (state) {
4777 case AMDGPU_IRQ_STATE_DISABLE:
4778 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
4779 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4780 TIME_STAMP_INT_ENABLE, 0);
4781 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4782 GENERIC0_INT_ENABLE, 0);
4783 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
4784 break;
4785 case AMDGPU_IRQ_STATE_ENABLE:
4786 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
4787 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4788 TIME_STAMP_INT_ENABLE, 1);
4789 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4790 GENERIC0_INT_ENABLE, 1);
4791 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
4792 break;
4793 default:
4794 break;
4795 }
4796 }
4797
gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)4798 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4799 struct amdgpu_irq_src *src,
4800 unsigned type,
4801 enum amdgpu_interrupt_state state)
4802 {
4803 switch (type) {
4804 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4805 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
4806 break;
4807 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
4808 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
4809 break;
4810 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4811 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4812 break;
4813 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4814 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4815 break;
4816 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4817 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4818 break;
4819 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4820 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4821 break;
4822 default:
4823 break;
4824 }
4825 return 0;
4826 }
4827
gfx_v12_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4828 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev,
4829 struct amdgpu_irq_src *source,
4830 struct amdgpu_iv_entry *entry)
4831 {
4832 u32 doorbell_offset = entry->src_data[0];
4833 u8 me_id, pipe_id, queue_id;
4834 struct amdgpu_ring *ring;
4835 int i;
4836
4837 DRM_DEBUG("IH: CP EOP\n");
4838
4839 if (adev->enable_mes && doorbell_offset) {
4840 struct amdgpu_userq_fence_driver *fence_drv = NULL;
4841 struct xarray *xa = &adev->userq_xa;
4842 unsigned long flags;
4843
4844 xa_lock_irqsave(xa, flags);
4845 fence_drv = xa_load(xa, doorbell_offset);
4846 if (fence_drv)
4847 amdgpu_userq_fence_driver_process(fence_drv);
4848 xa_unlock_irqrestore(xa, flags);
4849 } else {
4850 me_id = (entry->ring_id & 0x0c) >> 2;
4851 pipe_id = (entry->ring_id & 0x03) >> 0;
4852 queue_id = (entry->ring_id & 0x70) >> 4;
4853
4854 switch (me_id) {
4855 case 0:
4856 if (pipe_id == 0)
4857 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4858 else
4859 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
4860 break;
4861 case 1:
4862 case 2:
4863 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4864 ring = &adev->gfx.compute_ring[i];
4865 /* Per-queue interrupt is supported for MEC starting from VI.
4866 * The interrupt can only be enabled/disabled per pipe instead
4867 * of per queue.
4868 */
4869 if ((ring->me == me_id) &&
4870 (ring->pipe == pipe_id) &&
4871 (ring->queue == queue_id))
4872 amdgpu_fence_process(ring);
4873 }
4874 break;
4875 }
4876 }
4877
4878 return 0;
4879 }
4880
gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)4881 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4882 struct amdgpu_irq_src *source,
4883 unsigned int type,
4884 enum amdgpu_interrupt_state state)
4885 {
4886 u32 cp_int_cntl_reg, cp_int_cntl;
4887 int i, j;
4888
4889 switch (state) {
4890 case AMDGPU_IRQ_STATE_DISABLE:
4891 case AMDGPU_IRQ_STATE_ENABLE:
4892 for (i = 0; i < adev->gfx.me.num_me; i++) {
4893 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4894 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4895
4896 if (cp_int_cntl_reg) {
4897 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4898 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4899 PRIV_REG_INT_ENABLE,
4900 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4901 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4902 }
4903 }
4904 }
4905 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
4906 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
4907 /* MECs start at 1 */
4908 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);
4909
4910 if (cp_int_cntl_reg) {
4911 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4912 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4913 PRIV_REG_INT_ENABLE,
4914 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4915 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4916 }
4917 }
4918 }
4919 break;
4920 default:
4921 break;
4922 }
4923
4924 return 0;
4925 }
4926
gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)4927 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev,
4928 struct amdgpu_irq_src *source,
4929 unsigned type,
4930 enum amdgpu_interrupt_state state)
4931 {
4932 u32 cp_int_cntl_reg, cp_int_cntl;
4933 int i, j;
4934
4935 switch (state) {
4936 case AMDGPU_IRQ_STATE_DISABLE:
4937 case AMDGPU_IRQ_STATE_ENABLE:
4938 for (i = 0; i < adev->gfx.me.num_me; i++) {
4939 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4940 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4941
4942 if (cp_int_cntl_reg) {
4943 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4944 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4945 OPCODE_ERROR_INT_ENABLE,
4946 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4947 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4948 }
4949 }
4950 }
4951 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
4952 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
4953 /* MECs start at 1 */
4954 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);
4955
4956 if (cp_int_cntl_reg) {
4957 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4958 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4959 OPCODE_ERROR_INT_ENABLE,
4960 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4961 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4962 }
4963 }
4964 }
4965 break;
4966 default:
4967 break;
4968 }
4969 return 0;
4970 }
4971
gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)4972 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4973 struct amdgpu_irq_src *source,
4974 unsigned int type,
4975 enum amdgpu_interrupt_state state)
4976 {
4977 u32 cp_int_cntl_reg, cp_int_cntl;
4978 int i, j;
4979
4980 switch (state) {
4981 case AMDGPU_IRQ_STATE_DISABLE:
4982 case AMDGPU_IRQ_STATE_ENABLE:
4983 for (i = 0; i < adev->gfx.me.num_me; i++) {
4984 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4985 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4986
4987 if (cp_int_cntl_reg) {
4988 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4989 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4990 PRIV_INSTR_INT_ENABLE,
4991 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4992 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4993 }
4994 }
4995 }
4996 break;
4997 default:
4998 break;
4999 }
5000
5001 return 0;
5002 }
5003
gfx_v12_0_handle_priv_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)5004 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev,
5005 struct amdgpu_iv_entry *entry)
5006 {
5007 u8 me_id, pipe_id, queue_id;
5008 struct amdgpu_ring *ring;
5009 int i;
5010
5011 me_id = (entry->ring_id & 0x0c) >> 2;
5012 pipe_id = (entry->ring_id & 0x03) >> 0;
5013 queue_id = (entry->ring_id & 0x70) >> 4;
5014
5015 if (!adev->gfx.disable_kq) {
5016 switch (me_id) {
5017 case 0:
5018 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5019 ring = &adev->gfx.gfx_ring[i];
5020 if (ring->me == me_id && ring->pipe == pipe_id &&
5021 ring->queue == queue_id)
5022 drm_sched_fault(&ring->sched);
5023 }
5024 break;
5025 case 1:
5026 case 2:
5027 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5028 ring = &adev->gfx.compute_ring[i];
5029 if (ring->me == me_id && ring->pipe == pipe_id &&
5030 ring->queue == queue_id)
5031 drm_sched_fault(&ring->sched);
5032 }
5033 break;
5034 default:
5035 BUG();
5036 break;
5037 }
5038 }
5039 }
5040
gfx_v12_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5041 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev,
5042 struct amdgpu_irq_src *source,
5043 struct amdgpu_iv_entry *entry)
5044 {
5045 DRM_ERROR("Illegal register access in command stream\n");
5046 gfx_v12_0_handle_priv_fault(adev, entry);
5047 return 0;
5048 }
5049
gfx_v12_0_bad_op_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5050 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev,
5051 struct amdgpu_irq_src *source,
5052 struct amdgpu_iv_entry *entry)
5053 {
5054 DRM_ERROR("Illegal opcode in command stream \n");
5055 gfx_v12_0_handle_priv_fault(adev, entry);
5056 return 0;
5057 }
5058
gfx_v12_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5059 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev,
5060 struct amdgpu_irq_src *source,
5061 struct amdgpu_iv_entry *entry)
5062 {
5063 DRM_ERROR("Illegal instruction in command stream\n");
5064 gfx_v12_0_handle_priv_fault(adev, entry);
5065 return 0;
5066 }
5067
gfx_v12_0_emit_mem_sync(struct amdgpu_ring * ring)5068 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring)
5069 {
5070 const unsigned int gcr_cntl =
5071 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
5072 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
5073 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
5074 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
5075 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
5076 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
5077 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
5078 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
5079
5080 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
5081 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
5082 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
5083 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
5084 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
5085 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
5086 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
5087 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
5088 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
5089 }
5090
gfx_v12_ring_insert_nop(struct amdgpu_ring * ring,uint32_t num_nop)5091 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
5092 {
5093 /* Header itself is a NOP packet */
5094 if (num_nop == 1) {
5095 amdgpu_ring_write(ring, ring->funcs->nop);
5096 return;
5097 }
5098
5099 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/
5100 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));
5101
5102 /* Header is at index 0, followed by num_nops - 1 NOP packet's */
5103 amdgpu_ring_insert_nop(ring, num_nop - 1);
5104 }
5105
gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring * ring)5106 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
5107 {
5108 /* Emit the cleaner shader */
5109 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
5110 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */
5111 }
5112
gfx_v12_ip_print(struct amdgpu_ip_block * ip_block,struct drm_printer * p)5113 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
5114 {
5115 struct amdgpu_device *adev = ip_block->adev;
5116 uint32_t i, j, k, reg, index = 0;
5117 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
5118
5119 if (!adev->gfx.ip_dump_core)
5120 return;
5121
5122 for (i = 0; i < reg_count; i++)
5123 drm_printf(p, "%-50s \t 0x%08x\n",
5124 gc_reg_list_12_0[i].reg_name,
5125 adev->gfx.ip_dump_core[i]);
5126
5127 /* print compute queue registers for all instances */
5128 if (!adev->gfx.ip_dump_compute_queues)
5129 return;
5130
5131 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
5132 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
5133 adev->gfx.mec.num_mec,
5134 adev->gfx.mec.num_pipe_per_mec,
5135 adev->gfx.mec.num_queue_per_pipe);
5136
5137 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
5138 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
5139 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
5140 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
5141 for (reg = 0; reg < reg_count; reg++) {
5142 drm_printf(p, "%-50s \t 0x%08x\n",
5143 gc_cp_reg_list_12[reg].reg_name,
5144 adev->gfx.ip_dump_compute_queues[index + reg]);
5145 }
5146 index += reg_count;
5147 }
5148 }
5149 }
5150
5151 /* print gfx queue registers for all instances */
5152 if (!adev->gfx.ip_dump_gfx_queues)
5153 return;
5154
5155 index = 0;
5156 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
5157 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
5158 adev->gfx.me.num_me,
5159 adev->gfx.me.num_pipe_per_me,
5160 adev->gfx.me.num_queue_per_pipe);
5161
5162 for (i = 0; i < adev->gfx.me.num_me; i++) {
5163 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5164 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
5165 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
5166 for (reg = 0; reg < reg_count; reg++) {
5167 drm_printf(p, "%-50s \t 0x%08x\n",
5168 gc_gfx_queue_reg_list_12[reg].reg_name,
5169 adev->gfx.ip_dump_gfx_queues[index + reg]);
5170 }
5171 index += reg_count;
5172 }
5173 }
5174 }
5175 }
5176
gfx_v12_ip_dump(struct amdgpu_ip_block * ip_block)5177 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block)
5178 {
5179 struct amdgpu_device *adev = ip_block->adev;
5180 uint32_t i, j, k, reg, index = 0;
5181 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
5182
5183 if (!adev->gfx.ip_dump_core)
5184 return;
5185
5186 amdgpu_gfx_off_ctrl(adev, false);
5187 for (i = 0; i < reg_count; i++)
5188 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i]));
5189 amdgpu_gfx_off_ctrl(adev, true);
5190
5191 /* dump compute queue registers for all instances */
5192 if (!adev->gfx.ip_dump_compute_queues)
5193 return;
5194
5195 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
5196 amdgpu_gfx_off_ctrl(adev, false);
5197 mutex_lock(&adev->srbm_mutex);
5198 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
5199 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
5200 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
5201 /* ME0 is for GFX so start from 1 for CP */
5202 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
5203 for (reg = 0; reg < reg_count; reg++) {
5204 adev->gfx.ip_dump_compute_queues[index + reg] =
5205 RREG32(SOC15_REG_ENTRY_OFFSET(
5206 gc_cp_reg_list_12[reg]));
5207 }
5208 index += reg_count;
5209 }
5210 }
5211 }
5212 soc24_grbm_select(adev, 0, 0, 0, 0);
5213 mutex_unlock(&adev->srbm_mutex);
5214 amdgpu_gfx_off_ctrl(adev, true);
5215
5216 /* dump gfx queue registers for all instances */
5217 if (!adev->gfx.ip_dump_gfx_queues)
5218 return;
5219
5220 index = 0;
5221 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
5222 amdgpu_gfx_off_ctrl(adev, false);
5223 mutex_lock(&adev->srbm_mutex);
5224 for (i = 0; i < adev->gfx.me.num_me; i++) {
5225 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5226 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
5227 soc24_grbm_select(adev, i, j, k, 0);
5228
5229 for (reg = 0; reg < reg_count; reg++) {
5230 adev->gfx.ip_dump_gfx_queues[index + reg] =
5231 RREG32(SOC15_REG_ENTRY_OFFSET(
5232 gc_gfx_queue_reg_list_12[reg]));
5233 }
5234 index += reg_count;
5235 }
5236 }
5237 }
5238 soc24_grbm_select(adev, 0, 0, 0, 0);
5239 mutex_unlock(&adev->srbm_mutex);
5240 amdgpu_gfx_off_ctrl(adev, true);
5241 }
5242
gfx_v12_pipe_reset_support(struct amdgpu_device * adev)5243 static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev)
5244 {
5245 /* Disable the pipe reset until the CPFW fully support it.*/
5246 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n");
5247 return false;
5248 }
5249
gfx_v12_reset_gfx_pipe(struct amdgpu_ring * ring)5250 static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring)
5251 {
5252 struct amdgpu_device *adev = ring->adev;
5253 uint32_t reset_pipe = 0, clean_pipe = 0;
5254 int r;
5255
5256 if (!gfx_v12_pipe_reset_support(adev))
5257 return -EOPNOTSUPP;
5258
5259 gfx_v12_0_set_safe_mode(adev, 0);
5260 mutex_lock(&adev->srbm_mutex);
5261 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5262
5263 switch (ring->pipe) {
5264 case 0:
5265 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5266 PFP_PIPE0_RESET, 1);
5267 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5268 ME_PIPE0_RESET, 1);
5269 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5270 PFP_PIPE0_RESET, 0);
5271 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5272 ME_PIPE0_RESET, 0);
5273 break;
5274 case 1:
5275 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5276 PFP_PIPE1_RESET, 1);
5277 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
5278 ME_PIPE1_RESET, 1);
5279 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5280 PFP_PIPE1_RESET, 0);
5281 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
5282 ME_PIPE1_RESET, 0);
5283 break;
5284 default:
5285 break;
5286 }
5287
5288 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe);
5289 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe);
5290
5291 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -
5292 RS64_FW_UC_START_ADDR_LO;
5293 soc24_grbm_select(adev, 0, 0, 0, 0);
5294 mutex_unlock(&adev->srbm_mutex);
5295 gfx_v12_0_unset_safe_mode(adev, 0);
5296
5297 dev_info(adev->dev, "The ring %s pipe reset: %s\n", ring->name,
5298 r == 0 ? "successfully" : "failed");
5299 /* Sometimes the ME start pc counter can't cache correctly, so the
5300 * PC check only as a reference and pipe reset result rely on the
5301 * later ring test.
5302 */
5303 return 0;
5304 }
5305
gfx_v12_0_reset_kgq(struct amdgpu_ring * ring,unsigned int vmid,struct amdgpu_fence * timedout_fence)5306 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring,
5307 unsigned int vmid,
5308 struct amdgpu_fence *timedout_fence)
5309 {
5310 struct amdgpu_device *adev = ring->adev;
5311 int r;
5312
5313 amdgpu_ring_reset_helper_begin(ring, timedout_fence);
5314
5315 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false);
5316 if (r) {
5317 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r);
5318 r = gfx_v12_reset_gfx_pipe(ring);
5319 if (r)
5320 return r;
5321 }
5322
5323 r = gfx_v12_0_kgq_init_queue(ring, true);
5324 if (r) {
5325 dev_err(adev->dev, "failed to init kgq\n");
5326 return r;
5327 }
5328
5329 r = amdgpu_mes_map_legacy_queue(adev, ring);
5330 if (r) {
5331 dev_err(adev->dev, "failed to remap kgq\n");
5332 return r;
5333 }
5334
5335 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
5336 }
5337
gfx_v12_0_reset_compute_pipe(struct amdgpu_ring * ring)5338 static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring)
5339 {
5340 struct amdgpu_device *adev = ring->adev;
5341 uint32_t reset_pipe = 0, clean_pipe = 0;
5342 int r = 0;
5343
5344 if (!gfx_v12_pipe_reset_support(adev))
5345 return -EOPNOTSUPP;
5346
5347 gfx_v12_0_set_safe_mode(adev, 0);
5348 mutex_lock(&adev->srbm_mutex);
5349 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5350
5351 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
5352 clean_pipe = reset_pipe;
5353
5354 if (adev->gfx.rs64_enable) {
5355 switch (ring->pipe) {
5356 case 0:
5357 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5358 MEC_PIPE0_RESET, 1);
5359 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5360 MEC_PIPE0_RESET, 0);
5361 break;
5362 case 1:
5363 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5364 MEC_PIPE1_RESET, 1);
5365 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5366 MEC_PIPE1_RESET, 0);
5367 break;
5368 case 2:
5369 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5370 MEC_PIPE2_RESET, 1);
5371 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5372 MEC_PIPE2_RESET, 0);
5373 break;
5374 case 3:
5375 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,
5376 MEC_PIPE3_RESET, 1);
5377 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,
5378 MEC_PIPE3_RESET, 0);
5379 break;
5380 default:
5381 break;
5382 }
5383 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe);
5384 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe);
5385 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) -
5386 RS64_FW_UC_START_ADDR_LO;
5387 } else {
5388 switch (ring->pipe) {
5389 case 0:
5390 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,
5391 MEC_ME1_PIPE0_RESET, 1);
5392 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,
5393 MEC_ME1_PIPE0_RESET, 0);
5394 break;
5395 case 1:
5396 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,
5397 MEC_ME1_PIPE1_RESET, 1);
5398 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,
5399 MEC_ME1_PIPE1_RESET, 0);
5400 break;
5401 default:
5402 break;
5403 }
5404 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe);
5405 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe);
5406 /* Doesn't find the F32 MEC instruction pointer register, and suppose
5407 * the driver won't run into the F32 mode.
5408 */
5409 }
5410
5411 soc24_grbm_select(adev, 0, 0, 0, 0);
5412 mutex_unlock(&adev->srbm_mutex);
5413 gfx_v12_0_unset_safe_mode(adev, 0);
5414
5415 dev_info(adev->dev, "The ring %s pipe resets: %s\n", ring->name,
5416 r == 0 ? "successfully" : "failed");
5417 /* Need the ring test to verify the pipe reset result.*/
5418 return 0;
5419 }
5420
gfx_v12_0_reset_kcq(struct amdgpu_ring * ring,unsigned int vmid,struct amdgpu_fence * timedout_fence)5421 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring,
5422 unsigned int vmid,
5423 struct amdgpu_fence *timedout_fence)
5424 {
5425 struct amdgpu_device *adev = ring->adev;
5426 int r;
5427
5428 amdgpu_ring_reset_helper_begin(ring, timedout_fence);
5429
5430 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true);
5431 if (r) {
5432 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r);
5433 r = gfx_v12_0_reset_compute_pipe(ring);
5434 if (r)
5435 return r;
5436 }
5437
5438 r = gfx_v12_0_kcq_init_queue(ring, true);
5439 if (r) {
5440 dev_err(adev->dev, "failed to init kcq\n");
5441 return r;
5442 }
5443 r = amdgpu_mes_map_legacy_queue(adev, ring);
5444 if (r) {
5445 dev_err(adev->dev, "failed to remap kcq\n");
5446 return r;
5447 }
5448
5449 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
5450 }
5451
gfx_v12_0_ring_begin_use(struct amdgpu_ring * ring)5452 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring)
5453 {
5454 amdgpu_gfx_profile_ring_begin_use(ring);
5455
5456 amdgpu_gfx_enforce_isolation_ring_begin_use(ring);
5457 }
5458
gfx_v12_0_ring_end_use(struct amdgpu_ring * ring)5459 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring)
5460 {
5461 amdgpu_gfx_profile_ring_end_use(ring);
5462
5463 amdgpu_gfx_enforce_isolation_ring_end_use(ring);
5464 }
5465
5466 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = {
5467 .name = "gfx_v12_0",
5468 .early_init = gfx_v12_0_early_init,
5469 .late_init = gfx_v12_0_late_init,
5470 .sw_init = gfx_v12_0_sw_init,
5471 .sw_fini = gfx_v12_0_sw_fini,
5472 .hw_init = gfx_v12_0_hw_init,
5473 .hw_fini = gfx_v12_0_hw_fini,
5474 .suspend = gfx_v12_0_suspend,
5475 .resume = gfx_v12_0_resume,
5476 .is_idle = gfx_v12_0_is_idle,
5477 .wait_for_idle = gfx_v12_0_wait_for_idle,
5478 .set_clockgating_state = gfx_v12_0_set_clockgating_state,
5479 .set_powergating_state = gfx_v12_0_set_powergating_state,
5480 .get_clockgating_state = gfx_v12_0_get_clockgating_state,
5481 .dump_ip_state = gfx_v12_ip_dump,
5482 .print_ip_state = gfx_v12_ip_print,
5483 };
5484
5485 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = {
5486 .type = AMDGPU_RING_TYPE_GFX,
5487 .align_mask = 0xff,
5488 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5489 .support_64bit_ptrs = true,
5490 .secure_submission_supported = true,
5491 .get_rptr = gfx_v12_0_ring_get_rptr_gfx,
5492 .get_wptr = gfx_v12_0_ring_get_wptr_gfx,
5493 .set_wptr = gfx_v12_0_ring_set_wptr_gfx,
5494 .emit_frame_size = /* totally 242 maximum if 16 IBs */
5495 5 + /* COND_EXEC */
5496 7 + /* PIPELINE_SYNC */
5497 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5498 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5499 2 + /* VM_FLUSH */
5500 8 + /* FENCE for VM_FLUSH */
5501 5 + /* COND_EXEC */
5502 7 + /* HDP_flush */
5503 4 + /* VGT_flush */
5504 31 + /* DE_META */
5505 3 + /* CNTX_CTRL */
5506 5 + /* HDP_INVL */
5507 8 + 8 + /* FENCE x2 */
5508 8 + /* gfx_v12_0_emit_mem_sync */
5509 2, /* gfx_v12_0_ring_emit_cleaner_shader */
5510 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */
5511 .emit_ib = gfx_v12_0_ring_emit_ib_gfx,
5512 .emit_fence = gfx_v12_0_ring_emit_fence,
5513 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync,
5514 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush,
5515 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,
5516 .test_ring = gfx_v12_0_ring_test_ring,
5517 .test_ib = gfx_v12_0_ring_test_ib,
5518 .insert_nop = gfx_v12_ring_insert_nop,
5519 .pad_ib = amdgpu_ring_generic_pad_ib,
5520 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl,
5521 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec,
5522 .preempt_ib = gfx_v12_0_ring_preempt_ib,
5523 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl,
5524 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5525 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5526 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5527 .emit_mem_sync = gfx_v12_0_emit_mem_sync,
5528 .reset = gfx_v12_0_reset_kgq,
5529 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
5530 .begin_use = gfx_v12_0_ring_begin_use,
5531 .end_use = gfx_v12_0_ring_end_use,
5532 };
5533
5534 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = {
5535 .type = AMDGPU_RING_TYPE_COMPUTE,
5536 .align_mask = 0xff,
5537 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5538 .support_64bit_ptrs = true,
5539 .get_rptr = gfx_v12_0_ring_get_rptr_compute,
5540 .get_wptr = gfx_v12_0_ring_get_wptr_compute,
5541 .set_wptr = gfx_v12_0_ring_set_wptr_compute,
5542 .emit_frame_size =
5543 7 + /* gfx_v12_0_ring_emit_hdp_flush */
5544 5 + /* hdp invalidate */
5545 7 + /* gfx_v12_0_ring_emit_pipeline_sync */
5546 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5547 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5548 2 + /* gfx_v12_0_ring_emit_vm_flush */
5549 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */
5550 8 + /* gfx_v12_0_emit_mem_sync */
5551 2, /* gfx_v12_0_ring_emit_cleaner_shader */
5552 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */
5553 .emit_ib = gfx_v12_0_ring_emit_ib_compute,
5554 .emit_fence = gfx_v12_0_ring_emit_fence,
5555 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync,
5556 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush,
5557 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,
5558 .test_ring = gfx_v12_0_ring_test_ring,
5559 .test_ib = gfx_v12_0_ring_test_ib,
5560 .insert_nop = gfx_v12_ring_insert_nop,
5561 .pad_ib = amdgpu_ring_generic_pad_ib,
5562 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5563 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5564 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5565 .emit_mem_sync = gfx_v12_0_emit_mem_sync,
5566 .reset = gfx_v12_0_reset_kcq,
5567 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
5568 .begin_use = gfx_v12_0_ring_begin_use,
5569 .end_use = gfx_v12_0_ring_end_use,
5570 };
5571
5572 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = {
5573 .type = AMDGPU_RING_TYPE_KIQ,
5574 .align_mask = 0xff,
5575 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5576 .support_64bit_ptrs = true,
5577 .get_rptr = gfx_v12_0_ring_get_rptr_compute,
5578 .get_wptr = gfx_v12_0_ring_get_wptr_compute,
5579 .set_wptr = gfx_v12_0_ring_set_wptr_compute,
5580 .emit_frame_size =
5581 7 + /* gfx_v12_0_ring_emit_hdp_flush */
5582 5 + /*hdp invalidate */
5583 7 + /* gfx_v12_0_ring_emit_pipeline_sync */
5584 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5585 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5586 2 + /* gfx_v12_0_ring_emit_vm_flush */
5587 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */
5588 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */
5589 .emit_ib = gfx_v12_0_ring_emit_ib_compute,
5590 .emit_fence = gfx_v12_0_ring_emit_fence_kiq,
5591 .test_ring = gfx_v12_0_ring_test_ring,
5592 .test_ib = gfx_v12_0_ring_test_ib,
5593 .insert_nop = amdgpu_ring_insert_nop,
5594 .pad_ib = amdgpu_ring_generic_pad_ib,
5595 .emit_rreg = gfx_v12_0_ring_emit_rreg,
5596 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5597 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5598 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5599 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,
5600 };
5601
gfx_v12_0_set_ring_funcs(struct amdgpu_device * adev)5602 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev)
5603 {
5604 int i;
5605
5606 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq;
5607
5608 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5609 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx;
5610
5611 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5612 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute;
5613 }
5614
5615 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = {
5616 .set = gfx_v12_0_set_eop_interrupt_state,
5617 .process = gfx_v12_0_eop_irq,
5618 };
5619
5620 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = {
5621 .set = gfx_v12_0_set_priv_reg_fault_state,
5622 .process = gfx_v12_0_priv_reg_irq,
5623 };
5624
5625 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = {
5626 .set = gfx_v12_0_set_bad_op_fault_state,
5627 .process = gfx_v12_0_bad_op_irq,
5628 };
5629
5630 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = {
5631 .set = gfx_v12_0_set_priv_inst_fault_state,
5632 .process = gfx_v12_0_priv_inst_irq,
5633 };
5634
gfx_v12_0_set_irq_funcs(struct amdgpu_device * adev)5635 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev)
5636 {
5637 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5638 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs;
5639
5640 adev->gfx.priv_reg_irq.num_types = 1;
5641 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs;
5642
5643 adev->gfx.bad_op_irq.num_types = 1;
5644 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs;
5645
5646 adev->gfx.priv_inst_irq.num_types = 1;
5647 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs;
5648 }
5649
gfx_v12_0_set_imu_funcs(struct amdgpu_device * adev)5650 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev)
5651 {
5652 if (adev->flags & AMD_IS_APU)
5653 adev->gfx.imu.mode = MISSION_MODE;
5654 else
5655 adev->gfx.imu.mode = DEBUG_MODE;
5656
5657 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs;
5658 }
5659
gfx_v12_0_set_rlc_funcs(struct amdgpu_device * adev)5660 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev)
5661 {
5662 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs;
5663 }
5664
gfx_v12_0_set_mqd_funcs(struct amdgpu_device * adev)5665 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev)
5666 {
5667 /* set gfx eng mqd */
5668 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
5669 sizeof(struct v12_gfx_mqd);
5670 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
5671 gfx_v12_0_gfx_mqd_init;
5672 /* set compute eng mqd */
5673 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
5674 sizeof(struct v12_compute_mqd);
5675 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
5676 gfx_v12_0_compute_mqd_init;
5677 }
5678
gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device * adev,u32 bitmap)5679 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
5680 u32 bitmap)
5681 {
5682 u32 data;
5683
5684 if (!bitmap)
5685 return;
5686
5687 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5688 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5689
5690 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
5691 }
5692
gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device * adev)5693 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
5694 {
5695 u32 data, wgp_bitmask;
5696 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
5697 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);
5698
5699 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5700 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5701
5702 wgp_bitmask =
5703 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
5704
5705 return (~data) & wgp_bitmask;
5706 }
5707
gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device * adev)5708 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
5709 {
5710 u32 wgp_idx, wgp_active_bitmap;
5711 u32 cu_bitmap_per_wgp, cu_active_bitmap;
5712
5713 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev);
5714 cu_active_bitmap = 0;
5715
5716 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
5717 /* if there is one WGP enabled, it means 2 CUs will be enabled */
5718 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
5719 if (wgp_active_bitmap & (1 << wgp_idx))
5720 cu_active_bitmap |= cu_bitmap_per_wgp;
5721 }
5722
5723 return cu_active_bitmap;
5724 }
5725
gfx_v12_0_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)5726 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,
5727 struct amdgpu_cu_info *cu_info)
5728 {
5729 int i, j, k, counter, active_cu_number = 0;
5730 u32 mask, bitmap;
5731 unsigned disable_masks[8 * 2];
5732
5733 if (!adev || !cu_info)
5734 return -EINVAL;
5735
5736 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
5737
5738 mutex_lock(&adev->grbm_idx_mutex);
5739 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5740 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5741 bitmap = i * adev->gfx.config.max_sh_per_se + j;
5742 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1))
5743 continue;
5744 mask = 1;
5745 counter = 0;
5746 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5747 if (i < 8 && j < 2)
5748 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(
5749 adev, disable_masks[i * 2 + j]);
5750 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev);
5751
5752 /**
5753 * GFX12 could support more than 4 SEs, while the bitmap
5754 * in cu_info struct is 4x4 and ioctl interface struct
5755 * drm_amdgpu_info_device should keep stable.
5756 * So we use last two columns of bitmap to store cu mask for
5757 * SEs 4 to 7, the layout of the bitmap is as below:
5758 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}
5759 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}
5760 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}
5761 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}
5762 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}
5763 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]}
5764 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]}
5765 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]}
5766 */
5767 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap;
5768
5769 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5770 if (bitmap & mask)
5771 counter++;
5772
5773 mask <<= 1;
5774 }
5775 active_cu_number += counter;
5776 }
5777 }
5778 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5779 mutex_unlock(&adev->grbm_idx_mutex);
5780
5781 cu_info->number = active_cu_number;
5782 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5783
5784 return 0;
5785 }
5786
5787 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = {
5788 .type = AMD_IP_BLOCK_TYPE_GFX,
5789 .major = 12,
5790 .minor = 0,
5791 .rev = 0,
5792 .funcs = &gfx_v12_0_ip_funcs,
5793 };
5794