1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "imu_v12_0.h" 33 #include "soc24.h" 34 #include "nvd.h" 35 36 #include "gc/gc_12_0_0_offset.h" 37 #include "gc/gc_12_0_0_sh_mask.h" 38 #include "soc24_enum.h" 39 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h" 40 41 #include "soc15.h" 42 #include "clearstate_gfx12.h" 43 #include "v12_structs.h" 44 #include "gfx_v12_0.h" 45 #include "nbif_v6_3_1.h" 46 #include "mes_v12_0.h" 47 #include "mes_userqueue.h" 48 #include "amdgpu_userq_fence.h" 49 50 #define GFX12_NUM_GFX_RINGS 1 51 #define GFX12_MEC_HPD_SIZE 2048 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 56 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000 57 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 58 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01 59 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000 60 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 61 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000 62 63 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 64 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 65 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 66 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 67 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 68 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 69 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501 70 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000 71 72 73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc_kicker.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); 84 85 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 88 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 115 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 116 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 117 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 118 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 120 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 121 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 122 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 125 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL), 127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 128 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 139 /* cp header registers */ 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 148 /* SE status registers */ 149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 152 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 153 }; 154 155 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 156 /* compute registers */ 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 196 /* cp header registers */ 197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 204 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 205 }; 206 207 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 208 /* gfx queue registers */ 209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE), 210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID), 211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY), 212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM), 213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE), 214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI), 215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET), 216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL), 217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR), 218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR), 219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI), 220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST), 221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED), 222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL), 223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0), 224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0), 225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR), 226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI), 227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO), 228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI), 229 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 233 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 234 /* cp header registers */ 235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 242 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), 243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 250 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), 251 }; 252 253 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { 254 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) 257 }; 258 259 static const struct soc15_reg_golden golden_settings_gc_12_0[] = { 260 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), 261 }; 262 263 #define DEFAULT_SH_MEM_CONFIG \ 264 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 265 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 266 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 267 268 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev); 269 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev); 270 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev); 271 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev); 272 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev); 273 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev); 274 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 275 struct amdgpu_cu_info *cu_info); 276 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev); 277 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 278 u32 sh_num, u32 instance, int xcc_id); 279 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 280 281 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 282 uint32_t val); 283 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 284 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 285 uint16_t pasid, uint32_t flush_type, 286 bool all_hub, uint8_t dst_sel); 287 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 288 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 289 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 290 bool enable); 291 292 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 293 uint64_t queue_mask) 294 { 295 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 296 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 297 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 298 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 299 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 300 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 301 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 302 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 303 amdgpu_ring_write(kiq_ring, 0); 304 } 305 306 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 307 struct amdgpu_ring *ring) 308 { 309 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 310 uint64_t wptr_addr = ring->wptr_gpu_addr; 311 uint32_t me = 0, eng_sel = 0; 312 313 switch (ring->funcs->type) { 314 case AMDGPU_RING_TYPE_COMPUTE: 315 me = 1; 316 eng_sel = 0; 317 break; 318 case AMDGPU_RING_TYPE_GFX: 319 me = 0; 320 eng_sel = 4; 321 break; 322 case AMDGPU_RING_TYPE_MES: 323 me = 2; 324 eng_sel = 5; 325 break; 326 default: 327 WARN_ON(1); 328 } 329 330 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 331 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 332 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 333 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 334 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 335 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 336 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 337 PACKET3_MAP_QUEUES_ME((me)) | 338 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 339 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 340 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 341 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 342 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 343 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 344 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 345 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 346 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 347 } 348 349 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 350 struct amdgpu_ring *ring, 351 enum amdgpu_unmap_queues_action action, 352 u64 gpu_addr, u64 seq) 353 { 354 struct amdgpu_device *adev = kiq_ring->adev; 355 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 356 357 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 358 amdgpu_mes_unmap_legacy_queue(adev, ring, action, 359 gpu_addr, seq, 0); 360 return; 361 } 362 363 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 364 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 365 PACKET3_UNMAP_QUEUES_ACTION(action) | 366 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 367 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 368 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 369 amdgpu_ring_write(kiq_ring, 370 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 371 372 if (action == PREEMPT_QUEUES_NO_UNMAP) { 373 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 374 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 375 amdgpu_ring_write(kiq_ring, seq); 376 } else { 377 amdgpu_ring_write(kiq_ring, 0); 378 amdgpu_ring_write(kiq_ring, 0); 379 amdgpu_ring_write(kiq_ring, 0); 380 } 381 } 382 383 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 384 struct amdgpu_ring *ring, 385 u64 addr, u64 seq) 386 { 387 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 388 389 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 390 amdgpu_ring_write(kiq_ring, 391 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 392 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 393 PACKET3_QUERY_STATUS_COMMAND(2)); 394 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 395 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 396 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 397 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 398 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 399 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 400 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 401 } 402 403 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 404 uint16_t pasid, 405 uint32_t flush_type, 406 bool all_hub) 407 { 408 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 409 } 410 411 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = { 412 .kiq_set_resources = gfx_v12_0_kiq_set_resources, 413 .kiq_map_queues = gfx_v12_0_kiq_map_queues, 414 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues, 415 .kiq_query_status = gfx_v12_0_kiq_query_status, 416 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs, 417 .set_resources_size = 8, 418 .map_queues_size = 7, 419 .unmap_queues_size = 6, 420 .query_status_size = 7, 421 .invalidate_tlbs_size = 2, 422 }; 423 424 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 425 { 426 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs; 427 } 428 429 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 430 int mem_space, int opt, uint32_t addr0, 431 uint32_t addr1, uint32_t ref, 432 uint32_t mask, uint32_t inv) 433 { 434 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 435 amdgpu_ring_write(ring, 436 /* memory (1) or register (0) */ 437 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 438 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 439 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 440 WAIT_REG_MEM_ENGINE(eng_sel))); 441 442 if (mem_space) 443 BUG_ON(addr0 & 0x3); /* Dword align */ 444 amdgpu_ring_write(ring, addr0); 445 amdgpu_ring_write(ring, addr1); 446 amdgpu_ring_write(ring, ref); 447 amdgpu_ring_write(ring, mask); 448 amdgpu_ring_write(ring, inv); /* poll interval */ 449 } 450 451 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) 452 { 453 struct amdgpu_device *adev = ring->adev; 454 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 455 uint32_t tmp = 0; 456 unsigned i; 457 int r; 458 459 WREG32(scratch, 0xCAFEDEAD); 460 r = amdgpu_ring_alloc(ring, 5); 461 if (r) { 462 drm_err(adev_to_drm(adev), 463 "cp failed to lock ring %d (%d).\n", 464 ring->idx, r); 465 return r; 466 } 467 468 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 469 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 470 } else { 471 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 472 amdgpu_ring_write(ring, scratch - 473 PACKET3_SET_UCONFIG_REG_START); 474 amdgpu_ring_write(ring, 0xDEADBEEF); 475 } 476 amdgpu_ring_commit(ring); 477 478 for (i = 0; i < adev->usec_timeout; i++) { 479 tmp = RREG32(scratch); 480 if (tmp == 0xDEADBEEF) 481 break; 482 if (amdgpu_emu_mode == 1) 483 msleep(1); 484 else 485 udelay(1); 486 } 487 488 if (i >= adev->usec_timeout) 489 r = -ETIMEDOUT; 490 return r; 491 } 492 493 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 494 { 495 struct amdgpu_device *adev = ring->adev; 496 struct amdgpu_ib ib; 497 struct dma_fence *f = NULL; 498 unsigned index; 499 uint64_t gpu_addr; 500 uint32_t *cpu_ptr; 501 long r; 502 503 /* MES KIQ fw hasn't indirect buffer support for now */ 504 if (adev->enable_mes_kiq && 505 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 506 return 0; 507 508 memset(&ib, 0, sizeof(ib)); 509 510 r = amdgpu_device_wb_get(adev, &index); 511 if (r) 512 return r; 513 514 gpu_addr = adev->wb.gpu_addr + (index * 4); 515 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 516 cpu_ptr = &adev->wb.wb[index]; 517 518 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 519 if (r) { 520 drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); 521 goto err1; 522 } 523 524 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 526 ib.ptr[2] = lower_32_bits(gpu_addr); 527 ib.ptr[3] = upper_32_bits(gpu_addr); 528 ib.ptr[4] = 0xDEADBEEF; 529 ib.length_dw = 5; 530 531 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 532 if (r) 533 goto err2; 534 535 r = dma_fence_wait_timeout(f, false, timeout); 536 if (r == 0) { 537 r = -ETIMEDOUT; 538 goto err2; 539 } else if (r < 0) { 540 goto err2; 541 } 542 543 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 544 r = 0; 545 else 546 r = -EINVAL; 547 err2: 548 amdgpu_ib_free(&ib, NULL); 549 dma_fence_put(f); 550 err1: 551 amdgpu_device_wb_free(adev, index); 552 return r; 553 } 554 555 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev) 556 { 557 amdgpu_ucode_release(&adev->gfx.pfp_fw); 558 amdgpu_ucode_release(&adev->gfx.me_fw); 559 amdgpu_ucode_release(&adev->gfx.rlc_fw); 560 amdgpu_ucode_release(&adev->gfx.mec_fw); 561 562 kfree(adev->gfx.rlc.register_list_format); 563 } 564 565 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 566 { 567 const struct psp_firmware_header_v1_0 *toc_hdr; 568 int err = 0; 569 570 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 571 AMDGPU_UCODE_REQUIRED, 572 "amdgpu/%s_toc.bin", ucode_prefix); 573 if (err) 574 goto out; 575 576 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 577 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 578 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 579 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 580 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 581 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 582 return 0; 583 out: 584 amdgpu_ucode_release(&adev->psp.toc_fw); 585 return err; 586 } 587 588 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) 589 { 590 char ucode_prefix[30]; 591 int err; 592 const struct rlc_firmware_header_v2_0 *rlc_hdr; 593 uint16_t version_major; 594 uint16_t version_minor; 595 596 DRM_DEBUG("\n"); 597 598 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 599 600 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, 601 AMDGPU_UCODE_REQUIRED, 602 "amdgpu/%s_pfp.bin", ucode_prefix); 603 if (err) 604 goto out; 605 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 606 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 607 608 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, 609 AMDGPU_UCODE_REQUIRED, 610 "amdgpu/%s_me.bin", ucode_prefix); 611 if (err) 612 goto out; 613 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 614 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 615 616 if (!amdgpu_sriov_vf(adev)) { 617 if (amdgpu_is_kicker_fw(adev)) 618 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 619 AMDGPU_UCODE_REQUIRED, 620 "amdgpu/%s_rlc_kicker.bin", ucode_prefix); 621 else 622 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 623 AMDGPU_UCODE_REQUIRED, 624 "amdgpu/%s_rlc.bin", ucode_prefix); 625 if (err) 626 goto out; 627 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 628 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 629 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 630 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 631 if (err) 632 goto out; 633 } 634 635 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 636 AMDGPU_UCODE_REQUIRED, 637 "amdgpu/%s_mec.bin", ucode_prefix); 638 if (err) 639 goto out; 640 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 641 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 642 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 643 644 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 645 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix); 646 647 /* only one MEC for gfx 12 */ 648 adev->gfx.mec2_fw = NULL; 649 650 if (adev->gfx.imu.funcs) { 651 if (adev->gfx.imu.funcs->init_microcode) { 652 err = adev->gfx.imu.funcs->init_microcode(adev); 653 if (err) 654 dev_err(adev->dev, "Failed to load imu firmware!\n"); 655 } 656 } 657 658 out: 659 if (err) { 660 amdgpu_ucode_release(&adev->gfx.pfp_fw); 661 amdgpu_ucode_release(&adev->gfx.me_fw); 662 amdgpu_ucode_release(&adev->gfx.rlc_fw); 663 amdgpu_ucode_release(&adev->gfx.mec_fw); 664 } 665 666 return err; 667 } 668 669 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) 670 { 671 u32 count = 0; 672 const struct cs_section_def *sect = NULL; 673 const struct cs_extent_def *ext = NULL; 674 675 count += 1; 676 677 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 678 if (sect->id == SECT_CONTEXT) { 679 for (ext = sect->section; ext->extent != NULL; ++ext) 680 count += 2 + ext->reg_count; 681 } else 682 return 0; 683 } 684 685 return count; 686 } 687 688 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 689 { 690 u32 count = 0, clustercount = 0, i; 691 const struct cs_section_def *sect = NULL; 692 const struct cs_extent_def *ext = NULL; 693 694 if (adev->gfx.rlc.cs_data == NULL) 695 return; 696 if (buffer == NULL) 697 return; 698 699 count += 1; 700 701 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 702 if (sect->id == SECT_CONTEXT) { 703 for (ext = sect->section; ext->extent != NULL; ++ext) { 704 clustercount++; 705 buffer[count++] = ext->reg_count; 706 buffer[count++] = ext->reg_index; 707 708 for (i = 0; i < ext->reg_count; i++) 709 buffer[count++] = cpu_to_le32(ext->extent[i]); 710 } 711 } else 712 return; 713 } 714 715 buffer[0] = clustercount; 716 } 717 718 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev) 719 { 720 /* clear state block */ 721 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 722 &adev->gfx.rlc.clear_state_gpu_addr, 723 (void **)&adev->gfx.rlc.cs_ptr); 724 725 /* jump table block */ 726 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 727 &adev->gfx.rlc.cp_table_gpu_addr, 728 (void **)&adev->gfx.rlc.cp_table_ptr); 729 } 730 731 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 732 { 733 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 734 735 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 736 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 737 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 738 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 739 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 740 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 741 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 742 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 743 adev->gfx.rlc.rlcg_reg_access_supported = true; 744 } 745 746 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) 747 { 748 const struct cs_section_def *cs_data; 749 int r; 750 751 adev->gfx.rlc.cs_data = gfx12_cs_data; 752 753 cs_data = adev->gfx.rlc.cs_data; 754 755 if (cs_data) { 756 /* init clear state block */ 757 r = amdgpu_gfx_rlc_init_csb(adev); 758 if (r) 759 return r; 760 } 761 762 /* init spm vmid with 0xf */ 763 if (adev->gfx.rlc.funcs->update_spm_vmid) 764 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); 765 766 return 0; 767 } 768 769 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev) 770 { 771 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 772 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 773 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 774 } 775 776 static void gfx_v12_0_me_init(struct amdgpu_device *adev) 777 { 778 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 779 780 amdgpu_gfx_graphics_queue_acquire(adev); 781 } 782 783 static int gfx_v12_0_mec_init(struct amdgpu_device *adev) 784 { 785 int r; 786 u32 *hpd; 787 size_t mec_hpd_size; 788 789 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 790 791 /* take ownership of the relevant compute queues */ 792 amdgpu_gfx_compute_queue_acquire(adev); 793 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; 794 795 if (mec_hpd_size) { 796 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 797 AMDGPU_GEM_DOMAIN_GTT, 798 &adev->gfx.mec.hpd_eop_obj, 799 &adev->gfx.mec.hpd_eop_gpu_addr, 800 (void **)&hpd); 801 if (r) { 802 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 803 gfx_v12_0_mec_fini(adev); 804 return r; 805 } 806 807 memset(hpd, 0, mec_hpd_size); 808 809 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 810 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 811 } 812 813 return 0; 814 } 815 816 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 817 { 818 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 819 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 820 (address << SQ_IND_INDEX__INDEX__SHIFT)); 821 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 822 } 823 824 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 825 uint32_t thread, uint32_t regno, 826 uint32_t num, uint32_t *out) 827 { 828 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 829 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 830 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 831 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 832 (SQ_IND_INDEX__AUTO_INCR_MASK)); 833 while (num--) 834 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 835 } 836 837 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, 838 uint32_t xcc_id, 839 uint32_t simd, uint32_t wave, 840 uint32_t *dst, int *no_fields) 841 { 842 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 843 * field when performing a select_se_sh so it should be 844 * zero here */ 845 WARN_ON(simd != 0); 846 847 /* type 4 wave data */ 848 dst[(*no_fields)++] = 4; 849 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 850 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 851 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 852 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 853 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 854 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 855 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 856 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 857 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 858 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 859 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 860 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 861 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 862 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 863 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); 864 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 865 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); 866 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); 867 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); 868 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); 869 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 870 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 871 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); 872 } 873 874 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, 875 uint32_t xcc_id, uint32_t simd, 876 uint32_t wave, uint32_t start, 877 uint32_t size, uint32_t *dst) 878 { 879 WARN_ON(simd != 0); 880 881 wave_read_regs( 882 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 883 dst); 884 } 885 886 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev, 887 uint32_t xcc_id, uint32_t simd, 888 uint32_t wave, uint32_t thread, 889 uint32_t start, uint32_t size, 890 uint32_t *dst) 891 { 892 wave_read_regs( 893 adev, wave, thread, 894 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 895 } 896 897 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, 898 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 899 { 900 soc24_grbm_select(adev, me, pipe, q, vm); 901 } 902 903 /* all sizes are in bytes */ 904 #define MQD_SHADOW_BASE_SIZE 73728 905 #define MQD_SHADOW_BASE_ALIGNMENT 256 906 #define MQD_FWWORKAREA_SIZE 484 907 #define MQD_FWWORKAREA_ALIGNMENT 256 908 909 static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, 910 struct amdgpu_gfx_shadow_info *shadow_info) 911 { 912 /* for gfx */ 913 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 914 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 915 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 916 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 917 /* for compute */ 918 shadow_info->eop_size = GFX12_MEC_HPD_SIZE; 919 shadow_info->eop_alignment = 256; 920 } 921 922 static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev, 923 struct amdgpu_gfx_shadow_info *shadow_info, 924 bool skip_check) 925 { 926 if (adev->gfx.cp_gfx_shadow || skip_check) { 927 gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info); 928 return 0; 929 } 930 931 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 932 return -EINVAL; 933 } 934 935 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { 936 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter, 937 .select_se_sh = &gfx_v12_0_select_se_sh, 938 .read_wave_data = &gfx_v12_0_read_wave_data, 939 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs, 940 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs, 941 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, 942 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, 943 .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info, 944 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, 945 }; 946 947 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) 948 { 949 950 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 951 case IP_VERSION(12, 0, 0): 952 case IP_VERSION(12, 0, 1): 953 adev->gfx.config.max_hw_contexts = 8; 954 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 955 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 956 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 957 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 958 break; 959 default: 960 BUG(); 961 break; 962 } 963 964 return 0; 965 } 966 967 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 968 int me, int pipe, int queue) 969 { 970 int r; 971 struct amdgpu_ring *ring; 972 unsigned int irq_type; 973 974 ring = &adev->gfx.gfx_ring[ring_id]; 975 976 ring->me = me; 977 ring->pipe = pipe; 978 ring->queue = queue; 979 980 ring->ring_obj = NULL; 981 ring->use_doorbell = true; 982 983 if (!ring_id) 984 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 985 else 986 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 987 ring->vm_hub = AMDGPU_GFXHUB(0); 988 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 989 990 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 991 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 992 AMDGPU_RING_PRIO_DEFAULT, NULL); 993 if (r) 994 return r; 995 return 0; 996 } 997 998 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 999 int mec, int pipe, int queue) 1000 { 1001 int r; 1002 unsigned irq_type; 1003 struct amdgpu_ring *ring; 1004 unsigned int hw_prio; 1005 1006 ring = &adev->gfx.compute_ring[ring_id]; 1007 1008 /* mec0 is me1 */ 1009 ring->me = mec + 1; 1010 ring->pipe = pipe; 1011 ring->queue = queue; 1012 1013 ring->ring_obj = NULL; 1014 ring->use_doorbell = true; 1015 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1016 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1017 + (ring_id * GFX12_MEC_HPD_SIZE); 1018 ring->vm_hub = AMDGPU_GFXHUB(0); 1019 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1020 1021 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1022 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1023 + ring->pipe; 1024 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1025 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1026 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1027 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1028 hw_prio, NULL); 1029 if (r) 1030 return r; 1031 1032 return 0; 1033 } 1034 1035 static struct { 1036 SOC24_FIRMWARE_ID id; 1037 unsigned int offset; 1038 unsigned int size; 1039 unsigned int size_x16; 1040 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 1041 1042 #define RLC_TOC_OFFSET_DWUNIT 8 1043 #define RLC_SIZE_MULTIPLE 1024 1044 #define RLC_TOC_UMF_SIZE_inM 23ULL 1045 #define RLC_TOC_FORMAT_API 165ULL 1046 1047 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1048 { 1049 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 1050 1051 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 1052 rlc_autoload_info[ucode->id].id = ucode->id; 1053 rlc_autoload_info[ucode->id].offset = 1054 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 1055 rlc_autoload_info[ucode->id].size = 1056 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 1057 ucode->size * 4; 1058 ucode++; 1059 } 1060 } 1061 1062 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev) 1063 { 1064 uint32_t total_size = 0; 1065 SOC24_FIRMWARE_ID id; 1066 1067 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1068 1069 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 1070 total_size += rlc_autoload_info[id].size; 1071 1072 /* In case the offset in rlc toc ucode is aligned */ 1073 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 1074 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 1075 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 1076 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 1077 total_size = RLC_TOC_UMF_SIZE_inM << 20; 1078 1079 return total_size; 1080 } 1081 1082 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1083 { 1084 int r; 1085 uint32_t total_size; 1086 1087 total_size = gfx_v12_0_calc_toc_total_size(adev); 1088 1089 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1090 AMDGPU_GEM_DOMAIN_VRAM, 1091 &adev->gfx.rlc.rlc_autoload_bo, 1092 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1093 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1094 1095 if (r) { 1096 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1097 return r; 1098 } 1099 1100 return 0; 1101 } 1102 1103 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1104 SOC24_FIRMWARE_ID id, 1105 const void *fw_data, 1106 uint32_t fw_size) 1107 { 1108 uint32_t toc_offset; 1109 uint32_t toc_fw_size; 1110 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1111 1112 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 1113 return; 1114 1115 toc_offset = rlc_autoload_info[id].offset; 1116 toc_fw_size = rlc_autoload_info[id].size; 1117 1118 if (fw_size == 0) 1119 fw_size = toc_fw_size; 1120 1121 if (fw_size > toc_fw_size) 1122 fw_size = toc_fw_size; 1123 1124 memcpy(ptr + toc_offset, fw_data, fw_size); 1125 1126 if (fw_size < toc_fw_size) 1127 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1128 } 1129 1130 static void 1131 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1132 { 1133 void *data; 1134 uint32_t size; 1135 uint32_t *toc_ptr; 1136 1137 data = adev->psp.toc.start_addr; 1138 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 1139 1140 toc_ptr = (uint32_t *)data + size / 4 - 2; 1141 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 1142 1143 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 1144 data, size); 1145 } 1146 1147 static void 1148 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1149 { 1150 const __le32 *fw_data; 1151 uint32_t fw_size; 1152 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1153 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1154 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 1155 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1156 uint16_t version_major, version_minor; 1157 1158 /* pfp ucode */ 1159 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1160 adev->gfx.pfp_fw->data; 1161 /* instruction */ 1162 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1163 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1164 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1165 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP, 1166 fw_data, fw_size); 1167 /* data */ 1168 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1169 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1170 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1171 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK, 1172 fw_data, fw_size); 1173 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK, 1174 fw_data, fw_size); 1175 /* me ucode */ 1176 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1177 adev->gfx.me_fw->data; 1178 /* instruction */ 1179 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1180 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1181 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1182 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME, 1183 fw_data, fw_size); 1184 /* data */ 1185 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1186 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1187 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1188 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK, 1189 fw_data, fw_size); 1190 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK, 1191 fw_data, fw_size); 1192 /* mec ucode */ 1193 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1194 adev->gfx.mec_fw->data; 1195 /* instruction */ 1196 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1197 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1198 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1199 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 1200 fw_data, fw_size); 1201 /* data */ 1202 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1203 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1204 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1205 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 1206 fw_data, fw_size); 1207 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 1208 fw_data, fw_size); 1209 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 1210 fw_data, fw_size); 1211 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 1212 fw_data, fw_size); 1213 1214 /* rlc ucode */ 1215 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1216 adev->gfx.rlc_fw->data; 1217 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1218 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1219 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1220 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1221 fw_data, fw_size); 1222 1223 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1224 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1225 if (version_major == 2) { 1226 if (version_minor >= 1) { 1227 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1228 1229 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1230 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1231 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1232 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1233 fw_data, fw_size); 1234 1235 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1236 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1237 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1238 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1239 fw_data, fw_size); 1240 } 1241 if (version_minor >= 2) { 1242 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1243 1244 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1245 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1246 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1247 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1248 fw_data, fw_size); 1249 1250 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1251 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1252 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1253 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1254 fw_data, fw_size); 1255 } 1256 } 1257 } 1258 1259 static void 1260 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1261 { 1262 const __le32 *fw_data; 1263 uint32_t fw_size; 1264 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1265 1266 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1267 adev->sdma.instance[0].fw->data; 1268 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1269 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1270 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1271 1272 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1273 fw_data, fw_size); 1274 } 1275 1276 static void 1277 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1278 { 1279 const __le32 *fw_data; 1280 unsigned fw_size; 1281 const struct mes_firmware_header_v1_0 *mes_hdr; 1282 int pipe, ucode_id, data_id; 1283 1284 for (pipe = 0; pipe < 2; pipe++) { 1285 if (pipe == 0) { 1286 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1287 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1288 } else { 1289 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1290 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1291 } 1292 1293 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1294 adev->mes.fw[pipe]->data; 1295 1296 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1297 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1298 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1299 1300 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1301 1302 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1303 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1304 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1305 1306 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1307 } 1308 } 1309 1310 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1311 { 1312 uint32_t rlc_g_offset, rlc_g_size; 1313 uint64_t gpu_addr; 1314 uint32_t data; 1315 1316 /* RLC autoload sequence 2: copy ucode */ 1317 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1318 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1319 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev); 1320 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 1321 1322 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1323 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1324 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1325 1326 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1327 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1328 1329 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1330 1331 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 1332 /* RLC autoload sequence 3: load IMU fw */ 1333 if (adev->gfx.imu.funcs->load_microcode) 1334 adev->gfx.imu.funcs->load_microcode(adev); 1335 /* RLC autoload sequence 4 init IMU fw */ 1336 if (adev->gfx.imu.funcs->setup_imu) 1337 adev->gfx.imu.funcs->setup_imu(adev); 1338 if (adev->gfx.imu.funcs->start_imu) 1339 adev->gfx.imu.funcs->start_imu(adev); 1340 1341 /* RLC autoload sequence 5 disable gpa mode */ 1342 gfx_v12_0_disable_gpa_mode(adev); 1343 } else { 1344 /* unhalt rlc to start autoload without imu */ 1345 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1346 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1347 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1348 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data); 1349 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1350 } 1351 1352 return 0; 1353 } 1354 1355 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) 1356 { 1357 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 1358 uint32_t *ptr; 1359 uint32_t inst; 1360 1361 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL); 1362 if (!ptr) { 1363 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1364 adev->gfx.ip_dump_core = NULL; 1365 } else { 1366 adev->gfx.ip_dump_core = ptr; 1367 } 1368 1369 /* Allocate memory for compute queue registers for all the instances */ 1370 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 1371 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1372 adev->gfx.mec.num_queue_per_pipe; 1373 1374 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1375 if (!ptr) { 1376 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1377 adev->gfx.ip_dump_compute_queues = NULL; 1378 } else { 1379 adev->gfx.ip_dump_compute_queues = ptr; 1380 } 1381 1382 /* Allocate memory for gfx queue registers for all the instances */ 1383 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 1384 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * 1385 adev->gfx.me.num_queue_per_pipe; 1386 1387 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL); 1388 if (!ptr) { 1389 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n"); 1390 adev->gfx.ip_dump_gfx_queues = NULL; 1391 } else { 1392 adev->gfx.ip_dump_gfx_queues = ptr; 1393 } 1394 } 1395 1396 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 1397 { 1398 int i, j, k, r, ring_id = 0; 1399 unsigned num_compute_rings; 1400 int xcc_id = 0; 1401 struct amdgpu_device *adev = ip_block->adev; 1402 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */ 1403 1404 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler); 1405 1406 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1407 case IP_VERSION(12, 0, 0): 1408 case IP_VERSION(12, 0, 1): 1409 adev->gfx.me.num_me = 1; 1410 adev->gfx.me.num_pipe_per_me = 1; 1411 adev->gfx.me.num_queue_per_pipe = 8; 1412 adev->gfx.mec.num_mec = 1; 1413 adev->gfx.mec.num_pipe_per_mec = 2; 1414 adev->gfx.mec.num_queue_per_pipe = 4; 1415 break; 1416 default: 1417 adev->gfx.me.num_me = 1; 1418 adev->gfx.me.num_pipe_per_me = 1; 1419 adev->gfx.me.num_queue_per_pipe = 1; 1420 adev->gfx.mec.num_mec = 1; 1421 adev->gfx.mec.num_pipe_per_mec = 4; 1422 adev->gfx.mec.num_queue_per_pipe = 8; 1423 break; 1424 } 1425 1426 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1427 case IP_VERSION(12, 0, 0): 1428 case IP_VERSION(12, 0, 1): 1429 if (!adev->gfx.disable_uq && 1430 adev->gfx.me_fw_version >= 2780 && 1431 adev->gfx.pfp_fw_version >= 2840 && 1432 adev->gfx.mec_fw_version >= 3050 && 1433 adev->mes.fw_version[0] >= 123) { 1434 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1435 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; 1436 } 1437 break; 1438 default: 1439 break; 1440 } 1441 1442 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1443 case IP_VERSION(12, 0, 0): 1444 case IP_VERSION(12, 0, 1): 1445 if (adev->gfx.me_fw_version >= 2480 && 1446 adev->gfx.pfp_fw_version >= 2530 && 1447 adev->gfx.mec_fw_version >= 2680 && 1448 adev->mes.fw_version[0] >= 100) 1449 adev->gfx.enable_cleaner_shader = true; 1450 break; 1451 default: 1452 adev->gfx.enable_cleaner_shader = false; 1453 break; 1454 } 1455 1456 if (adev->gfx.num_compute_rings) { 1457 /* recalculate compute rings to use based on hardware configuration */ 1458 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1459 adev->gfx.mec.num_queue_per_pipe) / 2; 1460 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1461 num_compute_rings); 1462 } 1463 1464 /* EOP Event */ 1465 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1466 GFX_12_0_0__SRCID__CP_EOP_INTERRUPT, 1467 &adev->gfx.eop_irq); 1468 if (r) 1469 return r; 1470 1471 /* Bad opcode Event */ 1472 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1473 GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR, 1474 &adev->gfx.bad_op_irq); 1475 if (r) 1476 return r; 1477 1478 /* Privileged reg */ 1479 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1480 GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT, 1481 &adev->gfx.priv_reg_irq); 1482 if (r) 1483 return r; 1484 1485 /* Privileged inst */ 1486 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1487 GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1488 &adev->gfx.priv_inst_irq); 1489 if (r) 1490 return r; 1491 1492 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1493 1494 gfx_v12_0_me_init(adev); 1495 1496 r = gfx_v12_0_rlc_init(adev); 1497 if (r) { 1498 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1499 return r; 1500 } 1501 1502 r = gfx_v12_0_mec_init(adev); 1503 if (r) { 1504 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1505 return r; 1506 } 1507 1508 if (adev->gfx.num_gfx_rings) { 1509 /* set up the gfx ring */ 1510 for (i = 0; i < adev->gfx.me.num_me; i++) { 1511 for (j = 0; j < num_queue_per_pipe; j++) { 1512 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1513 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1514 continue; 1515 1516 r = gfx_v12_0_gfx_ring_init(adev, ring_id, 1517 i, k, j); 1518 if (r) 1519 return r; 1520 ring_id++; 1521 } 1522 } 1523 } 1524 } 1525 1526 if (adev->gfx.num_compute_rings) { 1527 ring_id = 0; 1528 /* set up the compute queues - allocate horizontally across pipes */ 1529 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1530 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1531 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1532 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1533 0, i, k, j)) 1534 continue; 1535 1536 r = gfx_v12_0_compute_ring_init(adev, ring_id, 1537 i, k, j); 1538 if (r) 1539 return r; 1540 1541 ring_id++; 1542 } 1543 } 1544 } 1545 } 1546 1547 adev->gfx.gfx_supported_reset = 1548 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 1549 adev->gfx.compute_supported_reset = 1550 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1551 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1552 case IP_VERSION(12, 0, 0): 1553 case IP_VERSION(12, 0, 1): 1554 if ((adev->gfx.me_fw_version >= 2660) && 1555 (adev->gfx.mec_fw_version >= 2920) && 1556 !amdgpu_sriov_vf(adev) && 1557 !adev->debug_disable_gpu_ring_reset) { 1558 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1559 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1560 } 1561 break; 1562 default: 1563 break; 1564 } 1565 1566 if (!adev->enable_mes_kiq) { 1567 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0); 1568 if (r) { 1569 dev_err(adev->dev, "Failed to init KIQ BOs!\n"); 1570 return r; 1571 } 1572 1573 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1574 if (r) 1575 return r; 1576 } 1577 1578 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0); 1579 if (r) 1580 return r; 1581 1582 /* allocate visible FB for rlc auto-loading fw */ 1583 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1584 r = gfx_v12_0_rlc_autoload_buffer_init(adev); 1585 if (r) 1586 return r; 1587 } 1588 1589 r = gfx_v12_0_gpu_early_init(adev); 1590 if (r) 1591 return r; 1592 1593 gfx_v12_0_alloc_ip_dump(adev); 1594 1595 r = amdgpu_gfx_sysfs_init(adev); 1596 if (r) 1597 return r; 1598 1599 return 0; 1600 } 1601 1602 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev) 1603 { 1604 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1605 &adev->gfx.pfp.pfp_fw_gpu_addr, 1606 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1607 1608 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1609 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1610 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1611 } 1612 1613 static void gfx_v12_0_me_fini(struct amdgpu_device *adev) 1614 { 1615 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1616 &adev->gfx.me.me_fw_gpu_addr, 1617 (void **)&adev->gfx.me.me_fw_ptr); 1618 1619 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1620 &adev->gfx.me.me_fw_data_gpu_addr, 1621 (void **)&adev->gfx.me.me_fw_data_ptr); 1622 } 1623 1624 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1625 { 1626 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1627 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1628 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1629 } 1630 1631 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 1632 { 1633 int i; 1634 struct amdgpu_device *adev = ip_block->adev; 1635 1636 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1637 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1638 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1639 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1640 1641 amdgpu_gfx_mqd_sw_fini(adev, 0); 1642 1643 if (!adev->enable_mes_kiq) { 1644 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1645 amdgpu_gfx_kiq_fini(adev, 0); 1646 } 1647 1648 gfx_v12_0_pfp_fini(adev); 1649 gfx_v12_0_me_fini(adev); 1650 gfx_v12_0_rlc_fini(adev); 1651 gfx_v12_0_mec_fini(adev); 1652 1653 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1654 gfx_v12_0_rlc_autoload_buffer_fini(adev); 1655 1656 gfx_v12_0_free_microcode(adev); 1657 1658 amdgpu_gfx_sysfs_fini(adev); 1659 1660 kfree(adev->gfx.ip_dump_core); 1661 kfree(adev->gfx.ip_dump_compute_queues); 1662 kfree(adev->gfx.ip_dump_gfx_queues); 1663 1664 return 0; 1665 } 1666 1667 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1668 u32 sh_num, u32 instance, int xcc_id) 1669 { 1670 u32 data; 1671 1672 if (instance == 0xffffffff) 1673 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1674 INSTANCE_BROADCAST_WRITES, 1); 1675 else 1676 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1677 instance); 1678 1679 if (se_num == 0xffffffff) 1680 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1681 1); 1682 else 1683 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1684 1685 if (sh_num == 0xffffffff) 1686 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1687 1); 1688 else 1689 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1690 1691 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1692 } 1693 1694 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1695 { 1696 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1697 1698 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE); 1699 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1700 GRBM_CC_GC_SA_UNIT_DISABLE, 1701 SA_DISABLE); 1702 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE); 1703 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1704 GRBM_GC_USER_SA_UNIT_DISABLE, 1705 SA_DISABLE); 1706 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1707 adev->gfx.config.max_shader_engines); 1708 1709 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1710 } 1711 1712 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1713 { 1714 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1715 u32 rb_mask; 1716 1717 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1718 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1719 CC_RB_BACKEND_DISABLE, 1720 BACKEND_DISABLE); 1721 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1722 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1723 GC_USER_RB_BACKEND_DISABLE, 1724 BACKEND_DISABLE); 1725 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1726 adev->gfx.config.max_shader_engines); 1727 1728 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1729 } 1730 1731 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev) 1732 { 1733 u32 rb_bitmap_per_sa; 1734 u32 rb_bitmap_width_per_sa; 1735 u32 max_sa; 1736 u32 active_sa_bitmap; 1737 u32 global_active_rb_bitmap; 1738 u32 active_rb_bitmap = 0; 1739 u32 i; 1740 1741 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1742 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev); 1743 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1744 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev); 1745 1746 /* generate active rb bitmap according to active sa bitmap */ 1747 max_sa = adev->gfx.config.max_shader_engines * 1748 adev->gfx.config.max_sh_per_se; 1749 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1750 adev->gfx.config.max_sh_per_se; 1751 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa); 1752 1753 for (i = 0; i < max_sa; i++) { 1754 if (active_sa_bitmap & (1 << i)) 1755 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa)); 1756 } 1757 1758 active_rb_bitmap &= global_active_rb_bitmap; 1759 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1760 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1761 } 1762 1763 #define LDS_APP_BASE 0x1 1764 #define SCRATCH_APP_BASE 0x2 1765 1766 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev) 1767 { 1768 int i; 1769 uint32_t sh_mem_bases; 1770 uint32_t data; 1771 1772 /* 1773 * Configure apertures: 1774 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1775 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1776 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1777 */ 1778 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1779 SCRATCH_APP_BASE; 1780 1781 mutex_lock(&adev->srbm_mutex); 1782 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1783 soc24_grbm_select(adev, 0, 0, 0, i); 1784 /* CP and shaders */ 1785 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1786 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1787 1788 /* Enable trap for each kfd vmid. */ 1789 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1790 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1791 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); 1792 } 1793 soc24_grbm_select(adev, 0, 0, 0, 0); 1794 mutex_unlock(&adev->srbm_mutex); 1795 } 1796 1797 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev) 1798 { 1799 /* TODO: harvest feature to be added later. */ 1800 } 1801 1802 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev) 1803 { 1804 } 1805 1806 static void gfx_v12_0_constants_init(struct amdgpu_device *adev) 1807 { 1808 u32 tmp; 1809 int i; 1810 1811 if (!amdgpu_sriov_vf(adev)) 1812 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1813 1814 gfx_v12_0_setup_rb(adev); 1815 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info); 1816 gfx_v12_0_get_tcc_info(adev); 1817 adev->gfx.config.pa_sc_tile_steering_override = 0; 1818 1819 /* XXX SH_MEM regs */ 1820 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1821 mutex_lock(&adev->srbm_mutex); 1822 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1823 soc24_grbm_select(adev, 0, 0, 0, i); 1824 /* CP and shaders */ 1825 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1826 if (i != 0) { 1827 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1828 (adev->gmc.private_aperture_start >> 48)); 1829 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1830 (adev->gmc.shared_aperture_start >> 48)); 1831 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1832 } 1833 } 1834 soc24_grbm_select(adev, 0, 0, 0, 0); 1835 1836 mutex_unlock(&adev->srbm_mutex); 1837 1838 gfx_v12_0_init_compute_vmid(adev); 1839 } 1840 1841 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev, 1842 int me, int pipe) 1843 { 1844 if (me != 0) 1845 return 0; 1846 1847 switch (pipe) { 1848 case 0: 1849 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 1850 default: 1851 return 0; 1852 } 1853 } 1854 1855 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev, 1856 int me, int pipe) 1857 { 1858 /* 1859 * amdgpu controls only the first MEC. That's why this function only 1860 * handles the setting of interrupts for this specific MEC. All other 1861 * pipes' interrupts are set by amdkfd. 1862 */ 1863 if (me != 1) 1864 return 0; 1865 1866 switch (pipe) { 1867 case 0: 1868 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 1869 case 1: 1870 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 1871 default: 1872 return 0; 1873 } 1874 } 1875 1876 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1877 bool enable) 1878 { 1879 u32 tmp, cp_int_cntl_reg; 1880 int i, j; 1881 1882 if (amdgpu_sriov_vf(adev)) 1883 return; 1884 1885 for (i = 0; i < adev->gfx.me.num_me; i++) { 1886 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 1887 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 1888 1889 if (cp_int_cntl_reg) { 1890 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 1891 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1892 enable ? 1 : 0); 1893 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1894 enable ? 1 : 0); 1895 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1896 enable ? 1 : 0); 1897 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1898 enable ? 1 : 0); 1899 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); 1900 } 1901 } 1902 } 1903 } 1904 1905 static int gfx_v12_0_init_csb(struct amdgpu_device *adev) 1906 { 1907 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1908 1909 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1910 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1911 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1912 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1913 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1914 1915 return 0; 1916 } 1917 1918 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev) 1919 { 1920 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1921 1922 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1923 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1924 } 1925 1926 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev) 1927 { 1928 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1929 udelay(50); 1930 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1931 udelay(50); 1932 } 1933 1934 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1935 bool enable) 1936 { 1937 uint32_t rlc_pg_cntl; 1938 1939 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1940 1941 if (!enable) { 1942 /* RLC_PG_CNTL[23] = 0 (default) 1943 * RLC will wait for handshake acks with SMU 1944 * GFXOFF will be enabled 1945 * RLC_PG_CNTL[23] = 1 1946 * RLC will not issue any message to SMU 1947 * hence no handshake between SMU & RLC 1948 * GFXOFF will be disabled 1949 */ 1950 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1951 } else 1952 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1953 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1954 } 1955 1956 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev) 1957 { 1958 /* TODO: enable rlc & smu handshake until smu 1959 * and gfxoff feature works as expected */ 1960 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1961 gfx_v12_0_rlc_smu_handshake_cntl(adev, false); 1962 1963 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1964 udelay(50); 1965 } 1966 1967 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev) 1968 { 1969 uint32_t tmp; 1970 1971 /* enable Save Restore Machine */ 1972 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1973 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1974 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1975 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1976 } 1977 1978 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev) 1979 { 1980 const struct rlc_firmware_header_v2_0 *hdr; 1981 const __le32 *fw_data; 1982 unsigned i, fw_size; 1983 1984 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1985 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1986 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1987 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1988 1989 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1990 RLCG_UCODE_LOADING_START_ADDRESS); 1991 1992 for (i = 0; i < fw_size; i++) 1993 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1994 le32_to_cpup(fw_data++)); 1995 1996 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1997 } 1998 1999 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2000 { 2001 const struct rlc_firmware_header_v2_2 *hdr; 2002 const __le32 *fw_data; 2003 unsigned i, fw_size; 2004 u32 tmp; 2005 2006 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2007 2008 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2009 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2010 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2011 2012 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2013 2014 for (i = 0; i < fw_size; i++) { 2015 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2016 msleep(1); 2017 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2018 le32_to_cpup(fw_data++)); 2019 } 2020 2021 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2022 2023 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2024 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2025 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2026 2027 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2028 for (i = 0; i < fw_size; i++) { 2029 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2030 msleep(1); 2031 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2032 le32_to_cpup(fw_data++)); 2033 } 2034 2035 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2036 2037 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2038 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2039 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2040 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2041 } 2042 2043 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev) 2044 { 2045 const struct rlc_firmware_header_v2_0 *hdr; 2046 uint16_t version_major; 2047 uint16_t version_minor; 2048 2049 if (!adev->gfx.rlc_fw) 2050 return -EINVAL; 2051 2052 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2053 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2054 2055 version_major = le16_to_cpu(hdr->header.header_version_major); 2056 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2057 2058 if (version_major == 2) { 2059 gfx_v12_0_load_rlcg_microcode(adev); 2060 if (amdgpu_dpm == 1) { 2061 if (version_minor >= 2) 2062 gfx_v12_0_load_rlc_iram_dram_microcode(adev); 2063 } 2064 2065 return 0; 2066 } 2067 2068 return -EINVAL; 2069 } 2070 2071 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev) 2072 { 2073 int r; 2074 2075 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2076 gfx_v12_0_init_csb(adev); 2077 2078 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2079 gfx_v12_0_rlc_enable_srm(adev); 2080 } else { 2081 if (amdgpu_sriov_vf(adev)) { 2082 gfx_v12_0_init_csb(adev); 2083 return 0; 2084 } 2085 2086 adev->gfx.rlc.funcs->stop(adev); 2087 2088 /* disable CG */ 2089 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2090 2091 /* disable PG */ 2092 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2093 2094 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2095 /* legacy rlc firmware loading */ 2096 r = gfx_v12_0_rlc_load_microcode(adev); 2097 if (r) 2098 return r; 2099 } 2100 2101 gfx_v12_0_init_csb(adev); 2102 2103 adev->gfx.rlc.funcs->start(adev); 2104 } 2105 2106 return 0; 2107 } 2108 2109 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev) 2110 { 2111 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2112 const struct gfx_firmware_header_v2_0 *me_hdr; 2113 const struct gfx_firmware_header_v2_0 *mec_hdr; 2114 uint32_t pipe_id, tmp; 2115 2116 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2117 adev->gfx.mec_fw->data; 2118 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2119 adev->gfx.me_fw->data; 2120 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2121 adev->gfx.pfp_fw->data; 2122 2123 /* config pfp program start addr */ 2124 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2125 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2126 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2127 (pfp_hdr->ucode_start_addr_hi << 30) | 2128 (pfp_hdr->ucode_start_addr_lo >> 2)); 2129 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2130 pfp_hdr->ucode_start_addr_hi >> 2); 2131 } 2132 soc24_grbm_select(adev, 0, 0, 0, 0); 2133 2134 /* reset pfp pipe */ 2135 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2136 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2137 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2138 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2139 2140 /* clear pfp pipe reset */ 2141 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2142 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2143 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2144 2145 /* config me program start addr */ 2146 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2147 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2148 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2149 (me_hdr->ucode_start_addr_hi << 30) | 2150 (me_hdr->ucode_start_addr_lo >> 2)); 2151 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2152 me_hdr->ucode_start_addr_hi>>2); 2153 } 2154 soc24_grbm_select(adev, 0, 0, 0, 0); 2155 2156 /* reset me pipe */ 2157 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2158 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2159 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2160 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2161 2162 /* clear me pipe reset */ 2163 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2164 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2165 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2166 2167 /* config mec program start addr */ 2168 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2169 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2170 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2171 mec_hdr->ucode_start_addr_lo >> 2 | 2172 mec_hdr->ucode_start_addr_hi << 30); 2173 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2174 mec_hdr->ucode_start_addr_hi >> 2); 2175 } 2176 soc24_grbm_select(adev, 0, 0, 0, 0); 2177 2178 /* reset mec pipe */ 2179 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2180 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2181 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2182 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2183 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2184 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2185 2186 /* clear mec pipe reset */ 2187 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2188 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2189 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2190 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2191 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2192 } 2193 2194 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev) 2195 { 2196 const struct gfx_firmware_header_v2_0 *cp_hdr; 2197 unsigned pipe_id, tmp; 2198 2199 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2200 adev->gfx.pfp_fw->data; 2201 mutex_lock(&adev->srbm_mutex); 2202 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2203 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2204 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2205 (cp_hdr->ucode_start_addr_hi << 30) | 2206 (cp_hdr->ucode_start_addr_lo >> 2)); 2207 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2208 cp_hdr->ucode_start_addr_hi>>2); 2209 2210 /* 2211 * Program CP_ME_CNTL to reset given PIPE to take 2212 * effect of CP_PFP_PRGRM_CNTR_START. 2213 */ 2214 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2215 if (pipe_id == 0) 2216 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2217 PFP_PIPE0_RESET, 1); 2218 else 2219 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2220 PFP_PIPE1_RESET, 1); 2221 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2222 2223 /* Clear pfp pipe0 reset bit. */ 2224 if (pipe_id == 0) 2225 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2226 PFP_PIPE0_RESET, 0); 2227 else 2228 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2229 PFP_PIPE1_RESET, 0); 2230 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2231 } 2232 soc24_grbm_select(adev, 0, 0, 0, 0); 2233 mutex_unlock(&adev->srbm_mutex); 2234 } 2235 2236 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev) 2237 { 2238 const struct gfx_firmware_header_v2_0 *cp_hdr; 2239 unsigned pipe_id, tmp; 2240 2241 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2242 adev->gfx.me_fw->data; 2243 mutex_lock(&adev->srbm_mutex); 2244 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2245 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2246 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2247 (cp_hdr->ucode_start_addr_hi << 30) | 2248 (cp_hdr->ucode_start_addr_lo >> 2) ); 2249 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2250 cp_hdr->ucode_start_addr_hi>>2); 2251 2252 /* 2253 * Program CP_ME_CNTL to reset given PIPE to take 2254 * effect of CP_ME_PRGRM_CNTR_START. 2255 */ 2256 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2257 if (pipe_id == 0) 2258 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2259 ME_PIPE0_RESET, 1); 2260 else 2261 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2262 ME_PIPE1_RESET, 1); 2263 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2264 2265 /* Clear pfp pipe0 reset bit. */ 2266 if (pipe_id == 0) 2267 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2268 ME_PIPE0_RESET, 0); 2269 else 2270 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2271 ME_PIPE1_RESET, 0); 2272 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2273 } 2274 soc24_grbm_select(adev, 0, 0, 0, 0); 2275 mutex_unlock(&adev->srbm_mutex); 2276 } 2277 2278 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev) 2279 { 2280 const struct gfx_firmware_header_v2_0 *cp_hdr; 2281 unsigned pipe_id; 2282 2283 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 2284 adev->gfx.mec_fw->data; 2285 mutex_lock(&adev->srbm_mutex); 2286 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 2287 soc24_grbm_select(adev, 1, pipe_id, 0, 0); 2288 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2289 cp_hdr->ucode_start_addr_lo >> 2 | 2290 cp_hdr->ucode_start_addr_hi << 30); 2291 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2292 cp_hdr->ucode_start_addr_hi >> 2); 2293 } 2294 soc24_grbm_select(adev, 0, 0, 0, 0); 2295 mutex_unlock(&adev->srbm_mutex); 2296 } 2297 2298 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2299 { 2300 uint32_t cp_status; 2301 uint32_t bootload_status; 2302 int i; 2303 2304 for (i = 0; i < adev->usec_timeout; i++) { 2305 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2306 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2307 2308 if ((cp_status == 0) && 2309 (REG_GET_FIELD(bootload_status, 2310 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2311 break; 2312 } 2313 udelay(1); 2314 if (amdgpu_emu_mode) 2315 msleep(10); 2316 } 2317 2318 if (i >= adev->usec_timeout) { 2319 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2320 return -ETIMEDOUT; 2321 } 2322 2323 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2324 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2325 gfx_v12_0_set_me_ucode_start_addr(adev); 2326 gfx_v12_0_set_mec_ucode_start_addr(adev); 2327 } 2328 2329 return 0; 2330 } 2331 2332 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2333 { 2334 int i; 2335 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2336 2337 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2338 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2339 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2340 2341 for (i = 0; i < adev->usec_timeout; i++) { 2342 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2343 break; 2344 udelay(1); 2345 } 2346 2347 if (i >= adev->usec_timeout) 2348 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2349 2350 return 0; 2351 } 2352 2353 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2354 { 2355 int r; 2356 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2357 const __le32 *fw_ucode, *fw_data; 2358 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2359 uint32_t tmp; 2360 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2361 2362 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2363 adev->gfx.pfp_fw->data; 2364 2365 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2366 2367 /* instruction */ 2368 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2369 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2370 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2371 /* data */ 2372 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2373 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2374 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2375 2376 /* 64kb align */ 2377 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2378 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2379 &adev->gfx.pfp.pfp_fw_obj, 2380 &adev->gfx.pfp.pfp_fw_gpu_addr, 2381 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2382 if (r) { 2383 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2384 gfx_v12_0_pfp_fini(adev); 2385 return r; 2386 } 2387 2388 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2389 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2390 &adev->gfx.pfp.pfp_fw_data_obj, 2391 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2392 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2393 if (r) { 2394 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2395 gfx_v12_0_pfp_fini(adev); 2396 return r; 2397 } 2398 2399 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2400 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2401 2402 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2403 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2404 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2405 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2406 2407 if (amdgpu_emu_mode == 1) 2408 amdgpu_device_flush_hdp(adev, NULL); 2409 2410 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2411 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2412 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2413 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2414 2415 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2416 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2417 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2418 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2419 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2420 2421 /* 2422 * Programming any of the CP_PFP_IC_BASE registers 2423 * forces invalidation of the ME L1 I$. Wait for the 2424 * invalidation complete 2425 */ 2426 for (i = 0; i < usec_timeout; i++) { 2427 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2428 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2429 INVALIDATE_CACHE_COMPLETE)) 2430 break; 2431 udelay(1); 2432 } 2433 2434 if (i >= usec_timeout) { 2435 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2436 return -EINVAL; 2437 } 2438 2439 /* Prime the L1 instruction caches */ 2440 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2441 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2442 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2443 /* Waiting for cache primed*/ 2444 for (i = 0; i < usec_timeout; i++) { 2445 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2446 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2447 ICACHE_PRIMED)) 2448 break; 2449 udelay(1); 2450 } 2451 2452 if (i >= usec_timeout) { 2453 dev_err(adev->dev, "failed to prime instruction cache\n"); 2454 return -EINVAL; 2455 } 2456 2457 mutex_lock(&adev->srbm_mutex); 2458 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2459 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2460 2461 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2462 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2463 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2464 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2465 } 2466 soc24_grbm_select(adev, 0, 0, 0, 0); 2467 mutex_unlock(&adev->srbm_mutex); 2468 2469 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2470 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2471 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2472 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2473 2474 /* Invalidate the data caches */ 2475 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2476 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2477 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2478 2479 for (i = 0; i < usec_timeout; i++) { 2480 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2481 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2482 INVALIDATE_DCACHE_COMPLETE)) 2483 break; 2484 udelay(1); 2485 } 2486 2487 if (i >= usec_timeout) { 2488 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2489 return -EINVAL; 2490 } 2491 2492 gfx_v12_0_set_pfp_ucode_start_addr(adev); 2493 2494 return 0; 2495 } 2496 2497 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2498 { 2499 int r; 2500 const struct gfx_firmware_header_v2_0 *me_hdr; 2501 const __le32 *fw_ucode, *fw_data; 2502 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2503 uint32_t tmp; 2504 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2505 2506 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2507 adev->gfx.me_fw->data; 2508 2509 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2510 2511 /* instruction */ 2512 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2513 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2514 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2515 /* data */ 2516 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2517 le32_to_cpu(me_hdr->data_offset_bytes)); 2518 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2519 2520 /* 64kb align*/ 2521 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2522 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2523 &adev->gfx.me.me_fw_obj, 2524 &adev->gfx.me.me_fw_gpu_addr, 2525 (void **)&adev->gfx.me.me_fw_ptr); 2526 if (r) { 2527 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2528 gfx_v12_0_me_fini(adev); 2529 return r; 2530 } 2531 2532 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2533 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2534 &adev->gfx.me.me_fw_data_obj, 2535 &adev->gfx.me.me_fw_data_gpu_addr, 2536 (void **)&adev->gfx.me.me_fw_data_ptr); 2537 if (r) { 2538 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2539 gfx_v12_0_me_fini(adev); 2540 return r; 2541 } 2542 2543 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2544 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2545 2546 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2547 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2548 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2549 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2550 2551 if (amdgpu_emu_mode == 1) 2552 amdgpu_device_flush_hdp(adev, NULL); 2553 2554 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2555 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2556 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2557 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2558 2559 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2560 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2561 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2562 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2563 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2564 2565 /* 2566 * Programming any of the CP_ME_IC_BASE registers 2567 * forces invalidation of the ME L1 I$. Wait for the 2568 * invalidation complete 2569 */ 2570 for (i = 0; i < usec_timeout; i++) { 2571 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2572 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2573 INVALIDATE_CACHE_COMPLETE)) 2574 break; 2575 udelay(1); 2576 } 2577 2578 if (i >= usec_timeout) { 2579 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2580 return -EINVAL; 2581 } 2582 2583 /* Prime the instruction caches */ 2584 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2585 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2586 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2587 2588 /* Waiting for instruction cache primed*/ 2589 for (i = 0; i < usec_timeout; i++) { 2590 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2591 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2592 ICACHE_PRIMED)) 2593 break; 2594 udelay(1); 2595 } 2596 2597 if (i >= usec_timeout) { 2598 dev_err(adev->dev, "failed to prime instruction cache\n"); 2599 return -EINVAL; 2600 } 2601 2602 mutex_lock(&adev->srbm_mutex); 2603 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2604 soc24_grbm_select(adev, 0, pipe_id, 0, 0); 2605 2606 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2607 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2608 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2609 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2610 } 2611 soc24_grbm_select(adev, 0, 0, 0, 0); 2612 mutex_unlock(&adev->srbm_mutex); 2613 2614 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2615 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2616 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2617 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2618 2619 /* Invalidate the data caches */ 2620 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2621 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2622 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2623 2624 for (i = 0; i < usec_timeout; i++) { 2625 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2626 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2627 INVALIDATE_DCACHE_COMPLETE)) 2628 break; 2629 udelay(1); 2630 } 2631 2632 if (i >= usec_timeout) { 2633 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2634 return -EINVAL; 2635 } 2636 2637 gfx_v12_0_set_me_ucode_start_addr(adev); 2638 2639 return 0; 2640 } 2641 2642 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2643 { 2644 int r; 2645 2646 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 2647 return -EINVAL; 2648 2649 gfx_v12_0_cp_gfx_enable(adev, false); 2650 2651 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev); 2652 if (r) { 2653 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2654 return r; 2655 } 2656 2657 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev); 2658 if (r) { 2659 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2660 return r; 2661 } 2662 2663 return 0; 2664 } 2665 2666 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev) 2667 { 2668 /* init the CP */ 2669 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 2670 adev->gfx.config.max_hw_contexts - 1); 2671 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 2672 2673 if (!amdgpu_async_gfx_ring) 2674 gfx_v12_0_cp_gfx_enable(adev, true); 2675 2676 return 0; 2677 } 2678 2679 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2680 CP_PIPE_ID pipe) 2681 { 2682 u32 tmp; 2683 2684 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 2685 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2686 2687 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 2688 } 2689 2690 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2691 struct amdgpu_ring *ring) 2692 { 2693 u32 tmp; 2694 2695 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 2696 if (ring->use_doorbell) { 2697 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2698 DOORBELL_OFFSET, ring->doorbell_index); 2699 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2700 DOORBELL_EN, 1); 2701 } else { 2702 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2703 DOORBELL_EN, 0); 2704 } 2705 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 2706 2707 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2708 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2709 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 2710 2711 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2712 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2713 } 2714 2715 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev) 2716 { 2717 struct amdgpu_ring *ring; 2718 u32 tmp; 2719 u32 rb_bufsz; 2720 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2721 2722 /* Set the write pointer delay */ 2723 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 2724 2725 /* set the RB to use vmid 0 */ 2726 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 2727 2728 /* Init gfx ring 0 for pipe 0 */ 2729 mutex_lock(&adev->srbm_mutex); 2730 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2731 2732 /* Set ring buffer size */ 2733 ring = &adev->gfx.gfx_ring[0]; 2734 rb_bufsz = order_base_2(ring->ring_size / 8); 2735 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2736 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2737 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2738 2739 /* Initialize the ring buffer's write pointers */ 2740 ring->wptr = 0; 2741 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2742 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2743 2744 /* set the wb address whether it's enabled or not */ 2745 rptr_addr = ring->rptr_gpu_addr; 2746 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2747 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2748 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2749 2750 wptr_gpu_addr = ring->wptr_gpu_addr; 2751 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 2752 lower_32_bits(wptr_gpu_addr)); 2753 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 2754 upper_32_bits(wptr_gpu_addr)); 2755 2756 mdelay(1); 2757 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 2758 2759 rb_addr = ring->gpu_addr >> 8; 2760 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 2761 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2762 2763 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 2764 2765 gfx_v12_0_cp_gfx_set_doorbell(adev, ring); 2766 mutex_unlock(&adev->srbm_mutex); 2767 2768 /* Switch to pipe 0 */ 2769 mutex_lock(&adev->srbm_mutex); 2770 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2771 mutex_unlock(&adev->srbm_mutex); 2772 2773 /* start the ring */ 2774 gfx_v12_0_cp_gfx_start(adev); 2775 return 0; 2776 } 2777 2778 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2779 { 2780 u32 data; 2781 2782 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2783 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2784 enable ? 0 : 1); 2785 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2786 enable ? 0 : 1); 2787 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2788 enable ? 0 : 1); 2789 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2790 enable ? 0 : 1); 2791 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2792 enable ? 0 : 1); 2793 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2794 enable ? 1 : 0); 2795 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2796 enable ? 1 : 0); 2797 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2798 enable ? 1 : 0); 2799 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2800 enable ? 1 : 0); 2801 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2802 enable ? 0 : 1); 2803 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 2804 2805 adev->gfx.kiq[0].ring.sched.ready = enable; 2806 2807 udelay(50); 2808 } 2809 2810 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 2811 { 2812 const struct gfx_firmware_header_v2_0 *mec_hdr; 2813 const __le32 *fw_ucode, *fw_data; 2814 u32 tmp, fw_ucode_size, fw_data_size; 2815 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 2816 u32 *fw_ucode_ptr, *fw_data_ptr; 2817 int r; 2818 2819 if (!adev->gfx.mec_fw) 2820 return -EINVAL; 2821 2822 gfx_v12_0_cp_compute_enable(adev, false); 2823 2824 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2825 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2826 2827 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2828 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2829 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2830 2831 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2832 le32_to_cpu(mec_hdr->data_offset_bytes)); 2833 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2834 2835 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2836 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2837 &adev->gfx.mec.mec_fw_obj, 2838 &adev->gfx.mec.mec_fw_gpu_addr, 2839 (void **)&fw_ucode_ptr); 2840 if (r) { 2841 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2842 gfx_v12_0_mec_fini(adev); 2843 return r; 2844 } 2845 2846 r = amdgpu_bo_create_reserved(adev, 2847 ALIGN(fw_data_size, 64 * 1024) * 2848 adev->gfx.mec.num_pipe_per_mec, 2849 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2850 &adev->gfx.mec.mec_fw_data_obj, 2851 &adev->gfx.mec.mec_fw_data_gpu_addr, 2852 (void **)&fw_data_ptr); 2853 if (r) { 2854 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2855 gfx_v12_0_mec_fini(adev); 2856 return r; 2857 } 2858 2859 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2860 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2861 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size); 2862 } 2863 2864 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2865 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2866 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2867 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2868 2869 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2870 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2871 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2872 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2873 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2874 2875 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2876 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2877 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2878 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2879 2880 mutex_lock(&adev->srbm_mutex); 2881 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2882 soc24_grbm_select(adev, 1, i, 0, 0); 2883 2884 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, 2885 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2886 i * ALIGN(fw_data_size, 64 * 1024))); 2887 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2888 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2889 i * ALIGN(fw_data_size, 64 * 1024))); 2890 2891 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2892 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2893 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2894 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2895 } 2896 mutex_unlock(&adev->srbm_mutex); 2897 soc24_grbm_select(adev, 0, 0, 0, 0); 2898 2899 /* Trigger an invalidation of the L1 instruction caches */ 2900 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2901 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2902 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2903 2904 /* Wait for invalidation complete */ 2905 for (i = 0; i < usec_timeout; i++) { 2906 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2907 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2908 INVALIDATE_DCACHE_COMPLETE)) 2909 break; 2910 udelay(1); 2911 } 2912 2913 if (i >= usec_timeout) { 2914 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2915 return -EINVAL; 2916 } 2917 2918 /* Trigger an invalidation of the L1 instruction caches */ 2919 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2920 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2921 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2922 2923 /* Wait for invalidation complete */ 2924 for (i = 0; i < usec_timeout; i++) { 2925 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2926 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2927 INVALIDATE_CACHE_COMPLETE)) 2928 break; 2929 udelay(1); 2930 } 2931 2932 if (i >= usec_timeout) { 2933 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2934 return -EINVAL; 2935 } 2936 2937 gfx_v12_0_set_mec_ucode_start_addr(adev); 2938 2939 return 0; 2940 } 2941 2942 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring) 2943 { 2944 uint32_t tmp; 2945 struct amdgpu_device *adev = ring->adev; 2946 2947 /* tell RLC which is KIQ queue */ 2948 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 2949 tmp &= 0xffffff00; 2950 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2951 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 2952 } 2953 2954 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev) 2955 { 2956 /* set graphics engine doorbell range */ 2957 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 2958 (adev->doorbell_index.gfx_ring0 * 2) << 2); 2959 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 2960 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 2961 2962 /* set compute engine doorbell range */ 2963 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 2964 (adev->doorbell_index.kiq * 2) << 2); 2965 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 2966 (adev->doorbell_index.userqueue_end * 2) << 2); 2967 } 2968 2969 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 2970 struct amdgpu_mqd_prop *prop) 2971 { 2972 struct v12_gfx_mqd *mqd = m; 2973 uint64_t hqd_gpu_addr, wb_gpu_addr; 2974 uint32_t tmp; 2975 uint32_t rb_bufsz; 2976 2977 /* set up gfx hqd wptr */ 2978 mqd->cp_gfx_hqd_wptr = 0; 2979 mqd->cp_gfx_hqd_wptr_hi = 0; 2980 2981 /* set the pointer to the MQD */ 2982 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 2983 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2984 2985 /* set up mqd control */ 2986 tmp = regCP_GFX_MQD_CONTROL_DEFAULT; 2987 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2988 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2989 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2990 mqd->cp_gfx_mqd_control = tmp; 2991 2992 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2993 tmp = regCP_GFX_HQD_VMID_DEFAULT; 2994 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2995 mqd->cp_gfx_hqd_vmid = 0; 2996 2997 /* set up default queue priority level 2998 * 0x0 = low priority, 0x1 = high priority */ 2999 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; 3000 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3001 mqd->cp_gfx_hqd_queue_priority = tmp; 3002 3003 /* set up time quantum */ 3004 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT; 3005 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3006 mqd->cp_gfx_hqd_quantum = tmp; 3007 3008 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3009 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3010 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3011 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3012 3013 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3014 wb_gpu_addr = prop->rptr_gpu_addr; 3015 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3016 mqd->cp_gfx_hqd_rptr_addr_hi = 3017 upper_32_bits(wb_gpu_addr) & 0xffff; 3018 3019 /* set up rb_wptr_poll addr */ 3020 wb_gpu_addr = prop->wptr_gpu_addr; 3021 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3022 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3023 3024 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3025 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3026 tmp = regCP_GFX_HQD_CNTL_DEFAULT; 3027 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3028 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3029 #ifdef __BIG_ENDIAN 3030 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3031 #endif 3032 if (prop->tmz_queue) 3033 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 3034 if (!prop->kernel_queue) 3035 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); 3036 mqd->cp_gfx_hqd_cntl = tmp; 3037 3038 /* set up cp_doorbell_control */ 3039 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT; 3040 if (prop->use_doorbell) { 3041 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3042 DOORBELL_OFFSET, prop->doorbell_index); 3043 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3044 DOORBELL_EN, 1); 3045 } else 3046 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3047 DOORBELL_EN, 0); 3048 mqd->cp_rb_doorbell_control = tmp; 3049 3050 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3051 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT; 3052 3053 /* active the queue */ 3054 mqd->cp_gfx_hqd_active = 1; 3055 3056 /* set gfx UQ items */ 3057 mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr); 3058 mqd->shadow_base_hi = upper_32_bits(prop->shadow_addr); 3059 mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr); 3060 mqd->fw_work_area_base_hi = upper_32_bits(prop->csa_addr); 3061 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3062 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3063 3064 return 0; 3065 } 3066 3067 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) 3068 { 3069 struct amdgpu_device *adev = ring->adev; 3070 struct v12_gfx_mqd *mqd = ring->mqd_ptr; 3071 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3072 3073 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3074 memset((void *)mqd, 0, sizeof(*mqd)); 3075 mutex_lock(&adev->srbm_mutex); 3076 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3077 amdgpu_ring_init_mqd(ring); 3078 soc24_grbm_select(adev, 0, 0, 0, 0); 3079 mutex_unlock(&adev->srbm_mutex); 3080 if (adev->gfx.me.mqd_backup[mqd_idx]) 3081 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3082 } else { 3083 /* restore mqd with the backup copy */ 3084 if (adev->gfx.me.mqd_backup[mqd_idx]) 3085 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3086 /* reset the ring */ 3087 ring->wptr = 0; 3088 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3089 amdgpu_ring_clear_ring(ring); 3090 } 3091 3092 return 0; 3093 } 3094 3095 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3096 { 3097 int i, r; 3098 3099 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3100 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false); 3101 if (r) 3102 return r; 3103 } 3104 3105 r = amdgpu_gfx_enable_kgq(adev, 0); 3106 if (r) 3107 return r; 3108 3109 return gfx_v12_0_cp_gfx_start(adev); 3110 } 3111 3112 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3113 struct amdgpu_mqd_prop *prop) 3114 { 3115 struct v12_compute_mqd *mqd = m; 3116 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3117 uint32_t tmp; 3118 3119 mqd->header = 0xC0310800; 3120 mqd->compute_pipelinestat_enable = 0x00000001; 3121 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3122 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3123 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3124 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3125 mqd->compute_misc_reserved = 0x00000007; 3126 3127 eop_base_addr = prop->eop_gpu_addr >> 8; 3128 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3129 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3130 3131 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3132 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 3133 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3134 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 3135 3136 mqd->cp_hqd_eop_control = tmp; 3137 3138 /* enable doorbell? */ 3139 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3140 3141 if (prop->use_doorbell) { 3142 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3143 DOORBELL_OFFSET, prop->doorbell_index); 3144 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3145 DOORBELL_EN, 1); 3146 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3147 DOORBELL_SOURCE, 0); 3148 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3149 DOORBELL_HIT, 0); 3150 } else { 3151 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3152 DOORBELL_EN, 0); 3153 } 3154 3155 mqd->cp_hqd_pq_doorbell_control = tmp; 3156 3157 /* disable the queue if it's active */ 3158 mqd->cp_hqd_dequeue_request = 0; 3159 mqd->cp_hqd_pq_rptr = 0; 3160 mqd->cp_hqd_pq_wptr_lo = 0; 3161 mqd->cp_hqd_pq_wptr_hi = 0; 3162 3163 /* set the pointer to the MQD */ 3164 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3165 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3166 3167 /* set MQD vmid to 0 */ 3168 tmp = regCP_MQD_CONTROL_DEFAULT; 3169 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3170 mqd->cp_mqd_control = tmp; 3171 3172 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3173 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3174 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3175 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3176 3177 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3178 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 3179 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3180 (order_base_2(prop->queue_size / 4) - 1)); 3181 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3182 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3183 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3184 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3185 if (prop->kernel_queue) { 3186 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3187 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3188 } 3189 if (prop->tmz_queue) 3190 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 3191 mqd->cp_hqd_pq_control = tmp; 3192 3193 /* set the wb address whether it's enabled or not */ 3194 wb_gpu_addr = prop->rptr_gpu_addr; 3195 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3196 mqd->cp_hqd_pq_rptr_report_addr_hi = 3197 upper_32_bits(wb_gpu_addr) & 0xffff; 3198 3199 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3200 wb_gpu_addr = prop->wptr_gpu_addr; 3201 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3202 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3203 3204 tmp = 0; 3205 /* enable the doorbell if requested */ 3206 if (prop->use_doorbell) { 3207 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 3208 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3209 DOORBELL_OFFSET, prop->doorbell_index); 3210 3211 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3212 DOORBELL_EN, 1); 3213 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3214 DOORBELL_SOURCE, 0); 3215 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3216 DOORBELL_HIT, 0); 3217 } 3218 3219 mqd->cp_hqd_pq_doorbell_control = tmp; 3220 3221 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3222 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 3223 3224 /* set the vmid for the queue */ 3225 mqd->cp_hqd_vmid = 0; 3226 3227 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 3228 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3229 mqd->cp_hqd_persistent_state = tmp; 3230 3231 /* set MIN_IB_AVAIL_SIZE */ 3232 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 3233 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3234 mqd->cp_hqd_ib_control = tmp; 3235 3236 /* set static priority for a compute queue/ring */ 3237 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3238 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3239 3240 mqd->cp_hqd_active = prop->hqd_active; 3241 3242 /* set UQ fenceaddress */ 3243 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3244 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3245 3246 return 0; 3247 } 3248 3249 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring) 3250 { 3251 struct amdgpu_device *adev = ring->adev; 3252 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3253 int j; 3254 3255 /* inactivate the queue */ 3256 if (amdgpu_sriov_vf(adev)) 3257 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3258 3259 /* disable wptr polling */ 3260 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3261 3262 /* write the EOP addr */ 3263 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3264 mqd->cp_hqd_eop_base_addr_lo); 3265 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3266 mqd->cp_hqd_eop_base_addr_hi); 3267 3268 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3269 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3270 mqd->cp_hqd_eop_control); 3271 3272 /* enable doorbell? */ 3273 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3274 mqd->cp_hqd_pq_doorbell_control); 3275 3276 /* disable the queue if it's active */ 3277 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3278 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3279 for (j = 0; j < adev->usec_timeout; j++) { 3280 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3281 break; 3282 udelay(1); 3283 } 3284 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3285 mqd->cp_hqd_dequeue_request); 3286 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3287 mqd->cp_hqd_pq_rptr); 3288 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3289 mqd->cp_hqd_pq_wptr_lo); 3290 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3291 mqd->cp_hqd_pq_wptr_hi); 3292 } 3293 3294 /* set the pointer to the MQD */ 3295 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3296 mqd->cp_mqd_base_addr_lo); 3297 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3298 mqd->cp_mqd_base_addr_hi); 3299 3300 /* set MQD vmid to 0 */ 3301 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3302 mqd->cp_mqd_control); 3303 3304 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3305 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3306 mqd->cp_hqd_pq_base_lo); 3307 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3308 mqd->cp_hqd_pq_base_hi); 3309 3310 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3311 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3312 mqd->cp_hqd_pq_control); 3313 3314 /* set the wb address whether it's enabled or not */ 3315 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3316 mqd->cp_hqd_pq_rptr_report_addr_lo); 3317 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3318 mqd->cp_hqd_pq_rptr_report_addr_hi); 3319 3320 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3321 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3322 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3323 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3324 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3325 3326 /* enable the doorbell if requested */ 3327 if (ring->use_doorbell) { 3328 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3329 (adev->doorbell_index.kiq * 2) << 2); 3330 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3331 (adev->doorbell_index.userqueue_end * 2) << 2); 3332 } 3333 3334 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3335 mqd->cp_hqd_pq_doorbell_control); 3336 3337 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3338 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3339 mqd->cp_hqd_pq_wptr_lo); 3340 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3341 mqd->cp_hqd_pq_wptr_hi); 3342 3343 /* set the vmid for the queue */ 3344 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3345 3346 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3347 mqd->cp_hqd_persistent_state); 3348 3349 /* activate the queue */ 3350 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3351 mqd->cp_hqd_active); 3352 3353 if (ring->use_doorbell) 3354 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3355 3356 return 0; 3357 } 3358 3359 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) 3360 { 3361 struct amdgpu_device *adev = ring->adev; 3362 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3363 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3364 3365 gfx_v12_0_kiq_setting(ring); 3366 3367 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3368 /* reset MQD to a clean status */ 3369 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3370 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3371 3372 /* reset ring buffer */ 3373 ring->wptr = 0; 3374 amdgpu_ring_clear_ring(ring); 3375 3376 mutex_lock(&adev->srbm_mutex); 3377 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3378 gfx_v12_0_kiq_init_register(ring); 3379 soc24_grbm_select(adev, 0, 0, 0, 0); 3380 mutex_unlock(&adev->srbm_mutex); 3381 } else { 3382 memset((void *)mqd, 0, sizeof(*mqd)); 3383 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3384 amdgpu_ring_clear_ring(ring); 3385 mutex_lock(&adev->srbm_mutex); 3386 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3387 amdgpu_ring_init_mqd(ring); 3388 gfx_v12_0_kiq_init_register(ring); 3389 soc24_grbm_select(adev, 0, 0, 0, 0); 3390 mutex_unlock(&adev->srbm_mutex); 3391 3392 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3393 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3394 } 3395 3396 return 0; 3397 } 3398 3399 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) 3400 { 3401 struct amdgpu_device *adev = ring->adev; 3402 struct v12_compute_mqd *mqd = ring->mqd_ptr; 3403 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3404 3405 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { 3406 memset((void *)mqd, 0, sizeof(*mqd)); 3407 mutex_lock(&adev->srbm_mutex); 3408 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3409 amdgpu_ring_init_mqd(ring); 3410 soc24_grbm_select(adev, 0, 0, 0, 0); 3411 mutex_unlock(&adev->srbm_mutex); 3412 3413 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3414 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3415 } else { 3416 /* restore MQD to a clean status */ 3417 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3418 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3419 /* reset ring buffer */ 3420 ring->wptr = 0; 3421 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3422 amdgpu_ring_clear_ring(ring); 3423 } 3424 3425 return 0; 3426 } 3427 3428 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev) 3429 { 3430 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring); 3431 adev->gfx.kiq[0].ring.sched.ready = true; 3432 return 0; 3433 } 3434 3435 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) 3436 { 3437 int i, r; 3438 3439 if (!amdgpu_async_gfx_ring) 3440 gfx_v12_0_cp_compute_enable(adev, true); 3441 3442 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3443 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false); 3444 if (r) 3445 return r; 3446 } 3447 3448 return amdgpu_gfx_enable_kcq(adev, 0); 3449 } 3450 3451 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) 3452 { 3453 int r, i; 3454 struct amdgpu_ring *ring; 3455 3456 if (!(adev->flags & AMD_IS_APU)) 3457 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3458 3459 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3460 /* legacy firmware loading */ 3461 r = gfx_v12_0_cp_gfx_load_microcode(adev); 3462 if (r) 3463 return r; 3464 3465 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev); 3466 if (r) 3467 return r; 3468 } 3469 3470 gfx_v12_0_cp_set_doorbell_range(adev); 3471 3472 if (amdgpu_async_gfx_ring) { 3473 gfx_v12_0_cp_compute_enable(adev, true); 3474 gfx_v12_0_cp_gfx_enable(adev, true); 3475 } 3476 3477 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3478 r = amdgpu_mes_kiq_hw_init(adev, 0); 3479 else 3480 r = gfx_v12_0_kiq_resume(adev); 3481 if (r) 3482 return r; 3483 3484 r = gfx_v12_0_kcq_resume(adev); 3485 if (r) 3486 return r; 3487 3488 if (!amdgpu_async_gfx_ring) { 3489 r = gfx_v12_0_cp_gfx_resume(adev); 3490 if (r) 3491 return r; 3492 } else { 3493 r = gfx_v12_0_cp_async_gfx_ring_resume(adev); 3494 if (r) 3495 return r; 3496 } 3497 3498 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3499 ring = &adev->gfx.gfx_ring[i]; 3500 r = amdgpu_ring_test_helper(ring); 3501 if (r) 3502 return r; 3503 } 3504 3505 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3506 ring = &adev->gfx.compute_ring[i]; 3507 r = amdgpu_ring_test_helper(ring); 3508 if (r) 3509 return r; 3510 } 3511 3512 return 0; 3513 } 3514 3515 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable) 3516 { 3517 gfx_v12_0_cp_gfx_enable(adev, enable); 3518 gfx_v12_0_cp_compute_enable(adev, enable); 3519 } 3520 3521 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) 3522 { 3523 int r; 3524 bool value; 3525 3526 r = adev->gfxhub.funcs->gart_enable(adev); 3527 if (r) 3528 return r; 3529 3530 amdgpu_device_flush_hdp(adev, NULL); 3531 3532 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 3533 3534 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3535 /* TODO investigate why this and the hdp flush above is needed, 3536 * are we missing a flush somewhere else? */ 3537 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 3538 3539 return 0; 3540 } 3541 3542 static int get_gb_addr_config(struct amdgpu_device *adev) 3543 { 3544 u32 gb_addr_config; 3545 3546 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 3547 if (gb_addr_config == 0) 3548 return -EINVAL; 3549 3550 adev->gfx.config.gb_addr_config_fields.num_pkrs = 3551 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 3552 3553 adev->gfx.config.gb_addr_config = gb_addr_config; 3554 3555 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 3556 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3557 GB_ADDR_CONFIG, NUM_PIPES); 3558 3559 adev->gfx.config.max_tile_pipes = 3560 adev->gfx.config.gb_addr_config_fields.num_pipes; 3561 3562 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 3563 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3564 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 3565 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 3566 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3567 GB_ADDR_CONFIG, NUM_RB_PER_SE); 3568 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 3569 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3570 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 3571 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 3572 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 3573 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 3574 3575 return 0; 3576 } 3577 3578 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 3579 { 3580 uint32_t data; 3581 3582 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 3583 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 3584 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 3585 3586 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 3587 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 3588 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 3589 } 3590 3591 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) 3592 { 3593 if (amdgpu_sriov_vf(adev)) 3594 return; 3595 3596 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3597 case IP_VERSION(12, 0, 0): 3598 case IP_VERSION(12, 0, 1): 3599 soc15_program_register_sequence(adev, 3600 golden_settings_gc_12_0, 3601 (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); 3602 3603 if (adev->rev_id == 0) 3604 soc15_program_register_sequence(adev, 3605 golden_settings_gc_12_0_rev0, 3606 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); 3607 break; 3608 default: 3609 break; 3610 } 3611 } 3612 3613 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 3614 { 3615 int r; 3616 struct amdgpu_device *adev = ip_block->adev; 3617 3618 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 3619 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3620 /* RLC autoload sequence 1: Program rlc ram */ 3621 if (adev->gfx.imu.funcs->program_rlc_ram) 3622 adev->gfx.imu.funcs->program_rlc_ram(adev); 3623 } 3624 /* rlc autoload firmware */ 3625 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev); 3626 if (r) 3627 return r; 3628 } else { 3629 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3630 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 3631 if (adev->gfx.imu.funcs->load_microcode) 3632 adev->gfx.imu.funcs->load_microcode(adev); 3633 if (adev->gfx.imu.funcs->setup_imu) 3634 adev->gfx.imu.funcs->setup_imu(adev); 3635 if (adev->gfx.imu.funcs->start_imu) 3636 adev->gfx.imu.funcs->start_imu(adev); 3637 } 3638 3639 /* disable gpa mode in backdoor loading */ 3640 gfx_v12_0_disable_gpa_mode(adev); 3641 } 3642 } 3643 3644 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 3645 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3646 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev); 3647 if (r) { 3648 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 3649 return r; 3650 } 3651 } 3652 3653 if (!amdgpu_emu_mode) 3654 gfx_v12_0_init_golden_registers(adev); 3655 3656 adev->gfx.is_poweron = true; 3657 3658 if (get_gb_addr_config(adev)) 3659 drm_warn(adev_to_drm(adev), "Invalid gb_addr_config !\n"); 3660 3661 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 3662 gfx_v12_0_config_gfx_rs64(adev); 3663 3664 r = gfx_v12_0_gfxhub_enable(adev); 3665 if (r) 3666 return r; 3667 3668 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT || 3669 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) && 3670 (amdgpu_dpm == 1)) { 3671 /** 3672 * For gfx 12, rlc firmware loading relies on smu firmware is 3673 * loaded firstly, so in direct type, it has to load smc ucode 3674 * here before rlc. 3675 */ 3676 r = amdgpu_pm_load_smu_firmware(adev, NULL); 3677 if (r) 3678 return r; 3679 } 3680 3681 gfx_v12_0_constants_init(adev); 3682 3683 if (adev->nbio.funcs->gc_doorbell_init) 3684 adev->nbio.funcs->gc_doorbell_init(adev); 3685 3686 r = gfx_v12_0_rlc_resume(adev); 3687 if (r) 3688 return r; 3689 3690 /* 3691 * init golden registers and rlc resume may override some registers, 3692 * reconfig them here 3693 */ 3694 gfx_v12_0_tcp_harvest(adev); 3695 3696 r = gfx_v12_0_cp_resume(adev); 3697 if (r) 3698 return r; 3699 3700 return r; 3701 } 3702 3703 static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev, 3704 bool enable) 3705 { 3706 unsigned int irq_type; 3707 int m, p, r; 3708 3709 if (adev->userq_funcs[AMDGPU_HW_IP_GFX]) { 3710 for (m = 0; m < adev->gfx.me.num_me; m++) { 3711 for (p = 0; p < adev->gfx.me.num_pipe_per_me; p++) { 3712 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p; 3713 if (enable) 3714 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3715 irq_type); 3716 else 3717 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3718 irq_type); 3719 if (r) 3720 return r; 3721 } 3722 } 3723 } 3724 3725 if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE]) { 3726 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 3727 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 3728 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 3729 + (m * adev->gfx.mec.num_pipe_per_mec) 3730 + p; 3731 if (enable) 3732 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 3733 irq_type); 3734 else 3735 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 3736 irq_type); 3737 if (r) 3738 return r; 3739 } 3740 } 3741 } 3742 3743 return 0; 3744 } 3745 3746 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 3747 { 3748 struct amdgpu_device *adev = ip_block->adev; 3749 uint32_t tmp; 3750 3751 cancel_delayed_work_sync(&adev->gfx.idle_work); 3752 3753 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3754 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3755 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 3756 gfx_v12_0_set_userq_eop_interrupts(adev, false); 3757 3758 if (!adev->no_hw_access) { 3759 if (amdgpu_async_gfx_ring) { 3760 if (amdgpu_gfx_disable_kgq(adev, 0)) 3761 DRM_ERROR("KGQ disable failed\n"); 3762 } 3763 3764 if (amdgpu_gfx_disable_kcq(adev, 0)) 3765 DRM_ERROR("KCQ disable failed\n"); 3766 3767 amdgpu_mes_kiq_hw_fini(adev, 0); 3768 } 3769 3770 if (amdgpu_sriov_vf(adev)) { 3771 gfx_v12_0_cp_gfx_enable(adev, false); 3772 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 3773 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3774 tmp &= 0xffffff00; 3775 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3776 3777 return 0; 3778 } 3779 gfx_v12_0_cp_enable(adev, false); 3780 gfx_v12_0_enable_gui_idle_interrupt(adev, false); 3781 3782 adev->gfxhub.funcs->gart_disable(adev); 3783 3784 adev->gfx.is_poweron = false; 3785 3786 return 0; 3787 } 3788 3789 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) 3790 { 3791 return gfx_v12_0_hw_fini(ip_block); 3792 } 3793 3794 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) 3795 { 3796 return gfx_v12_0_hw_init(ip_block); 3797 } 3798 3799 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 3800 { 3801 struct amdgpu_device *adev = ip_block->adev; 3802 3803 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 3804 GRBM_STATUS, GUI_ACTIVE)) 3805 return false; 3806 else 3807 return true; 3808 } 3809 3810 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 3811 { 3812 unsigned i; 3813 u32 tmp; 3814 struct amdgpu_device *adev = ip_block->adev; 3815 3816 for (i = 0; i < adev->usec_timeout; i++) { 3817 /* read MC_STATUS */ 3818 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 3819 GRBM_STATUS__GUI_ACTIVE_MASK; 3820 3821 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3822 return 0; 3823 udelay(1); 3824 } 3825 return -ETIMEDOUT; 3826 } 3827 3828 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3829 { 3830 uint64_t clock = 0; 3831 3832 if (adev->smuio.funcs && 3833 adev->smuio.funcs->get_gpu_clock_counter) 3834 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 3835 else 3836 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 3837 3838 return clock; 3839 } 3840 3841 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) 3842 { 3843 struct amdgpu_device *adev = ip_block->adev; 3844 3845 switch (amdgpu_user_queue) { 3846 case -1: 3847 case 0: 3848 default: 3849 adev->gfx.disable_kq = false; 3850 adev->gfx.disable_uq = true; 3851 break; 3852 case 1: 3853 adev->gfx.disable_kq = false; 3854 adev->gfx.disable_uq = false; 3855 break; 3856 case 2: 3857 adev->gfx.disable_kq = true; 3858 adev->gfx.disable_uq = false; 3859 break; 3860 } 3861 3862 adev->gfx.funcs = &gfx_v12_0_gfx_funcs; 3863 3864 if (adev->gfx.disable_kq) { 3865 adev->gfx.num_gfx_rings = 0; 3866 adev->gfx.num_compute_rings = 0; 3867 } else { 3868 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS; 3869 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 3870 AMDGPU_MAX_COMPUTE_RINGS); 3871 } 3872 3873 gfx_v12_0_set_kiq_pm4_funcs(adev); 3874 gfx_v12_0_set_ring_funcs(adev); 3875 gfx_v12_0_set_irq_funcs(adev); 3876 gfx_v12_0_set_rlc_funcs(adev); 3877 gfx_v12_0_set_mqd_funcs(adev); 3878 gfx_v12_0_set_imu_funcs(adev); 3879 3880 gfx_v12_0_init_rlcg_reg_access_ctrl(adev); 3881 3882 return gfx_v12_0_init_microcode(adev); 3883 } 3884 3885 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) 3886 { 3887 struct amdgpu_device *adev = ip_block->adev; 3888 int r; 3889 3890 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3891 if (r) 3892 return r; 3893 3894 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3895 if (r) 3896 return r; 3897 3898 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 3899 if (r) 3900 return r; 3901 3902 r = gfx_v12_0_set_userq_eop_interrupts(adev, true); 3903 if (r) 3904 return r; 3905 3906 return 0; 3907 } 3908 3909 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev) 3910 { 3911 uint32_t rlc_cntl; 3912 3913 /* if RLC is not enabled, do nothing */ 3914 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 3915 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3916 } 3917 3918 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, 3919 int xcc_id) 3920 { 3921 uint32_t data; 3922 unsigned i; 3923 3924 data = RLC_SAFE_MODE__CMD_MASK; 3925 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3926 3927 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 3928 3929 /* wait for RLC_SAFE_MODE */ 3930 for (i = 0; i < adev->usec_timeout; i++) { 3931 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 3932 RLC_SAFE_MODE, CMD)) 3933 break; 3934 udelay(1); 3935 } 3936 } 3937 3938 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, 3939 int xcc_id) 3940 { 3941 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 3942 } 3943 3944 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, 3945 bool enable) 3946 { 3947 uint32_t def, data; 3948 3949 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3950 return; 3951 3952 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 3953 3954 if (enable) 3955 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3956 else 3957 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3958 3959 if (def != data) 3960 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 3961 } 3962 3963 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, 3964 int xcc_id, 3965 struct amdgpu_ring *ring, 3966 unsigned vmid) 3967 { 3968 u32 reg, data; 3969 3970 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3971 if (amdgpu_sriov_is_pp_one_vf(adev)) 3972 data = RREG32_NO_KIQ(reg); 3973 else 3974 data = RREG32(reg); 3975 3976 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 3977 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 3978 3979 if (amdgpu_sriov_is_pp_one_vf(adev)) 3980 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 3981 else 3982 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 3983 3984 if (ring 3985 && amdgpu_sriov_is_pp_one_vf(adev) 3986 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 3987 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 3988 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 3989 amdgpu_ring_emit_wreg(ring, reg, data); 3990 } 3991 } 3992 3993 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = { 3994 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled, 3995 .set_safe_mode = gfx_v12_0_set_safe_mode, 3996 .unset_safe_mode = gfx_v12_0_unset_safe_mode, 3997 .init = gfx_v12_0_rlc_init, 3998 .get_csb_size = gfx_v12_0_get_csb_size, 3999 .get_csb_buffer = gfx_v12_0_get_csb_buffer, 4000 .resume = gfx_v12_0_rlc_resume, 4001 .stop = gfx_v12_0_rlc_stop, 4002 .reset = gfx_v12_0_rlc_reset, 4003 .start = gfx_v12_0_rlc_start, 4004 .update_spm_vmid = gfx_v12_0_update_spm_vmid, 4005 }; 4006 4007 #if 0 4008 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 4009 { 4010 /* TODO */ 4011 } 4012 4013 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 4014 { 4015 /* TODO */ 4016 } 4017 #endif 4018 4019 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 4020 enum amd_powergating_state state) 4021 { 4022 struct amdgpu_device *adev = ip_block->adev; 4023 bool enable = (state == AMD_PG_STATE_GATE); 4024 4025 if (amdgpu_sriov_vf(adev)) 4026 return 0; 4027 4028 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4029 case IP_VERSION(12, 0, 0): 4030 case IP_VERSION(12, 0, 1): 4031 amdgpu_gfx_off_ctrl(adev, enable); 4032 break; 4033 default: 4034 break; 4035 } 4036 4037 return 0; 4038 } 4039 4040 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4041 bool enable) 4042 { 4043 uint32_t def, data; 4044 4045 if (!(adev->cg_flags & 4046 (AMD_CG_SUPPORT_GFX_CGCG | 4047 AMD_CG_SUPPORT_GFX_CGLS | 4048 AMD_CG_SUPPORT_GFX_3D_CGCG | 4049 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4050 return; 4051 4052 if (enable) { 4053 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4054 4055 /* unset CGCG override */ 4056 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4057 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4058 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4059 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4060 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4061 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4062 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4063 4064 /* update CGCG override bits */ 4065 if (def != data) 4066 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4067 4068 /* enable cgcg FSM(0x0000363F) */ 4069 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4070 4071 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4072 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4073 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4074 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4075 } 4076 4077 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4078 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4079 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4080 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4081 } 4082 4083 if (def != data) 4084 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4085 4086 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4087 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4088 4089 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4090 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4091 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4092 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4093 } 4094 4095 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4096 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4097 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4098 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4099 } 4100 4101 if (def != data) 4102 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4103 4104 /* set IDLE_POLL_COUNT(0x00900100) */ 4105 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4106 4107 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4108 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4109 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4110 4111 if (def != data) 4112 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4113 4114 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4115 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4116 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4117 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4118 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4119 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4120 4121 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4122 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4123 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4124 4125 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4126 if (adev->sdma.num_instances > 1) { 4127 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4128 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4129 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4130 } 4131 } else { 4132 /* Program RLC_CGCG_CGLS_CTRL */ 4133 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4134 4135 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4136 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4137 4138 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4139 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4140 4141 if (def != data) 4142 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4143 4144 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4145 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4146 4147 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4148 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4149 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4150 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4151 4152 if (def != data) 4153 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4154 } 4155 } 4156 4157 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4158 bool enable) 4159 { 4160 uint32_t data, def; 4161 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4162 return; 4163 4164 /* It is disabled by HW by default */ 4165 if (enable) { 4166 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4167 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4168 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4169 4170 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4171 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4172 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4173 4174 if (def != data) 4175 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4176 } 4177 } else { 4178 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4179 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4180 4181 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4182 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4183 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4184 4185 if (def != data) 4186 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4187 } 4188 } 4189 } 4190 4191 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev, 4192 bool enable) 4193 { 4194 uint32_t def, data; 4195 4196 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4197 return; 4198 4199 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4200 4201 if (enable) 4202 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4203 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 4204 else 4205 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 4206 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 4207 4208 if (def != data) 4209 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4210 } 4211 4212 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev, 4213 bool enable) 4214 { 4215 uint32_t def, data; 4216 4217 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4218 return; 4219 4220 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4221 4222 if (enable) 4223 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4224 else 4225 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4226 4227 if (def != data) 4228 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4229 } 4230 4231 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4232 bool enable) 4233 { 4234 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4235 4236 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable); 4237 4238 gfx_v12_0_update_medium_grain_clock_gating(adev, enable); 4239 4240 gfx_v12_0_update_repeater_fgcg(adev, enable); 4241 4242 gfx_v12_0_update_sram_fgcg(adev, enable); 4243 4244 gfx_v12_0_update_perf_clk(adev, enable); 4245 4246 if (adev->cg_flags & 4247 (AMD_CG_SUPPORT_GFX_MGCG | 4248 AMD_CG_SUPPORT_GFX_CGLS | 4249 AMD_CG_SUPPORT_GFX_CGCG | 4250 AMD_CG_SUPPORT_GFX_3D_CGCG | 4251 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4252 gfx_v12_0_enable_gui_idle_interrupt(adev, enable); 4253 4254 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4255 4256 return 0; 4257 } 4258 4259 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 4260 enum amd_clockgating_state state) 4261 { 4262 struct amdgpu_device *adev = ip_block->adev; 4263 4264 if (amdgpu_sriov_vf(adev)) 4265 return 0; 4266 4267 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4268 case IP_VERSION(12, 0, 0): 4269 case IP_VERSION(12, 0, 1): 4270 gfx_v12_0_update_gfx_clock_gating(adev, 4271 state == AMD_CG_STATE_GATE); 4272 break; 4273 default: 4274 break; 4275 } 4276 4277 return 0; 4278 } 4279 4280 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 4281 { 4282 struct amdgpu_device *adev = ip_block->adev; 4283 int data; 4284 4285 /* AMD_CG_SUPPORT_GFX_MGCG */ 4286 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4287 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4288 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4289 4290 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 4291 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 4292 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 4293 4294 /* AMD_CG_SUPPORT_GFX_FGCG */ 4295 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 4296 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 4297 4298 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 4299 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 4300 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 4301 4302 /* AMD_CG_SUPPORT_GFX_CGCG */ 4303 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4304 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4305 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4306 4307 /* AMD_CG_SUPPORT_GFX_CGLS */ 4308 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4309 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4310 4311 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4312 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4313 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4314 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4315 4316 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4317 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4318 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4319 } 4320 4321 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4322 { 4323 /* gfx12 is 32bit rptr*/ 4324 return *(uint32_t *)ring->rptr_cpu_addr; 4325 } 4326 4327 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4328 { 4329 struct amdgpu_device *adev = ring->adev; 4330 u64 wptr; 4331 4332 /* XXX check if swapping is necessary on BE */ 4333 if (ring->use_doorbell) { 4334 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4335 } else { 4336 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 4337 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 4338 } 4339 4340 return wptr; 4341 } 4342 4343 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4344 { 4345 struct amdgpu_device *adev = ring->adev; 4346 4347 if (ring->use_doorbell) { 4348 /* XXX check if swapping is necessary on BE */ 4349 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4350 ring->wptr); 4351 WDOORBELL64(ring->doorbell_index, ring->wptr); 4352 } else { 4353 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 4354 lower_32_bits(ring->wptr)); 4355 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 4356 upper_32_bits(ring->wptr)); 4357 } 4358 } 4359 4360 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4361 { 4362 /* gfx12 hardware is 32bit rptr */ 4363 return *(uint32_t *)ring->rptr_cpu_addr; 4364 } 4365 4366 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4367 { 4368 u64 wptr; 4369 4370 /* XXX check if swapping is necessary on BE */ 4371 if (ring->use_doorbell) 4372 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 4373 else 4374 BUG(); 4375 return wptr; 4376 } 4377 4378 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4379 { 4380 struct amdgpu_device *adev = ring->adev; 4381 4382 /* XXX check if swapping is necessary on BE */ 4383 if (ring->use_doorbell) { 4384 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 4385 ring->wptr); 4386 WDOORBELL64(ring->doorbell_index, ring->wptr); 4387 } else { 4388 BUG(); /* only DOORBELL method supported on gfx12 now */ 4389 } 4390 } 4391 4392 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4393 { 4394 struct amdgpu_device *adev = ring->adev; 4395 u32 ref_and_mask, reg_mem_engine; 4396 4397 if (!adev->gfx.funcs->get_hdp_flush_mask) { 4398 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 4399 return; 4400 } 4401 4402 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); 4403 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4404 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4405 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4406 ref_and_mask, ref_and_mask, 0x20); 4407 } 4408 4409 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4410 struct amdgpu_job *job, 4411 struct amdgpu_ib *ib, 4412 uint32_t flags) 4413 { 4414 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4415 u32 header, control = 0; 4416 4417 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4418 4419 control |= ib->length_dw | (vmid << 24); 4420 4421 amdgpu_ring_write(ring, header); 4422 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4423 amdgpu_ring_write(ring, 4424 #ifdef __BIG_ENDIAN 4425 (2 << 0) | 4426 #endif 4427 lower_32_bits(ib->gpu_addr)); 4428 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4429 amdgpu_ring_write(ring, control); 4430 } 4431 4432 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4433 struct amdgpu_job *job, 4434 struct amdgpu_ib *ib, 4435 uint32_t flags) 4436 { 4437 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4438 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4439 4440 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4441 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4442 amdgpu_ring_write(ring, 4443 #ifdef __BIG_ENDIAN 4444 (2 << 0) | 4445 #endif 4446 lower_32_bits(ib->gpu_addr)); 4447 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4448 amdgpu_ring_write(ring, control); 4449 } 4450 4451 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4452 u64 seq, unsigned flags) 4453 { 4454 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4455 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4456 4457 /* RELEASE_MEM - flush caches, send int */ 4458 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4459 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4460 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4461 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4462 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4463 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4464 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4465 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4466 4467 /* 4468 * the address should be Qword aligned if 64bit write, Dword 4469 * aligned if only send 32bit data low (discard data high) 4470 */ 4471 if (write64bit) 4472 BUG_ON(addr & 0x7); 4473 else 4474 BUG_ON(addr & 0x3); 4475 amdgpu_ring_write(ring, lower_32_bits(addr)); 4476 amdgpu_ring_write(ring, upper_32_bits(addr)); 4477 amdgpu_ring_write(ring, lower_32_bits(seq)); 4478 amdgpu_ring_write(ring, upper_32_bits(seq)); 4479 amdgpu_ring_write(ring, 0); 4480 } 4481 4482 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4483 { 4484 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4485 uint32_t seq = ring->fence_drv.sync_seq; 4486 uint64_t addr = ring->fence_drv.gpu_addr; 4487 4488 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4489 upper_32_bits(addr), seq, 0xffffffff, 4); 4490 } 4491 4492 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 4493 uint16_t pasid, uint32_t flush_type, 4494 bool all_hub, uint8_t dst_sel) 4495 { 4496 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 4497 amdgpu_ring_write(ring, 4498 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 4499 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 4500 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 4501 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 4502 } 4503 4504 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4505 unsigned vmid, uint64_t pd_addr) 4506 { 4507 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4508 4509 /* compute doesn't have PFP */ 4510 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4511 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4512 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4513 amdgpu_ring_write(ring, 0x0); 4514 } 4515 } 4516 4517 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4518 u64 seq, unsigned int flags) 4519 { 4520 struct amdgpu_device *adev = ring->adev; 4521 4522 /* we only allocate 32bit for each seq wb address */ 4523 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4524 4525 /* write fence seq to the "addr" */ 4526 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4527 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4528 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4529 amdgpu_ring_write(ring, lower_32_bits(addr)); 4530 amdgpu_ring_write(ring, upper_32_bits(addr)); 4531 amdgpu_ring_write(ring, lower_32_bits(seq)); 4532 4533 if (flags & AMDGPU_FENCE_FLAG_INT) { 4534 /* set register to trigger INT */ 4535 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4536 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4537 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4538 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 4539 amdgpu_ring_write(ring, 0); 4540 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4541 } 4542 } 4543 4544 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 4545 uint32_t flags) 4546 { 4547 uint32_t dw2 = 0; 4548 4549 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4550 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4551 /* set load_global_config & load_global_uconfig */ 4552 dw2 |= 0x8001; 4553 /* set load_cs_sh_regs */ 4554 dw2 |= 0x01000000; 4555 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4556 dw2 |= 0x10002; 4557 } 4558 4559 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4560 amdgpu_ring_write(ring, dw2); 4561 amdgpu_ring_write(ring, 0); 4562 } 4563 4564 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring, 4565 uint64_t addr) 4566 { 4567 unsigned ret; 4568 4569 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4570 amdgpu_ring_write(ring, lower_32_bits(addr)); 4571 amdgpu_ring_write(ring, upper_32_bits(addr)); 4572 /* discard following DWs if *cond_exec_gpu_addr==0 */ 4573 amdgpu_ring_write(ring, 0); 4574 ret = ring->wptr & ring->buf_mask; 4575 /* patch dummy value later */ 4576 amdgpu_ring_write(ring, 0); 4577 4578 return ret; 4579 } 4580 4581 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) 4582 { 4583 int i, r = 0; 4584 struct amdgpu_device *adev = ring->adev; 4585 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4586 struct amdgpu_ring *kiq_ring = &kiq->ring; 4587 unsigned long flags; 4588 4589 if (adev->enable_mes) 4590 return -EINVAL; 4591 4592 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4593 return -EINVAL; 4594 4595 spin_lock_irqsave(&kiq->ring_lock, flags); 4596 4597 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4598 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4599 return -ENOMEM; 4600 } 4601 4602 /* assert preemption condition */ 4603 amdgpu_ring_set_preempt_cond_exec(ring, false); 4604 4605 /* assert IB preemption, emit the trailing fence */ 4606 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4607 ring->trail_fence_gpu_addr, 4608 ++ring->trail_seq); 4609 amdgpu_ring_commit(kiq_ring); 4610 4611 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4612 4613 /* poll the trailing fence */ 4614 for (i = 0; i < adev->usec_timeout; i++) { 4615 if (ring->trail_seq == 4616 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4617 break; 4618 udelay(1); 4619 } 4620 4621 if (i >= adev->usec_timeout) { 4622 r = -EINVAL; 4623 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4624 } 4625 4626 /* deassert preemption condition */ 4627 amdgpu_ring_set_preempt_cond_exec(ring, true); 4628 return r; 4629 } 4630 4631 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 4632 uint32_t reg_val_offs) 4633 { 4634 struct amdgpu_device *adev = ring->adev; 4635 4636 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4637 amdgpu_ring_write(ring, 0 | /* src: register*/ 4638 (5 << 8) | /* dst: memory */ 4639 (1 << 20)); /* write confirm */ 4640 amdgpu_ring_write(ring, reg); 4641 amdgpu_ring_write(ring, 0); 4642 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4643 reg_val_offs * 4)); 4644 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4645 reg_val_offs * 4)); 4646 } 4647 4648 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, 4649 uint32_t reg, 4650 uint32_t val) 4651 { 4652 uint32_t cmd = 0; 4653 4654 switch (ring->funcs->type) { 4655 case AMDGPU_RING_TYPE_GFX: 4656 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4657 break; 4658 case AMDGPU_RING_TYPE_KIQ: 4659 cmd = (1 << 16); /* no inc addr */ 4660 break; 4661 default: 4662 cmd = WR_CONFIRM; 4663 break; 4664 } 4665 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4666 amdgpu_ring_write(ring, cmd); 4667 amdgpu_ring_write(ring, reg); 4668 amdgpu_ring_write(ring, 0); 4669 amdgpu_ring_write(ring, val); 4670 } 4671 4672 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4673 uint32_t val, uint32_t mask) 4674 { 4675 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4676 } 4677 4678 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4679 uint32_t reg0, uint32_t reg1, 4680 uint32_t ref, uint32_t mask) 4681 { 4682 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4683 4684 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4685 ref, mask, 0x20); 4686 } 4687 4688 static void 4689 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4690 uint32_t me, uint32_t pipe, 4691 enum amdgpu_interrupt_state state) 4692 { 4693 uint32_t cp_int_cntl, cp_int_cntl_reg; 4694 4695 if (!me) { 4696 switch (pipe) { 4697 case 0: 4698 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 4699 break; 4700 default: 4701 DRM_DEBUG("invalid pipe %d\n", pipe); 4702 return; 4703 } 4704 } else { 4705 DRM_DEBUG("invalid me %d\n", me); 4706 return; 4707 } 4708 4709 switch (state) { 4710 case AMDGPU_IRQ_STATE_DISABLE: 4711 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4712 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4713 TIME_STAMP_INT_ENABLE, 0); 4714 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4715 GENERIC0_INT_ENABLE, 0); 4716 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4717 break; 4718 case AMDGPU_IRQ_STATE_ENABLE: 4719 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4720 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4721 TIME_STAMP_INT_ENABLE, 1); 4722 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4723 GENERIC0_INT_ENABLE, 1); 4724 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4725 break; 4726 default: 4727 break; 4728 } 4729 } 4730 4731 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4732 int me, int pipe, 4733 enum amdgpu_interrupt_state state) 4734 { 4735 u32 mec_int_cntl, mec_int_cntl_reg; 4736 4737 /* 4738 * amdgpu controls only the first MEC. That's why this function only 4739 * handles the setting of interrupts for this specific MEC. All other 4740 * pipes' interrupts are set by amdkfd. 4741 */ 4742 4743 if (me == 1) { 4744 switch (pipe) { 4745 case 0: 4746 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 4747 break; 4748 case 1: 4749 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 4750 break; 4751 default: 4752 DRM_DEBUG("invalid pipe %d\n", pipe); 4753 return; 4754 } 4755 } else { 4756 DRM_DEBUG("invalid me %d\n", me); 4757 return; 4758 } 4759 4760 switch (state) { 4761 case AMDGPU_IRQ_STATE_DISABLE: 4762 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4763 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4764 TIME_STAMP_INT_ENABLE, 0); 4765 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4766 GENERIC0_INT_ENABLE, 0); 4767 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4768 break; 4769 case AMDGPU_IRQ_STATE_ENABLE: 4770 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 4771 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4772 TIME_STAMP_INT_ENABLE, 1); 4773 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4774 GENERIC0_INT_ENABLE, 1); 4775 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 4776 break; 4777 default: 4778 break; 4779 } 4780 } 4781 4782 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4783 struct amdgpu_irq_src *src, 4784 unsigned type, 4785 enum amdgpu_interrupt_state state) 4786 { 4787 switch (type) { 4788 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4789 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4790 break; 4791 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4792 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4793 break; 4794 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4795 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4796 break; 4797 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4798 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4799 break; 4800 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4801 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4802 break; 4803 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4804 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4805 break; 4806 default: 4807 break; 4808 } 4809 return 0; 4810 } 4811 4812 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, 4813 struct amdgpu_irq_src *source, 4814 struct amdgpu_iv_entry *entry) 4815 { 4816 u32 doorbell_offset = entry->src_data[0]; 4817 u8 me_id, pipe_id, queue_id; 4818 struct amdgpu_ring *ring; 4819 int i; 4820 4821 DRM_DEBUG("IH: CP EOP\n"); 4822 4823 if (adev->enable_mes && doorbell_offset) { 4824 struct amdgpu_userq_fence_driver *fence_drv = NULL; 4825 struct xarray *xa = &adev->userq_xa; 4826 unsigned long flags; 4827 4828 xa_lock_irqsave(xa, flags); 4829 fence_drv = xa_load(xa, doorbell_offset); 4830 if (fence_drv) 4831 amdgpu_userq_fence_driver_process(fence_drv); 4832 xa_unlock_irqrestore(xa, flags); 4833 } else { 4834 me_id = (entry->ring_id & 0x0c) >> 2; 4835 pipe_id = (entry->ring_id & 0x03) >> 0; 4836 queue_id = (entry->ring_id & 0x70) >> 4; 4837 4838 switch (me_id) { 4839 case 0: 4840 if (pipe_id == 0) 4841 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4842 else 4843 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4844 break; 4845 case 1: 4846 case 2: 4847 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4848 ring = &adev->gfx.compute_ring[i]; 4849 /* Per-queue interrupt is supported for MEC starting from VI. 4850 * The interrupt can only be enabled/disabled per pipe instead 4851 * of per queue. 4852 */ 4853 if ((ring->me == me_id) && 4854 (ring->pipe == pipe_id) && 4855 (ring->queue == queue_id)) 4856 amdgpu_fence_process(ring); 4857 } 4858 break; 4859 } 4860 } 4861 4862 return 0; 4863 } 4864 4865 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4866 struct amdgpu_irq_src *source, 4867 unsigned int type, 4868 enum amdgpu_interrupt_state state) 4869 { 4870 u32 cp_int_cntl_reg, cp_int_cntl; 4871 int i, j; 4872 4873 switch (state) { 4874 case AMDGPU_IRQ_STATE_DISABLE: 4875 case AMDGPU_IRQ_STATE_ENABLE: 4876 for (i = 0; i < adev->gfx.me.num_me; i++) { 4877 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4878 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4879 4880 if (cp_int_cntl_reg) { 4881 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4882 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4883 PRIV_REG_INT_ENABLE, 4884 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4885 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4886 } 4887 } 4888 } 4889 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4890 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4891 /* MECs start at 1 */ 4892 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4893 4894 if (cp_int_cntl_reg) { 4895 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4896 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4897 PRIV_REG_INT_ENABLE, 4898 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4899 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4900 } 4901 } 4902 } 4903 break; 4904 default: 4905 break; 4906 } 4907 4908 return 0; 4909 } 4910 4911 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev, 4912 struct amdgpu_irq_src *source, 4913 unsigned type, 4914 enum amdgpu_interrupt_state state) 4915 { 4916 u32 cp_int_cntl_reg, cp_int_cntl; 4917 int i, j; 4918 4919 switch (state) { 4920 case AMDGPU_IRQ_STATE_DISABLE: 4921 case AMDGPU_IRQ_STATE_ENABLE: 4922 for (i = 0; i < adev->gfx.me.num_me; i++) { 4923 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4924 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4925 4926 if (cp_int_cntl_reg) { 4927 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4928 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4929 OPCODE_ERROR_INT_ENABLE, 4930 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4931 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4932 } 4933 } 4934 } 4935 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4936 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4937 /* MECs start at 1 */ 4938 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j); 4939 4940 if (cp_int_cntl_reg) { 4941 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4942 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4943 OPCODE_ERROR_INT_ENABLE, 4944 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4945 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4946 } 4947 } 4948 } 4949 break; 4950 default: 4951 break; 4952 } 4953 return 0; 4954 } 4955 4956 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4957 struct amdgpu_irq_src *source, 4958 unsigned int type, 4959 enum amdgpu_interrupt_state state) 4960 { 4961 u32 cp_int_cntl_reg, cp_int_cntl; 4962 int i, j; 4963 4964 switch (state) { 4965 case AMDGPU_IRQ_STATE_DISABLE: 4966 case AMDGPU_IRQ_STATE_ENABLE: 4967 for (i = 0; i < adev->gfx.me.num_me; i++) { 4968 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 4969 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); 4970 4971 if (cp_int_cntl_reg) { 4972 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 4973 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4974 PRIV_INSTR_INT_ENABLE, 4975 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4976 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 4977 } 4978 } 4979 } 4980 break; 4981 default: 4982 break; 4983 } 4984 4985 return 0; 4986 } 4987 4988 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, 4989 struct amdgpu_iv_entry *entry) 4990 { 4991 u8 me_id, pipe_id, queue_id; 4992 struct amdgpu_ring *ring; 4993 int i; 4994 4995 me_id = (entry->ring_id & 0x0c) >> 2; 4996 pipe_id = (entry->ring_id & 0x03) >> 0; 4997 queue_id = (entry->ring_id & 0x70) >> 4; 4998 4999 if (!adev->gfx.disable_kq) { 5000 switch (me_id) { 5001 case 0: 5002 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5003 ring = &adev->gfx.gfx_ring[i]; 5004 if (ring->me == me_id && ring->pipe == pipe_id && 5005 ring->queue == queue_id) 5006 drm_sched_fault(&ring->sched); 5007 } 5008 break; 5009 case 1: 5010 case 2: 5011 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5012 ring = &adev->gfx.compute_ring[i]; 5013 if (ring->me == me_id && ring->pipe == pipe_id && 5014 ring->queue == queue_id) 5015 drm_sched_fault(&ring->sched); 5016 } 5017 break; 5018 default: 5019 BUG(); 5020 break; 5021 } 5022 } 5023 } 5024 5025 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, 5026 struct amdgpu_irq_src *source, 5027 struct amdgpu_iv_entry *entry) 5028 { 5029 DRM_ERROR("Illegal register access in command stream\n"); 5030 gfx_v12_0_handle_priv_fault(adev, entry); 5031 return 0; 5032 } 5033 5034 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, 5035 struct amdgpu_irq_src *source, 5036 struct amdgpu_iv_entry *entry) 5037 { 5038 DRM_ERROR("Illegal opcode in command stream\n"); 5039 gfx_v12_0_handle_priv_fault(adev, entry); 5040 return 0; 5041 } 5042 5043 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev, 5044 struct amdgpu_irq_src *source, 5045 struct amdgpu_iv_entry *entry) 5046 { 5047 DRM_ERROR("Illegal instruction in command stream\n"); 5048 gfx_v12_0_handle_priv_fault(adev, entry); 5049 return 0; 5050 } 5051 5052 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring) 5053 { 5054 const unsigned int gcr_cntl = 5055 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 5056 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 5057 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 5058 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 5059 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 5060 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 5061 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 5062 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 5063 5064 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 5065 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 5066 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 5067 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 5068 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 5069 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 5070 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 5071 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 5072 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 5073 } 5074 5075 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 5076 { 5077 /* Header itself is a NOP packet */ 5078 if (num_nop == 1) { 5079 amdgpu_ring_write(ring, ring->funcs->nop); 5080 return; 5081 } 5082 5083 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 5084 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 5085 5086 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 5087 amdgpu_ring_insert_nop(ring, num_nop - 1); 5088 } 5089 5090 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 5091 { 5092 /* Emit the cleaner shader */ 5093 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 5094 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 5095 } 5096 5097 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 5098 { 5099 struct amdgpu_device *adev = ip_block->adev; 5100 uint32_t i, j, k, reg, index = 0; 5101 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5102 5103 if (!adev->gfx.ip_dump_core) 5104 return; 5105 5106 for (i = 0; i < reg_count; i++) 5107 drm_printf(p, "%-50s \t 0x%08x\n", 5108 gc_reg_list_12_0[i].reg_name, 5109 adev->gfx.ip_dump_core[i]); 5110 5111 /* print compute queue registers for all instances */ 5112 if (!adev->gfx.ip_dump_compute_queues) 5113 return; 5114 5115 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5116 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n", 5117 adev->gfx.mec.num_mec, 5118 adev->gfx.mec.num_pipe_per_mec, 5119 adev->gfx.mec.num_queue_per_pipe); 5120 5121 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5122 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5123 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5124 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k); 5125 for (reg = 0; reg < reg_count; reg++) { 5126 drm_printf(p, "%-50s \t 0x%08x\n", 5127 gc_cp_reg_list_12[reg].reg_name, 5128 adev->gfx.ip_dump_compute_queues[index + reg]); 5129 } 5130 index += reg_count; 5131 } 5132 } 5133 } 5134 5135 /* print gfx queue registers for all instances */ 5136 if (!adev->gfx.ip_dump_gfx_queues) 5137 return; 5138 5139 index = 0; 5140 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5141 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n", 5142 adev->gfx.me.num_me, 5143 adev->gfx.me.num_pipe_per_me, 5144 adev->gfx.me.num_queue_per_pipe); 5145 5146 for (i = 0; i < adev->gfx.me.num_me; i++) { 5147 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5148 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5149 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k); 5150 for (reg = 0; reg < reg_count; reg++) { 5151 drm_printf(p, "%-50s \t 0x%08x\n", 5152 gc_gfx_queue_reg_list_12[reg].reg_name, 5153 adev->gfx.ip_dump_gfx_queues[index + reg]); 5154 } 5155 index += reg_count; 5156 } 5157 } 5158 } 5159 } 5160 5161 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) 5162 { 5163 struct amdgpu_device *adev = ip_block->adev; 5164 uint32_t i, j, k, reg, index = 0; 5165 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); 5166 5167 if (!adev->gfx.ip_dump_core) 5168 return; 5169 5170 amdgpu_gfx_off_ctrl(adev, false); 5171 for (i = 0; i < reg_count; i++) 5172 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i])); 5173 amdgpu_gfx_off_ctrl(adev, true); 5174 5175 /* dump compute queue registers for all instances */ 5176 if (!adev->gfx.ip_dump_compute_queues) 5177 return; 5178 5179 reg_count = ARRAY_SIZE(gc_cp_reg_list_12); 5180 amdgpu_gfx_off_ctrl(adev, false); 5181 mutex_lock(&adev->srbm_mutex); 5182 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 5183 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 5184 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 5185 /* ME0 is for GFX so start from 1 for CP */ 5186 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); 5187 for (reg = 0; reg < reg_count; reg++) { 5188 adev->gfx.ip_dump_compute_queues[index + reg] = 5189 RREG32(SOC15_REG_ENTRY_OFFSET( 5190 gc_cp_reg_list_12[reg])); 5191 } 5192 index += reg_count; 5193 } 5194 } 5195 } 5196 soc24_grbm_select(adev, 0, 0, 0, 0); 5197 mutex_unlock(&adev->srbm_mutex); 5198 amdgpu_gfx_off_ctrl(adev, true); 5199 5200 /* dump gfx queue registers for all instances */ 5201 if (!adev->gfx.ip_dump_gfx_queues) 5202 return; 5203 5204 index = 0; 5205 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12); 5206 amdgpu_gfx_off_ctrl(adev, false); 5207 mutex_lock(&adev->srbm_mutex); 5208 for (i = 0; i < adev->gfx.me.num_me; i++) { 5209 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { 5210 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { 5211 soc24_grbm_select(adev, i, j, k, 0); 5212 5213 for (reg = 0; reg < reg_count; reg++) { 5214 adev->gfx.ip_dump_gfx_queues[index + reg] = 5215 RREG32(SOC15_REG_ENTRY_OFFSET( 5216 gc_gfx_queue_reg_list_12[reg])); 5217 } 5218 index += reg_count; 5219 } 5220 } 5221 } 5222 soc24_grbm_select(adev, 0, 0, 0, 0); 5223 mutex_unlock(&adev->srbm_mutex); 5224 amdgpu_gfx_off_ctrl(adev, true); 5225 } 5226 5227 static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev) 5228 { 5229 /* Disable the pipe reset until the CPFW fully support it.*/ 5230 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 5231 return false; 5232 } 5233 5234 static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring) 5235 { 5236 struct amdgpu_device *adev = ring->adev; 5237 uint32_t reset_pipe = 0, clean_pipe = 0; 5238 int r; 5239 5240 if (!gfx_v12_pipe_reset_support(adev)) 5241 return -EOPNOTSUPP; 5242 5243 gfx_v12_0_set_safe_mode(adev, 0); 5244 mutex_lock(&adev->srbm_mutex); 5245 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5246 5247 switch (ring->pipe) { 5248 case 0: 5249 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5250 PFP_PIPE0_RESET, 1); 5251 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5252 ME_PIPE0_RESET, 1); 5253 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5254 PFP_PIPE0_RESET, 0); 5255 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5256 ME_PIPE0_RESET, 0); 5257 break; 5258 case 1: 5259 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5260 PFP_PIPE1_RESET, 1); 5261 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 5262 ME_PIPE1_RESET, 1); 5263 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5264 PFP_PIPE1_RESET, 0); 5265 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 5266 ME_PIPE1_RESET, 0); 5267 break; 5268 default: 5269 break; 5270 } 5271 5272 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 5273 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 5274 5275 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 5276 RS64_FW_UC_START_ADDR_LO; 5277 soc24_grbm_select(adev, 0, 0, 0, 0); 5278 mutex_unlock(&adev->srbm_mutex); 5279 gfx_v12_0_unset_safe_mode(adev, 0); 5280 5281 dev_info(adev->dev, "The ring %s pipe reset: %s\n", ring->name, 5282 r == 0 ? "successfully" : "failed"); 5283 /* Sometimes the ME start pc counter can't cache correctly, so the 5284 * PC check only as a reference and pipe reset result rely on the 5285 * later ring test. 5286 */ 5287 return 0; 5288 } 5289 5290 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, 5291 unsigned int vmid, 5292 struct amdgpu_fence *timedout_fence) 5293 { 5294 struct amdgpu_device *adev = ring->adev; 5295 bool use_mmio = false; 5296 int r; 5297 5298 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 5299 5300 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0); 5301 if (r) { 5302 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 5303 r = gfx_v12_reset_gfx_pipe(ring); 5304 if (r) 5305 return r; 5306 } 5307 5308 if (use_mmio) { 5309 r = gfx_v12_0_kgq_init_queue(ring, true); 5310 if (r) { 5311 dev_err(adev->dev, "failed to init kgq\n"); 5312 return r; 5313 } 5314 5315 r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 5316 if (r) { 5317 dev_err(adev->dev, "failed to remap kgq\n"); 5318 return r; 5319 } 5320 } 5321 5322 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 5323 } 5324 5325 static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring) 5326 { 5327 struct amdgpu_device *adev = ring->adev; 5328 uint32_t reset_pipe = 0, clean_pipe = 0; 5329 int r = 0; 5330 5331 if (!gfx_v12_pipe_reset_support(adev)) 5332 return -EOPNOTSUPP; 5333 5334 gfx_v12_0_set_safe_mode(adev, 0); 5335 mutex_lock(&adev->srbm_mutex); 5336 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5337 5338 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 5339 clean_pipe = reset_pipe; 5340 5341 if (adev->gfx.rs64_enable) { 5342 switch (ring->pipe) { 5343 case 0: 5344 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5345 MEC_PIPE0_RESET, 1); 5346 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5347 MEC_PIPE0_RESET, 0); 5348 break; 5349 case 1: 5350 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5351 MEC_PIPE1_RESET, 1); 5352 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5353 MEC_PIPE1_RESET, 0); 5354 break; 5355 case 2: 5356 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5357 MEC_PIPE2_RESET, 1); 5358 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5359 MEC_PIPE2_RESET, 0); 5360 break; 5361 case 3: 5362 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL, 5363 MEC_PIPE3_RESET, 1); 5364 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL, 5365 MEC_PIPE3_RESET, 0); 5366 break; 5367 default: 5368 break; 5369 } 5370 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe); 5371 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe); 5372 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 5373 RS64_FW_UC_START_ADDR_LO; 5374 } else { 5375 switch (ring->pipe) { 5376 case 0: 5377 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5378 MEC_ME1_PIPE0_RESET, 1); 5379 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5380 MEC_ME1_PIPE0_RESET, 0); 5381 break; 5382 case 1: 5383 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 5384 MEC_ME1_PIPE1_RESET, 1); 5385 clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL, 5386 MEC_ME1_PIPE1_RESET, 0); 5387 break; 5388 default: 5389 break; 5390 } 5391 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe); 5392 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe); 5393 /* Doesn't find the F32 MEC instruction pointer register, and suppose 5394 * the driver won't run into the F32 mode. 5395 */ 5396 } 5397 5398 soc24_grbm_select(adev, 0, 0, 0, 0); 5399 mutex_unlock(&adev->srbm_mutex); 5400 gfx_v12_0_unset_safe_mode(adev, 0); 5401 5402 dev_info(adev->dev, "The ring %s pipe resets: %s\n", ring->name, 5403 r == 0 ? "successfully" : "failed"); 5404 /* Need the ring test to verify the pipe reset result.*/ 5405 return 0; 5406 } 5407 5408 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, 5409 unsigned int vmid, 5410 struct amdgpu_fence *timedout_fence) 5411 { 5412 struct amdgpu_device *adev = ring->adev; 5413 int r; 5414 5415 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 5416 5417 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true, 0); 5418 if (r) { 5419 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); 5420 r = gfx_v12_0_reset_compute_pipe(ring); 5421 if (r) 5422 return r; 5423 } 5424 5425 r = gfx_v12_0_kcq_init_queue(ring, true); 5426 if (r) { 5427 dev_err(adev->dev, "failed to init kcq\n"); 5428 return r; 5429 } 5430 r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 5431 if (r) { 5432 dev_err(adev->dev, "failed to remap kcq\n"); 5433 return r; 5434 } 5435 5436 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 5437 } 5438 5439 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) 5440 { 5441 amdgpu_gfx_profile_ring_begin_use(ring); 5442 5443 amdgpu_gfx_enforce_isolation_ring_begin_use(ring); 5444 } 5445 5446 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring) 5447 { 5448 amdgpu_gfx_profile_ring_end_use(ring); 5449 5450 amdgpu_gfx_enforce_isolation_ring_end_use(ring); 5451 } 5452 5453 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { 5454 .name = "gfx_v12_0", 5455 .early_init = gfx_v12_0_early_init, 5456 .late_init = gfx_v12_0_late_init, 5457 .sw_init = gfx_v12_0_sw_init, 5458 .sw_fini = gfx_v12_0_sw_fini, 5459 .hw_init = gfx_v12_0_hw_init, 5460 .hw_fini = gfx_v12_0_hw_fini, 5461 .suspend = gfx_v12_0_suspend, 5462 .resume = gfx_v12_0_resume, 5463 .is_idle = gfx_v12_0_is_idle, 5464 .wait_for_idle = gfx_v12_0_wait_for_idle, 5465 .set_clockgating_state = gfx_v12_0_set_clockgating_state, 5466 .set_powergating_state = gfx_v12_0_set_powergating_state, 5467 .get_clockgating_state = gfx_v12_0_get_clockgating_state, 5468 .dump_ip_state = gfx_v12_ip_dump, 5469 .print_ip_state = gfx_v12_ip_print, 5470 }; 5471 5472 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { 5473 .type = AMDGPU_RING_TYPE_GFX, 5474 .align_mask = 0xff, 5475 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5476 .support_64bit_ptrs = true, 5477 .secure_submission_supported = true, 5478 .get_rptr = gfx_v12_0_ring_get_rptr_gfx, 5479 .get_wptr = gfx_v12_0_ring_get_wptr_gfx, 5480 .set_wptr = gfx_v12_0_ring_set_wptr_gfx, 5481 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5482 5 + /* COND_EXEC */ 5483 7 + /* PIPELINE_SYNC */ 5484 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5485 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5486 2 + /* VM_FLUSH */ 5487 8 + /* FENCE for VM_FLUSH */ 5488 5 + /* COND_EXEC */ 5489 7 + /* HDP_flush */ 5490 4 + /* VGT_flush */ 5491 31 + /* DE_META */ 5492 3 + /* CNTX_CTRL */ 5493 5 + /* HDP_INVL */ 5494 8 + 8 + /* FENCE x2 */ 5495 8 + /* gfx_v12_0_emit_mem_sync */ 5496 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5497 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */ 5498 .emit_ib = gfx_v12_0_ring_emit_ib_gfx, 5499 .emit_fence = gfx_v12_0_ring_emit_fence, 5500 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5501 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5502 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5503 .test_ring = gfx_v12_0_ring_test_ring, 5504 .test_ib = gfx_v12_0_ring_test_ib, 5505 .insert_nop = gfx_v12_ring_insert_nop, 5506 .pad_ib = amdgpu_ring_generic_pad_ib, 5507 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl, 5508 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec, 5509 .preempt_ib = gfx_v12_0_ring_preempt_ib, 5510 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5511 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5512 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5513 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5514 .reset = gfx_v12_0_reset_kgq, 5515 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5516 .begin_use = gfx_v12_0_ring_begin_use, 5517 .end_use = gfx_v12_0_ring_end_use, 5518 }; 5519 5520 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { 5521 .type = AMDGPU_RING_TYPE_COMPUTE, 5522 .align_mask = 0xff, 5523 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5524 .support_64bit_ptrs = true, 5525 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5526 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5527 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5528 .emit_frame_size = 5529 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5530 5 + /* hdp invalidate */ 5531 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5532 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5533 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5534 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5535 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */ 5536 8 + /* gfx_v12_0_emit_mem_sync */ 5537 2, /* gfx_v12_0_ring_emit_cleaner_shader */ 5538 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5539 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5540 .emit_fence = gfx_v12_0_ring_emit_fence, 5541 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync, 5542 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush, 5543 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5544 .test_ring = gfx_v12_0_ring_test_ring, 5545 .test_ib = gfx_v12_0_ring_test_ib, 5546 .insert_nop = gfx_v12_ring_insert_nop, 5547 .pad_ib = amdgpu_ring_generic_pad_ib, 5548 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5549 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5550 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5551 .emit_mem_sync = gfx_v12_0_emit_mem_sync, 5552 .reset = gfx_v12_0_reset_kcq, 5553 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, 5554 .begin_use = gfx_v12_0_ring_begin_use, 5555 .end_use = gfx_v12_0_ring_end_use, 5556 }; 5557 5558 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { 5559 .type = AMDGPU_RING_TYPE_KIQ, 5560 .align_mask = 0xff, 5561 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5562 .support_64bit_ptrs = true, 5563 .get_rptr = gfx_v12_0_ring_get_rptr_compute, 5564 .get_wptr = gfx_v12_0_ring_get_wptr_compute, 5565 .set_wptr = gfx_v12_0_ring_set_wptr_compute, 5566 .emit_frame_size = 5567 7 + /* gfx_v12_0_ring_emit_hdp_flush */ 5568 5 + /*hdp invalidate */ 5569 7 + /* gfx_v12_0_ring_emit_pipeline_sync */ 5570 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5571 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5572 2 + /* gfx_v12_0_ring_emit_vm_flush */ 5573 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5574 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */ 5575 .emit_ib = gfx_v12_0_ring_emit_ib_compute, 5576 .emit_fence = gfx_v12_0_ring_emit_fence_kiq, 5577 .test_ring = gfx_v12_0_ring_test_ring, 5578 .test_ib = gfx_v12_0_ring_test_ib, 5579 .insert_nop = amdgpu_ring_insert_nop, 5580 .pad_ib = amdgpu_ring_generic_pad_ib, 5581 .emit_rreg = gfx_v12_0_ring_emit_rreg, 5582 .emit_wreg = gfx_v12_0_ring_emit_wreg, 5583 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, 5584 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, 5585 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, 5586 }; 5587 5588 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) 5589 { 5590 int i; 5591 5592 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq; 5593 5594 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5595 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx; 5596 5597 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5598 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute; 5599 } 5600 5601 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = { 5602 .set = gfx_v12_0_set_eop_interrupt_state, 5603 .process = gfx_v12_0_eop_irq, 5604 }; 5605 5606 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = { 5607 .set = gfx_v12_0_set_priv_reg_fault_state, 5608 .process = gfx_v12_0_priv_reg_irq, 5609 }; 5610 5611 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = { 5612 .set = gfx_v12_0_set_bad_op_fault_state, 5613 .process = gfx_v12_0_bad_op_irq, 5614 }; 5615 5616 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = { 5617 .set = gfx_v12_0_set_priv_inst_fault_state, 5618 .process = gfx_v12_0_priv_inst_irq, 5619 }; 5620 5621 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev) 5622 { 5623 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5624 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs; 5625 5626 adev->gfx.priv_reg_irq.num_types = 1; 5627 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs; 5628 5629 adev->gfx.bad_op_irq.num_types = 1; 5630 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs; 5631 5632 adev->gfx.priv_inst_irq.num_types = 1; 5633 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs; 5634 } 5635 5636 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev) 5637 { 5638 if (adev->flags & AMD_IS_APU) 5639 adev->gfx.imu.mode = MISSION_MODE; 5640 else 5641 adev->gfx.imu.mode = DEBUG_MODE; 5642 5643 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs; 5644 } 5645 5646 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev) 5647 { 5648 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs; 5649 } 5650 5651 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev) 5652 { 5653 /* set gfx eng mqd */ 5654 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 5655 sizeof(struct v12_gfx_mqd); 5656 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 5657 gfx_v12_0_gfx_mqd_init; 5658 /* set compute eng mqd */ 5659 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 5660 sizeof(struct v12_compute_mqd); 5661 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 5662 gfx_v12_0_compute_mqd_init; 5663 } 5664 5665 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5666 u32 bitmap) 5667 { 5668 u32 data; 5669 5670 if (!bitmap) 5671 return; 5672 5673 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5674 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5675 5676 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 5677 } 5678 5679 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5680 { 5681 u32 data, wgp_bitmask; 5682 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 5683 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 5684 5685 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5686 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5687 5688 wgp_bitmask = 5689 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5690 5691 return (~data) & wgp_bitmask; 5692 } 5693 5694 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5695 { 5696 u32 wgp_idx, wgp_active_bitmap; 5697 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5698 5699 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev); 5700 cu_active_bitmap = 0; 5701 5702 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5703 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5704 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5705 if (wgp_active_bitmap & (1 << wgp_idx)) 5706 cu_active_bitmap |= cu_bitmap_per_wgp; 5707 } 5708 5709 return cu_active_bitmap; 5710 } 5711 5712 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, 5713 struct amdgpu_cu_info *cu_info) 5714 { 5715 int i, j, k, counter, active_cu_number = 0; 5716 u32 mask, bitmap; 5717 unsigned disable_masks[8 * 2]; 5718 5719 if (!adev || !cu_info) 5720 return -EINVAL; 5721 5722 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2); 5723 5724 mutex_lock(&adev->grbm_idx_mutex); 5725 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5726 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5727 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5728 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1)) 5729 continue; 5730 mask = 1; 5731 counter = 0; 5732 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5733 if (i < 8 && j < 2) 5734 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh( 5735 adev, disable_masks[i * 2 + j]); 5736 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev); 5737 5738 /** 5739 * GFX12 could support more than 4 SEs, while the bitmap 5740 * in cu_info struct is 4x4 and ioctl interface struct 5741 * drm_amdgpu_info_device should keep stable. 5742 * So we use last two columns of bitmap to store cu mask for 5743 * SEs 4 to 7, the layout of the bitmap is as below: 5744 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 5745 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 5746 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 5747 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 5748 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 5749 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 5750 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 5751 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 5752 */ 5753 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; 5754 5755 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5756 if (bitmap & mask) 5757 counter++; 5758 5759 mask <<= 1; 5760 } 5761 active_cu_number += counter; 5762 } 5763 } 5764 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5765 mutex_unlock(&adev->grbm_idx_mutex); 5766 5767 cu_info->number = active_cu_number; 5768 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5769 5770 return 0; 5771 } 5772 5773 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = { 5774 .type = AMD_IP_BLOCK_TYPE_GFX, 5775 .major = 12, 5776 .minor = 0, 5777 .rev = 0, 5778 .funcs = &gfx_v12_0_ip_funcs, 5779 }; 5780