1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/clock/qcom,gcc-msm8960.h> 5#include <dt-bindings/clock/qcom,lcc-msm8960.h> 6#include <dt-bindings/reset/qcom,gcc-msm8960.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8960.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,gsbi.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 model = "Qualcomm APQ8064"; 16 compatible = "qcom,apq8064"; 17 interrupt-parent = <&intc>; 18 19 reserved-memory { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges; 23 24 smem_region: smem@80000000 { 25 reg = <0x80000000 0x200000>; 26 no-map; 27 }; 28 29 wcnss_mem: wcnss@8f000000 { 30 reg = <0x8f000000 0x700000>; 31 no-map; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu0: cpu@0 { 40 compatible = "qcom,krait"; 41 enable-method = "qcom,kpss-acc-v1"; 42 device_type = "cpu"; 43 reg = <0>; 44 next-level-cache = <&l2>; 45 qcom,acc = <&acc0>; 46 qcom,saw = <&saw0>; 47 cpu-idle-states = <&cpu_spc>; 48 }; 49 50 cpu1: cpu@1 { 51 compatible = "qcom,krait"; 52 enable-method = "qcom,kpss-acc-v1"; 53 device_type = "cpu"; 54 reg = <1>; 55 next-level-cache = <&l2>; 56 qcom,acc = <&acc1>; 57 qcom,saw = <&saw1>; 58 cpu-idle-states = <&cpu_spc>; 59 }; 60 61 cpu2: cpu@2 { 62 compatible = "qcom,krait"; 63 enable-method = "qcom,kpss-acc-v1"; 64 device_type = "cpu"; 65 reg = <2>; 66 next-level-cache = <&l2>; 67 qcom,acc = <&acc2>; 68 qcom,saw = <&saw2>; 69 cpu-idle-states = <&cpu_spc>; 70 }; 71 72 cpu3: cpu@3 { 73 compatible = "qcom,krait"; 74 enable-method = "qcom,kpss-acc-v1"; 75 device_type = "cpu"; 76 reg = <3>; 77 next-level-cache = <&l2>; 78 qcom,acc = <&acc3>; 79 qcom,saw = <&saw3>; 80 cpu-idle-states = <&cpu_spc>; 81 }; 82 83 l2: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 }; 88 89 idle-states { 90 cpu_spc: cpu-spc { 91 compatible = "qcom,idle-state-spc", 92 "arm,idle-state"; 93 entry-latency-us = <400>; 94 exit-latency-us = <900>; 95 min-residency-us = <3000>; 96 }; 97 }; 98 }; 99 100 memory@0 { 101 device_type = "memory"; 102 reg = <0x0 0x0>; 103 }; 104 105 thermal-zones { 106 cpu0-thermal { 107 polling-delay-passive = <250>; 108 polling-delay = <1000>; 109 110 thermal-sensors = <&tsens 7>; 111 coefficients = <1199 0>; 112 113 trips { 114 cpu_alert0: trip0 { 115 temperature = <75000>; 116 hysteresis = <2000>; 117 type = "passive"; 118 }; 119 cpu_crit0: trip1 { 120 temperature = <110000>; 121 hysteresis = <2000>; 122 type = "critical"; 123 }; 124 }; 125 }; 126 127 cpu1-thermal { 128 polling-delay-passive = <250>; 129 polling-delay = <1000>; 130 131 thermal-sensors = <&tsens 8>; 132 coefficients = <1132 0>; 133 134 trips { 135 cpu_alert1: trip0 { 136 temperature = <75000>; 137 hysteresis = <2000>; 138 type = "passive"; 139 }; 140 cpu_crit1: trip1 { 141 temperature = <110000>; 142 hysteresis = <2000>; 143 type = "critical"; 144 }; 145 }; 146 }; 147 148 cpu2-thermal { 149 polling-delay-passive = <250>; 150 polling-delay = <1000>; 151 152 thermal-sensors = <&tsens 9>; 153 coefficients = <1199 0>; 154 155 trips { 156 cpu_alert2: trip0 { 157 temperature = <75000>; 158 hysteresis = <2000>; 159 type = "passive"; 160 }; 161 cpu_crit2: trip1 { 162 temperature = <110000>; 163 hysteresis = <2000>; 164 type = "critical"; 165 }; 166 }; 167 }; 168 169 cpu3-thermal { 170 polling-delay-passive = <250>; 171 polling-delay = <1000>; 172 173 thermal-sensors = <&tsens 10>; 174 coefficients = <1132 0>; 175 176 trips { 177 cpu_alert3: trip0 { 178 temperature = <75000>; 179 hysteresis = <2000>; 180 type = "passive"; 181 }; 182 cpu_crit3: trip1 { 183 temperature = <110000>; 184 hysteresis = <2000>; 185 type = "critical"; 186 }; 187 }; 188 }; 189 }; 190 191 cpu-pmu { 192 compatible = "qcom,krait-pmu"; 193 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 194 }; 195 196 clocks { 197 cxo_board: cxo_board { 198 compatible = "fixed-clock"; 199 #clock-cells = <0>; 200 clock-frequency = <19200000>; 201 }; 202 203 pxo_board: pxo_board { 204 compatible = "fixed-clock"; 205 #clock-cells = <0>; 206 clock-frequency = <27000000>; 207 }; 208 209 sleep_clk: sleep_clk { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <32768>; 213 }; 214 }; 215 216 smem { 217 compatible = "qcom,smem"; 218 memory-region = <&smem_region>; 219 220 hwlocks = <&sfpb_mutex 3>; 221 }; 222 223 smsm { 224 compatible = "qcom,smsm"; 225 226 #address-cells = <1>; 227 #size-cells = <0>; 228 229 qcom,ipc-1 = <&l2cc 8 4>; 230 qcom,ipc-2 = <&l2cc 8 14>; 231 qcom,ipc-3 = <&l2cc 8 23>; 232 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; 233 234 apps_smsm: apps@0 { 235 reg = <0>; 236 #qcom,smem-state-cells = <1>; 237 }; 238 239 modem_smsm: modem@1 { 240 reg = <1>; 241 interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>; 242 243 interrupt-controller; 244 #interrupt-cells = <2>; 245 }; 246 247 q6_smsm: q6@2 { 248 reg = <2>; 249 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 250 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 }; 254 255 wcnss_smsm: wcnss@3 { 256 reg = <3>; 257 interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>; 258 259 interrupt-controller; 260 #interrupt-cells = <2>; 261 }; 262 263 dsps_smsm: dsps@4 { 264 reg = <4>; 265 interrupts = <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>; 266 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 }; 270 }; 271 272 firmware { 273 scm { 274 compatible = "qcom,scm-apq8064", "qcom,scm"; 275 276 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; 277 clock-names = "core"; 278 }; 279 }; 280 281 replicator { 282 compatible = "arm,coresight-static-replicator"; 283 284 clocks = <&rpmcc RPM_QDSS_CLK>; 285 clock-names = "apb_pclk"; 286 287 in-ports { 288 port { 289 replicator_in: endpoint { 290 remote-endpoint = <&funnel_out>; 291 }; 292 }; 293 }; 294 295 out-ports { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 299 port@0 { 300 reg = <0>; 301 replicator_out0: endpoint { 302 remote-endpoint = <&etb_in>; 303 }; 304 }; 305 306 port@1 { 307 reg = <1>; 308 replicator_out1: endpoint { 309 remote-endpoint = <&tpiu_in>; 310 }; 311 }; 312 }; 313 }; 314 315 soc: soc { 316 #address-cells = <1>; 317 #size-cells = <1>; 318 ranges; 319 compatible = "simple-bus"; 320 321 tlmm_pinmux: pinctrl@800000 { 322 compatible = "qcom,apq8064-pinctrl"; 323 reg = <0x800000 0x4000>; 324 325 gpio-controller; 326 gpio-ranges = <&tlmm_pinmux 0 0 90>; 327 #gpio-cells = <2>; 328 interrupt-controller; 329 #interrupt-cells = <2>; 330 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 331 332 pinctrl-names = "default"; 333 pinctrl-0 = <&ps_hold_default_state>; 334 }; 335 336 sfpb_mutex: hwmutex@1200600 { 337 compatible = "qcom,sfpb-mutex"; 338 reg = <0x01200600 0x100>; 339 #hwlock-cells = <1>; 340 }; 341 342 intc: interrupt-controller@2000000 { 343 compatible = "qcom,msm-qgic2"; 344 interrupt-controller; 345 #interrupt-cells = <3>; 346 reg = <0x02000000 0x1000>, 347 <0x02002000 0x1000>; 348 }; 349 350 timer@200a000 { 351 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", 352 "qcom,msm-timer"; 353 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 354 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 355 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 356 reg = <0x0200a000 0x100>; 357 clock-frequency = <27000000>; 358 clocks = <&sleep_clk>; 359 clock-names = "sleep"; 360 cpu-offset = <0x80000>; 361 }; 362 363 acc0: clock-controller@2088000 { 364 compatible = "qcom,kpss-acc-v1"; 365 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 366 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 367 clock-names = "pll8_vote", "pxo"; 368 clock-output-names = "acpu0_aux"; 369 #clock-cells = <0>; 370 }; 371 372 acc1: clock-controller@2098000 { 373 compatible = "qcom,kpss-acc-v1"; 374 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 375 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 376 clock-names = "pll8_vote", "pxo"; 377 clock-output-names = "acpu1_aux"; 378 #clock-cells = <0>; 379 }; 380 381 acc2: clock-controller@20a8000 { 382 compatible = "qcom,kpss-acc-v1"; 383 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; 384 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 385 clock-names = "pll8_vote", "pxo"; 386 clock-output-names = "acpu2_aux"; 387 #clock-cells = <0>; 388 }; 389 390 acc3: clock-controller@20b8000 { 391 compatible = "qcom,kpss-acc-v1"; 392 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; 393 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 394 clock-names = "pll8_vote", "pxo"; 395 clock-output-names = "acpu3_aux"; 396 #clock-cells = <0>; 397 }; 398 399 saw0: power-manager@2089000 { 400 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 401 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 402 403 saw0_vreg: regulator { 404 regulator-min-microvolt = <850000>; 405 regulator-max-microvolt = <1300000>; 406 }; 407 }; 408 409 saw1: power-manager@2099000 { 410 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 411 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 412 413 saw1_vreg: regulator { 414 regulator-min-microvolt = <850000>; 415 regulator-max-microvolt = <1300000>; 416 }; 417 }; 418 419 saw2: power-manager@20a9000 { 420 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 421 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; 422 423 saw2_vreg: regulator { 424 regulator-min-microvolt = <850000>; 425 regulator-max-microvolt = <1300000>; 426 }; 427 }; 428 429 saw3: power-manager@20b9000 { 430 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 431 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; 432 433 saw3_vreg: regulator { 434 regulator-min-microvolt = <850000>; 435 regulator-max-microvolt = <1300000>; 436 }; 437 }; 438 439 sps_sic_non_secure: interrupt-controller@12100000 { 440 compatible = "qcom,apq8064-sps-sic", "syscon"; 441 reg = <0x12100000 0x10000>; 442 }; 443 444 gsbi1: gsbi@12440000 { 445 status = "disabled"; 446 compatible = "qcom,gsbi-v1.0.0"; 447 cell-index = <1>; 448 reg = <0x12440000 0x100>; 449 clocks = <&gcc GSBI1_H_CLK>; 450 clock-names = "iface"; 451 #address-cells = <1>; 452 #size-cells = <1>; 453 ranges; 454 455 syscon-tcsr = <&tcsr>; 456 457 gsbi1_serial: serial@12450000 { 458 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 459 reg = <0x12450000 0x100>, 460 <0x12400000 0x03>; 461 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 463 clock-names = "core", "iface"; 464 status = "disabled"; 465 }; 466 467 gsbi1_i2c: i2c@12460000 { 468 compatible = "qcom,i2c-qup-v1.1.1"; 469 pinctrl-0 = <&i2c1_default_state>; 470 pinctrl-1 = <&i2c1_sleep_state>; 471 pinctrl-names = "default", "sleep"; 472 reg = <0x12460000 0x1000>; 473 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 475 clock-names = "core", "iface"; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 status = "disabled"; 479 }; 480 481 }; 482 483 gsbi2: gsbi@12480000 { 484 status = "disabled"; 485 compatible = "qcom,gsbi-v1.0.0"; 486 cell-index = <2>; 487 reg = <0x12480000 0x100>; 488 clocks = <&gcc GSBI2_H_CLK>; 489 clock-names = "iface"; 490 #address-cells = <1>; 491 #size-cells = <1>; 492 ranges; 493 494 syscon-tcsr = <&tcsr>; 495 496 gsbi2_i2c: i2c@124a0000 { 497 compatible = "qcom,i2c-qup-v1.1.1"; 498 reg = <0x124a0000 0x1000>; 499 pinctrl-0 = <&i2c2_default_state>; 500 pinctrl-1 = <&i2c2_sleep_state>; 501 pinctrl-names = "default", "sleep"; 502 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 504 clock-names = "core", "iface"; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 status = "disabled"; 508 }; 509 }; 510 511 gsbi3: gsbi@16200000 { 512 status = "disabled"; 513 compatible = "qcom,gsbi-v1.0.0"; 514 cell-index = <3>; 515 reg = <0x16200000 0x100>; 516 clocks = <&gcc GSBI3_H_CLK>; 517 clock-names = "iface"; 518 #address-cells = <1>; 519 #size-cells = <1>; 520 ranges; 521 gsbi3_i2c: i2c@16280000 { 522 compatible = "qcom,i2c-qup-v1.1.1"; 523 pinctrl-0 = <&i2c3_default_state>; 524 pinctrl-1 = <&i2c3_sleep_state>; 525 pinctrl-names = "default", "sleep"; 526 reg = <0x16280000 0x1000>; 527 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&gcc GSBI3_QUP_CLK>, 529 <&gcc GSBI3_H_CLK>; 530 clock-names = "core", "iface"; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 status = "disabled"; 534 }; 535 }; 536 537 gsbi4: gsbi@16300000 { 538 status = "disabled"; 539 compatible = "qcom,gsbi-v1.0.0"; 540 cell-index = <4>; 541 reg = <0x16300000 0x03>; 542 clocks = <&gcc GSBI4_H_CLK>; 543 clock-names = "iface"; 544 #address-cells = <1>; 545 #size-cells = <1>; 546 ranges; 547 548 gsbi4_serial: serial@16340000 { 549 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 550 reg = <0x16340000 0x100>, 551 <0x16300000 0x3>; 552 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 553 pinctrl-0 = <&gsbi4_uart_pin_a>; 554 pinctrl-names = "default"; 555 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 556 clock-names = "core", "iface"; 557 status = "disabled"; 558 }; 559 560 gsbi4_i2c: i2c@16380000 { 561 compatible = "qcom,i2c-qup-v1.1.1"; 562 pinctrl-0 = <&i2c4_default_state>; 563 pinctrl-1 = <&i2c4_sleep_state>; 564 pinctrl-names = "default", "sleep"; 565 reg = <0x16380000 0x1000>; 566 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&gcc GSBI4_QUP_CLK>, 568 <&gcc GSBI4_H_CLK>; 569 clock-names = "core", "iface"; 570 status = "disabled"; 571 }; 572 }; 573 574 gsbi5: gsbi@1a200000 { 575 status = "disabled"; 576 compatible = "qcom,gsbi-v1.0.0"; 577 cell-index = <5>; 578 reg = <0x1a200000 0x03>; 579 clocks = <&gcc GSBI5_H_CLK>; 580 clock-names = "iface"; 581 #address-cells = <1>; 582 #size-cells = <1>; 583 ranges; 584 585 gsbi5_serial: serial@1a240000 { 586 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 587 reg = <0x1a240000 0x100>, 588 <0x1a200000 0x03>; 589 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 591 clock-names = "core", "iface"; 592 status = "disabled"; 593 }; 594 595 gsbi5_spi: spi@1a280000 { 596 compatible = "qcom,spi-qup-v1.1.1"; 597 reg = <0x1a280000 0x1000>; 598 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 599 pinctrl-0 = <&spi5_default_state>; 600 pinctrl-1 = <&spi5_sleep_state>; 601 pinctrl-names = "default", "sleep"; 602 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 603 clock-names = "core", "iface"; 604 status = "disabled"; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 }; 608 }; 609 610 gsbi6: gsbi@16500000 { 611 status = "disabled"; 612 compatible = "qcom,gsbi-v1.0.0"; 613 cell-index = <6>; 614 reg = <0x16500000 0x03>; 615 clocks = <&gcc GSBI6_H_CLK>; 616 clock-names = "iface"; 617 #address-cells = <1>; 618 #size-cells = <1>; 619 ranges; 620 621 gsbi6_serial: serial@16540000 { 622 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 623 reg = <0x16540000 0x100>, 624 <0x16500000 0x03>; 625 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 627 clock-names = "core", "iface"; 628 status = "disabled"; 629 }; 630 631 gsbi6_i2c: i2c@16580000 { 632 compatible = "qcom,i2c-qup-v1.1.1"; 633 pinctrl-0 = <&i2c6_default_state>; 634 pinctrl-1 = <&i2c6_sleep_state>; 635 pinctrl-names = "default", "sleep"; 636 reg = <0x16580000 0x1000>; 637 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&gcc GSBI6_QUP_CLK>, 639 <&gcc GSBI6_H_CLK>; 640 clock-names = "core", "iface"; 641 status = "disabled"; 642 }; 643 }; 644 645 gsbi7: gsbi@16600000 { 646 status = "disabled"; 647 compatible = "qcom,gsbi-v1.0.0"; 648 cell-index = <7>; 649 reg = <0x16600000 0x100>; 650 clocks = <&gcc GSBI7_H_CLK>; 651 clock-names = "iface"; 652 #address-cells = <1>; 653 #size-cells = <1>; 654 ranges; 655 syscon-tcsr = <&tcsr>; 656 657 gsbi7_serial: serial@16640000 { 658 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 659 reg = <0x16640000 0x1000>, 660 <0x16600000 0x1000>; 661 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 663 clock-names = "core", "iface"; 664 status = "disabled"; 665 }; 666 667 gsbi7_i2c: i2c@16680000 { 668 compatible = "qcom,i2c-qup-v1.1.1"; 669 pinctrl-0 = <&i2c7_default_state>; 670 pinctrl-1 = <&i2c7_sleep_state>; 671 pinctrl-names = "default", "sleep"; 672 reg = <0x16680000 0x1000>; 673 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&gcc GSBI7_QUP_CLK>, 675 <&gcc GSBI7_H_CLK>; 676 clock-names = "core", "iface"; 677 status = "disabled"; 678 }; 679 }; 680 681 rng@1a500000 { 682 compatible = "qcom,prng"; 683 reg = <0x1a500000 0x200>; 684 clocks = <&gcc PRNG_CLK>; 685 clock-names = "core"; 686 }; 687 688 ssbi2: ssbi@c00000 { 689 compatible = "qcom,ssbi"; 690 reg = <0x00c00000 0x1000>; 691 qcom,controller-type = "pmic-arbiter"; 692 }; 693 694 ssbi: ssbi@500000 { 695 compatible = "qcom,ssbi"; 696 reg = <0x00500000 0x1000>; 697 qcom,controller-type = "pmic-arbiter"; 698 }; 699 700 qfprom: efuse@700000 { 701 compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; 702 reg = <0x00700000 0x1000>; 703 #address-cells = <1>; 704 #size-cells = <1>; 705 706 tsens_calib: calib@404 { 707 reg = <0x404 0x10>; 708 }; 709 tsens_backup: backup-calib@414 { 710 reg = <0x414 0x10>; 711 }; 712 }; 713 714 gcc: clock-controller@900000 { 715 compatible = "qcom,gcc-apq8064", "syscon"; 716 reg = <0x00900000 0x4000>; 717 #clock-cells = <1>; 718 #reset-cells = <1>; 719 clocks = <&cxo_board>, 720 <&pxo_board>, 721 <&lcc PLL4>; 722 clock-names = "cxo", "pxo", "pll4"; 723 724 tsens: thermal-sensor { 725 compatible = "qcom,msm8960-tsens"; 726 727 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 728 nvmem-cell-names = "calib", "calib_backup"; 729 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 730 interrupt-names = "uplow"; 731 732 #qcom,sensors = <11>; 733 #thermal-sensor-cells = <1>; 734 }; 735 }; 736 737 lcc: clock-controller@28000000 { 738 compatible = "qcom,lcc-apq8064"; 739 reg = <0x28000000 0x1000>; 740 #clock-cells = <1>; 741 #reset-cells = <1>; 742 clocks = <&pxo_board>, 743 <&gcc PLL4_VOTE>, 744 <0>, 745 <0>, <0>, 746 <0>, <0>, 747 <0>; 748 clock-names = "pxo", 749 "pll4_vote", 750 "mi2s_codec_clk", 751 "codec_i2s_mic_codec_clk", 752 "spare_i2s_mic_codec_clk", 753 "codec_i2s_spkr_codec_clk", 754 "spare_i2s_spkr_codec_clk", 755 "pcm_codec_clk"; 756 }; 757 758 mmcc: clock-controller@4000000 { 759 compatible = "qcom,mmcc-apq8064"; 760 reg = <0x4000000 0x1000>; 761 #clock-cells = <1>; 762 #power-domain-cells = <1>; 763 #reset-cells = <1>; 764 clocks = <&pxo_board>, 765 <&gcc PLL3>, 766 <&gcc PLL8_VOTE>, 767 <&dsi0_phy 1>, 768 <&dsi0_phy 0>, 769 <&dsi1_phy 1>, 770 <&dsi1_phy 0>, 771 <&hdmi_phy>, 772 <&mdp>; 773 clock-names = "pxo", 774 "pll3", 775 "pll8_vote", 776 "dsi1pll", 777 "dsi1pllbyte", 778 "dsi2pll", 779 "dsi2pllbyte", 780 "hdmipll", 781 "lvdspll"; 782 }; 783 784 l2cc: clock-controller@2011000 { 785 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; 786 reg = <0x2011000 0x1000>; 787 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 788 clock-names = "pll8_vote", "pxo"; 789 #clock-cells = <0>; 790 }; 791 792 rpm: rpm@108000 { 793 compatible = "qcom,rpm-apq8064"; 794 reg = <0x108000 0x1000>; 795 qcom,ipc = <&l2cc 0x8 2>; 796 797 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 798 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 799 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 800 interrupt-names = "ack", "err", "wakeup"; 801 802 rpmcc: clock-controller { 803 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; 804 #clock-cells = <1>; 805 clocks = <&pxo_board>, <&cxo_board>; 806 clock-names = "pxo", "cxo"; 807 }; 808 }; 809 810 usb1: usb@12500000 { 811 compatible = "qcom,ci-hdrc"; 812 reg = <0x12500000 0x200>, 813 <0x12500200 0x200>; 814 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 816 clock-names = "core", "iface"; 817 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 818 assigned-clock-rates = <60000000>; 819 resets = <&gcc USB_HS1_RESET>; 820 reset-names = "core"; 821 phy_type = "ulpi"; 822 ahb-burst-config = <0>; 823 phys = <&usb_hs1_phy>; 824 phy-names = "usb-phy"; 825 status = "disabled"; 826 #reset-cells = <1>; 827 828 ulpi { 829 usb_hs1_phy: phy { 830 compatible = "qcom,usb-hs-phy-apq8064", 831 "qcom,usb-hs-phy"; 832 clocks = <&sleep_clk>, <&cxo_board>; 833 clock-names = "sleep", "ref"; 834 resets = <&usb1 0>; 835 reset-names = "por"; 836 #phy-cells = <0>; 837 }; 838 }; 839 }; 840 841 usb3: usb@12520000 { 842 compatible = "qcom,ci-hdrc"; 843 reg = <0x12520000 0x200>, 844 <0x12520200 0x200>; 845 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; 847 clock-names = "core", "iface"; 848 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; 849 assigned-clock-rates = <60000000>; 850 resets = <&gcc USB_HS3_RESET>; 851 reset-names = "core"; 852 phy_type = "ulpi"; 853 ahb-burst-config = <0>; 854 phys = <&usb_hs3_phy>; 855 phy-names = "usb-phy"; 856 status = "disabled"; 857 #reset-cells = <1>; 858 859 ulpi { 860 usb_hs3_phy: phy { 861 compatible = "qcom,usb-hs-phy-apq8064", 862 "qcom,usb-hs-phy"; 863 #phy-cells = <0>; 864 clocks = <&sleep_clk>, <&cxo_board>; 865 clock-names = "sleep", "ref"; 866 resets = <&usb3 0>; 867 reset-names = "por"; 868 }; 869 }; 870 }; 871 872 usb4: usb@12530000 { 873 compatible = "qcom,ci-hdrc"; 874 reg = <0x12530000 0x200>, 875 <0x12530200 0x200>; 876 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; 878 clock-names = "core", "iface"; 879 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; 880 assigned-clock-rates = <60000000>; 881 resets = <&gcc USB_HS4_RESET>; 882 reset-names = "core"; 883 phy_type = "ulpi"; 884 ahb-burst-config = <0>; 885 phys = <&usb_hs4_phy>; 886 phy-names = "usb-phy"; 887 status = "disabled"; 888 #reset-cells = <1>; 889 890 ulpi { 891 usb_hs4_phy: phy { 892 compatible = "qcom,usb-hs-phy-apq8064", 893 "qcom,usb-hs-phy"; 894 #phy-cells = <0>; 895 clocks = <&sleep_clk>, <&cxo_board>; 896 clock-names = "sleep", "ref"; 897 resets = <&usb4 0>; 898 reset-names = "por"; 899 }; 900 }; 901 }; 902 903 sata_phy0: phy@1b400000 { 904 compatible = "qcom,apq8064-sata-phy"; 905 status = "disabled"; 906 reg = <0x1b400000 0x200>; 907 clocks = <&gcc SATA_PHY_CFG_CLK>; 908 clock-names = "cfg"; 909 #phy-cells = <0>; 910 }; 911 912 sata0: sata@29000000 { 913 compatible = "qcom,apq8064-ahci", "generic-ahci"; 914 status = "disabled"; 915 reg = <0x29000000 0x180>; 916 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 917 918 clocks = <&gcc SFAB_SATA_S_H_CLK>, 919 <&gcc SATA_H_CLK>, 920 <&gcc SATA_A_CLK>, 921 <&gcc SATA_RXOOB_CLK>, 922 <&gcc SATA_PMALIVE_CLK>; 923 clock-names = "slave_iface", 924 "iface", 925 "core", 926 "rxoob", 927 "pmalive"; 928 929 assigned-clocks = <&gcc SATA_RXOOB_CLK>, 930 <&gcc SATA_PMALIVE_CLK>; 931 assigned-clock-rates = <100000000>, <100000000>; 932 933 phys = <&sata_phy0>; 934 phy-names = "sata-phy"; 935 ports-implemented = <0x1>; 936 }; 937 938 sdcc3: mmc@12180000 { 939 compatible = "arm,pl18x", "arm,primecell"; 940 arm,primecell-periphid = <0x00051180>; 941 status = "disabled"; 942 reg = <0x12180000 0x2000>; 943 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 945 clock-names = "mclk", "apb_pclk"; 946 bus-width = <4>; 947 cap-sd-highspeed; 948 cap-mmc-highspeed; 949 max-frequency = <192000000>; 950 no-1-8-v; 951 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 952 dma-names = "tx", "rx"; 953 }; 954 955 sdcc3bam: dma-controller@12182000 { 956 compatible = "qcom,bam-v1.3.0"; 957 reg = <0x12182000 0x8000>; 958 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&gcc SDC3_H_CLK>; 960 clock-names = "bam_clk"; 961 #dma-cells = <1>; 962 qcom,ee = <0>; 963 }; 964 965 sdcc4: mmc@121c0000 { 966 compatible = "arm,pl18x", "arm,primecell"; 967 arm,primecell-periphid = <0x00051180>; 968 status = "disabled"; 969 reg = <0x121c0000 0x2000>; 970 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 972 clock-names = "mclk", "apb_pclk"; 973 bus-width = <4>; 974 cap-sd-highspeed; 975 cap-mmc-highspeed; 976 max-frequency = <48000000>; 977 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; 978 dma-names = "tx", "rx"; 979 pinctrl-names = "default"; 980 pinctrl-0 = <&sdc4_default_state>; 981 }; 982 983 sdcc4bam: dma-controller@121c2000 { 984 compatible = "qcom,bam-v1.3.0"; 985 reg = <0x121c2000 0x8000>; 986 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&gcc SDC4_H_CLK>; 988 clock-names = "bam_clk"; 989 #dma-cells = <1>; 990 qcom,ee = <0>; 991 }; 992 993 sdcc1: mmc@12400000 { 994 status = "disabled"; 995 compatible = "arm,pl18x", "arm,primecell"; 996 pinctrl-names = "default"; 997 pinctrl-0 = <&sdcc1_default_state>; 998 arm,primecell-periphid = <0x00051180>; 999 reg = <0x12400000 0x2000>; 1000 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1002 clock-names = "mclk", "apb_pclk"; 1003 bus-width = <8>; 1004 max-frequency = <96000000>; 1005 non-removable; 1006 cap-sd-highspeed; 1007 cap-mmc-highspeed; 1008 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 1009 dma-names = "tx", "rx"; 1010 }; 1011 1012 sdcc1bam: dma-controller@12402000 { 1013 compatible = "qcom,bam-v1.3.0"; 1014 reg = <0x12402000 0x8000>; 1015 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&gcc SDC1_H_CLK>; 1017 clock-names = "bam_clk"; 1018 #dma-cells = <1>; 1019 qcom,ee = <0>; 1020 }; 1021 1022 tcsr: syscon@1a400000 { 1023 compatible = "qcom,tcsr-apq8064", "syscon"; 1024 reg = <0x1a400000 0x100>; 1025 }; 1026 1027 gpu: gpu@4300000 { 1028 compatible = "qcom,adreno-320.2", "qcom,adreno"; 1029 reg = <0x04300000 0x20000>; 1030 reg-names = "kgsl_3d0_reg_memory"; 1031 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1032 interrupt-names = "kgsl_3d0_irq"; 1033 clock-names = 1034 "core", 1035 "iface", 1036 "mem", 1037 "mem_iface"; 1038 clocks = 1039 <&mmcc GFX3D_CLK>, 1040 <&mmcc GFX3D_AHB_CLK>, 1041 <&mmcc GFX3D_AXI_CLK>, 1042 <&mmcc MMSS_IMEM_AHB_CLK>; 1043 1044 iommus = <&gfx3d 0 1045 &gfx3d 1 1046 &gfx3d 2 1047 &gfx3d 3 1048 &gfx3d 4 1049 &gfx3d 5 1050 &gfx3d 6 1051 &gfx3d 7 1052 &gfx3d 8 1053 &gfx3d 9 1054 &gfx3d 10 1055 &gfx3d 11 1056 &gfx3d 12 1057 &gfx3d 13 1058 &gfx3d 14 1059 &gfx3d 15 1060 &gfx3d 16 1061 &gfx3d 17 1062 &gfx3d 18 1063 &gfx3d 19 1064 &gfx3d 20 1065 &gfx3d 21 1066 &gfx3d 22 1067 &gfx3d 23 1068 &gfx3d 24 1069 &gfx3d 25 1070 &gfx3d 26 1071 &gfx3d 27 1072 &gfx3d 28 1073 &gfx3d 29 1074 &gfx3d 30 1075 &gfx3d 31 1076 &gfx3d1 0 1077 &gfx3d1 1 1078 &gfx3d1 2 1079 &gfx3d1 3 1080 &gfx3d1 4 1081 &gfx3d1 5 1082 &gfx3d1 6 1083 &gfx3d1 7 1084 &gfx3d1 8 1085 &gfx3d1 9 1086 &gfx3d1 10 1087 &gfx3d1 11 1088 &gfx3d1 12 1089 &gfx3d1 13 1090 &gfx3d1 14 1091 &gfx3d1 15 1092 &gfx3d1 16 1093 &gfx3d1 17 1094 &gfx3d1 18 1095 &gfx3d1 19 1096 &gfx3d1 20 1097 &gfx3d1 21 1098 &gfx3d1 22 1099 &gfx3d1 23 1100 &gfx3d1 24 1101 &gfx3d1 25 1102 &gfx3d1 26 1103 &gfx3d1 27 1104 &gfx3d1 28 1105 &gfx3d1 29 1106 &gfx3d1 30 1107 &gfx3d1 31>; 1108 1109 operating-points-v2 = <&gpu_opp_table>; 1110 1111 gpu_opp_table: opp-table { 1112 compatible = "operating-points-v2"; 1113 1114 opp-450000000 { 1115 opp-hz = /bits/ 64 <450000000>; 1116 }; 1117 1118 opp-27000000 { 1119 opp-hz = /bits/ 64 <27000000>; 1120 }; 1121 }; 1122 }; 1123 1124 mmss_sfpb: syscon@5700000 { 1125 compatible = "qcom,apq8064-mmss-sfpb", "syscon"; 1126 reg = <0x5700000 0x70>; 1127 }; 1128 1129 dsi0: dsi@4700000 { 1130 compatible = "qcom,apq8064-dsi-ctrl", 1131 "qcom,mdss-dsi-ctrl"; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1135 reg = <0x04700000 0x200>; 1136 reg-names = "dsi_ctrl"; 1137 1138 clocks = <&mmcc DSI_M_AHB_CLK>, 1139 <&mmcc DSI_S_AHB_CLK>, 1140 <&mmcc AMP_AHB_CLK>, 1141 <&mmcc DSI_CLK>, 1142 <&mmcc DSI1_BYTE_CLK>, 1143 <&mmcc DSI_PIXEL_CLK>, 1144 <&mmcc DSI1_ESC_CLK>; 1145 clock-names = "iface", "bus", "core_mmss", 1146 "src", "byte", "pixel", 1147 "core"; 1148 1149 assigned-clocks = <&mmcc DSI1_BYTE_SRC>, 1150 <&mmcc DSI1_ESC_SRC>, 1151 <&mmcc DSI_SRC>, 1152 <&mmcc DSI_PIXEL_SRC>; 1153 assigned-clock-parents = <&dsi0_phy 0>, 1154 <&dsi0_phy 0>, 1155 <&dsi0_phy 1>, 1156 <&dsi0_phy 1>; 1157 syscon-sfpb = <&mmss_sfpb>; 1158 phys = <&dsi0_phy>; 1159 status = "disabled"; 1160 1161 ports { 1162 #address-cells = <1>; 1163 #size-cells = <0>; 1164 1165 port@0 { 1166 reg = <0>; 1167 dsi0_in: endpoint { 1168 }; 1169 }; 1170 1171 port@1 { 1172 reg = <1>; 1173 dsi0_out: endpoint { 1174 }; 1175 }; 1176 }; 1177 }; 1178 1179 1180 dsi0_phy: phy@4700200 { 1181 compatible = "qcom,dsi-phy-28nm-8960"; 1182 #clock-cells = <1>; 1183 #phy-cells = <0>; 1184 1185 reg = <0x04700200 0x100>, 1186 <0x04700300 0x200>, 1187 <0x04700500 0x5c>; 1188 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; 1189 clock-names = "iface", "ref"; 1190 clocks = <&mmcc DSI_M_AHB_CLK>, 1191 <&pxo_board>; 1192 status = "disabled"; 1193 }; 1194 1195 dsi1: dsi@5800000 { 1196 compatible = "qcom,mdss-dsi-ctrl"; 1197 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1198 reg = <0x05800000 0x200>; 1199 reg-names = "dsi_ctrl"; 1200 1201 clocks = <&mmcc DSI2_M_AHB_CLK>, 1202 <&mmcc DSI2_S_AHB_CLK>, 1203 <&mmcc AMP_AHB_CLK>, 1204 <&mmcc DSI2_CLK>, 1205 <&mmcc DSI2_BYTE_CLK>, 1206 <&mmcc DSI2_PIXEL_CLK>, 1207 <&mmcc DSI2_ESC_CLK>; 1208 clock-names = "iface", 1209 "bus", 1210 "core_mmss", 1211 "src", 1212 "byte", 1213 "pixel", 1214 "core"; 1215 1216 assigned-clocks = <&mmcc DSI2_BYTE_SRC>, 1217 <&mmcc DSI2_ESC_SRC>, 1218 <&mmcc DSI2_SRC>, 1219 <&mmcc DSI2_PIXEL_SRC>; 1220 assigned-clock-parents = <&dsi1_phy 0>, 1221 <&dsi1_phy 0>, 1222 <&dsi1_phy 1>, 1223 <&dsi1_phy 1>; 1224 1225 syscon-sfpb = <&mmss_sfpb>; 1226 phys = <&dsi1_phy>; 1227 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 1231 status = "disabled"; 1232 1233 ports { 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 1237 port@0 { 1238 reg = <0>; 1239 dsi1_in: endpoint { 1240 }; 1241 }; 1242 1243 port@1 { 1244 reg = <1>; 1245 dsi1_out: endpoint { 1246 }; 1247 }; 1248 }; 1249 }; 1250 1251 1252 dsi1_phy: dsi-phy@5800200 { 1253 compatible = "qcom,dsi-phy-28nm-8960"; 1254 reg = <0x05800200 0x100>, 1255 <0x05800300 0x200>, 1256 <0x05800500 0x5c>; 1257 reg-names = "dsi_pll", 1258 "dsi_phy", 1259 "dsi_phy_regulator"; 1260 clock-names = "iface", 1261 "ref"; 1262 clocks = <&mmcc DSI2_M_AHB_CLK>, 1263 <&pxo_board>; 1264 #clock-cells = <1>; 1265 #phy-cells = <0>; 1266 1267 status = "disabled"; 1268 }; 1269 1270 mdp_port0: iommu@7500000 { 1271 compatible = "qcom,apq8064-iommu"; 1272 #iommu-cells = <1>; 1273 clock-names = 1274 "smmu_pclk", 1275 "iommu_clk"; 1276 clocks = 1277 <&mmcc SMMU_AHB_CLK>, 1278 <&mmcc MDP_AXI_CLK>; 1279 reg = <0x07500000 0x100000>; 1280 interrupts = 1281 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1283 qcom,ncb = <2>; 1284 }; 1285 1286 mdp_port1: iommu@7600000 { 1287 compatible = "qcom,apq8064-iommu"; 1288 #iommu-cells = <1>; 1289 clock-names = 1290 "smmu_pclk", 1291 "iommu_clk"; 1292 clocks = 1293 <&mmcc SMMU_AHB_CLK>, 1294 <&mmcc MDP_AXI_CLK>; 1295 reg = <0x07600000 0x100000>; 1296 interrupts = 1297 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1299 qcom,ncb = <2>; 1300 }; 1301 1302 gfx3d: iommu@7c00000 { 1303 compatible = "qcom,apq8064-iommu"; 1304 #iommu-cells = <1>; 1305 clock-names = 1306 "smmu_pclk", 1307 "iommu_clk"; 1308 clocks = 1309 <&mmcc SMMU_AHB_CLK>, 1310 <&mmcc GFX3D_AXI_CLK>; 1311 reg = <0x07c00000 0x100000>; 1312 interrupts = 1313 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1315 qcom,ncb = <3>; 1316 }; 1317 1318 gfx3d1: iommu@7d00000 { 1319 compatible = "qcom,apq8064-iommu"; 1320 #iommu-cells = <1>; 1321 clock-names = 1322 "smmu_pclk", 1323 "iommu_clk"; 1324 clocks = 1325 <&mmcc SMMU_AHB_CLK>, 1326 <&mmcc GFX3D_AXI_CLK>; 1327 reg = <0x07d00000 0x100000>; 1328 interrupts = 1329 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 1331 qcom,ncb = <3>; 1332 }; 1333 1334 pcie: pcie@1b500000 { 1335 compatible = "qcom,pcie-apq8064"; 1336 reg = <0x1b500000 0x1000>, 1337 <0x1b502000 0x80>, 1338 <0x1b600000 0x100>, 1339 <0x0ff00000 0x100000>; 1340 reg-names = "dbi", "elbi", "parf", "config"; 1341 device_type = "pci"; 1342 linux,pci-domain = <0>; 1343 bus-range = <0x00 0xff>; 1344 num-lanes = <1>; 1345 #address-cells = <3>; 1346 #size-cells = <2>; 1347 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */ 1348 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */ 1349 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1350 interrupt-names = "msi"; 1351 #interrupt-cells = <1>; 1352 interrupt-map-mask = <0 0 0 0x7>; 1353 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1354 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1355 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1356 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1357 clocks = <&gcc PCIE_A_CLK>, 1358 <&gcc PCIE_H_CLK>, 1359 <&gcc PCIE_PHY_REF_CLK>; 1360 clock-names = "core", "iface", "phy"; 1361 resets = <&gcc PCIE_ACLK_RESET>, 1362 <&gcc PCIE_HCLK_RESET>, 1363 <&gcc PCIE_POR_RESET>, 1364 <&gcc PCIE_PCI_RESET>, 1365 <&gcc PCIE_PHY_RESET>; 1366 reset-names = "axi", "ahb", "por", "pci", "phy"; 1367 status = "disabled"; 1368 1369 pcie@0 { 1370 device_type = "pci"; 1371 reg = <0x0 0x0 0x0 0x0 0x0>; 1372 bus-range = <0x01 0xff>; 1373 1374 #address-cells = <3>; 1375 #size-cells = <2>; 1376 ranges; 1377 }; 1378 }; 1379 1380 hdmi: hdmi-tx@4a00000 { 1381 compatible = "qcom,hdmi-tx-8960"; 1382 pinctrl-names = "default"; 1383 pinctrl-0 = <&hdmi_pinctrl>; 1384 reg = <0x04a00000 0x2f0>; 1385 reg-names = "core_physical"; 1386 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1387 clocks = <&mmcc HDMI_APP_CLK>, 1388 <&mmcc HDMI_M_AHB_CLK>, 1389 <&mmcc HDMI_S_AHB_CLK>; 1390 clock-names = "core", 1391 "master_iface", 1392 "slave_iface"; 1393 1394 phys = <&hdmi_phy>; 1395 1396 status = "disabled"; 1397 1398 ports { 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 1402 port@0 { 1403 reg = <0>; 1404 hdmi_in: endpoint { 1405 }; 1406 }; 1407 1408 port@1 { 1409 reg = <1>; 1410 hdmi_out: endpoint { 1411 }; 1412 }; 1413 }; 1414 }; 1415 1416 hdmi_phy: phy@4a00400 { 1417 compatible = "qcom,hdmi-phy-8960"; 1418 reg = <0x4a00400 0x60>, 1419 <0x4a00500 0x100>; 1420 reg-names = "hdmi_phy", 1421 "hdmi_pll"; 1422 1423 clocks = <&mmcc HDMI_S_AHB_CLK>; 1424 clock-names = "slave_iface"; 1425 #phy-cells = <0>; 1426 #clock-cells = <0>; 1427 1428 status = "disabled"; 1429 }; 1430 1431 mdp: display-controller@5100000 { 1432 compatible = "qcom,mdp4"; 1433 reg = <0x05100000 0xf0000>; 1434 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1435 clocks = <&mmcc MDP_CLK>, 1436 <&mmcc MDP_AHB_CLK>, 1437 <&mmcc MDP_AXI_CLK>, 1438 <&mmcc MDP_LUT_CLK>, 1439 <&mmcc HDMI_TV_CLK>, 1440 <&mmcc MDP_TV_CLK>, 1441 <&mmcc LVDS_CLK>, 1442 <&rpmcc RPM_PXO_CLK>; 1443 clock-names = "core_clk", 1444 "iface_clk", 1445 "bus_clk", 1446 "lut_clk", 1447 "hdmi_clk", 1448 "tv_clk", 1449 "lcdc_clk", 1450 "pxo"; 1451 1452 #clock-cells = <0>; 1453 1454 iommus = <&mdp_port0 0 1455 &mdp_port0 2 1456 &mdp_port1 0 1457 &mdp_port1 2>; 1458 1459 ports { 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 1463 port@0 { 1464 reg = <0>; 1465 mdp_lvds_out: endpoint { 1466 }; 1467 }; 1468 1469 port@1 { 1470 reg = <1>; 1471 mdp_dsi1_out: endpoint { 1472 }; 1473 }; 1474 1475 port@2 { 1476 reg = <2>; 1477 mdp_dsi2_out: endpoint { 1478 }; 1479 }; 1480 1481 port@3 { 1482 reg = <3>; 1483 mdp_dtv_out: endpoint { 1484 }; 1485 }; 1486 }; 1487 }; 1488 1489 riva: riva-pil@3200800 { 1490 compatible = "qcom,riva-pil"; 1491 1492 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; 1493 reg-names = "ccu", "dxe", "pmu"; 1494 1495 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 1496 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; 1497 interrupt-names = "wdog", "fatal"; 1498 1499 memory-region = <&wcnss_mem>; 1500 1501 status = "disabled"; 1502 1503 iris { 1504 compatible = "qcom,wcn3660"; 1505 1506 clocks = <&cxo_board>; 1507 clock-names = "xo"; 1508 }; 1509 1510 smd-edge { 1511 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; 1512 1513 qcom,ipc = <&l2cc 8 25>; 1514 qcom,smd-edge = <6>; 1515 1516 label = "riva"; 1517 1518 wcnss { 1519 compatible = "qcom,wcnss"; 1520 qcom,smd-channels = "WCNSS_CTRL"; 1521 1522 qcom,mmio = <&riva>; 1523 1524 bluetooth { 1525 compatible = "qcom,wcnss-bt"; 1526 }; 1527 1528 wifi { 1529 compatible = "qcom,wcnss-wlan"; 1530 1531 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1533 interrupt-names = "tx", "rx"; 1534 1535 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1536 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1537 }; 1538 }; 1539 }; 1540 }; 1541 1542 etb@1a01000 { 1543 compatible = "arm,coresight-etb10", "arm,primecell"; 1544 reg = <0x1a01000 0x1000>; 1545 1546 clocks = <&rpmcc RPM_QDSS_CLK>; 1547 clock-names = "apb_pclk"; 1548 1549 in-ports { 1550 port { 1551 etb_in: endpoint { 1552 remote-endpoint = <&replicator_out0>; 1553 }; 1554 }; 1555 }; 1556 }; 1557 1558 tpiu@1a03000 { 1559 compatible = "arm,coresight-tpiu", "arm,primecell"; 1560 reg = <0x1a03000 0x1000>; 1561 1562 clocks = <&rpmcc RPM_QDSS_CLK>; 1563 clock-names = "apb_pclk"; 1564 1565 in-ports { 1566 port { 1567 tpiu_in: endpoint { 1568 remote-endpoint = <&replicator_out1>; 1569 }; 1570 }; 1571 }; 1572 }; 1573 1574 funnel@1a04000 { 1575 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1576 reg = <0x1a04000 0x1000>; 1577 1578 clocks = <&rpmcc RPM_QDSS_CLK>; 1579 clock-names = "apb_pclk"; 1580 1581 in-ports { 1582 #address-cells = <1>; 1583 #size-cells = <0>; 1584 1585 /* 1586 * Not described input ports: 1587 * 2 - connected to STM component 1588 * 3 - not-connected 1589 * 6 - not-connected 1590 * 7 - not-connected 1591 */ 1592 port@0 { 1593 reg = <0>; 1594 funnel_in0: endpoint { 1595 remote-endpoint = <&etm0_out>; 1596 }; 1597 }; 1598 port@1 { 1599 reg = <1>; 1600 funnel_in1: endpoint { 1601 remote-endpoint = <&etm1_out>; 1602 }; 1603 }; 1604 port@4 { 1605 reg = <4>; 1606 funnel_in4: endpoint { 1607 remote-endpoint = <&etm2_out>; 1608 }; 1609 }; 1610 port@5 { 1611 reg = <5>; 1612 funnel_in5: endpoint { 1613 remote-endpoint = <&etm3_out>; 1614 }; 1615 }; 1616 }; 1617 1618 out-ports { 1619 port { 1620 funnel_out: endpoint { 1621 remote-endpoint = <&replicator_in>; 1622 }; 1623 }; 1624 }; 1625 }; 1626 1627 etm@1a1c000 { 1628 compatible = "arm,coresight-etm3x", "arm,primecell"; 1629 reg = <0x1a1c000 0x1000>; 1630 1631 clocks = <&rpmcc RPM_QDSS_CLK>; 1632 clock-names = "apb_pclk"; 1633 1634 cpu = <&cpu0>; 1635 1636 out-ports { 1637 port { 1638 etm0_out: endpoint { 1639 remote-endpoint = <&funnel_in0>; 1640 }; 1641 }; 1642 }; 1643 }; 1644 1645 etm@1a1d000 { 1646 compatible = "arm,coresight-etm3x", "arm,primecell"; 1647 reg = <0x1a1d000 0x1000>; 1648 1649 clocks = <&rpmcc RPM_QDSS_CLK>; 1650 clock-names = "apb_pclk"; 1651 1652 cpu = <&cpu1>; 1653 1654 out-ports { 1655 port { 1656 etm1_out: endpoint { 1657 remote-endpoint = <&funnel_in1>; 1658 }; 1659 }; 1660 }; 1661 }; 1662 1663 etm@1a1e000 { 1664 compatible = "arm,coresight-etm3x", "arm,primecell"; 1665 reg = <0x1a1e000 0x1000>; 1666 1667 clocks = <&rpmcc RPM_QDSS_CLK>; 1668 clock-names = "apb_pclk"; 1669 1670 cpu = <&cpu2>; 1671 1672 out-ports { 1673 port { 1674 etm2_out: endpoint { 1675 remote-endpoint = <&funnel_in4>; 1676 }; 1677 }; 1678 }; 1679 }; 1680 1681 etm@1a1f000 { 1682 compatible = "arm,coresight-etm3x", "arm,primecell"; 1683 reg = <0x1a1f000 0x1000>; 1684 1685 clocks = <&rpmcc RPM_QDSS_CLK>; 1686 clock-names = "apb_pclk"; 1687 1688 cpu = <&cpu3>; 1689 1690 out-ports { 1691 port { 1692 etm3_out: endpoint { 1693 remote-endpoint = <&funnel_in5>; 1694 }; 1695 }; 1696 }; 1697 }; 1698 }; 1699}; 1700#include "qcom-apq8064-pins.dtsi" 1701