xref: /linux/drivers/gpu/drm/amd/amdgpu/clearstate_gfx12.h (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 /*
2  * Copyright 2023 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef __CLEARSTATE_GFX12_H_
24 #define __CLEARSTATE_GFX12_H_
25 
26 static const unsigned int gfx12_SECT_CONTEXT_def_1[] = {
27 0x00000000, //mmSC_MEM_TEMPORAL
28 0x00000000, //mmSC_MEM_SPEC_READ
29 0x00000000, //mmPA_SC_VPORT_0_TL
30 0x00000000, //mmPA_SC_VPORT_0_BR
31 0x00000000, //mmPA_SC_VPORT_1_TL
32 0x00000000, //mmPA_SC_VPORT_1_BR
33 0x00000000, //mmPA_SC_VPORT_2_TL
34 0x00000000, //mmPA_SC_VPORT_2_BR
35 0x00000000, //mmPA_SC_VPORT_3_TL
36 0x00000000, //mmPA_SC_VPORT_3_BR
37 0x00000000, //mmPA_SC_VPORT_4_TL
38 0x00000000, //mmPA_SC_VPORT_4_BR
39 0x00000000, //mmPA_SC_VPORT_5_TL
40 0x00000000, //mmPA_SC_VPORT_5_BR
41 0x00000000, //mmPA_SC_VPORT_6_TL
42 0x00000000, //mmPA_SC_VPORT_6_BR
43 0x00000000, //mmPA_SC_VPORT_7_TL
44 0x00000000, //mmPA_SC_VPORT_7_BR
45 0x00000000, //mmPA_SC_VPORT_8_TL
46 0x00000000, //mmPA_SC_VPORT_8_BR
47 0x00000000, //mmPA_SC_VPORT_9_TL
48 0x00000000, //mmPA_SC_VPORT_9_BR
49 0x00000000, //mmPA_SC_VPORT_10_TL
50 0x00000000, //mmPA_SC_VPORT_10_BR
51 0x00000000, //mmPA_SC_VPORT_11_TL
52 0x00000000, //mmPA_SC_VPORT_11_BR
53 0x00000000, //mmPA_SC_VPORT_12_TL
54 0x00000000, //mmPA_SC_VPORT_12_BR
55 0x00000000, //mmPA_SC_VPORT_13_TL
56 0x00000000, //mmPA_SC_VPORT_13_BR
57 0x00000000, //mmPA_SC_VPORT_14_TL
58 0x00000000, //mmPA_SC_VPORT_14_BR
59 0x00000000, //mmPA_SC_VPORT_15_TL
60 0x00000000, //mmPA_SC_VPORT_15_BR
61 };
62 
63 static const unsigned int gfx12_SECT_CONTEXT_def_2[] = {
64 0x00000000, //mmPA_CL_PROG_NEAR_CLIP_Z
65 0x00000000, //mmPA_RATE_CNTL
66 };
67 
68 static const unsigned int gfx12_SECT_CONTEXT_def_3[] = {
69 0x00000000, //mmCP_PERFMON_CNTX_CNTL
70 };
71 
72 static const unsigned int gfx12_SECT_CONTEXT_def_4[] = {
73 0x00000000, //mmCONTEXT_RESERVED_REG0
74 0x00000000, //mmCONTEXT_RESERVED_REG1
75 0x00000000, //mmPA_SC_CLIPRECT_0_EXT
76 0x00000000, //mmPA_SC_CLIPRECT_1_EXT
77 0x00000000, //mmPA_SC_CLIPRECT_2_EXT
78 0x00000000, //mmPA_SC_CLIPRECT_3_EXT
79 };
80 
81 static const unsigned int gfx12_SECT_CONTEXT_def_5[] = {
82 0x00000000, //mmPA_SC_HIZ_INFO
83 0x00000000, //mmPA_SC_HIS_INFO
84 0x00000000, //mmPA_SC_HIZ_BASE
85 0x00000000, //mmPA_SC_HIZ_BASE_EXT
86 0x00000000, //mmPA_SC_HIZ_SIZE_XY
87 0x00000000, //mmPA_SC_HIS_BASE
88 0x00000000, //mmPA_SC_HIS_BASE_EXT
89 0x00000000, //mmPA_SC_HIS_SIZE_XY
90 0x00000000, //mmPA_SC_BINNER_OUTPUT_TIMEOUT_CNTL
91 0x00000000, //mmPA_SC_BINNER_DYNAMIC_BATCH_LIMIT
92 0x00000000, //mmPA_SC_HISZ_CONTROL
93 };
94 
95 static const unsigned int gfx12_SECT_CONTEXT_def_6[] = {
96 0x00000000, //mmCB_MEM0_INFO
97 0x00000000, //mmCB_MEM1_INFO
98 0x00000000, //mmCB_MEM2_INFO
99 0x00000000, //mmCB_MEM3_INFO
100 0x00000000, //mmCB_MEM4_INFO
101 0x00000000, //mmCB_MEM5_INFO
102 0x00000000, //mmCB_MEM6_INFO
103 0x00000000, //mmCB_MEM7_INFO
104 };
105 
106 static const struct cs_extent_def gfx12_SECT_CONTEXT_defs[] = {
107     {gfx12_SECT_CONTEXT_def_1, 0x0000a03e, 34 },
108     {gfx12_SECT_CONTEXT_def_2, 0x0000a0cc, 2 },
109     {gfx12_SECT_CONTEXT_def_3, 0x0000a0d8, 1 },
110     {gfx12_SECT_CONTEXT_def_4, 0x0000a0db, 6 },
111     {gfx12_SECT_CONTEXT_def_5, 0x0000a2e5, 11 },
112     {gfx12_SECT_CONTEXT_def_6, 0x0000a3c0, 8 },
113     { 0, 0, 0 }
114 };
115 
116 static const struct cs_section_def gfx12_cs_data[] = {
117     { gfx12_SECT_CONTEXT_defs, SECT_CONTEXT },
118     { 0, SECT_NONE }
119 };
120 
121 #endif /* __CLEARSTATE_GFX12_H_ */
122