1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/slab.h>
26 #include <linux/list.h>
27 #include "kfd_device_queue_manager.h"
28 #include "kfd_priv.h"
29 #include "kfd_kernel_queue.h"
30 #include "amdgpu_amdkfd.h"
31 #include "amdgpu_reset.h"
32
get_queue_by_qid(struct process_queue_manager * pqm,unsigned int qid)33 static inline struct process_queue_node *get_queue_by_qid(
34 struct process_queue_manager *pqm, unsigned int qid)
35 {
36 struct process_queue_node *pqn;
37
38 list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
39 if ((pqn->q && pqn->q->properties.queue_id == qid) ||
40 (pqn->kq && pqn->kq->queue->properties.queue_id == qid))
41 return pqn;
42 }
43
44 return NULL;
45 }
46
assign_queue_slot_by_qid(struct process_queue_manager * pqm,unsigned int qid)47 static int assign_queue_slot_by_qid(struct process_queue_manager *pqm,
48 unsigned int qid)
49 {
50 if (qid >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS)
51 return -EINVAL;
52
53 if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) {
54 pr_err("Cannot create new queue because requested qid(%u) is in use\n", qid);
55 return -ENOSPC;
56 }
57
58 return 0;
59 }
60
find_available_queue_slot(struct process_queue_manager * pqm,unsigned int * qid)61 static int find_available_queue_slot(struct process_queue_manager *pqm,
62 unsigned int *qid)
63 {
64 unsigned long found;
65
66 found = find_first_zero_bit(pqm->queue_slot_bitmap,
67 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
68
69 pr_debug("The new slot id %lu\n", found);
70
71 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
72 pr_info("Cannot open more queues for process with pid %d\n",
73 pqm->process->lead_thread->pid);
74 return -ENOMEM;
75 }
76
77 set_bit(found, pqm->queue_slot_bitmap);
78 *qid = found;
79
80 return 0;
81 }
82
kfd_process_dequeue_from_device(struct kfd_process_device * pdd)83 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd)
84 {
85 struct kfd_node *dev = pdd->dev;
86
87 if (pdd->already_dequeued)
88 return;
89 /* The MES context flush needs to filter out the case which the
90 * KFD process is created without setting up the MES context and
91 * queue for creating a compute queue.
92 */
93 dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd);
94 if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr &&
95 down_read_trylock(&dev->adev->reset_domain->sem)) {
96 amdgpu_mes_flush_shader_debugger(dev->adev,
97 pdd->proc_ctx_gpu_addr,
98 ffs(pdd->dev->xcc_mask) - 1);
99 up_read(&dev->adev->reset_domain->sem);
100 }
101 pdd->already_dequeued = true;
102 }
103
pqm_set_gws(struct process_queue_manager * pqm,unsigned int qid,void * gws)104 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid,
105 void *gws)
106 {
107 struct mqd_update_info minfo = {0};
108 struct kfd_node *dev = NULL;
109 struct process_queue_node *pqn;
110 struct kfd_process_device *pdd;
111 struct kgd_mem *mem = NULL;
112 int ret;
113
114 pqn = get_queue_by_qid(pqm, qid);
115 if (!pqn) {
116 pr_err("Queue id does not match any known queue\n");
117 return -EINVAL;
118 }
119
120 if (pqn->q)
121 dev = pqn->q->device;
122 if (WARN_ON(!dev))
123 return -ENODEV;
124
125 pdd = kfd_get_process_device_data(dev, pqm->process);
126 if (!pdd) {
127 pr_err("Process device data doesn't exist\n");
128 return -EINVAL;
129 }
130
131 /* Only allow one queue per process can have GWS assigned */
132 if (gws && pdd->qpd.num_gws)
133 return -EBUSY;
134
135 if (!gws && pdd->qpd.num_gws == 0)
136 return -EINVAL;
137
138 if ((KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) &&
139 KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) &&
140 KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0)) &&
141 !dev->kfd->shared_resources.enable_mes) {
142 if (gws)
143 ret = amdgpu_amdkfd_add_gws_to_process(pdd->process->kgd_process_info,
144 gws, &mem);
145 else
146 ret = amdgpu_amdkfd_remove_gws_from_process(pdd->process->kgd_process_info,
147 pqn->q->gws);
148 if (unlikely(ret))
149 return ret;
150 pqn->q->gws = mem;
151 } else {
152 /*
153 * Intentionally set GWS to a non-NULL value
154 * for devices that do not use GWS for global wave
155 * synchronization but require the formality
156 * of setting GWS for cooperative groups.
157 */
158 pqn->q->gws = gws ? ERR_PTR(-ENOMEM) : NULL;
159 }
160
161 pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0;
162 minfo.update_flag = gws ? UPDATE_FLAG_IS_GWS : 0;
163
164 return pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
165 pqn->q, &minfo);
166 }
167
kfd_process_dequeue_from_all_devices(struct kfd_process * p)168 void kfd_process_dequeue_from_all_devices(struct kfd_process *p)
169 {
170 int i;
171
172 for (i = 0; i < p->n_pdds; i++)
173 kfd_process_dequeue_from_device(p->pdds[i]);
174 }
175
pqm_init(struct process_queue_manager * pqm,struct kfd_process * p)176 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p)
177 {
178 INIT_LIST_HEAD(&pqm->queues);
179 pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS,
180 GFP_KERNEL);
181 if (!pqm->queue_slot_bitmap)
182 return -ENOMEM;
183 pqm->process = p;
184
185 return 0;
186 }
187
pqm_clean_queue_resource(struct process_queue_manager * pqm,struct process_queue_node * pqn)188 static void pqm_clean_queue_resource(struct process_queue_manager *pqm,
189 struct process_queue_node *pqn)
190 {
191 struct kfd_node *dev;
192 struct kfd_process_device *pdd;
193
194 dev = pqn->q->device;
195
196 pdd = kfd_get_process_device_data(dev, pqm->process);
197 if (!pdd) {
198 pr_err("Process device data doesn't exist\n");
199 return;
200 }
201
202 if (pqn->q->gws) {
203 if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) &&
204 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 4) &&
205 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 5, 0) &&
206 !dev->kfd->shared_resources.enable_mes)
207 amdgpu_amdkfd_remove_gws_from_process(
208 pqm->process->kgd_process_info, pqn->q->gws);
209 pdd->qpd.num_gws = 0;
210 }
211
212 if (dev->kfd->shared_resources.enable_mes) {
213 amdgpu_amdkfd_free_kernel_mem(dev->adev, &pqn->q->gang_ctx_bo);
214 amdgpu_amdkfd_free_kernel_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart);
215 }
216 }
217
pqm_uninit(struct process_queue_manager * pqm)218 void pqm_uninit(struct process_queue_manager *pqm)
219 {
220 struct process_queue_node *pqn, *next;
221
222 list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) {
223 if (pqn->q) {
224 struct kfd_process_device *pdd = kfd_get_process_device_data(pqn->q->device,
225 pqm->process);
226 if (pdd) {
227 kfd_queue_unref_bo_vas(pdd, &pqn->q->properties);
228 kfd_queue_release_buffers(pdd, &pqn->q->properties);
229 } else {
230 WARN_ON(!pdd);
231 }
232 pqm_clean_queue_resource(pqm, pqn);
233 }
234
235 kfd_procfs_del_queue(pqn->q);
236 uninit_queue(pqn->q);
237 list_del(&pqn->process_queue_list);
238 kfree(pqn);
239 }
240
241 bitmap_free(pqm->queue_slot_bitmap);
242 pqm->queue_slot_bitmap = NULL;
243 }
244
init_user_queue(struct process_queue_manager * pqm,struct kfd_node * dev,struct queue ** q,struct queue_properties * q_properties,unsigned int qid)245 static int init_user_queue(struct process_queue_manager *pqm,
246 struct kfd_node *dev, struct queue **q,
247 struct queue_properties *q_properties,
248 unsigned int qid)
249 {
250 int retval;
251
252 /* Doorbell initialized in user space*/
253 q_properties->doorbell_ptr = NULL;
254 q_properties->exception_status = KFD_EC_MASK(EC_QUEUE_NEW);
255
256 /* let DQM handle it*/
257 q_properties->vmid = 0;
258 q_properties->queue_id = qid;
259
260 retval = init_queue(q, q_properties);
261 if (retval != 0)
262 return retval;
263
264 (*q)->device = dev;
265 (*q)->process = pqm->process;
266
267 if (dev->kfd->shared_resources.enable_mes) {
268 retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev,
269 AMDGPU_MES_GANG_CTX_SIZE,
270 AMDGPU_GEM_DOMAIN_GTT,
271 &(*q)->gang_ctx_bo,
272 &(*q)->gang_ctx_gpu_addr,
273 &(*q)->gang_ctx_cpu_ptr,
274 false);
275 if (retval) {
276 pr_err("failed to allocate gang context bo\n");
277 goto cleanup;
278 }
279 memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE);
280
281 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work
282 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell)
283 */
284 if (dev->adev != amdgpu_ttm_adev(q_properties->wptr_bo->tbo.bdev)) {
285 pr_err("Queue memory allocated to wrong device\n");
286 retval = -EINVAL;
287 goto free_gang_ctx_bo;
288 }
289
290 retval = amdgpu_amdkfd_map_gtt_bo_to_gart(q_properties->wptr_bo,
291 &(*q)->wptr_bo_gart);
292 if (retval) {
293 pr_err("Failed to map wptr bo to GART\n");
294 goto free_gang_ctx_bo;
295 }
296 }
297
298 pr_debug("PQM After init queue");
299 return 0;
300
301 free_gang_ctx_bo:
302 amdgpu_amdkfd_free_kernel_mem(dev->adev, &(*q)->gang_ctx_bo);
303 cleanup:
304 uninit_queue(*q);
305 *q = NULL;
306 return retval;
307 }
308
pqm_create_queue(struct process_queue_manager * pqm,struct kfd_node * dev,struct queue_properties * properties,unsigned int * qid,const struct kfd_criu_queue_priv_data * q_data,const void * restore_mqd,const void * restore_ctl_stack,uint32_t * p_doorbell_offset_in_process)309 int pqm_create_queue(struct process_queue_manager *pqm,
310 struct kfd_node *dev,
311 struct queue_properties *properties,
312 unsigned int *qid,
313 const struct kfd_criu_queue_priv_data *q_data,
314 const void *restore_mqd,
315 const void *restore_ctl_stack,
316 uint32_t *p_doorbell_offset_in_process)
317 {
318 int retval;
319 struct kfd_process_device *pdd;
320 struct queue *q;
321 struct process_queue_node *pqn;
322 struct kernel_queue *kq;
323 enum kfd_queue_type type = properties->type;
324 unsigned int max_queues = 127; /* HWS limit */
325
326 /*
327 * On GFX 9.4.3/9.5.0, increase the number of queues that
328 * can be created to 255. No HWS limit on GFX 9.4.3/9.5.0.
329 */
330 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) ||
331 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) ||
332 KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0))
333 max_queues = 255;
334
335 q = NULL;
336 kq = NULL;
337
338 pdd = kfd_get_process_device_data(dev, pqm->process);
339 if (!pdd) {
340 pr_err("Process device data doesn't exist\n");
341 return -1;
342 }
343
344 /*
345 * for debug process, verify that it is within the static queues limit
346 * currently limit is set to half of the total avail HQD slots
347 * If we are just about to create DIQ, the is_debug flag is not set yet
348 * Hence we also check the type as well
349 */
350 if (pdd->qpd.is_debug)
351 max_queues = dev->kfd->device_info.max_no_of_hqd/2;
352
353 if (pdd->qpd.queue_count >= max_queues)
354 return -ENOSPC;
355
356 if (q_data) {
357 retval = assign_queue_slot_by_qid(pqm, q_data->q_id);
358 *qid = q_data->q_id;
359 } else
360 retval = find_available_queue_slot(pqm, qid);
361
362 if (retval != 0)
363 return retval;
364
365 /* Register process if this is the first queue */
366 if (list_empty(&pdd->qpd.queues_list) &&
367 list_empty(&pdd->qpd.priv_queue_list))
368 dev->dqm->ops.register_process(dev->dqm, &pdd->qpd);
369
370 /* Allocate proc_ctx_bo only if MES is enabled and this is the first queue */
371 if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) {
372 retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev,
373 AMDGPU_MES_PROC_CTX_SIZE,
374 AMDGPU_GEM_DOMAIN_GTT,
375 &pdd->proc_ctx_bo,
376 &pdd->proc_ctx_gpu_addr,
377 &pdd->proc_ctx_cpu_ptr,
378 false);
379 if (retval) {
380 dev_err(dev->adev->dev, "failed to allocate process context bo\n");
381 return retval;
382 }
383 memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE);
384 }
385
386 pqn = kzalloc_obj(*pqn);
387 if (!pqn) {
388 retval = -ENOMEM;
389 goto err_allocate_pqn;
390 }
391
392 switch (type) {
393 case KFD_QUEUE_TYPE_SDMA:
394 case KFD_QUEUE_TYPE_SDMA_XGMI:
395 case KFD_QUEUE_TYPE_SDMA_BY_ENG_ID:
396 /* SDMA queues are always allocated statically no matter
397 * which scheduler mode is used. We also do not need to
398 * check whether a SDMA queue can be allocated here, because
399 * allocate_sdma_queue() in create_queue() has the
400 * corresponding check logic.
401 */
402 retval = init_user_queue(pqm, dev, &q, properties, *qid);
403 if (retval != 0)
404 goto err_create_queue;
405 pqn->q = q;
406 pqn->kq = NULL;
407 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data,
408 restore_mqd, restore_ctl_stack);
409 print_queue(q);
410 break;
411
412 case KFD_QUEUE_TYPE_COMPUTE:
413 /* check if there is over subscription */
414 if ((dev->dqm->sched_policy ==
415 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) &&
416 ((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) ||
417 (dev->dqm->active_queue_count >= get_cp_queues_num(dev->dqm)))) {
418 pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n");
419 retval = -EPERM;
420 goto err_create_queue;
421 }
422
423 retval = init_user_queue(pqm, dev, &q, properties, *qid);
424 if (retval != 0)
425 goto err_create_queue;
426 pqn->q = q;
427 pqn->kq = NULL;
428 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data,
429 restore_mqd, restore_ctl_stack);
430 print_queue(q);
431 break;
432 default:
433 WARN(1, "Invalid queue type %d", type);
434 retval = -EINVAL;
435 }
436
437 if (retval != 0) {
438 if ((type == KFD_QUEUE_TYPE_SDMA ||
439 type == KFD_QUEUE_TYPE_SDMA_XGMI ||
440 type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) &&
441 retval == -ENOMEM)
442 pr_warn("process pid %d DQM create queue type %d failed. ret %d\n",
443 pqm->process->lead_thread->pid, type, retval);
444 else
445 pr_err("process pid %d DQM create queue type %d failed. ret %d\n",
446 pqm->process->lead_thread->pid, type, retval);
447 goto err_create_queue;
448 }
449
450 if (q && p_doorbell_offset_in_process) {
451 /* Return the doorbell offset within the doorbell page
452 * to the caller so it can be passed up to user mode
453 * (in bytes).
454 * relative doorbell index = Absolute doorbell index -
455 * absolute index of first doorbell in the page.
456 */
457 uint32_t first_db_index = amdgpu_doorbell_index_on_bar(pdd->dev->adev,
458 pdd->qpd.proc_doorbells,
459 0,
460 pdd->dev->kfd->device_info.doorbell_size);
461
462 *p_doorbell_offset_in_process = (q->properties.doorbell_off
463 - first_db_index) * sizeof(uint32_t);
464 }
465
466 pr_debug("PQM After DQM create queue\n");
467
468 list_add(&pqn->process_queue_list, &pqm->queues);
469
470 if (q) {
471 pr_debug("PQM done creating queue\n");
472 kfd_procfs_add_queue(q);
473 print_queue_properties(&q->properties);
474 }
475
476 return retval;
477
478 err_create_queue:
479 uninit_queue(q);
480 if (kq)
481 kernel_queue_uninit(kq);
482 kfree(pqn);
483 err_allocate_pqn:
484 /* check if queues list is empty unregister process from device */
485 clear_bit(*qid, pqm->queue_slot_bitmap);
486 if (list_empty(&pdd->qpd.queues_list) &&
487 list_empty(&pdd->qpd.priv_queue_list))
488 dev->dqm->ops.unregister_process(dev->dqm, &pdd->qpd);
489 return retval;
490 }
491
pqm_destroy_queue(struct process_queue_manager * pqm,unsigned int qid)492 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)
493 {
494 struct process_queue_node *pqn;
495 struct kfd_process_device *pdd;
496 struct device_queue_manager *dqm;
497 struct kfd_node *dev;
498 int retval;
499
500 dqm = NULL;
501
502 retval = 0;
503
504 pqn = get_queue_by_qid(pqm, qid);
505 if (!pqn) {
506 pr_err("Queue id does not match any known queue\n");
507 return -EINVAL;
508 }
509
510 dev = NULL;
511 if (pqn->kq)
512 dev = pqn->kq->dev;
513 if (pqn->q)
514 dev = pqn->q->device;
515 if (WARN_ON(!dev))
516 return -ENODEV;
517
518 pdd = kfd_get_process_device_data(dev, pqm->process);
519 if (!pdd) {
520 pr_err("Process device data doesn't exist\n");
521 return -1;
522 }
523
524 if (pqn->kq) {
525 /* destroy kernel queue (DIQ) */
526 dqm = pqn->kq->dev->dqm;
527 dqm->ops.destroy_kernel_queue(dqm, pqn->kq, &pdd->qpd);
528 kernel_queue_uninit(pqn->kq);
529 }
530
531 if (pqn->q) {
532 retval = kfd_queue_unref_bo_vas(pdd, &pqn->q->properties);
533 if (retval)
534 goto err_destroy_queue;
535
536 dqm = pqn->q->device->dqm;
537 retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q);
538 if (retval) {
539 pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n",
540 pdd->pasid,
541 pqn->q->properties.queue_id, retval);
542 if (retval != -ETIME && retval != -EIO)
543 goto err_destroy_queue;
544 }
545 kfd_procfs_del_queue(pqn->q);
546 kfd_queue_release_buffers(pdd, &pqn->q->properties);
547 pqm_clean_queue_resource(pqm, pqn);
548 uninit_queue(pqn->q);
549 }
550
551 list_del(&pqn->process_queue_list);
552 kfree(pqn);
553 clear_bit(qid, pqm->queue_slot_bitmap);
554
555 if (list_empty(&pdd->qpd.queues_list) &&
556 list_empty(&pdd->qpd.priv_queue_list))
557 dqm->ops.unregister_process(dqm, &pdd->qpd);
558
559 err_destroy_queue:
560 return retval;
561 }
562
pqm_update_queue_properties(struct process_queue_manager * pqm,unsigned int qid,struct queue_properties * p)563 int pqm_update_queue_properties(struct process_queue_manager *pqm,
564 unsigned int qid, struct queue_properties *p)
565 {
566 int retval;
567 struct process_queue_node *pqn;
568
569 pqn = get_queue_by_qid(pqm, qid);
570 if (!pqn || !pqn->q) {
571 pr_debug("No queue %d exists for update operation\n", qid);
572 return -EFAULT;
573 }
574
575 /*
576 * Update with NULL ring address is used to disable the queue
577 */
578 if (p->queue_address && p->queue_size) {
579 struct kfd_process_device *pdd;
580 struct amdgpu_vm *vm;
581 struct queue *q = pqn->q;
582 int err;
583
584 pdd = kfd_get_process_device_data(q->device, q->process);
585 if (!pdd)
586 return -ENODEV;
587 vm = drm_priv_to_vm(pdd->drm_priv);
588 err = amdgpu_bo_reserve(vm->root.bo, false);
589 if (err)
590 return err;
591
592 if (kfd_queue_buffer_get(vm, (void *)p->queue_address, &p->ring_bo,
593 p->queue_size)) {
594 pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n",
595 p->queue_address, p->queue_size);
596 amdgpu_bo_unreserve(vm->root.bo);
597 return -EFAULT;
598 }
599
600 kfd_queue_unref_bo_va(vm, &pqn->q->properties.ring_bo);
601 kfd_queue_buffer_put(&pqn->q->properties.ring_bo);
602 amdgpu_bo_unreserve(vm->root.bo);
603
604 pqn->q->properties.ring_bo = p->ring_bo;
605 }
606
607 pqn->q->properties.queue_address = p->queue_address;
608 pqn->q->properties.queue_size = p->queue_size;
609 pqn->q->properties.queue_percent = p->queue_percent;
610 pqn->q->properties.priority = p->priority;
611 pqn->q->properties.pm4_target_xcc = p->pm4_target_xcc;
612
613 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
614 pqn->q, NULL);
615 if (retval != 0)
616 return retval;
617
618 return 0;
619 }
620
pqm_update_mqd(struct process_queue_manager * pqm,unsigned int qid,struct mqd_update_info * minfo)621 int pqm_update_mqd(struct process_queue_manager *pqm,
622 unsigned int qid, struct mqd_update_info *minfo)
623 {
624 int retval;
625 struct process_queue_node *pqn;
626
627 pqn = get_queue_by_qid(pqm, qid);
628 if (!pqn) {
629 pr_debug("No queue %d exists for update operation\n", qid);
630 return -EFAULT;
631 }
632
633 /* CUs are masked for debugger requirements so deny user mask */
634 if (pqn->q->properties.is_dbg_wa && minfo && minfo->cu_mask.ptr)
635 return -EBUSY;
636
637 /* ASICs that have WGPs must enforce pairwise enabled mask checks. */
638 if (minfo && minfo->cu_mask.ptr &&
639 KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0)) {
640 int i;
641
642 for (i = 0; i < minfo->cu_mask.count; i += 2) {
643 uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3;
644
645 if (cu_pair && cu_pair != 0x3) {
646 pr_debug("CUs must be adjacent pairwise enabled.\n");
647 return -EINVAL;
648 }
649 }
650 }
651
652 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
653 pqn->q, minfo);
654 if (retval != 0)
655 return retval;
656
657 if (minfo && minfo->cu_mask.ptr)
658 pqn->q->properties.is_user_cu_masked = true;
659
660 return 0;
661 }
662
pqm_get_user_queue(struct process_queue_manager * pqm,unsigned int qid)663 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm,
664 unsigned int qid)
665 {
666 struct process_queue_node *pqn;
667
668 pqn = get_queue_by_qid(pqm, qid);
669 return pqn ? pqn->q : NULL;
670 }
671
pqm_get_wave_state(struct process_queue_manager * pqm,unsigned int qid,void __user * ctl_stack,u32 * ctl_stack_used_size,u32 * save_area_used_size)672 int pqm_get_wave_state(struct process_queue_manager *pqm,
673 unsigned int qid,
674 void __user *ctl_stack,
675 u32 *ctl_stack_used_size,
676 u32 *save_area_used_size)
677 {
678 struct process_queue_node *pqn;
679
680 pqn = get_queue_by_qid(pqm, qid);
681 if (!pqn) {
682 pr_debug("amdkfd: No queue %d exists for operation\n",
683 qid);
684 return -EFAULT;
685 }
686
687 return pqn->q->device->dqm->ops.get_wave_state(pqn->q->device->dqm,
688 pqn->q,
689 ctl_stack,
690 ctl_stack_used_size,
691 save_area_used_size);
692 }
693
pqm_get_queue_snapshot(struct process_queue_manager * pqm,uint64_t exception_clear_mask,void __user * buf,int * num_qss_entries,uint32_t * entry_size)694 int pqm_get_queue_snapshot(struct process_queue_manager *pqm,
695 uint64_t exception_clear_mask,
696 void __user *buf,
697 int *num_qss_entries,
698 uint32_t *entry_size)
699 {
700 struct process_queue_node *pqn;
701 struct kfd_queue_snapshot_entry src;
702 uint32_t tmp_entry_size = *entry_size, tmp_qss_entries = *num_qss_entries;
703 int r = 0;
704
705 *num_qss_entries = 0;
706 if (!(*entry_size))
707 return -EINVAL;
708
709 *entry_size = min_t(size_t, *entry_size, sizeof(struct kfd_queue_snapshot_entry));
710 mutex_lock(&pqm->process->event_mutex);
711
712 memset(&src, 0, sizeof(src));
713
714 list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
715 if (!pqn->q)
716 continue;
717
718 if (*num_qss_entries < tmp_qss_entries) {
719 set_queue_snapshot_entry(pqn->q, exception_clear_mask, &src);
720
721 if (copy_to_user(buf, &src, *entry_size)) {
722 r = -EFAULT;
723 break;
724 }
725 buf += tmp_entry_size;
726 }
727 *num_qss_entries += 1;
728 }
729
730 mutex_unlock(&pqm->process->event_mutex);
731 return r;
732 }
733
get_queue_data_sizes(struct kfd_process_device * pdd,struct queue * q,uint32_t * mqd_size,uint32_t * ctl_stack_size)734 static int get_queue_data_sizes(struct kfd_process_device *pdd,
735 struct queue *q,
736 uint32_t *mqd_size,
737 uint32_t *ctl_stack_size)
738 {
739 int ret;
740
741 ret = pqm_get_queue_checkpoint_info(&pdd->process->pqm,
742 q->properties.queue_id,
743 mqd_size,
744 ctl_stack_size);
745 if (ret)
746 pr_err("Failed to get queue dump info (%d)\n", ret);
747
748 return ret;
749 }
750
kfd_process_get_queue_info(struct kfd_process * p,uint32_t * num_queues,uint64_t * priv_data_sizes)751 int kfd_process_get_queue_info(struct kfd_process *p,
752 uint32_t *num_queues,
753 uint64_t *priv_data_sizes)
754 {
755 uint32_t extra_data_sizes = 0;
756 struct queue *q;
757 int i;
758 int ret;
759
760 *num_queues = 0;
761
762 /* Run over all PDDs of the process */
763 for (i = 0; i < p->n_pdds; i++) {
764 struct kfd_process_device *pdd = p->pdds[i];
765
766 list_for_each_entry(q, &pdd->qpd.queues_list, list) {
767 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
768 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
769 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
770 uint32_t mqd_size, ctl_stack_size;
771
772 *num_queues = *num_queues + 1;
773
774 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size);
775 if (ret)
776 return ret;
777
778 extra_data_sizes += mqd_size + ctl_stack_size;
779 } else {
780 pr_err("Unsupported queue type (%d)\n", q->properties.type);
781 return -EOPNOTSUPP;
782 }
783 }
784 }
785 *priv_data_sizes = extra_data_sizes +
786 (*num_queues * sizeof(struct kfd_criu_queue_priv_data));
787
788 return 0;
789 }
790
pqm_checkpoint_mqd(struct process_queue_manager * pqm,unsigned int qid,void * mqd,void * ctl_stack)791 static int pqm_checkpoint_mqd(struct process_queue_manager *pqm,
792 unsigned int qid,
793 void *mqd,
794 void *ctl_stack)
795 {
796 struct process_queue_node *pqn;
797
798 pqn = get_queue_by_qid(pqm, qid);
799 if (!pqn) {
800 pr_debug("amdkfd: No queue %d exists for operation\n", qid);
801 return -EFAULT;
802 }
803
804 if (!pqn->q->device->dqm->ops.checkpoint_mqd) {
805 pr_err("amdkfd: queue dumping not supported on this device\n");
806 return -EOPNOTSUPP;
807 }
808
809 return pqn->q->device->dqm->ops.checkpoint_mqd(pqn->q->device->dqm,
810 pqn->q, mqd, ctl_stack);
811 }
812
criu_checkpoint_queue(struct kfd_process_device * pdd,struct queue * q,struct kfd_criu_queue_priv_data * q_data)813 static int criu_checkpoint_queue(struct kfd_process_device *pdd,
814 struct queue *q,
815 struct kfd_criu_queue_priv_data *q_data)
816 {
817 uint8_t *mqd, *ctl_stack;
818 int ret;
819
820 mqd = (void *)(q_data + 1);
821 ctl_stack = mqd + q_data->mqd_size;
822
823 q_data->gpu_id = pdd->user_gpu_id;
824 q_data->type = q->properties.type;
825 q_data->format = q->properties.format;
826 q_data->q_id = q->properties.queue_id;
827 q_data->q_address = q->properties.queue_address;
828 q_data->q_size = q->properties.queue_size;
829 q_data->priority = q->properties.priority;
830 q_data->q_percent = q->properties.queue_percent;
831 q_data->read_ptr_addr = (uint64_t)q->properties.read_ptr;
832 q_data->write_ptr_addr = (uint64_t)q->properties.write_ptr;
833 q_data->doorbell_id = q->doorbell_id;
834
835 q_data->sdma_id = q->sdma_id;
836
837 q_data->eop_ring_buffer_address =
838 q->properties.eop_ring_buffer_address;
839
840 q_data->eop_ring_buffer_size = q->properties.eop_ring_buffer_size;
841
842 q_data->ctx_save_restore_area_address =
843 q->properties.ctx_save_restore_area_address;
844
845 q_data->ctx_save_restore_area_size =
846 q->properties.ctx_save_restore_area_size;
847
848 q_data->gws = !!q->gws;
849
850 ret = pqm_checkpoint_mqd(&pdd->process->pqm, q->properties.queue_id, mqd, ctl_stack);
851 if (ret) {
852 pr_err("Failed checkpoint queue_mqd (%d)\n", ret);
853 return ret;
854 }
855
856 pr_debug("Dumping Queue: gpu_id:%x queue_id:%u\n", q_data->gpu_id, q_data->q_id);
857 return ret;
858 }
859
criu_checkpoint_queues_device(struct kfd_process_device * pdd,uint8_t __user * user_priv,unsigned int * q_index,uint64_t * queues_priv_data_offset)860 static int criu_checkpoint_queues_device(struct kfd_process_device *pdd,
861 uint8_t __user *user_priv,
862 unsigned int *q_index,
863 uint64_t *queues_priv_data_offset)
864 {
865 unsigned int q_private_data_size = 0;
866 uint8_t *q_private_data = NULL; /* Local buffer to store individual queue private data */
867 struct queue *q;
868 int ret = 0;
869
870 list_for_each_entry(q, &pdd->qpd.queues_list, list) {
871 struct kfd_criu_queue_priv_data *q_data;
872 uint64_t q_data_size;
873 uint32_t mqd_size;
874 uint32_t ctl_stack_size;
875
876 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE &&
877 q->properties.type != KFD_QUEUE_TYPE_SDMA &&
878 q->properties.type != KFD_QUEUE_TYPE_SDMA_XGMI) {
879
880 pr_err("Unsupported queue type (%d)\n", q->properties.type);
881 ret = -EOPNOTSUPP;
882 break;
883 }
884
885 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size);
886 if (ret)
887 break;
888
889 q_data_size = sizeof(*q_data) + mqd_size + ctl_stack_size;
890
891 /* Increase local buffer space if needed */
892 if (q_private_data_size < q_data_size) {
893 kfree(q_private_data);
894
895 q_private_data = kzalloc(q_data_size, GFP_KERNEL);
896 if (!q_private_data) {
897 ret = -ENOMEM;
898 break;
899 }
900 q_private_data_size = q_data_size;
901 }
902
903 q_data = (struct kfd_criu_queue_priv_data *)q_private_data;
904
905 /*
906 * data stored in this order:
907 * priv_data, mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]...
908 */
909 q_data->mqd_size = mqd_size;
910 q_data->ctl_stack_size = ctl_stack_size;
911
912 ret = criu_checkpoint_queue(pdd, q, q_data);
913 if (ret)
914 break;
915
916 q_data->object_type = KFD_CRIU_OBJECT_TYPE_QUEUE;
917
918 ret = copy_to_user(user_priv + *queues_priv_data_offset,
919 q_data, q_data_size);
920 if (ret) {
921 ret = -EFAULT;
922 break;
923 }
924 *queues_priv_data_offset += q_data_size;
925 *q_index = *q_index + 1;
926 }
927
928 kfree(q_private_data);
929
930 return ret;
931 }
932
kfd_criu_checkpoint_queues(struct kfd_process * p,uint8_t __user * user_priv_data,uint64_t * priv_data_offset)933 int kfd_criu_checkpoint_queues(struct kfd_process *p,
934 uint8_t __user *user_priv_data,
935 uint64_t *priv_data_offset)
936 {
937 int ret = 0, pdd_index, q_index = 0;
938
939 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) {
940 struct kfd_process_device *pdd = p->pdds[pdd_index];
941
942 /*
943 * criu_checkpoint_queues_device will copy data to user and update q_index and
944 * queues_priv_data_offset
945 */
946 ret = criu_checkpoint_queues_device(pdd, user_priv_data, &q_index,
947 priv_data_offset);
948
949 if (ret)
950 break;
951 }
952
953 return ret;
954 }
955
set_queue_properties_from_criu(struct queue_properties * qp,struct kfd_criu_queue_priv_data * q_data,uint32_t num_xcc)956 static void set_queue_properties_from_criu(struct queue_properties *qp,
957 struct kfd_criu_queue_priv_data *q_data, uint32_t num_xcc)
958 {
959 qp->is_interop = false;
960 qp->queue_percent = q_data->q_percent;
961 qp->priority = q_data->priority;
962 qp->queue_address = q_data->q_address;
963 qp->queue_size = q_data->q_size;
964 qp->read_ptr = (uint32_t *) q_data->read_ptr_addr;
965 qp->write_ptr = (uint32_t *) q_data->write_ptr_addr;
966 qp->eop_ring_buffer_address = q_data->eop_ring_buffer_address;
967 qp->eop_ring_buffer_size = q_data->eop_ring_buffer_size;
968 qp->ctx_save_restore_area_address = q_data->ctx_save_restore_area_address;
969 qp->ctx_save_restore_area_size = q_data->ctx_save_restore_area_size;
970 if (q_data->type == KFD_QUEUE_TYPE_COMPUTE)
971 qp->ctl_stack_size = q_data->ctl_stack_size / num_xcc;
972 else
973 qp->ctl_stack_size = q_data->ctl_stack_size;
974
975 qp->type = q_data->type;
976 qp->format = q_data->format;
977 }
978
kfd_criu_restore_queue(struct kfd_process * p,uint8_t __user * user_priv_ptr,uint64_t * priv_data_offset,uint64_t max_priv_data_size)979 int kfd_criu_restore_queue(struct kfd_process *p,
980 uint8_t __user *user_priv_ptr,
981 uint64_t *priv_data_offset,
982 uint64_t max_priv_data_size)
983 {
984 uint8_t *mqd, *ctl_stack, *q_extra_data = NULL;
985 struct kfd_criu_queue_priv_data *q_data;
986 struct kfd_process_device *pdd;
987 uint64_t q_extra_data_size;
988 struct queue_properties qp;
989 unsigned int queue_id;
990 int ret = 0;
991
992 if (*priv_data_offset + sizeof(*q_data) > max_priv_data_size)
993 return -EINVAL;
994
995 q_data = kmalloc_obj(*q_data);
996 if (!q_data)
997 return -ENOMEM;
998
999 ret = copy_from_user(q_data, user_priv_ptr + *priv_data_offset, sizeof(*q_data));
1000 if (ret) {
1001 ret = -EFAULT;
1002 goto exit;
1003 }
1004
1005 *priv_data_offset += sizeof(*q_data);
1006 q_extra_data_size = (uint64_t)q_data->ctl_stack_size + q_data->mqd_size;
1007
1008 if (*priv_data_offset + q_extra_data_size > max_priv_data_size) {
1009 ret = -EINVAL;
1010 goto exit;
1011 }
1012
1013 q_extra_data = kmalloc(q_extra_data_size, GFP_KERNEL);
1014 if (!q_extra_data) {
1015 ret = -ENOMEM;
1016 goto exit;
1017 }
1018
1019 ret = copy_from_user(q_extra_data, user_priv_ptr + *priv_data_offset, q_extra_data_size);
1020 if (ret) {
1021 ret = -EFAULT;
1022 goto exit;
1023 }
1024
1025 *priv_data_offset += q_extra_data_size;
1026
1027 pdd = kfd_process_device_data_by_id(p, q_data->gpu_id);
1028 if (!pdd) {
1029 pr_err("Failed to get pdd\n");
1030 ret = -EINVAL;
1031 goto exit;
1032 }
1033
1034 /*
1035 * data stored in this order:
1036 * mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]...
1037 */
1038 mqd = q_extra_data;
1039 ctl_stack = mqd + q_data->mqd_size;
1040
1041 memset(&qp, 0, sizeof(qp));
1042 set_queue_properties_from_criu(&qp, q_data, NUM_XCC(pdd->dev->adev->gfx.xcc_mask));
1043
1044 print_queue_properties(&qp);
1045
1046 ret = pqm_create_queue(&p->pqm, pdd->dev, &qp, &queue_id, q_data, mqd, ctl_stack, NULL);
1047 if (ret) {
1048 pr_err("Failed to create new queue err:%d\n", ret);
1049 goto exit;
1050 }
1051
1052 if (q_data->gws)
1053 ret = pqm_set_gws(&p->pqm, q_data->q_id, pdd->dev->gws);
1054
1055 exit:
1056 if (ret)
1057 pr_err("Failed to restore queue (%d)\n", ret);
1058 else
1059 pr_debug("Queue id %d was restored successfully\n", queue_id);
1060
1061 kfree(q_data);
1062 kfree(q_extra_data);
1063
1064 return ret;
1065 }
1066
pqm_get_queue_checkpoint_info(struct process_queue_manager * pqm,unsigned int qid,uint32_t * mqd_size,uint32_t * ctl_stack_size)1067 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm,
1068 unsigned int qid,
1069 uint32_t *mqd_size,
1070 uint32_t *ctl_stack_size)
1071 {
1072 struct process_queue_node *pqn;
1073
1074 pqn = get_queue_by_qid(pqm, qid);
1075 if (!pqn) {
1076 pr_debug("amdkfd: No queue %d exists for operation\n", qid);
1077 return -EFAULT;
1078 }
1079
1080 if (!pqn->q->device->dqm->ops.get_queue_checkpoint_info) {
1081 pr_err("amdkfd: queue dumping not supported on this device\n");
1082 return -EOPNOTSUPP;
1083 }
1084
1085 pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm,
1086 pqn->q, mqd_size,
1087 ctl_stack_size);
1088 return 0;
1089 }
1090
1091 #if defined(CONFIG_DEBUG_FS)
1092
pqm_debugfs_mqds(struct seq_file * m,void * data)1093 int pqm_debugfs_mqds(struct seq_file *m, void *data)
1094 {
1095 struct process_queue_manager *pqm = data;
1096 struct process_queue_node *pqn;
1097 struct queue *q;
1098 enum KFD_MQD_TYPE mqd_type;
1099 struct mqd_manager *mqd_mgr;
1100 int r = 0, xcc, num_xccs = 1;
1101 void *mqd;
1102 uint64_t size = 0;
1103
1104 list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
1105 if (pqn->q) {
1106 q = pqn->q;
1107 switch (q->properties.type) {
1108 case KFD_QUEUE_TYPE_SDMA:
1109 case KFD_QUEUE_TYPE_SDMA_XGMI:
1110 seq_printf(m, " SDMA queue on device %x\n",
1111 q->device->id);
1112 mqd_type = KFD_MQD_TYPE_SDMA;
1113 break;
1114 case KFD_QUEUE_TYPE_COMPUTE:
1115 seq_printf(m, " Compute queue on device %x\n",
1116 q->device->id);
1117 mqd_type = KFD_MQD_TYPE_CP;
1118 num_xccs = NUM_XCC(q->device->xcc_mask);
1119 break;
1120 default:
1121 seq_printf(m,
1122 " Queue node with bad user queue type %d on device %x\n",
1123 q->properties.type, q->device->id);
1124 continue;
1125 }
1126 mqd_mgr = q->device->dqm->mqd_mgrs[mqd_type];
1127 size = mqd_mgr->mqd_stride(mqd_mgr,
1128 &q->properties);
1129 }
1130
1131 for (xcc = 0; xcc < num_xccs; xcc++) {
1132 mqd = q->mqd + size * xcc;
1133 r = mqd_mgr->debugfs_show_mqd(m, mqd);
1134 if (r != 0)
1135 break;
1136 }
1137 }
1138
1139 return r;
1140 }
1141
1142 #endif
1143