1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
9 #define _ASM_X86_AMD_IOMMU_TYPES_H
10
11 #include <linux/bitfield.h>
12 #include <linux/iommu.h>
13 #include <linux/types.h>
14 #include <linux/mmu_notifier.h>
15 #include <linux/mutex.h>
16 #include <linux/msi.h>
17 #include <linux/list.h>
18 #include <linux/spinlock.h>
19 #include <linux/pci.h>
20 #include <linux/irqreturn.h>
21 #include <linux/generic_pt/iommu.h>
22
23 /*
24 * Maximum number of IOMMUs supported
25 */
26 #define MAX_IOMMUS 32
27
28 /*
29 * some size calculation constants
30 */
31 #define DEV_TABLE_ENTRY_SIZE 32
32
33 /* Capability offsets used by the driver */
34 #define MMIO_CAP_HDR_OFFSET 0x00
35 #define MMIO_RANGE_OFFSET 0x0c
36 #define MMIO_MISC_OFFSET 0x10
37
38 /* Masks, shifts and macros to parse the device range capability */
39 #define MMIO_RANGE_LD_MASK 0xff000000
40 #define MMIO_RANGE_FD_MASK 0x00ff0000
41 #define MMIO_RANGE_BUS_MASK 0x0000ff00
42 #define MMIO_RANGE_LD_SHIFT 24
43 #define MMIO_RANGE_FD_SHIFT 16
44 #define MMIO_RANGE_BUS_SHIFT 8
45 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
46 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
47 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
48 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
49
50 /* Flag masks for the AMD IOMMU exclusion range */
51 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
52 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
53
54 /* Used offsets into the MMIO space */
55 #define MMIO_DEV_TABLE_OFFSET 0x0000
56 #define MMIO_CMD_BUF_OFFSET 0x0008
57 #define MMIO_EVT_BUF_OFFSET 0x0010
58 #define MMIO_CONTROL_OFFSET 0x0018
59 #define MMIO_EXCL_BASE_OFFSET 0x0020
60 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
61 #define MMIO_EXT_FEATURES 0x0030
62 #define MMIO_PPR_LOG_OFFSET 0x0038
63 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0
64 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8
65 #define MMIO_MSI_ADDR_LO_OFFSET 0x015C
66 #define MMIO_MSI_ADDR_HI_OFFSET 0x0160
67 #define MMIO_MSI_DATA_OFFSET 0x0164
68 #define MMIO_INTCAPXT_EVT_OFFSET 0x0170
69 #define MMIO_INTCAPXT_PPR_OFFSET 0x0178
70 #define MMIO_INTCAPXT_GALOG_OFFSET 0x0180
71 #define MMIO_EXT_FEATURES2 0x01A0
72 #define MMIO_CMD_HEAD_OFFSET 0x2000
73 #define MMIO_CMD_TAIL_OFFSET 0x2008
74 #define MMIO_EVT_HEAD_OFFSET 0x2010
75 #define MMIO_EVT_TAIL_OFFSET 0x2018
76 #define MMIO_STATUS_OFFSET 0x2020
77 #define MMIO_PPR_HEAD_OFFSET 0x2030
78 #define MMIO_PPR_TAIL_OFFSET 0x2038
79 #define MMIO_GA_HEAD_OFFSET 0x2040
80 #define MMIO_GA_TAIL_OFFSET 0x2048
81 #define MMIO_CNTR_CONF_OFFSET 0x4000
82 #define MMIO_CNTR_REG_OFFSET 0x40000
83 #define MMIO_REG_END_OFFSET 0x80000
84
85
86
87 /* Extended Feature Bits */
88 #define FEATURE_PREFETCH BIT_ULL(0)
89 #define FEATURE_PPR BIT_ULL(1)
90 #define FEATURE_X2APIC BIT_ULL(2)
91 #define FEATURE_NX BIT_ULL(3)
92 #define FEATURE_GT BIT_ULL(4)
93 #define FEATURE_IA BIT_ULL(6)
94 #define FEATURE_GA BIT_ULL(7)
95 #define FEATURE_HE BIT_ULL(8)
96 #define FEATURE_PC BIT_ULL(9)
97 #define FEATURE_HATS GENMASK_ULL(11, 10)
98 #define FEATURE_GATS GENMASK_ULL(13, 12)
99 #define FEATURE_GLX GENMASK_ULL(15, 14)
100 #define FEATURE_GAM_VAPIC BIT_ULL(21)
101 #define FEATURE_PASMAX GENMASK_ULL(36, 32)
102 #define FEATURE_GIOSUP BIT_ULL(48)
103 #define FEATURE_HASUP BIT_ULL(49)
104 #define FEATURE_EPHSUP BIT_ULL(50)
105 #define FEATURE_HDSUP BIT_ULL(52)
106 #define FEATURE_SNP BIT_ULL(63)
107
108
109 /* Extended Feature 2 Bits */
110 #define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5)
111 #define FEATURE_SNPAVICSUP_GAM(x) \
112 (FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1)
113 #define FEATURE_HT_RANGE_IGNORE BIT_ULL(11)
114
115 #define FEATURE_NUM_INT_REMAP_SUP GENMASK_ULL(9, 8)
116 #define FEATURE_NUM_INT_REMAP_SUP_2K(x) \
117 (FIELD_GET(FEATURE_NUM_INT_REMAP_SUP, x) == 0x1)
118
119 /* Note:
120 * The current driver only support 16-bit PASID.
121 * Currently, hardware only implement upto 16-bit PASID
122 * even though the spec says it could have upto 20 bits.
123 */
124 #define PASID_MASK 0x0000ffff
125
126 /* MMIO status bits */
127 #define MMIO_STATUS_EVT_OVERFLOW_MASK BIT(0)
128 #define MMIO_STATUS_EVT_INT_MASK BIT(1)
129 #define MMIO_STATUS_COM_WAIT_INT_MASK BIT(2)
130 #define MMIO_STATUS_EVT_RUN_MASK BIT(3)
131 #define MMIO_STATUS_PPR_OVERFLOW_MASK BIT(5)
132 #define MMIO_STATUS_PPR_INT_MASK BIT(6)
133 #define MMIO_STATUS_PPR_RUN_MASK BIT(7)
134 #define MMIO_STATUS_GALOG_RUN_MASK BIT(8)
135 #define MMIO_STATUS_GALOG_OVERFLOW_MASK BIT(9)
136 #define MMIO_STATUS_GALOG_INT_MASK BIT(10)
137
138 /* event logging constants */
139 #define EVENT_ENTRY_SIZE 0x10
140 #define EVENT_TYPE_SHIFT 28
141 #define EVENT_TYPE_MASK 0xf
142 #define EVENT_TYPE_ILL_DEV 0x1
143 #define EVENT_TYPE_IO_FAULT 0x2
144 #define EVENT_TYPE_DEV_TAB_ERR 0x3
145 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
146 #define EVENT_TYPE_ILL_CMD 0x5
147 #define EVENT_TYPE_CMD_HARD_ERR 0x6
148 #define EVENT_TYPE_IOTLB_INV_TO 0x7
149 #define EVENT_TYPE_INV_DEV_REQ 0x8
150 #define EVENT_TYPE_INV_PPR_REQ 0x9
151 #define EVENT_TYPE_RMP_FAULT 0xd
152 #define EVENT_TYPE_RMP_HW_ERR 0xe
153 #define EVENT_DEVID_MASK 0xffff
154 #define EVENT_DEVID_SHIFT 0
155 #define EVENT_DOMID_MASK_LO 0xffff
156 #define EVENT_DOMID_MASK_HI 0xf0000
157 #define EVENT_FLAGS_MASK 0xfff
158 #define EVENT_FLAGS_SHIFT 0x10
159 #define EVENT_FLAG_RW 0x020
160 #define EVENT_FLAG_I 0x008
161
162 /* feature control bits */
163 #define CONTROL_IOMMU_EN 0
164 #define CONTROL_HT_TUN_EN 1
165 #define CONTROL_EVT_LOG_EN 2
166 #define CONTROL_EVT_INT_EN 3
167 #define CONTROL_COMWAIT_EN 4
168 #define CONTROL_INV_TIMEOUT 5
169 #define CONTROL_PASSPW_EN 8
170 #define CONTROL_RESPASSPW_EN 9
171 #define CONTROL_COHERENT_EN 10
172 #define CONTROL_ISOC_EN 11
173 #define CONTROL_CMDBUF_EN 12
174 #define CONTROL_PPRLOG_EN 13
175 #define CONTROL_PPRINT_EN 14
176 #define CONTROL_PPR_EN 15
177 #define CONTROL_GT_EN 16
178 #define CONTROL_GA_EN 17
179 #define CONTROL_GAM_EN 25
180 #define CONTROL_GALOG_EN 28
181 #define CONTROL_GAINT_EN 29
182 #define CONTROL_NUM_INT_REMAP_MODE 43
183 #define CONTROL_NUM_INT_REMAP_MODE_MASK 0x03
184 #define CONTROL_NUM_INT_REMAP_MODE_2K 0x01
185 #define CONTROL_EPH_EN 45
186 #define CONTROL_XT_EN 50
187 #define CONTROL_INTCAPXT_EN 51
188 #define CONTROL_IRTCACHEDIS 59
189 #define CONTROL_SNPAVIC_EN 61
190
191 #define CTRL_INV_TO_MASK 7
192 #define CTRL_INV_TO_NONE 0
193 #define CTRL_INV_TO_1MS 1
194 #define CTRL_INV_TO_10MS 2
195 #define CTRL_INV_TO_100MS 3
196 #define CTRL_INV_TO_1S 4
197 #define CTRL_INV_TO_10S 5
198 #define CTRL_INV_TO_100S 6
199
200 /* command specific defines */
201 #define CMD_COMPL_WAIT 0x01
202 #define CMD_INV_DEV_ENTRY 0x02
203 #define CMD_INV_IOMMU_PAGES 0x03
204 #define CMD_INV_IOTLB_PAGES 0x04
205 #define CMD_INV_IRT 0x05
206 #define CMD_COMPLETE_PPR 0x07
207 #define CMD_INV_ALL 0x08
208
209 #define CMD_COMPL_WAIT_STORE_MASK 0x01
210 #define CMD_COMPL_WAIT_INT_MASK 0x02
211 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
212 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
213 #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04
214
215 #define PPR_STATUS_MASK 0xf
216 #define PPR_STATUS_SHIFT 12
217
218 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
219
220 /* macros and definitions for device table entries */
221 #define DEV_ENTRY_VALID 0x00
222 #define DEV_ENTRY_TRANSLATION 0x01
223 #define DEV_ENTRY_HAD 0x07
224 #define DEV_ENTRY_PPR 0x34
225 #define DEV_ENTRY_IR 0x3d
226 #define DEV_ENTRY_IW 0x3e
227 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
228 #define DEV_ENTRY_EX 0x67
229 #define DEV_ENTRY_SYSMGT1 0x68
230 #define DEV_ENTRY_SYSMGT2 0x69
231 #define DTE_DATA1_SYSMGT_MASK GENMASK_ULL(41, 40)
232
233 #define DEV_ENTRY_IRQ_TBL_EN 0x80
234 #define DEV_ENTRY_INIT_PASS 0xb8
235 #define DEV_ENTRY_EINT_PASS 0xb9
236 #define DEV_ENTRY_NMI_PASS 0xba
237 #define DEV_ENTRY_LINT0_PASS 0xbe
238 #define DEV_ENTRY_LINT1_PASS 0xbf
239 #define DEV_ENTRY_MODE_MASK 0x07
240 #define DEV_ENTRY_MODE_SHIFT 0x09
241
242 #define MAX_DEV_TABLE_ENTRIES 0xffff
243
244 /* constants to configure the command buffer */
245 #define CMD_BUFFER_SIZE 8192
246 #define CMD_BUFFER_UNINITIALIZED 1
247 #define CMD_BUFFER_ENTRIES 512
248 #define MMIO_CMD_SIZE_SHIFT 56
249 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
250 #define MMIO_CMD_HEAD_MASK GENMASK_ULL(18, 4) /* Command buffer head ptr field [18:4] */
251 #define MMIO_CMD_BUFFER_HEAD(x) FIELD_GET(MMIO_CMD_HEAD_MASK, (x))
252 #define MMIO_CMD_TAIL_MASK GENMASK_ULL(18, 4) /* Command buffer tail ptr field [18:4] */
253 #define MMIO_CMD_BUFFER_TAIL(x) FIELD_GET(MMIO_CMD_TAIL_MASK, (x))
254
255 /* constants for event buffer handling */
256 #define EVT_BUFFER_SIZE 8192 /* 512 entries */
257 #define EVT_LEN_MASK (0x9ULL << 56)
258
259 /* Constants for PPR Log handling */
260 #define PPR_LOG_ENTRIES 512
261 #define PPR_LOG_SIZE_SHIFT 56
262 #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT)
263 #define PPR_ENTRY_SIZE 16
264 #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
265
266 /* PAGE_SERVICE_REQUEST PPR Log Buffer Entry flags */
267 #define PPR_FLAG_EXEC 0x002 /* Execute permission requested */
268 #define PPR_FLAG_READ 0x004 /* Read permission requested */
269 #define PPR_FLAG_WRITE 0x020 /* Write permission requested */
270 #define PPR_FLAG_US 0x040 /* 1: User, 0: Supervisor */
271 #define PPR_FLAG_RVSD 0x080 /* Reserved bit not zero */
272 #define PPR_FLAG_GN 0x100 /* GVA and PASID is valid */
273
274 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
275 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL)
276 #define PPR_DEVID(x) ((x) & 0xffffULL)
277 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL)
278 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL)
279 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL)
280 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
281
282 #define PPR_REQ_FAULT 0x01
283
284 /* Constants for GA Log handling */
285 #define GA_LOG_ENTRIES 512
286 #define GA_LOG_SIZE_SHIFT 56
287 #define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT)
288 #define GA_ENTRY_SIZE 8
289 #define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES)
290
291 #define GA_TAG(x) (u32)(x & 0xffffffffULL)
292 #define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL)
293 #define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
294
295 #define GA_GUEST_NR 0x1
296
297 #define IOMMU_IN_ADDR_BIT_SIZE 52
298 #define IOMMU_OUT_ADDR_BIT_SIZE 52
299
300 /*
301 * This bitmap is used to advertise the page sizes our hardware support
302 * to the IOMMU core, which will then use this information to split
303 * physically contiguous memory regions it is mapping into page sizes
304 * that we support.
305 *
306 * 512GB Pages are not supported due to a hardware bug
307 * Page sizes >= the 52 bit max physical address of the CPU are not supported.
308 */
309 #define AMD_IOMMU_PGSIZES (GENMASK_ULL(51, 12) ^ SZ_512G)
310
311 /* Special mode where page-sizes are limited to 4 KiB */
312 #define AMD_IOMMU_PGSIZES_4K (PAGE_SIZE)
313
314 /* 4K, 2MB, 1G page sizes are supported */
315 #define AMD_IOMMU_PGSIZES_V2 (PAGE_SIZE | (1ULL << 21) | (1ULL << 30))
316
317 /* Bit value definition for dte irq remapping fields*/
318 #define DTE_IRQ_PHYS_ADDR_MASK GENMASK_ULL(51, 6)
319 #define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60)
320 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
321 #define DTE_IRQ_REMAP_ENABLE 1ULL
322
323 #define DTE_INTTAB_ALIGNMENT 128
324 #define DTE_INTTABLEN_MASK (0xfULL << 1)
325 #define DTE_INTTABLEN_VALUE_512 9ULL
326 #define DTE_INTTABLEN_512 (DTE_INTTABLEN_VALUE_512 << 1)
327 #define MAX_IRQS_PER_TABLE_512 BIT(DTE_INTTABLEN_VALUE_512)
328 #define DTE_INTTABLEN_VALUE_2K 11ULL
329 #define DTE_INTTABLEN_2K (DTE_INTTABLEN_VALUE_2K << 1)
330 #define MAX_IRQS_PER_TABLE_2K BIT(DTE_INTTABLEN_VALUE_2K)
331
332 #define PAGE_MODE_NONE 0x00
333 #define PAGE_MODE_1_LEVEL 0x01
334 #define PAGE_MODE_2_LEVEL 0x02
335 #define PAGE_MODE_3_LEVEL 0x03
336 #define PAGE_MODE_4_LEVEL 0x04
337 #define PAGE_MODE_5_LEVEL 0x05
338 #define PAGE_MODE_6_LEVEL 0x06
339 #define PAGE_MODE_7_LEVEL 0x07
340
341 #define GUEST_PGTABLE_4_LEVEL 0x00
342 #define GUEST_PGTABLE_5_LEVEL 0x01
343
344 #define PM_ADDR_MASK 0x000ffffffffff000ULL
345
346 /*
347 * Bit value definition for DTE fields
348 */
349 #define DTE_FLAG_V BIT_ULL(0)
350 #define DTE_FLAG_TV BIT_ULL(1)
351 #define DTE_FLAG_HAD (3ULL << 7)
352 #define DTE_FLAG_GIOV BIT_ULL(54)
353 #define DTE_FLAG_GV BIT_ULL(55)
354 #define DTE_GLX GENMASK_ULL(57, 56)
355 #define DTE_FLAG_IR BIT_ULL(61)
356 #define DTE_FLAG_IW BIT_ULL(62)
357
358 #define DTE_FLAG_IOTLB BIT_ULL(32)
359 #define DTE_FLAG_MASK (0x3ffULL << 32)
360 #define DEV_DOMID_MASK 0xffffULL
361
362 #define DTE_GCR3_14_12 GENMASK_ULL(60, 58)
363 #define DTE_GCR3_30_15 GENMASK_ULL(31, 16)
364 #define DTE_GCR3_51_31 GENMASK_ULL(63, 43)
365
366 #define DTE_GPT_LEVEL_SHIFT 54
367 #define DTE_GPT_LEVEL_MASK GENMASK_ULL(55, 54)
368
369 #define GCR3_VALID 0x01ULL
370
371 /* DTE[128:179] | DTE[184:191] */
372 #define DTE_DATA2_INTR_MASK ~GENMASK_ULL(55, 52)
373
374 #define IOMMU_PROT_MASK 0x03
375 #define IOMMU_PROT_IR 0x01
376 #define IOMMU_PROT_IW 0x02
377
378 #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2)
379
380 /* IOMMU capabilities */
381 #define IOMMU_CAP_IOTLB 24
382 #define IOMMU_CAP_NPCACHE 26
383 #define IOMMU_CAP_EFR 27
384
385 /* IOMMU IVINFO */
386 #define IOMMU_IVINFO_OFFSET 36
387 #define IOMMU_IVINFO_EFRSUP BIT(0)
388 #define IOMMU_IVINFO_DMA_REMAP BIT(1)
389
390 /* IOMMU Feature Reporting Field (for IVHD type 10h */
391 #define IOMMU_FEAT_GASUP_SHIFT 6
392
393 /* IOMMU HATDIS for IVHD type 11h and 40h */
394 #define IOMMU_IVHD_ATTR_HATDIS_SHIFT 0
395
396 /* IOMMU Extended Feature Register (EFR) */
397 #define IOMMU_EFR_XTSUP_SHIFT 2
398 #define IOMMU_EFR_GASUP_SHIFT 7
399 #define IOMMU_EFR_MSICAPMMIOSUP_SHIFT 46
400
401 #define MAX_DOMAIN_ID 65536
402
403 /* Timeout stuff */
404 #define LOOP_TIMEOUT 100000
405 #define MMIO_STATUS_TIMEOUT 2000000
406
407 extern bool amd_iommu_dump;
408 #define DUMP_printk(format, arg...) \
409 do { \
410 if (amd_iommu_dump) \
411 pr_info(format, ## arg); \
412 } while(0);
413
414 /* global flag if IOMMUs cache non-present entries */
415 extern bool amd_iommu_np_cache;
416 /* Only true if all IOMMUs support device IOTLBs */
417 extern bool amd_iommu_iotlb_sup;
418
419 struct irq_remap_table {
420 raw_spinlock_t lock;
421 unsigned min_index;
422 u32 *table;
423 };
424
425 /* Interrupt remapping feature used? */
426 extern bool amd_iommu_irq_remap;
427
428 extern const struct iommu_ops amd_iommu_ops;
429
430 /* IVRS indicates that pre-boot remapping was enabled */
431 extern bool amdr_ivrs_remap_support;
432
433 #define PCI_SBDF_TO_SEGID(sbdf) (((sbdf) >> 16) & 0xffff)
434 #define PCI_SBDF_TO_DEVID(sbdf) ((sbdf) & 0xffff)
435 #define PCI_SEG_DEVID_TO_SBDF(seg, devid) ((((u32)(seg) & 0xffff) << 16) | \
436 ((devid) & 0xffff))
437
438 /* Make iterating over all pci segment easier */
439 #define for_each_pci_segment(pci_seg) \
440 list_for_each_entry((pci_seg), &amd_iommu_pci_seg_list, list)
441 #define for_each_pci_segment_safe(pci_seg, next) \
442 list_for_each_entry_safe((pci_seg), (next), &amd_iommu_pci_seg_list, list)
443 /*
444 * Make iterating over all IOMMUs easier
445 */
446 #define for_each_iommu(iommu) \
447 list_for_each_entry((iommu), &amd_iommu_list, list)
448 #define for_each_iommu_safe(iommu, next) \
449 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
450 /* Making iterating over protection_domain->dev_data_list easier */
451 #define for_each_pdom_dev_data(pdom_dev_data, pdom) \
452 list_for_each_entry(pdom_dev_data, &pdom->dev_data_list, list)
453 #define for_each_pdom_dev_data_safe(pdom_dev_data, next, pdom) \
454 list_for_each_entry_safe((pdom_dev_data), (next), &pdom->dev_data_list, list)
455
456 #define for_each_ivhd_dte_flags(entry) \
457 list_for_each_entry((entry), &amd_ivhd_dev_flags_list, list)
458
459 struct amd_iommu;
460 struct iommu_domain;
461 struct irq_domain;
462 struct amd_irte_ops;
463
464 #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0)
465
466 struct gcr3_tbl_info {
467 u64 *gcr3_tbl; /* Guest CR3 table */
468 int glx; /* Number of levels for GCR3 table */
469 u32 pasid_cnt; /* Track attached PASIDs */
470 u16 domid; /* Per device domain ID */
471 };
472
473 enum protection_domain_mode {
474 PD_MODE_NONE,
475 PD_MODE_V1,
476 PD_MODE_V2,
477 };
478
479 /* Track dev_data/PASID list for the protection domain */
480 struct pdom_dev_data {
481 /* Points to attached device data */
482 struct iommu_dev_data *dev_data;
483 /* PASID attached to the protection domain */
484 ioasid_t pasid;
485 /* For protection_domain->dev_data_list */
486 struct list_head list;
487 };
488
489 /* Keeps track of the IOMMUs attached to protection domain */
490 struct pdom_iommu_info {
491 struct amd_iommu *iommu; /* IOMMUs attach to protection domain */
492 u32 refcnt; /* Count of attached dev/pasid per domain/IOMMU */
493 };
494
495 /*
496 * This structure contains generic data for IOMMU protection domains
497 * independent of their use.
498 */
499 struct protection_domain {
500 union {
501 struct iommu_domain domain;
502 struct pt_iommu iommu;
503 struct pt_iommu_amdv1 amdv1;
504 struct pt_iommu_x86_64 amdv2;
505 };
506 struct list_head dev_list; /* List of all devices in this domain */
507 spinlock_t lock; /* mostly used to lock the page table*/
508 u16 id; /* the domain id written to the device table */
509 enum protection_domain_mode pd_mode; /* Track page table type */
510 bool dirty_tracking; /* dirty tracking is enabled in the domain */
511 struct xarray iommu_array; /* per-IOMMU reference count */
512
513 struct mmu_notifier mn; /* mmu notifier for the SVA domain */
514 struct list_head dev_data_list; /* List of pdom_dev_data */
515 };
516 PT_IOMMU_CHECK_DOMAIN(struct protection_domain, iommu, domain);
517 PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv1.iommu, domain);
518 PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv2.iommu, domain);
519
520 /*
521 * This structure contains information about one PCI segment in the system.
522 */
523 struct amd_iommu_pci_seg {
524 /* List with all PCI segments in the system */
525 struct list_head list;
526
527 /* List of all available dev_data structures */
528 struct llist_head dev_data_list;
529
530 /* PCI segment number */
531 u16 id;
532
533 /* Largest PCI device id we expect translation requests for */
534 u16 last_bdf;
535
536 /* Size of the device table */
537 u32 dev_table_size;
538
539 /*
540 * device table virtual address
541 *
542 * Pointer to the per PCI segment device table.
543 * It is indexed by the PCI device id or the HT unit id and contains
544 * information about the domain the device belongs to as well as the
545 * page table root pointer.
546 */
547 struct dev_table_entry *dev_table;
548
549 /*
550 * The rlookup iommu table is used to find the IOMMU which is
551 * responsible for a specific device. It is indexed by the PCI
552 * device id.
553 */
554 struct amd_iommu **rlookup_table;
555
556 /*
557 * This table is used to find the irq remapping table for a given
558 * device id quickly.
559 */
560 struct irq_remap_table **irq_lookup_table;
561
562 /*
563 * Pointer to a device table which the content of old device table
564 * will be copied to. It's only be used in kdump kernel.
565 */
566 struct dev_table_entry *old_dev_tbl_cpy;
567
568 /*
569 * The alias table is a driver specific data structure which contains the
570 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
571 * More than one device can share the same requestor id.
572 */
573 u16 *alias_table;
574
575 /*
576 * A list of required unity mappings we find in ACPI. It is not locked
577 * because as runtime it is only read. It is created at ACPI table
578 * parsing time.
579 */
580 struct list_head unity_map;
581 };
582
583 /*
584 * Structure where we save information about one hardware AMD IOMMU in the
585 * system.
586 */
587 struct amd_iommu {
588 struct list_head list;
589
590 /* Index within the IOMMU array */
591 int index;
592
593 /* locks the accesses to the hardware */
594 raw_spinlock_t lock;
595
596 /* Pointer to PCI device of this IOMMU */
597 struct pci_dev *dev;
598
599 /* Cache pdev to root device for resume quirks */
600 struct pci_dev *root_pdev;
601
602 /* physical address of MMIO space */
603 u64 mmio_phys;
604
605 /* physical end address of MMIO space */
606 u64 mmio_phys_end;
607
608 /* virtual address of MMIO space */
609 u8 __iomem *mmio_base;
610
611 /* capabilities of that IOMMU read from ACPI */
612 u32 cap;
613
614 /* flags read from acpi table */
615 u8 acpi_flags;
616
617 /* Extended features */
618 u64 features;
619
620 /* Extended features 2 */
621 u64 features2;
622
623 /* PCI device id of the IOMMU device */
624 u16 devid;
625
626 /*
627 * Capability pointer. There could be more than one IOMMU per PCI
628 * device function if there are more than one AMD IOMMU capability
629 * pointers.
630 */
631 u16 cap_ptr;
632
633 /* pci domain of this IOMMU */
634 struct amd_iommu_pci_seg *pci_seg;
635
636 /* start of exclusion range of that IOMMU */
637 u64 exclusion_start;
638 /* length of exclusion range of that IOMMU */
639 u64 exclusion_length;
640
641 /* command buffer virtual address */
642 u8 *cmd_buf;
643 u32 cmd_buf_head;
644 u32 cmd_buf_tail;
645
646 /* event buffer virtual address */
647 u8 *evt_buf;
648
649 /* Name for event log interrupt */
650 unsigned char evt_irq_name[16];
651
652 /* Base of the PPR log, if present */
653 u8 *ppr_log;
654
655 /* Name for PPR log interrupt */
656 unsigned char ppr_irq_name[16];
657
658 /* Base of the GA log, if present */
659 u8 *ga_log;
660
661 /* Name for GA log interrupt */
662 unsigned char ga_irq_name[16];
663
664 /* Tail of the GA log, if present */
665 u8 *ga_log_tail;
666
667 /* true if interrupts for this IOMMU are already enabled */
668 bool int_enabled;
669
670 /* if one, we need to send a completion wait command */
671 bool need_sync;
672
673 /* true if disable irte caching */
674 bool irtcachedis_enabled;
675
676 /* Handle for IOMMU core code */
677 struct iommu_device iommu;
678
679 /*
680 * We can't rely on the BIOS to restore all values on reinit, so we
681 * need to stash them
682 */
683
684 /* The iommu BAR */
685 u32 stored_addr_lo;
686 u32 stored_addr_hi;
687
688 /*
689 * Each iommu has 6 l1s, each of which is documented as having 0x12
690 * registers
691 */
692 u32 stored_l1[6][0x12];
693
694 /* The l2 indirect registers */
695 u32 stored_l2[0x83];
696
697 /* The maximum PC banks and counters/bank (PCSup=1) */
698 u8 max_banks;
699 u8 max_counters;
700 #ifdef CONFIG_IRQ_REMAP
701 struct irq_domain *ir_domain;
702
703 struct amd_irte_ops *irte_ops;
704 #endif
705
706 u32 flags;
707 volatile u64 *cmd_sem;
708 atomic64_t cmd_sem_val;
709 /*
710 * Track physical address to directly use it in build_completion_wait()
711 * and avoid adding any special checks and handling for kdump.
712 */
713 u64 cmd_sem_paddr;
714
715 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
716 /* DebugFS Info */
717 struct dentry *debugfs;
718 int dbg_mmio_offset;
719 int dbg_cap_offset;
720 #endif
721
722 /* IOPF support */
723 struct iopf_queue *iopf_queue;
724 unsigned char iopfq_name[32];
725 };
726
dev_to_amd_iommu(struct device * dev)727 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev)
728 {
729 struct iommu_device *iommu = dev_to_iommu_device(dev);
730
731 return container_of(iommu, struct amd_iommu, iommu);
732 }
733
734 #define ACPIHID_UID_LEN 256
735 #define ACPIHID_HID_LEN 9
736
737 struct acpihid_map_entry {
738 struct list_head list;
739 u8 uid[ACPIHID_UID_LEN];
740 u8 hid[ACPIHID_HID_LEN];
741 u32 devid;
742 u32 root_devid;
743 bool cmd_line;
744 struct iommu_group *group;
745 };
746
747 struct devid_map {
748 struct list_head list;
749 u8 id;
750 u32 devid;
751 bool cmd_line;
752 };
753
754 #define AMD_IOMMU_DEVICE_FLAG_ATS_SUP 0x1 /* ATS feature supported */
755 #define AMD_IOMMU_DEVICE_FLAG_PRI_SUP 0x2 /* PRI feature supported */
756 #define AMD_IOMMU_DEVICE_FLAG_PASID_SUP 0x4 /* PASID context supported */
757 /* Device may request execution on memory pages */
758 #define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP 0x8
759 /* Device may request super-user privileges */
760 #define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10
761
762 /*
763 * This struct contains device specific data for the IOMMU
764 */
765 struct iommu_dev_data {
766 /*Protect against attach/detach races */
767 struct mutex mutex;
768 spinlock_t dte_lock; /* DTE lock for 256-bit access */
769
770 struct list_head list; /* For domain->dev_list */
771 struct llist_node dev_data_list; /* For global dev_data_list */
772 struct protection_domain *domain; /* Domain the device is bound to */
773 struct gcr3_tbl_info gcr3_info; /* Per-device GCR3 table */
774 struct device *dev;
775 u16 devid; /* PCI Device ID */
776
777 unsigned int max_irqs; /* Maximum IRQs supported by device */
778 u32 max_pasids; /* Max supported PASIDs */
779 u32 flags; /* Holds AMD_IOMMU_DEVICE_FLAG_<*> */
780 int ats_qdep;
781 u8 ats_enabled :1; /* ATS state */
782 u8 pri_enabled :1; /* PRI state */
783 u8 pasid_enabled:1; /* PASID state */
784 u8 pri_tlp :1; /* PASID TLB required for
785 PPR completions */
786 u8 ppr :1; /* Enable device PPR support */
787 bool use_vapic; /* Enable device to use vapic mode */
788 bool defer_attach;
789
790 struct ratelimit_state rs; /* Ratelimit IOPF messages */
791 };
792
793 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
794 extern struct list_head ioapic_map;
795 extern struct list_head hpet_map;
796 extern struct list_head acpihid_map;
797
798 /*
799 * List with all PCI segments in the system. This list is not locked because
800 * it is only written at driver initialization time
801 */
802 extern struct list_head amd_iommu_pci_seg_list;
803
804 /*
805 * List with all IOMMUs in the system. This list is not locked because it is
806 * only written and read at driver initialization or suspend time
807 */
808 extern struct list_head amd_iommu_list;
809
810 /*
811 * Structure defining one entry in the device table
812 */
813 struct dev_table_entry {
814 union {
815 u64 data[4];
816 u128 data128[2];
817 };
818 };
819
820 /*
821 * Structure defining one entry in the command buffer
822 */
823 struct iommu_cmd {
824 u32 data[4];
825 };
826
827 /*
828 * Structure to sture persistent DTE flags from IVHD
829 */
830 struct ivhd_dte_flags {
831 struct list_head list;
832 u16 segid;
833 u16 devid_first;
834 u16 devid_last;
835 struct dev_table_entry dte;
836 };
837
838 /*
839 * One entry for unity mappings parsed out of the ACPI table.
840 */
841 struct unity_map_entry {
842 struct list_head list;
843
844 /* starting device id this entry is used for (including) */
845 u16 devid_start;
846 /* end device id this entry is used for (including) */
847 u16 devid_end;
848
849 /* start address to unity map (including) */
850 u64 address_start;
851 /* end address to unity map (including) */
852 u64 address_end;
853
854 /* required protection */
855 int prot;
856 };
857
858 /*
859 * Data structures for device handling
860 */
861
862 extern bool amd_iommu_force_isolation;
863
864 /* Max levels of glxval supported */
865 extern int amd_iommu_max_glx_val;
866
867 /* IDA to track protection domain IDs */
868 extern struct ida pdom_ids;
869
870 /* Global EFR and EFR2 registers */
871 extern u64 amd_iommu_efr;
872 extern u64 amd_iommu_efr2;
873
get_ioapic_devid(int id)874 static inline int get_ioapic_devid(int id)
875 {
876 struct devid_map *entry;
877
878 list_for_each_entry(entry, &ioapic_map, list) {
879 if (entry->id == id)
880 return entry->devid;
881 }
882
883 return -EINVAL;
884 }
885
get_hpet_devid(int id)886 static inline int get_hpet_devid(int id)
887 {
888 struct devid_map *entry;
889
890 list_for_each_entry(entry, &hpet_map, list) {
891 if (entry->id == id)
892 return entry->devid;
893 }
894
895 return -EINVAL;
896 }
897
898 enum amd_iommu_intr_mode_type {
899 AMD_IOMMU_GUEST_IR_LEGACY,
900
901 /* This mode is not visible to users. It is used when
902 * we cannot fully enable vAPIC and fallback to only support
903 * legacy interrupt remapping via 128-bit IRTE.
904 */
905 AMD_IOMMU_GUEST_IR_LEGACY_GA,
906 AMD_IOMMU_GUEST_IR_VAPIC,
907 };
908
909 #define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \
910 x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
911
912 #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC)
913
914 union irte {
915 u32 val;
916 struct {
917 u32 valid : 1,
918 no_fault : 1,
919 int_type : 3,
920 rq_eoi : 1,
921 dm : 1,
922 rsvd_1 : 1,
923 destination : 8,
924 vector : 8,
925 rsvd_2 : 8;
926 } fields;
927 };
928
929 #define APICID_TO_IRTE_DEST_LO(x) (x & 0xffffff)
930 #define APICID_TO_IRTE_DEST_HI(x) ((x >> 24) & 0xff)
931
932 union irte_ga_lo {
933 u64 val;
934
935 /* For int remapping */
936 struct {
937 u64 valid : 1,
938 no_fault : 1,
939 /* ------ */
940 int_type : 3,
941 rq_eoi : 1,
942 dm : 1,
943 /* ------ */
944 guest_mode : 1,
945 destination : 24,
946 ga_tag : 32;
947 } fields_remap;
948
949 /* For guest vAPIC */
950 struct {
951 u64 valid : 1,
952 no_fault : 1,
953 /* ------ */
954 ga_log_intr : 1,
955 rsvd1 : 3,
956 is_run : 1,
957 /* ------ */
958 guest_mode : 1,
959 destination : 24,
960 ga_tag : 32;
961 } fields_vapic;
962 };
963
964 union irte_ga_hi {
965 u64 val;
966 struct {
967 u64 vector : 8,
968 rsvd_1 : 4,
969 ga_root_ptr : 40,
970 rsvd_2 : 4,
971 destination : 8;
972 } fields;
973 };
974
975 struct irte_ga {
976 union {
977 struct {
978 union irte_ga_lo lo;
979 union irte_ga_hi hi;
980 };
981 u128 irte;
982 };
983 };
984
985 struct irq_2_irte {
986 u16 devid; /* Device ID for IRTE table */
987 u16 index; /* Index into IRTE table*/
988 };
989
990 struct amd_ir_data {
991 struct amd_iommu *iommu;
992 struct irq_2_irte irq_2_irte;
993 struct msi_msg msi_entry;
994 void *entry; /* Pointer to union irte or struct irte_ga */
995
996 /**
997 * Store information for activate/de-activate
998 * Guest virtual APIC mode during runtime.
999 */
1000 struct irq_cfg *cfg;
1001 int ga_vector;
1002 u64 ga_root_ptr;
1003 u32 ga_tag;
1004 };
1005
1006 struct amd_irte_ops {
1007 void (*prepare)(void *, u32, bool, u8, u32, int);
1008 void (*activate)(struct amd_iommu *iommu, void *, u16, u16);
1009 void (*deactivate)(struct amd_iommu *iommu, void *, u16, u16);
1010 void (*set_affinity)(struct amd_iommu *iommu, void *, u16, u16, u8, u32);
1011 void *(*get)(struct irq_remap_table *, int);
1012 void (*set_allocated)(struct irq_remap_table *, int);
1013 bool (*is_allocated)(struct irq_remap_table *, int);
1014 void (*clear_allocated)(struct irq_remap_table *, int);
1015 };
1016
1017 #ifdef CONFIG_IRQ_REMAP
1018 extern struct amd_irte_ops irte_32_ops;
1019 extern struct amd_irte_ops irte_128_ops;
1020 #endif
1021
1022 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
1023