1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28
29 #include "ObjectID.h"
30 #include "atomfirmware.h"
31
32 #include "dc_bios_types.h"
33 #include "include/grph_object_ctrl_defs.h"
34 #include "include/bios_parser_interface.h"
35 #include "include/logger_interface.h"
36
37 #include "command_table2.h"
38
39 #include "bios_parser_helper.h"
40 #include "command_table_helper2.h"
41 #include "bios_parser2.h"
42 #include "bios_parser_types_internal2.h"
43 #include "bios_parser_interface.h"
44
45 #include "bios_parser_common.h"
46
47 #define DC_LOGGER \
48 bp->base.ctx->logger
49
50 #define LAST_RECORD_TYPE 0xff
51 #define SMU9_SYSPLL0_ID 0
52
53 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
54 struct atom_i2c_record *record,
55 struct graphics_object_i2c_info *info);
56
57 static enum bp_result bios_parser_get_firmware_info(
58 struct dc_bios *dcb,
59 struct dc_firmware_info *info);
60
61 static enum bp_result bios_parser_get_encoder_cap_info(
62 struct dc_bios *dcb,
63 struct graphics_object_id object_id,
64 struct bp_encoder_cap_info *info);
65
66 static enum bp_result get_firmware_info_v3_1(
67 struct bios_parser *bp,
68 struct dc_firmware_info *info);
69
70 static enum bp_result get_firmware_info_v3_2(
71 struct bios_parser *bp,
72 struct dc_firmware_info *info);
73
74 static enum bp_result get_firmware_info_v3_4(
75 struct bios_parser *bp,
76 struct dc_firmware_info *info);
77
78 static enum bp_result get_firmware_info_v3_5(
79 struct bios_parser *bp,
80 struct dc_firmware_info *info);
81
82 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
83 struct atom_display_object_path_v2 *object);
84
85 static struct atom_encoder_caps_record *get_encoder_cap_record(
86 struct bios_parser *bp,
87 struct atom_display_object_path_v2 *object);
88
89 #define BIOS_IMAGE_SIZE_OFFSET 2
90 #define BIOS_IMAGE_SIZE_UNIT 512
91
92 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
93
bios_parser2_destruct(struct bios_parser * bp)94 static void bios_parser2_destruct(struct bios_parser *bp)
95 {
96 kfree(bp->base.bios_local_image);
97 kfree(bp->base.integrated_info);
98 }
99
firmware_parser_destroy(struct dc_bios ** dcb)100 static void firmware_parser_destroy(struct dc_bios **dcb)
101 {
102 struct bios_parser *bp = BP_FROM_DCB(*dcb);
103
104 if (!bp) {
105 BREAK_TO_DEBUGGER();
106 return;
107 }
108
109 bios_parser2_destruct(bp);
110
111 kfree(bp);
112 *dcb = NULL;
113 }
114
get_atom_data_table_revision(struct atom_common_table_header * atom_data_tbl,struct atom_data_revision * tbl_revision)115 static void get_atom_data_table_revision(
116 struct atom_common_table_header *atom_data_tbl,
117 struct atom_data_revision *tbl_revision)
118 {
119 if (!tbl_revision)
120 return;
121
122 /* initialize the revision to 0 which is invalid revision */
123 tbl_revision->major = 0;
124 tbl_revision->minor = 0;
125
126 if (!atom_data_tbl)
127 return;
128
129 tbl_revision->major =
130 (uint32_t) atom_data_tbl->format_revision & 0x3f;
131 tbl_revision->minor =
132 (uint32_t) atom_data_tbl->content_revision & 0x3f;
133 }
134
135 /* BIOS oject table displaypath is per connector.
136 * There is extra path not for connector. BIOS fill its encoderid as 0
137 */
bios_parser_get_connectors_number(struct dc_bios * dcb)138 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
139 {
140 struct bios_parser *bp = BP_FROM_DCB(dcb);
141 unsigned int count = 0;
142 unsigned int i;
143
144 switch (bp->object_info_tbl.revision.minor) {
145 default:
146 case 4:
147 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++)
148 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
149 count++;
150
151 break;
152
153 case 5:
154 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++)
155 if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0)
156 count++;
157
158 break;
159 }
160 return count;
161 }
162
bios_parser_get_connector_id(struct dc_bios * dcb,uint8_t i)163 static struct graphics_object_id bios_parser_get_connector_id(
164 struct dc_bios *dcb,
165 uint8_t i)
166 {
167 struct bios_parser *bp = BP_FROM_DCB(dcb);
168 struct graphics_object_id object_id = dal_graphics_object_id_init(
169 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
170 struct object_info_table *tbl = &bp->object_info_tbl;
171 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
172
173 struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5;
174
175 switch (bp->object_info_tbl.revision.minor) {
176 default:
177 case 4:
178 if (v1_4->number_of_path > i) {
179 /* If display_objid is generic object id, the encoderObj
180 * /extencoderobjId should be 0
181 */
182 if (v1_4->display_path[i].encoderobjid != 0 &&
183 v1_4->display_path[i].display_objid != 0)
184 object_id = object_id_from_bios_object_id(
185 v1_4->display_path[i].display_objid);
186 }
187 break;
188
189 case 5:
190 if (v1_5->number_of_path > i) {
191 /* If display_objid is generic object id, the encoderObjId
192 * should be 0
193 */
194 if (v1_5->display_path[i].encoderobjid != 0 &&
195 v1_5->display_path[i].display_objid != 0)
196 object_id = object_id_from_bios_object_id(
197 v1_5->display_path[i].display_objid);
198 }
199 break;
200 }
201 return object_id;
202 }
203
bios_parser_get_src_obj(struct dc_bios * dcb,struct graphics_object_id object_id,uint32_t index,struct graphics_object_id * src_object_id)204 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
205 struct graphics_object_id object_id, uint32_t index,
206 struct graphics_object_id *src_object_id)
207 {
208 (void)index;
209 struct bios_parser *bp = BP_FROM_DCB(dcb);
210 unsigned int i;
211 enum bp_result bp_result = BP_RESULT_BADINPUT;
212 struct graphics_object_id obj_id = { 0 };
213 struct object_info_table *tbl = &bp->object_info_tbl;
214
215 if (!src_object_id)
216 return bp_result;
217
218 switch (object_id.type) {
219 /* Encoder's Source is GPU. BIOS does not provide GPU, since all
220 * displaypaths point to same GPU (0x1100). Hardcode GPU object type
221 */
222 case OBJECT_TYPE_ENCODER:
223 /* TODO: since num of src must be less than 2.
224 * If found in for loop, should break.
225 * DAL2 implementation may be changed too
226 */
227 switch (bp->object_info_tbl.revision.minor) {
228 default:
229 case 4:
230 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
231 obj_id = object_id_from_bios_object_id(
232 tbl->v1_4->display_path[i].encoderobjid);
233 if (object_id.type == obj_id.type &&
234 object_id.id == obj_id.id &&
235 object_id.enum_id == obj_id.enum_id) {
236 *src_object_id =
237 object_id_from_bios_object_id(
238 0x1100);
239 /* break; */
240 }
241 }
242 bp_result = BP_RESULT_OK;
243 break;
244
245 case 5:
246 for (i = 0; i < tbl->v1_5->number_of_path; i++) {
247 obj_id = object_id_from_bios_object_id(
248 tbl->v1_5->display_path[i].encoderobjid);
249 if (object_id.type == obj_id.type &&
250 object_id.id == obj_id.id &&
251 object_id.enum_id == obj_id.enum_id) {
252 *src_object_id =
253 object_id_from_bios_object_id(
254 0x1100);
255 /* break; */
256 }
257 }
258 bp_result = BP_RESULT_OK;
259 break;
260 }
261 break;
262 case OBJECT_TYPE_CONNECTOR:
263 switch (bp->object_info_tbl.revision.minor) {
264 default:
265 case 4:
266 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
267 obj_id = object_id_from_bios_object_id(
268 tbl->v1_4->display_path[i]
269 .display_objid);
270
271 if (object_id.type == obj_id.type &&
272 object_id.id == obj_id.id &&
273 object_id.enum_id == obj_id.enum_id) {
274 *src_object_id =
275 object_id_from_bios_object_id(
276 tbl->v1_4
277 ->display_path[i]
278 .encoderobjid);
279 /* break; */
280 }
281 }
282 bp_result = BP_RESULT_OK;
283 break;
284 }
285 bp_result = BP_RESULT_OK;
286 break;
287 case 5:
288 for (i = 0; i < tbl->v1_5->number_of_path; i++) {
289 obj_id = object_id_from_bios_object_id(
290 tbl->v1_5->display_path[i].display_objid);
291
292 if (object_id.type == obj_id.type &&
293 object_id.id == obj_id.id &&
294 object_id.enum_id == obj_id.enum_id) {
295 *src_object_id = object_id_from_bios_object_id(
296 tbl->v1_5->display_path[i].encoderobjid);
297 /* break; */
298 }
299 }
300 bp_result = BP_RESULT_OK;
301 break;
302
303 default:
304 bp_result = BP_RESULT_OK;
305 break;
306 }
307
308 return bp_result;
309 }
310
311 /* from graphics_object_id, find display path which includes the object_id */
get_bios_object(struct bios_parser * bp,struct graphics_object_id id)312 static struct atom_display_object_path_v2 *get_bios_object(
313 struct bios_parser *bp,
314 struct graphics_object_id id)
315 {
316 unsigned int i;
317 struct graphics_object_id obj_id = {0};
318
319 switch (id.type) {
320 case OBJECT_TYPE_ENCODER:
321 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
322 obj_id = object_id_from_bios_object_id(
323 bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
324 if (id.type == obj_id.type && id.id == obj_id.id
325 && id.enum_id == obj_id.enum_id)
326 return &bp->object_info_tbl.v1_4->display_path[i];
327 }
328 fallthrough;
329 case OBJECT_TYPE_CONNECTOR:
330 case OBJECT_TYPE_GENERIC:
331 /* Both Generic and Connector Object ID
332 * will be stored on display_objid
333 */
334 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
335 obj_id = object_id_from_bios_object_id(
336 bp->object_info_tbl.v1_4->display_path[i].display_objid);
337 if (id.type == obj_id.type && id.id == obj_id.id
338 && id.enum_id == obj_id.enum_id)
339 return &bp->object_info_tbl.v1_4->display_path[i];
340 }
341 fallthrough;
342 default:
343 return NULL;
344 }
345 }
346
347 /* from graphics_object_id, find display path which includes the object_id */
get_bios_object_from_path_v3(struct bios_parser * bp,struct graphics_object_id id)348 static struct atom_display_object_path_v3 *get_bios_object_from_path_v3(struct bios_parser *bp,
349 struct graphics_object_id id)
350 {
351 unsigned int i;
352 struct graphics_object_id obj_id = {0};
353
354 switch (id.type) {
355 case OBJECT_TYPE_ENCODER:
356 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
357 obj_id = object_id_from_bios_object_id(
358 bp->object_info_tbl.v1_5->display_path[i].encoderobjid);
359 if (id.type == obj_id.type && id.id == obj_id.id
360 && id.enum_id == obj_id.enum_id)
361 return &bp->object_info_tbl.v1_5->display_path[i];
362 }
363 break;
364
365 case OBJECT_TYPE_CONNECTOR:
366 case OBJECT_TYPE_GENERIC:
367 /* Both Generic and Connector Object ID
368 * will be stored on display_objid
369 */
370 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
371 obj_id = object_id_from_bios_object_id(
372 bp->object_info_tbl.v1_5->display_path[i].display_objid);
373 if (id.type == obj_id.type && id.id == obj_id.id
374 && id.enum_id == obj_id.enum_id)
375 return &bp->object_info_tbl.v1_5->display_path[i];
376 }
377 break;
378
379 default:
380 return NULL;
381 }
382
383 return NULL;
384 }
385
bios_parser_get_i2c_info(struct dc_bios * dcb,struct graphics_object_id id,struct graphics_object_i2c_info * info)386 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
387 struct graphics_object_id id,
388 struct graphics_object_i2c_info *info)
389 {
390 uint32_t offset;
391 struct atom_display_object_path_v2 *object;
392
393 struct atom_display_object_path_v3 *object_path_v3;
394
395 struct atom_common_record_header *header;
396 struct atom_i2c_record *record;
397 struct atom_i2c_record dummy_record = {0};
398 struct bios_parser *bp = BP_FROM_DCB(dcb);
399 int i;
400
401 if (!info)
402 return BP_RESULT_BADINPUT;
403
404 if (id.type == OBJECT_TYPE_GENERIC) {
405 dummy_record.i2c_id = id.id;
406
407 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
408 return BP_RESULT_OK;
409 else
410 return BP_RESULT_NORECORD;
411 }
412
413 switch (bp->object_info_tbl.revision.minor) {
414 case 4:
415 default:
416 object = get_bios_object(bp, id);
417
418 if (!object)
419 return BP_RESULT_BADINPUT;
420
421 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
422 break;
423 case 5:
424 object_path_v3 = get_bios_object_from_path_v3(bp, id);
425
426 if (!object_path_v3)
427 return BP_RESULT_BADINPUT;
428
429 offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset;
430 break;
431 }
432
433 for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
434 header = GET_IMAGE(struct atom_common_record_header, offset);
435
436 if (!header)
437 return BP_RESULT_BADBIOSTABLE;
438
439 if (header->record_type == LAST_RECORD_TYPE ||
440 !header->record_size)
441 break;
442
443 if (header->record_type == ATOM_I2C_RECORD_TYPE
444 && sizeof(struct atom_i2c_record) <=
445 header->record_size) {
446 /* get the I2C info */
447 record = (struct atom_i2c_record *) header;
448
449 if (get_gpio_i2c_info(bp, record, info) ==
450 BP_RESULT_OK)
451 return BP_RESULT_OK;
452 }
453
454 offset += header->record_size;
455 }
456
457 return BP_RESULT_NORECORD;
458 }
459
get_gpio_i2c_info(struct bios_parser * bp,struct atom_i2c_record * record,struct graphics_object_i2c_info * info)460 static enum bp_result get_gpio_i2c_info(
461 struct bios_parser *bp,
462 struct atom_i2c_record *record,
463 struct graphics_object_i2c_info *info)
464 {
465 struct atom_gpio_pin_lut_v2_1 *header;
466 uint32_t count = 0;
467 unsigned int table_index = 0;
468 bool find_valid = false;
469 struct atom_gpio_pin_assignment *pin;
470
471 if (!info)
472 return BP_RESULT_BADINPUT;
473
474 /* get the GPIO_I2C info */
475 if (!DATA_TABLES(gpio_pin_lut))
476 return BP_RESULT_BADBIOSTABLE;
477
478 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
479 DATA_TABLES(gpio_pin_lut));
480 if (!header)
481 return BP_RESULT_BADBIOSTABLE;
482
483 if (sizeof(struct atom_common_table_header) +
484 sizeof(struct atom_gpio_pin_assignment) >
485 le16_to_cpu(header->table_header.structuresize))
486 return BP_RESULT_BADBIOSTABLE;
487
488 /* TODO: is version change? */
489 if (header->table_header.content_revision != 1)
490 return BP_RESULT_UNSUPPORTED;
491
492 /* get data count */
493 count = (le16_to_cpu(header->table_header.structuresize)
494 - sizeof(struct atom_common_table_header))
495 / sizeof(struct atom_gpio_pin_assignment);
496
497 if (!bios_get_image(&bp->base, DATA_TABLES(gpio_pin_lut),
498 le16_to_cpu(header->table_header.structuresize)))
499 return BP_RESULT_BADBIOSTABLE;
500
501 pin = (struct atom_gpio_pin_assignment *) header->gpio_pin;
502
503 for (table_index = 0; table_index < count; table_index++) {
504 if (((record->i2c_id & I2C_HW_CAP) == (pin->gpio_id & I2C_HW_CAP)) &&
505 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == (pin->gpio_id & I2C_HW_ENGINE_ID_MASK)) &&
506 ((record->i2c_id & I2C_HW_LANE_MUX) == (pin->gpio_id & I2C_HW_LANE_MUX))) {
507 /* still valid */
508 find_valid = true;
509 break;
510 }
511 pin = (struct atom_gpio_pin_assignment *)((uint8_t *)pin + sizeof(struct atom_gpio_pin_assignment));
512 }
513
514 /* If we don't find the entry that we are looking for then
515 * we will return BP_Result_BadBiosTable.
516 */
517 if (find_valid == false)
518 return BP_RESULT_BADBIOSTABLE;
519
520 /* get the GPIO_I2C_INFO */
521 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
522 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
523 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
524 info->i2c_slave_address = record->i2c_slave_addr;
525
526 /* TODO: check how to get register offset for en, Y, etc. */
527 info->gpio_info.clk_a_register_index = le16_to_cpu(pin->data_a_reg_index);
528 info->gpio_info.clk_a_shift = pin->gpio_bitshift;
529
530 return BP_RESULT_OK;
531 }
532
get_hpd_record_for_path_v3(struct bios_parser * bp,struct atom_display_object_path_v3 * object)533 static struct atom_hpd_int_record *get_hpd_record_for_path_v3(struct bios_parser *bp,
534 struct atom_display_object_path_v3 *object)
535 {
536 struct atom_common_record_header *header;
537 uint32_t offset;
538 int i;
539
540 if (!object) {
541 BREAK_TO_DEBUGGER(); /* Invalid object */
542 return NULL;
543 }
544
545 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
546
547 for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
548 header = GET_IMAGE(struct atom_common_record_header, offset);
549
550 if (!header)
551 return NULL;
552
553 if (header->record_type == ATOM_RECORD_END_TYPE ||
554 !header->record_size)
555 break;
556
557 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
558 && sizeof(struct atom_hpd_int_record) <=
559 header->record_size)
560 return (struct atom_hpd_int_record *) header;
561
562 offset += header->record_size;
563 }
564
565 return NULL;
566 }
567
bios_parser_get_hpd_info(struct dc_bios * dcb,struct graphics_object_id id,struct graphics_object_hpd_info * info)568 static enum bp_result bios_parser_get_hpd_info(
569 struct dc_bios *dcb,
570 struct graphics_object_id id,
571 struct graphics_object_hpd_info *info)
572 {
573 struct bios_parser *bp = BP_FROM_DCB(dcb);
574 struct atom_display_object_path_v2 *object;
575 struct atom_display_object_path_v3 *object_path_v3;
576 struct atom_hpd_int_record *record = NULL;
577
578 if (!info)
579 return BP_RESULT_BADINPUT;
580
581 switch (bp->object_info_tbl.revision.minor) {
582 case 4:
583 default:
584 object = get_bios_object(bp, id);
585
586 if (!object)
587 return BP_RESULT_BADINPUT;
588
589 record = get_hpd_record(bp, object);
590 break;
591 case 5:
592 object_path_v3 = get_bios_object_from_path_v3(bp, id);
593
594 if (!object_path_v3)
595 return BP_RESULT_BADINPUT;
596
597 record = get_hpd_record_for_path_v3(bp, object_path_v3);
598 break;
599 }
600
601 if (record != NULL) {
602 info->hpd_int_gpio_uid = record->pin_id;
603 info->hpd_active = record->plugin_pin_state;
604 return BP_RESULT_OK;
605 }
606
607 return BP_RESULT_NORECORD;
608 }
609
get_hpd_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)610 static struct atom_hpd_int_record *get_hpd_record(
611 struct bios_parser *bp,
612 struct atom_display_object_path_v2 *object)
613 {
614 struct atom_common_record_header *header;
615 uint32_t offset;
616 int i;
617
618 if (!object) {
619 BREAK_TO_DEBUGGER(); /* Invalid object */
620 return NULL;
621 }
622
623 offset = le16_to_cpu(object->disp_recordoffset)
624 + bp->object_info_tbl_offset;
625
626 for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
627 header = GET_IMAGE(struct atom_common_record_header, offset);
628
629 if (!header)
630 return NULL;
631
632 if (header->record_type == LAST_RECORD_TYPE ||
633 !header->record_size)
634 break;
635
636 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
637 && sizeof(struct atom_hpd_int_record) <=
638 header->record_size)
639 return (struct atom_hpd_int_record *) header;
640
641 offset += header->record_size;
642 }
643
644 return NULL;
645 }
646
647 /**
648 * bios_parser_get_gpio_pin_info
649 * Get GpioPin information of input gpio id
650 *
651 * @dcb: pointer to the DC BIOS
652 * @gpio_id: GPIO ID
653 * @info: GpioPin information structure
654 * return: Bios parser result code
655 * note:
656 * to get the GPIO PIN INFO, we need:
657 * 1. get the GPIO_ID from other object table, see GetHPDInfo()
658 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
659 * to get the registerA offset/mask
660 */
bios_parser_get_gpio_pin_info(struct dc_bios * dcb,uint32_t gpio_id,struct gpio_pin_info * info)661 static enum bp_result bios_parser_get_gpio_pin_info(
662 struct dc_bios *dcb,
663 uint32_t gpio_id,
664 struct gpio_pin_info *info)
665 {
666 struct bios_parser *bp = BP_FROM_DCB(dcb);
667 struct atom_gpio_pin_lut_v2_1 *header;
668 uint32_t count = 0;
669 uint32_t i = 0;
670
671 if (!DATA_TABLES(gpio_pin_lut))
672 return BP_RESULT_BADBIOSTABLE;
673
674 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
675 DATA_TABLES(gpio_pin_lut));
676 if (!header)
677 return BP_RESULT_BADBIOSTABLE;
678
679 if (sizeof(struct atom_common_table_header) +
680 sizeof(struct atom_gpio_pin_assignment)
681 > le16_to_cpu(header->table_header.structuresize))
682 return BP_RESULT_BADBIOSTABLE;
683
684 if (header->table_header.content_revision != 1)
685 return BP_RESULT_UNSUPPORTED;
686
687 /* Temporary hard code gpio pin info */
688 count = (le16_to_cpu(header->table_header.structuresize)
689 - sizeof(struct atom_common_table_header))
690 / sizeof(struct atom_gpio_pin_assignment);
691
692 if (!bios_get_image(&bp->base, DATA_TABLES(gpio_pin_lut),
693 le16_to_cpu(header->table_header.structuresize)))
694 return BP_RESULT_BADBIOSTABLE;
695
696 for (i = 0; i < count; ++i) {
697 if (header->gpio_pin[i].gpio_id != gpio_id)
698 continue;
699
700 info->offset =
701 (uint32_t) le16_to_cpu(
702 header->gpio_pin[i].data_a_reg_index);
703 info->offset_y = info->offset + 2;
704 info->offset_en = info->offset + 1;
705 info->offset_mask = info->offset - 1;
706
707 if (header->gpio_pin[i].gpio_bitshift >= 32)
708 return BP_RESULT_BADBIOSTABLE;
709
710 info->mask = 1u << header->gpio_pin[i].gpio_bitshift;
711 info->mask_y = info->mask + 2;
712 info->mask_en = info->mask + 1;
713 info->mask_mask = info->mask - 1;
714
715 return BP_RESULT_OK;
716 }
717
718 return BP_RESULT_NORECORD;
719 }
720
device_type_from_device_id(uint16_t device_id)721 static struct device_id device_type_from_device_id(uint16_t device_id)
722 {
723
724 struct device_id result_device_id;
725
726 result_device_id.raw_device_tag = device_id;
727
728 switch (device_id) {
729 case ATOM_DISPLAY_LCD1_SUPPORT:
730 result_device_id.device_type = DEVICE_TYPE_LCD;
731 result_device_id.enum_id = 1;
732 break;
733
734 case ATOM_DISPLAY_LCD2_SUPPORT:
735 result_device_id.device_type = DEVICE_TYPE_LCD;
736 result_device_id.enum_id = 2;
737 break;
738
739 case ATOM_DISPLAY_DFP1_SUPPORT:
740 result_device_id.device_type = DEVICE_TYPE_DFP;
741 result_device_id.enum_id = 1;
742 break;
743
744 case ATOM_DISPLAY_DFP2_SUPPORT:
745 result_device_id.device_type = DEVICE_TYPE_DFP;
746 result_device_id.enum_id = 2;
747 break;
748
749 case ATOM_DISPLAY_DFP3_SUPPORT:
750 result_device_id.device_type = DEVICE_TYPE_DFP;
751 result_device_id.enum_id = 3;
752 break;
753
754 case ATOM_DISPLAY_DFP4_SUPPORT:
755 result_device_id.device_type = DEVICE_TYPE_DFP;
756 result_device_id.enum_id = 4;
757 break;
758
759 case ATOM_DISPLAY_DFP5_SUPPORT:
760 result_device_id.device_type = DEVICE_TYPE_DFP;
761 result_device_id.enum_id = 5;
762 break;
763
764 case ATOM_DISPLAY_DFP6_SUPPORT:
765 result_device_id.device_type = DEVICE_TYPE_DFP;
766 result_device_id.enum_id = 6;
767 break;
768
769 default:
770 BREAK_TO_DEBUGGER(); /* Invalid device Id */
771 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
772 result_device_id.enum_id = 0;
773 }
774 return result_device_id;
775 }
776
bios_parser_get_device_tag(struct dc_bios * dcb,struct graphics_object_id connector_object_id,uint32_t device_tag_index,struct connector_device_tag_info * info)777 static enum bp_result bios_parser_get_device_tag(
778 struct dc_bios *dcb,
779 struct graphics_object_id connector_object_id,
780 uint32_t device_tag_index,
781 struct connector_device_tag_info *info)
782 {
783 (void)device_tag_index;
784 struct bios_parser *bp = BP_FROM_DCB(dcb);
785 struct atom_display_object_path_v2 *object;
786
787 struct atom_display_object_path_v3 *object_path_v3;
788
789
790 if (!info)
791 return BP_RESULT_BADINPUT;
792
793 switch (bp->object_info_tbl.revision.minor) {
794 case 4:
795 default:
796 /* getBiosObject will return MXM object */
797 object = get_bios_object(bp, connector_object_id);
798
799 if (!object) {
800 BREAK_TO_DEBUGGER(); /* Invalid object id */
801 return BP_RESULT_BADINPUT;
802 }
803
804 info->acpi_device = 0; /* BIOS no longer provides this */
805 info->dev_id = device_type_from_device_id(object->device_tag);
806 break;
807 case 5:
808 object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id);
809
810 if (!object_path_v3) {
811 BREAK_TO_DEBUGGER(); /* Invalid object id */
812 return BP_RESULT_BADINPUT;
813 }
814 info->acpi_device = 0; /* BIOS no longer provides this */
815 info->dev_id = device_type_from_device_id(object_path_v3->device_tag);
816 break;
817 }
818
819 return BP_RESULT_OK;
820 }
821
get_ss_info_v4_1(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)822 static enum bp_result get_ss_info_v4_1(
823 struct bios_parser *bp,
824 uint32_t id,
825 uint32_t index,
826 struct spread_spectrum_info *ss_info)
827 {
828 (void)index;
829 enum bp_result result = BP_RESULT_OK;
830 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
831 struct atom_smu_info_v3_3 *smu_info = NULL;
832
833 if (!ss_info)
834 return BP_RESULT_BADINPUT;
835
836 if (!DATA_TABLES(dce_info))
837 return BP_RESULT_BADBIOSTABLE;
838
839 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
840 DATA_TABLES(dce_info));
841 if (!disp_cntl_tbl)
842 return BP_RESULT_BADBIOSTABLE;
843
844
845 ss_info->type.STEP_AND_DELAY_INFO = false;
846 ss_info->spread_percentage_divider = 1000;
847 /* BIOS no longer uses target clock. Always enable for now */
848 ss_info->target_clock_range = 0xffffffff;
849
850 switch (id) {
851 case AS_SIGNAL_TYPE_DVI:
852 ss_info->spread_spectrum_percentage =
853 disp_cntl_tbl->dvi_ss_percentage;
854 ss_info->spread_spectrum_range =
855 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
856 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
857 ss_info->type.CENTER_MODE = true;
858
859 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
860 break;
861 case AS_SIGNAL_TYPE_HDMI:
862 ss_info->spread_spectrum_percentage =
863 disp_cntl_tbl->hdmi_ss_percentage;
864 ss_info->spread_spectrum_range =
865 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
866 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
867 ss_info->type.CENTER_MODE = true;
868
869 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
870 break;
871 /* TODO LVDS not support anymore? */
872 case AS_SIGNAL_TYPE_DISPLAY_PORT:
873 ss_info->spread_spectrum_percentage =
874 disp_cntl_tbl->dp_ss_percentage;
875 ss_info->spread_spectrum_range =
876 disp_cntl_tbl->dp_ss_rate_10hz * 10;
877 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
878 ss_info->type.CENTER_MODE = true;
879
880 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
881 break;
882 case AS_SIGNAL_TYPE_GPU_PLL:
883 /* atom_firmware: DAL only get data from dce_info table.
884 * if data within smu_info is needed for DAL, VBIOS should
885 * copy it into dce_info
886 */
887 result = BP_RESULT_UNSUPPORTED;
888 break;
889 case AS_SIGNAL_TYPE_XGMI:
890 smu_info = GET_IMAGE(struct atom_smu_info_v3_3,
891 DATA_TABLES(smu_info));
892 if (!smu_info)
893 return BP_RESULT_BADBIOSTABLE;
894 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage);
895 ss_info->spread_spectrum_percentage =
896 smu_info->waflclk_ss_percentage;
897 ss_info->spread_spectrum_range =
898 smu_info->gpuclk_ss_rate_10hz * 10;
899 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
900 ss_info->type.CENTER_MODE = true;
901
902 DC_LOG_BIOS("AS_SIGNAL_TYPE_XGMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
903 break;
904 default:
905 result = BP_RESULT_UNSUPPORTED;
906 }
907
908 return result;
909 }
910
get_ss_info_v4_2(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)911 static enum bp_result get_ss_info_v4_2(
912 struct bios_parser *bp,
913 uint32_t id,
914 uint32_t index,
915 struct spread_spectrum_info *ss_info)
916 {
917 (void)index;
918 enum bp_result result = BP_RESULT_OK;
919 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
920 struct atom_smu_info_v3_1 *smu_info = NULL;
921
922 if (!ss_info)
923 return BP_RESULT_BADINPUT;
924
925 if (!DATA_TABLES(dce_info))
926 return BP_RESULT_BADBIOSTABLE;
927
928 if (!DATA_TABLES(smu_info))
929 return BP_RESULT_BADBIOSTABLE;
930
931 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
932 DATA_TABLES(dce_info));
933 if (!disp_cntl_tbl)
934 return BP_RESULT_BADBIOSTABLE;
935
936 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
937 if (!smu_info)
938 return BP_RESULT_BADBIOSTABLE;
939
940 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage);
941 ss_info->type.STEP_AND_DELAY_INFO = false;
942 ss_info->spread_percentage_divider = 1000;
943 /* BIOS no longer uses target clock. Always enable for now */
944 ss_info->target_clock_range = 0xffffffff;
945
946 switch (id) {
947 case AS_SIGNAL_TYPE_DVI:
948 ss_info->spread_spectrum_percentage =
949 disp_cntl_tbl->dvi_ss_percentage;
950 ss_info->spread_spectrum_range =
951 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
952 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
953 ss_info->type.CENTER_MODE = true;
954
955 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
956 break;
957 case AS_SIGNAL_TYPE_HDMI:
958 ss_info->spread_spectrum_percentage =
959 disp_cntl_tbl->hdmi_ss_percentage;
960 ss_info->spread_spectrum_range =
961 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
962 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
963 ss_info->type.CENTER_MODE = true;
964
965 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
966 break;
967 /* TODO LVDS not support anymore? */
968 case AS_SIGNAL_TYPE_DISPLAY_PORT:
969 ss_info->spread_spectrum_percentage =
970 smu_info->gpuclk_ss_percentage;
971 ss_info->spread_spectrum_range =
972 smu_info->gpuclk_ss_rate_10hz * 10;
973 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
974 ss_info->type.CENTER_MODE = true;
975
976 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
977 break;
978 case AS_SIGNAL_TYPE_GPU_PLL:
979 /* atom_firmware: DAL only get data from dce_info table.
980 * if data within smu_info is needed for DAL, VBIOS should
981 * copy it into dce_info
982 */
983 result = BP_RESULT_UNSUPPORTED;
984 break;
985 default:
986 result = BP_RESULT_UNSUPPORTED;
987 }
988
989 return result;
990 }
991
get_ss_info_v4_5(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)992 static enum bp_result get_ss_info_v4_5(
993 struct bios_parser *bp,
994 uint32_t id,
995 uint32_t index,
996 struct spread_spectrum_info *ss_info)
997 {
998 (void)index;
999 enum bp_result result = BP_RESULT_OK;
1000 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
1001
1002 if (!ss_info)
1003 return BP_RESULT_BADINPUT;
1004
1005 if (!DATA_TABLES(dce_info))
1006 return BP_RESULT_BADBIOSTABLE;
1007
1008 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
1009 DATA_TABLES(dce_info));
1010 if (!disp_cntl_tbl)
1011 return BP_RESULT_BADBIOSTABLE;
1012
1013 ss_info->type.STEP_AND_DELAY_INFO = false;
1014 ss_info->spread_percentage_divider = 1000;
1015 /* BIOS no longer uses target clock. Always enable for now */
1016 ss_info->target_clock_range = 0xffffffff;
1017
1018 switch (id) {
1019 case AS_SIGNAL_TYPE_DVI:
1020 ss_info->spread_spectrum_percentage =
1021 disp_cntl_tbl->dvi_ss_percentage;
1022 ss_info->spread_spectrum_range =
1023 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
1024 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1025 ss_info->type.CENTER_MODE = true;
1026
1027 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1028 break;
1029 case AS_SIGNAL_TYPE_HDMI:
1030 ss_info->spread_spectrum_percentage =
1031 disp_cntl_tbl->hdmi_ss_percentage;
1032 ss_info->spread_spectrum_range =
1033 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
1034 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1035 ss_info->type.CENTER_MODE = true;
1036
1037 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1038 break;
1039 case AS_SIGNAL_TYPE_DISPLAY_PORT:
1040 if (bp->base.integrated_info) {
1041 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", bp->base.integrated_info->gpuclk_ss_percentage);
1042 ss_info->spread_spectrum_percentage =
1043 bp->base.integrated_info->gpuclk_ss_percentage;
1044 ss_info->type.CENTER_MODE =
1045 bp->base.integrated_info->gpuclk_ss_type;
1046 } else {
1047 ss_info->spread_spectrum_percentage =
1048 disp_cntl_tbl->dp_ss_percentage;
1049 ss_info->spread_spectrum_range =
1050 disp_cntl_tbl->dp_ss_rate_10hz * 10;
1051 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1052 ss_info->type.CENTER_MODE = true;
1053 }
1054 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1055 break;
1056 case AS_SIGNAL_TYPE_GPU_PLL:
1057 /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore.
1058 * SMU Display PLL supposed to be without spread.
1059 * Better place for it would be in atom_display_controller_info_v4_5 table.
1060 */
1061 result = BP_RESULT_UNSUPPORTED;
1062 break;
1063 default:
1064 result = BP_RESULT_UNSUPPORTED;
1065 break;
1066 }
1067
1068 return result;
1069 }
1070
1071 /**
1072 * bios_parser_get_spread_spectrum_info
1073 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
1074 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
1075 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
1076 * ver 3.1,
1077 * there is only one entry for each signal /ss id. However, there is
1078 * no planning of supporting multiple spread Sprectum entry for EverGreen
1079 * @dcb: pointer to the DC BIOS
1080 * @signal: ASSignalType to be converted to info index
1081 * @index: number of entries that match the converted info index
1082 * @ss_info: sprectrum information structure,
1083 * return: Bios parser result code
1084 */
bios_parser_get_spread_spectrum_info(struct dc_bios * dcb,enum as_signal_type signal,uint32_t index,struct spread_spectrum_info * ss_info)1085 static enum bp_result bios_parser_get_spread_spectrum_info(
1086 struct dc_bios *dcb,
1087 enum as_signal_type signal,
1088 uint32_t index,
1089 struct spread_spectrum_info *ss_info)
1090 {
1091 struct bios_parser *bp = BP_FROM_DCB(dcb);
1092 enum bp_result result = BP_RESULT_UNSUPPORTED;
1093 struct atom_common_table_header *header;
1094 struct atom_data_revision tbl_revision;
1095
1096 if (!ss_info) /* check for bad input */
1097 return BP_RESULT_BADINPUT;
1098
1099 if (!DATA_TABLES(dce_info))
1100 return BP_RESULT_UNSUPPORTED;
1101
1102 header = GET_IMAGE(struct atom_common_table_header,
1103 DATA_TABLES(dce_info));
1104 get_atom_data_table_revision(header, &tbl_revision);
1105
1106 switch (tbl_revision.major) {
1107 case 4:
1108 switch (tbl_revision.minor) {
1109 case 1:
1110 return get_ss_info_v4_1(bp, signal, index, ss_info);
1111 case 2:
1112 case 3:
1113 case 4:
1114 return get_ss_info_v4_2(bp, signal, index, ss_info);
1115 case 5:
1116 return get_ss_info_v4_5(bp, signal, index, ss_info);
1117
1118 default:
1119 ASSERT(0);
1120 break;
1121 }
1122 break;
1123 default:
1124 break;
1125 }
1126 /* there can not be more then one entry for SS Info table */
1127 return result;
1128 }
1129
get_soc_bb_info_v4_4(struct bios_parser * bp,struct bp_soc_bb_info * soc_bb_info)1130 static enum bp_result get_soc_bb_info_v4_4(
1131 struct bios_parser *bp,
1132 struct bp_soc_bb_info *soc_bb_info)
1133 {
1134 enum bp_result result = BP_RESULT_OK;
1135 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
1136
1137 if (!soc_bb_info)
1138 return BP_RESULT_BADINPUT;
1139
1140 if (!DATA_TABLES(dce_info))
1141 return BP_RESULT_BADBIOSTABLE;
1142
1143 if (!DATA_TABLES(smu_info))
1144 return BP_RESULT_BADBIOSTABLE;
1145
1146 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
1147 DATA_TABLES(dce_info));
1148 if (!disp_cntl_tbl)
1149 return BP_RESULT_BADBIOSTABLE;
1150
1151 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
1152 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
1153 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
1154
1155 return result;
1156 }
1157
get_soc_bb_info_v4_5(struct bios_parser * bp,struct bp_soc_bb_info * soc_bb_info)1158 static enum bp_result get_soc_bb_info_v4_5(
1159 struct bios_parser *bp,
1160 struct bp_soc_bb_info *soc_bb_info)
1161 {
1162 enum bp_result result = BP_RESULT_OK;
1163 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
1164
1165 if (!soc_bb_info)
1166 return BP_RESULT_BADINPUT;
1167
1168 if (!DATA_TABLES(dce_info))
1169 return BP_RESULT_BADBIOSTABLE;
1170
1171 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
1172 DATA_TABLES(dce_info));
1173 if (!disp_cntl_tbl)
1174 return BP_RESULT_BADBIOSTABLE;
1175
1176 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
1177 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
1178 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
1179
1180 return result;
1181 }
1182
bios_parser_get_soc_bb_info(struct dc_bios * dcb,struct bp_soc_bb_info * soc_bb_info)1183 static enum bp_result bios_parser_get_soc_bb_info(
1184 struct dc_bios *dcb,
1185 struct bp_soc_bb_info *soc_bb_info)
1186 {
1187 struct bios_parser *bp = BP_FROM_DCB(dcb);
1188 enum bp_result result = BP_RESULT_UNSUPPORTED;
1189 struct atom_common_table_header *header;
1190 struct atom_data_revision tbl_revision;
1191
1192 if (!soc_bb_info) /* check for bad input */
1193 return BP_RESULT_BADINPUT;
1194
1195 if (!DATA_TABLES(dce_info))
1196 return BP_RESULT_UNSUPPORTED;
1197
1198 header = GET_IMAGE(struct atom_common_table_header,
1199 DATA_TABLES(dce_info));
1200 get_atom_data_table_revision(header, &tbl_revision);
1201
1202 switch (tbl_revision.major) {
1203 case 4:
1204 switch (tbl_revision.minor) {
1205 case 1:
1206 case 2:
1207 case 3:
1208 break;
1209 case 4:
1210 result = get_soc_bb_info_v4_4(bp, soc_bb_info);
1211 break;
1212 case 5:
1213 result = get_soc_bb_info_v4_5(bp, soc_bb_info);
1214 break;
1215 default:
1216 break;
1217 }
1218 break;
1219 default:
1220 break;
1221 }
1222
1223 return result;
1224 }
1225
get_disp_caps_v4_1(struct bios_parser * bp,uint8_t * dce_caps)1226 static enum bp_result get_disp_caps_v4_1(
1227 struct bios_parser *bp,
1228 uint8_t *dce_caps)
1229 {
1230 enum bp_result result = BP_RESULT_OK;
1231 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
1232
1233 if (!dce_caps)
1234 return BP_RESULT_BADINPUT;
1235
1236 if (!DATA_TABLES(dce_info))
1237 return BP_RESULT_BADBIOSTABLE;
1238
1239 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
1240 DATA_TABLES(dce_info));
1241
1242 if (!disp_cntl_tbl)
1243 return BP_RESULT_BADBIOSTABLE;
1244
1245 *dce_caps = disp_cntl_tbl->display_caps;
1246
1247 return result;
1248 }
1249
get_disp_caps_v4_2(struct bios_parser * bp,uint8_t * dce_caps)1250 static enum bp_result get_disp_caps_v4_2(
1251 struct bios_parser *bp,
1252 uint8_t *dce_caps)
1253 {
1254 enum bp_result result = BP_RESULT_OK;
1255 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
1256
1257 if (!dce_caps)
1258 return BP_RESULT_BADINPUT;
1259
1260 if (!DATA_TABLES(dce_info))
1261 return BP_RESULT_BADBIOSTABLE;
1262
1263 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
1264 DATA_TABLES(dce_info));
1265
1266 if (!disp_cntl_tbl)
1267 return BP_RESULT_BADBIOSTABLE;
1268
1269 *dce_caps = disp_cntl_tbl->display_caps;
1270
1271 return result;
1272 }
1273
get_disp_caps_v4_3(struct bios_parser * bp,uint8_t * dce_caps)1274 static enum bp_result get_disp_caps_v4_3(
1275 struct bios_parser *bp,
1276 uint8_t *dce_caps)
1277 {
1278 enum bp_result result = BP_RESULT_OK;
1279 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL;
1280
1281 if (!dce_caps)
1282 return BP_RESULT_BADINPUT;
1283
1284 if (!DATA_TABLES(dce_info))
1285 return BP_RESULT_BADBIOSTABLE;
1286
1287 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3,
1288 DATA_TABLES(dce_info));
1289
1290 if (!disp_cntl_tbl)
1291 return BP_RESULT_BADBIOSTABLE;
1292
1293 *dce_caps = disp_cntl_tbl->display_caps;
1294
1295 return result;
1296 }
1297
get_disp_caps_v4_4(struct bios_parser * bp,uint8_t * dce_caps)1298 static enum bp_result get_disp_caps_v4_4(
1299 struct bios_parser *bp,
1300 uint8_t *dce_caps)
1301 {
1302 enum bp_result result = BP_RESULT_OK;
1303 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
1304
1305 if (!dce_caps)
1306 return BP_RESULT_BADINPUT;
1307
1308 if (!DATA_TABLES(dce_info))
1309 return BP_RESULT_BADBIOSTABLE;
1310
1311 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
1312 DATA_TABLES(dce_info));
1313
1314 if (!disp_cntl_tbl)
1315 return BP_RESULT_BADBIOSTABLE;
1316
1317 *dce_caps = disp_cntl_tbl->display_caps;
1318
1319 return result;
1320 }
1321
get_disp_caps_v4_5(struct bios_parser * bp,uint8_t * dce_caps)1322 static enum bp_result get_disp_caps_v4_5(
1323 struct bios_parser *bp,
1324 uint8_t *dce_caps)
1325 {
1326 enum bp_result result = BP_RESULT_OK;
1327 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
1328
1329 if (!dce_caps)
1330 return BP_RESULT_BADINPUT;
1331
1332 if (!DATA_TABLES(dce_info))
1333 return BP_RESULT_BADBIOSTABLE;
1334
1335 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
1336 DATA_TABLES(dce_info));
1337
1338 if (!disp_cntl_tbl)
1339 return BP_RESULT_BADBIOSTABLE;
1340
1341 *dce_caps = disp_cntl_tbl->display_caps;
1342
1343 return result;
1344 }
1345
bios_parser_get_lttpr_interop(struct dc_bios * dcb,uint8_t * dce_caps)1346 static enum bp_result bios_parser_get_lttpr_interop(
1347 struct dc_bios *dcb,
1348 uint8_t *dce_caps)
1349 {
1350 struct bios_parser *bp = BP_FROM_DCB(dcb);
1351 enum bp_result result = BP_RESULT_UNSUPPORTED;
1352 struct atom_common_table_header *header;
1353 struct atom_data_revision tbl_revision;
1354
1355 if (!DATA_TABLES(dce_info))
1356 return BP_RESULT_UNSUPPORTED;
1357
1358 header = GET_IMAGE(struct atom_common_table_header,
1359 DATA_TABLES(dce_info));
1360 get_atom_data_table_revision(header, &tbl_revision);
1361 switch (tbl_revision.major) {
1362 case 4:
1363 switch (tbl_revision.minor) {
1364 case 1:
1365 result = get_disp_caps_v4_1(bp, dce_caps);
1366 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1367 break;
1368 case 2:
1369 result = get_disp_caps_v4_2(bp, dce_caps);
1370 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1371 break;
1372 case 3:
1373 result = get_disp_caps_v4_3(bp, dce_caps);
1374 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1375 break;
1376 case 4:
1377 result = get_disp_caps_v4_4(bp, dce_caps);
1378 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1379 break;
1380 case 5:
1381 result = get_disp_caps_v4_5(bp, dce_caps);
1382 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1383 break;
1384
1385 default:
1386 break;
1387 }
1388 break;
1389 default:
1390 break;
1391 }
1392 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor);
1393 return result;
1394 }
1395
bios_parser_get_lttpr_caps(struct dc_bios * dcb,uint8_t * dce_caps)1396 static enum bp_result bios_parser_get_lttpr_caps(
1397 struct dc_bios *dcb,
1398 uint8_t *dce_caps)
1399 {
1400 struct bios_parser *bp = BP_FROM_DCB(dcb);
1401 enum bp_result result = BP_RESULT_UNSUPPORTED;
1402 struct atom_common_table_header *header;
1403 struct atom_data_revision tbl_revision;
1404
1405 if (!DATA_TABLES(dce_info))
1406 return BP_RESULT_UNSUPPORTED;
1407
1408 *dce_caps = 0;
1409 header = GET_IMAGE(struct atom_common_table_header,
1410 DATA_TABLES(dce_info));
1411 get_atom_data_table_revision(header, &tbl_revision);
1412 switch (tbl_revision.major) {
1413 case 4:
1414 switch (tbl_revision.minor) {
1415 case 1:
1416 result = get_disp_caps_v4_1(bp, dce_caps);
1417 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1418 break;
1419 case 2:
1420 result = get_disp_caps_v4_2(bp, dce_caps);
1421 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1422 break;
1423 case 3:
1424 result = get_disp_caps_v4_3(bp, dce_caps);
1425 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1426 break;
1427 case 4:
1428 result = get_disp_caps_v4_4(bp, dce_caps);
1429 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1430 break;
1431 case 5:
1432 result = get_disp_caps_v4_5(bp, dce_caps);
1433 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1434 break;
1435 default:
1436 break;
1437 }
1438 break;
1439 default:
1440 break;
1441 }
1442 DC_LOG_BIOS("DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor);
1443 if (dcb->ctx->dc->config.force_bios_enable_lttpr && *dce_caps == 0) {
1444 *dce_caps = 1;
1445 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: forced enabled");
1446 }
1447 return result;
1448 }
1449
get_embedded_panel_info_v2_1(struct bios_parser * bp,struct embedded_panel_info * info)1450 static enum bp_result get_embedded_panel_info_v2_1(
1451 struct bios_parser *bp,
1452 struct embedded_panel_info *info)
1453 {
1454 struct lcd_info_v2_1 *lvds;
1455
1456 if (!info)
1457 return BP_RESULT_BADINPUT;
1458
1459 if (!DATA_TABLES(lcd_info))
1460 return BP_RESULT_UNSUPPORTED;
1461
1462 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
1463
1464 if (!lvds)
1465 return BP_RESULT_BADBIOSTABLE;
1466
1467 /* TODO: previous vv1_3, should v2_1 */
1468 if (!((lvds->table_header.format_revision == 2)
1469 && (lvds->table_header.content_revision >= 1)))
1470 return BP_RESULT_UNSUPPORTED;
1471
1472 memset(info, 0, sizeof(struct embedded_panel_info));
1473
1474 /* We need to convert from 10KHz units into KHz units */
1475 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
1476 /* usHActive does not include borders, according to VBIOS team */
1477 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
1478 /* usHBlanking_Time includes borders, so we should really be
1479 * subtractingborders duing this translation, but LVDS generally
1480 * doesn't have borders, so we should be okay leaving this as is for
1481 * now. May need to revisit if we ever have LVDS with borders
1482 */
1483 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time);
1484 /* usVActive does not include borders, according to VBIOS team*/
1485 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active);
1486 /* usVBlanking_Time includes borders, so we should really be
1487 * subtracting borders duing this translation, but LVDS generally
1488 * doesn't have borders, so we should be okay leaving this as is for
1489 * now. May need to revisit if we ever have LVDS with borders
1490 */
1491 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time);
1492 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset);
1493 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width);
1494 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset);
1495 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth);
1496 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
1497 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
1498
1499 /* not provided by VBIOS */
1500 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
1501
1502 info->lcd_timing.misc_info.H_SYNC_POLARITY = !(lvds->lcd_timing.miscinfo &
1503 ATOM_HSYNC_POLARITY);
1504 info->lcd_timing.misc_info.V_SYNC_POLARITY = !(lvds->lcd_timing.miscinfo &
1505 ATOM_VSYNC_POLARITY);
1506
1507 /* not provided by VBIOS */
1508 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
1509
1510 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
1511 & ATOM_H_REPLICATIONBY2);
1512 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
1513 & ATOM_V_REPLICATIONBY2);
1514 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo
1515 & ATOM_COMPOSITESYNC);
1516 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
1517
1518 /* not provided by VBIOS*/
1519 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
1520 /* not provided by VBIOS*/
1521 info->ss_id = 0;
1522
1523 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
1524
1525 return BP_RESULT_OK;
1526 }
1527
bios_parser_get_embedded_panel_info(struct dc_bios * dcb,struct embedded_panel_info * info)1528 static enum bp_result bios_parser_get_embedded_panel_info(
1529 struct dc_bios *dcb,
1530 struct embedded_panel_info *info)
1531 {
1532 struct bios_parser
1533 *bp = BP_FROM_DCB(dcb);
1534 struct atom_common_table_header *header;
1535 struct atom_data_revision tbl_revision;
1536
1537 if (!DATA_TABLES(lcd_info))
1538 return BP_RESULT_FAILURE;
1539
1540 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info));
1541
1542 if (!header)
1543 return BP_RESULT_BADBIOSTABLE;
1544
1545 get_atom_data_table_revision(header, &tbl_revision);
1546
1547 switch (tbl_revision.major) {
1548 case 2:
1549 switch (tbl_revision.minor) {
1550 case 1:
1551 return get_embedded_panel_info_v2_1(bp, info);
1552 default:
1553 break;
1554 }
1555 break;
1556 default:
1557 break;
1558 }
1559
1560 return BP_RESULT_FAILURE;
1561 }
1562
get_support_mask_for_device_id(struct device_id device_id)1563 static uint32_t get_support_mask_for_device_id(struct device_id device_id)
1564 {
1565 enum dal_device_type device_type = device_id.device_type;
1566 uint32_t enum_id = device_id.enum_id;
1567
1568 switch (device_type) {
1569 case DEVICE_TYPE_LCD:
1570 switch (enum_id) {
1571 case 1:
1572 return ATOM_DISPLAY_LCD1_SUPPORT;
1573 default:
1574 break;
1575 }
1576 break;
1577 case DEVICE_TYPE_DFP:
1578 switch (enum_id) {
1579 case 1:
1580 return ATOM_DISPLAY_DFP1_SUPPORT;
1581 case 2:
1582 return ATOM_DISPLAY_DFP2_SUPPORT;
1583 case 3:
1584 return ATOM_DISPLAY_DFP3_SUPPORT;
1585 case 4:
1586 return ATOM_DISPLAY_DFP4_SUPPORT;
1587 case 5:
1588 return ATOM_DISPLAY_DFP5_SUPPORT;
1589 case 6:
1590 return ATOM_DISPLAY_DFP6_SUPPORT;
1591 default:
1592 break;
1593 }
1594 break;
1595 default:
1596 break;
1597 }
1598
1599 /* Unidentified device ID, return empty support mask. */
1600 return 0;
1601 }
1602
bios_parser_is_device_id_supported(struct dc_bios * dcb,struct device_id id)1603 static bool bios_parser_is_device_id_supported(
1604 struct dc_bios *dcb,
1605 struct device_id id)
1606 {
1607 struct bios_parser *bp = BP_FROM_DCB(dcb);
1608
1609 uint32_t mask = get_support_mask_for_device_id(id);
1610
1611 switch (bp->object_info_tbl.revision.minor) {
1612 case 4:
1613 default:
1614 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0;
1615 break;
1616 case 5:
1617 return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0;
1618 break;
1619 }
1620 }
1621
bios_parser_get_ss_entry_number(struct dc_bios * dcb,enum as_signal_type signal)1622 static uint32_t bios_parser_get_ss_entry_number(
1623 struct dc_bios *dcb,
1624 enum as_signal_type signal)
1625 {
1626 (void)dcb;
1627 (void)signal;
1628 /* TODO: DAL2 atomfirmware implementation does not need this.
1629 * why DAL3 need this?
1630 */
1631 return 1;
1632 }
1633
bios_parser_transmitter_control(struct dc_bios * dcb,struct bp_transmitter_control * cntl)1634 static enum bp_result bios_parser_transmitter_control(
1635 struct dc_bios *dcb,
1636 struct bp_transmitter_control *cntl)
1637 {
1638 struct bios_parser *bp = BP_FROM_DCB(dcb);
1639
1640 if (!bp->cmd_tbl.transmitter_control)
1641 return BP_RESULT_FAILURE;
1642
1643 return bp->cmd_tbl.transmitter_control(bp, cntl);
1644 }
1645
bios_parser_encoder_control(struct dc_bios * dcb,struct bp_encoder_control * cntl)1646 static enum bp_result bios_parser_encoder_control(
1647 struct dc_bios *dcb,
1648 struct bp_encoder_control *cntl)
1649 {
1650 struct bios_parser *bp = BP_FROM_DCB(dcb);
1651
1652 if (!bp->cmd_tbl.dig_encoder_control)
1653 return BP_RESULT_FAILURE;
1654
1655 return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1656 }
1657
bios_parser_set_pixel_clock(struct dc_bios * dcb,struct bp_pixel_clock_parameters * bp_params)1658 static enum bp_result bios_parser_set_pixel_clock(
1659 struct dc_bios *dcb,
1660 struct bp_pixel_clock_parameters *bp_params)
1661 {
1662 struct bios_parser *bp = BP_FROM_DCB(dcb);
1663
1664 if (!bp->cmd_tbl.set_pixel_clock)
1665 return BP_RESULT_FAILURE;
1666
1667 return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1668 }
1669
bios_parser_set_dce_clock(struct dc_bios * dcb,struct bp_set_dce_clock_parameters * bp_params)1670 static enum bp_result bios_parser_set_dce_clock(
1671 struct dc_bios *dcb,
1672 struct bp_set_dce_clock_parameters *bp_params)
1673 {
1674 struct bios_parser *bp = BP_FROM_DCB(dcb);
1675
1676 if (!bp->cmd_tbl.set_dce_clock)
1677 return BP_RESULT_FAILURE;
1678
1679 return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1680 }
1681
bios_parser_program_crtc_timing(struct dc_bios * dcb,struct bp_hw_crtc_timing_parameters * bp_params)1682 static enum bp_result bios_parser_program_crtc_timing(
1683 struct dc_bios *dcb,
1684 struct bp_hw_crtc_timing_parameters *bp_params)
1685 {
1686 struct bios_parser *bp = BP_FROM_DCB(dcb);
1687
1688 if (!bp->cmd_tbl.set_crtc_timing)
1689 return BP_RESULT_FAILURE;
1690
1691 return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1692 }
1693
bios_parser_enable_crtc(struct dc_bios * dcb,enum controller_id id,bool enable)1694 static enum bp_result bios_parser_enable_crtc(
1695 struct dc_bios *dcb,
1696 enum controller_id id,
1697 bool enable)
1698 {
1699 struct bios_parser *bp = BP_FROM_DCB(dcb);
1700
1701 if (!bp->cmd_tbl.enable_crtc)
1702 return BP_RESULT_FAILURE;
1703
1704 return bp->cmd_tbl.enable_crtc(bp, id, enable);
1705 }
1706
bios_parser_enable_disp_power_gating(struct dc_bios * dcb,enum controller_id controller_id,enum bp_pipe_control_action action)1707 static enum bp_result bios_parser_enable_disp_power_gating(
1708 struct dc_bios *dcb,
1709 enum controller_id controller_id,
1710 enum bp_pipe_control_action action)
1711 {
1712 struct bios_parser *bp = BP_FROM_DCB(dcb);
1713
1714 if (!bp->cmd_tbl.enable_disp_power_gating)
1715 return BP_RESULT_FAILURE;
1716
1717 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1718 action);
1719 }
1720
bios_parser_enable_lvtma_control(struct dc_bios * dcb,uint8_t uc_pwr_on,uint8_t pwrseq_instance,uint8_t bypass_panel_control_wait)1721 static enum bp_result bios_parser_enable_lvtma_control(
1722 struct dc_bios *dcb,
1723 uint8_t uc_pwr_on,
1724 uint8_t pwrseq_instance,
1725 uint8_t bypass_panel_control_wait)
1726 {
1727 struct bios_parser *bp = BP_FROM_DCB(dcb);
1728
1729 if (!bp->cmd_tbl.enable_lvtma_control)
1730 return BP_RESULT_FAILURE;
1731
1732 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, pwrseq_instance, bypass_panel_control_wait);
1733 }
1734
bios_parser_is_accelerated_mode(struct dc_bios * dcb)1735 static bool bios_parser_is_accelerated_mode(
1736 struct dc_bios *dcb)
1737 {
1738 return bios_is_accelerated_mode(dcb);
1739 }
1740
1741 /**
1742 * bios_parser_set_scratch_critical_state - update critical state bit
1743 * in VBIOS scratch register
1744 *
1745 * @dcb: pointer to the DC BIO
1746 * @state: set or reset state
1747 */
bios_parser_set_scratch_critical_state(struct dc_bios * dcb,bool state)1748 static void bios_parser_set_scratch_critical_state(
1749 struct dc_bios *dcb,
1750 bool state)
1751 {
1752 bios_set_scratch_critical_state(dcb, state);
1753 }
1754
bios_parser_get_firmware_info(struct dc_bios * dcb,struct dc_firmware_info * info)1755 static enum bp_result bios_parser_get_firmware_info(
1756 struct dc_bios *dcb,
1757 struct dc_firmware_info *info)
1758 {
1759 struct bios_parser *bp = BP_FROM_DCB(dcb);
1760 static enum bp_result result = BP_RESULT_BADBIOSTABLE;
1761 struct atom_common_table_header *header;
1762
1763 struct atom_data_revision revision;
1764
1765 if (info && DATA_TABLES(firmwareinfo)) {
1766 header = GET_IMAGE(struct atom_common_table_header,
1767 DATA_TABLES(firmwareinfo));
1768 get_atom_data_table_revision(header, &revision);
1769 switch (revision.major) {
1770 case 3:
1771 switch (revision.minor) {
1772 case 1:
1773 result = get_firmware_info_v3_1(bp, info);
1774 break;
1775 case 2:
1776 case 3:
1777 result = get_firmware_info_v3_2(bp, info);
1778 break;
1779 case 4:
1780 result = get_firmware_info_v3_4(bp, info);
1781 break;
1782 case 5:
1783 result = get_firmware_info_v3_5(bp, info);
1784 break;
1785 default:
1786 break;
1787 }
1788 break;
1789 default:
1790 break;
1791 }
1792 }
1793
1794 return result;
1795 }
1796
get_firmware_info_v3_1(struct bios_parser * bp,struct dc_firmware_info * info)1797 static enum bp_result get_firmware_info_v3_1(
1798 struct bios_parser *bp,
1799 struct dc_firmware_info *info)
1800 {
1801 struct atom_firmware_info_v3_1 *firmware_info;
1802 struct atom_firmware_info_v3_2 *firmware_info32;
1803 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1804
1805 if (!info)
1806 return BP_RESULT_BADINPUT;
1807
1808 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1809 DATA_TABLES(firmwareinfo));
1810 firmware_info32 = GET_IMAGE(struct atom_firmware_info_v3_2,
1811 DATA_TABLES(firmwareinfo));
1812
1813 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1814 DATA_TABLES(dce_info));
1815
1816 if (!firmware_info || !firmware_info32 || !dce_info)
1817 return BP_RESULT_BADBIOSTABLE;
1818
1819 memset(info, 0, sizeof(*info));
1820
1821 /* Pixel clock pll information. */
1822 /* We need to convert from 10KHz units into KHz units */
1823 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1824 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1825
1826 /* 27MHz for Vega10: */
1827 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1828
1829 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1830 if (info->pll_info.crystal_frequency == 0)
1831 info->pll_info.crystal_frequency = 27000;
1832 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1833 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1834 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1835
1836 /* Get GPU PLL VCO Clock */
1837
1838 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1839 /* VBIOS gives in 10KHz */
1840 info->smu_gpu_pll_output_freq =
1841 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1842 }
1843
1844 /* These fields are marked as reserved in v3_1, but they appear to be populated
1845 * properly.
1846 */
1847 if (firmware_info32 && firmware_info32->board_i2c_feature_id == 0x2) {
1848 info->oem_i2c_present = true;
1849 info->oem_i2c_obj_id = firmware_info32->board_i2c_feature_gpio_id;
1850 } else {
1851 info->oem_i2c_present = false;
1852 }
1853
1854 return BP_RESULT_OK;
1855 }
1856
get_firmware_info_v3_2(struct bios_parser * bp,struct dc_firmware_info * info)1857 static enum bp_result get_firmware_info_v3_2(
1858 struct bios_parser *bp,
1859 struct dc_firmware_info *info)
1860 {
1861 struct atom_firmware_info_v3_2 *firmware_info;
1862 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1863 struct atom_common_table_header *header;
1864 struct atom_data_revision revision;
1865 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1866 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1867
1868 if (!info)
1869 return BP_RESULT_BADINPUT;
1870
1871 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1872 DATA_TABLES(firmwareinfo));
1873
1874 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1875 DATA_TABLES(dce_info));
1876
1877 if (!firmware_info || !dce_info)
1878 return BP_RESULT_BADBIOSTABLE;
1879
1880 memset(info, 0, sizeof(*info));
1881
1882 header = GET_IMAGE(struct atom_common_table_header,
1883 DATA_TABLES(smu_info));
1884 get_atom_data_table_revision(header, &revision);
1885
1886 if (revision.minor == 2) {
1887 /* Vega12 */
1888 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1889 DATA_TABLES(smu_info));
1890 if (!smu_info_v3_2)
1891 return BP_RESULT_BADBIOSTABLE;
1892
1893 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_2->gpuclk_ss_percentage);
1894
1895 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1896 } else if (revision.minor == 3) {
1897 /* Vega20 */
1898 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1899 DATA_TABLES(smu_info));
1900 if (!smu_info_v3_3)
1901 return BP_RESULT_BADBIOSTABLE;
1902
1903 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_3->gpuclk_ss_percentage);
1904
1905 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1906 }
1907
1908 // We need to convert from 10KHz units into KHz units.
1909 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1910
1911 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1912 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1913 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1914 if (info->pll_info.crystal_frequency == 0) {
1915 if (revision.minor == 2)
1916 info->pll_info.crystal_frequency = 27000;
1917 else if (revision.minor == 3)
1918 info->pll_info.crystal_frequency = 100000;
1919 }
1920 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1921 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1922 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1923
1924 /* Get GPU PLL VCO Clock */
1925 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1926 if (revision.minor == 2)
1927 info->smu_gpu_pll_output_freq =
1928 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1929 else if (revision.minor == 3)
1930 info->smu_gpu_pll_output_freq =
1931 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1932 }
1933
1934 if (firmware_info->board_i2c_feature_id == 0x2) {
1935 info->oem_i2c_present = true;
1936 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
1937 } else {
1938 info->oem_i2c_present = false;
1939 }
1940
1941 return BP_RESULT_OK;
1942 }
1943
get_firmware_info_v3_4(struct bios_parser * bp,struct dc_firmware_info * info)1944 static enum bp_result get_firmware_info_v3_4(
1945 struct bios_parser *bp,
1946 struct dc_firmware_info *info)
1947 {
1948 struct atom_firmware_info_v3_4 *firmware_info;
1949 struct atom_common_table_header *header;
1950 struct atom_data_revision revision;
1951 struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL;
1952 struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL;
1953
1954 struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL;
1955 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL;
1956 struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL;
1957
1958 if (!info)
1959 return BP_RESULT_BADINPUT;
1960
1961 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4,
1962 DATA_TABLES(firmwareinfo));
1963
1964 if (!firmware_info)
1965 return BP_RESULT_BADBIOSTABLE;
1966
1967 memset(info, 0, sizeof(*info));
1968
1969 header = GET_IMAGE(struct atom_common_table_header,
1970 DATA_TABLES(dce_info));
1971
1972 get_atom_data_table_revision(header, &revision);
1973
1974 switch (revision.major) {
1975 case 4:
1976 switch (revision.minor) {
1977 case 5:
1978 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5,
1979 DATA_TABLES(dce_info));
1980
1981 if (!dce_info_v4_5)
1982 return BP_RESULT_BADBIOSTABLE;
1983
1984 /* 100MHz expected */
1985 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;
1986 info->dp_phy_ref_clk = dce_info_v4_5->dpphy_refclk_10khz * 10;
1987 /* 50MHz expected */
1988 info->i2c_engine_ref_clk = dce_info_v4_5->i2c_engine_refclk_10khz * 10;
1989
1990 /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */
1991 break;
1992
1993 case 4:
1994 dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
1995 DATA_TABLES(dce_info));
1996
1997 if (!dce_info_v4_4)
1998 return BP_RESULT_BADBIOSTABLE;
1999
2000 /* 100MHz expected */
2001 info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10;
2002 info->dp_phy_ref_clk = dce_info_v4_4->dpphy_refclk_10khz * 10;
2003 /* 50MHz expected */
2004 info->i2c_engine_ref_clk = dce_info_v4_4->i2c_engine_refclk_10khz * 10;
2005
2006 /* Get SMU Display PLL VCO Frequency in KHz*/
2007 info->smu_gpu_pll_output_freq = dce_info_v4_4->dispclk_pll_vco_freq * 10;
2008 break;
2009
2010 default:
2011 /* should not come here, keep as backup, as was before */
2012 dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1,
2013 DATA_TABLES(dce_info));
2014
2015 if (!dce_info_v4_1)
2016 return BP_RESULT_BADBIOSTABLE;
2017
2018 info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10;
2019 info->dp_phy_ref_clk = dce_info_v4_1->dpphy_refclk_10khz * 10;
2020 info->i2c_engine_ref_clk = dce_info_v4_1->i2c_engine_refclk_10khz * 10;
2021 break;
2022 }
2023 break;
2024
2025 default:
2026 ASSERT(0);
2027 break;
2028 }
2029
2030 header = GET_IMAGE(struct atom_common_table_header,
2031 DATA_TABLES(smu_info));
2032 get_atom_data_table_revision(header, &revision);
2033
2034 switch (revision.major) {
2035 case 3:
2036 switch (revision.minor) {
2037 case 5:
2038 smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5,
2039 DATA_TABLES(smu_info));
2040
2041 if (!smu_info_v3_5)
2042 return BP_RESULT_BADBIOSTABLE;
2043 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_5->gpuclk_ss_percentage);
2044 info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10;
2045 break;
2046
2047 default:
2048 break;
2049 }
2050 break;
2051
2052 case 4:
2053 switch (revision.minor) {
2054 case 0:
2055 smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0,
2056 DATA_TABLES(smu_info));
2057
2058 if (!smu_info_v4_0)
2059 return BP_RESULT_BADBIOSTABLE;
2060
2061 /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */
2062 break;
2063
2064 default:
2065 break;
2066 }
2067 break;
2068
2069 default:
2070 break;
2071 }
2072
2073 // We need to convert from 10KHz units into KHz units.
2074 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
2075
2076 if (firmware_info->board_i2c_feature_id == 0x2) {
2077 info->oem_i2c_present = true;
2078 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
2079 } else {
2080 info->oem_i2c_present = false;
2081 }
2082
2083 return BP_RESULT_OK;
2084 }
2085
get_firmware_info_v3_5(struct bios_parser * bp,struct dc_firmware_info * info)2086 static enum bp_result get_firmware_info_v3_5(
2087 struct bios_parser *bp,
2088 struct dc_firmware_info *info)
2089 {
2090 struct atom_firmware_info_v3_5 *firmware_info;
2091 struct atom_common_table_header *header;
2092 struct atom_data_revision revision;
2093 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL;
2094
2095 if (!info)
2096 return BP_RESULT_BADINPUT;
2097
2098 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_5,
2099 DATA_TABLES(firmwareinfo));
2100
2101 if (!firmware_info)
2102 return BP_RESULT_BADBIOSTABLE;
2103
2104 memset(info, 0, sizeof(*info));
2105
2106 if (firmware_info->board_i2c_feature_id == 0x2) {
2107 info->oem_i2c_present = true;
2108 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
2109 } else {
2110 info->oem_i2c_present = false;
2111 }
2112
2113 header = GET_IMAGE(struct atom_common_table_header,
2114 DATA_TABLES(dce_info));
2115
2116 get_atom_data_table_revision(header, &revision);
2117
2118 switch (revision.major) {
2119 case 4:
2120 switch (revision.minor) {
2121 case 5:
2122 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5,
2123 DATA_TABLES(dce_info));
2124
2125 if (!dce_info_v4_5)
2126 return BP_RESULT_BADBIOSTABLE;
2127
2128 /* 100MHz expected */
2129 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;
2130 break;
2131 default:
2132 break;
2133 }
2134 break;
2135 default:
2136 break;
2137 }
2138
2139
2140 return BP_RESULT_OK;
2141 }
2142
bios_parser_get_encoder_cap_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_encoder_cap_info * info)2143 static enum bp_result bios_parser_get_encoder_cap_info(
2144 struct dc_bios *dcb,
2145 struct graphics_object_id object_id,
2146 struct bp_encoder_cap_info *info)
2147 {
2148 struct bios_parser *bp = BP_FROM_DCB(dcb);
2149 struct atom_display_object_path_v2 *object;
2150 struct atom_encoder_caps_record *record = NULL;
2151
2152 if (!info)
2153 return BP_RESULT_BADINPUT;
2154
2155 #if defined(CONFIG_DRM_AMD_DC_FP)
2156 /* encoder cap record not available in v1_5 */
2157 if (bp->object_info_tbl.revision.minor == 5)
2158 return BP_RESULT_NORECORD;
2159 #endif
2160
2161 object = get_bios_object(bp, object_id);
2162
2163 if (!object)
2164 return BP_RESULT_BADINPUT;
2165
2166 record = get_encoder_cap_record(bp, object);
2167 if (!record)
2168 return BP_RESULT_NORECORD;
2169 DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x", record->encodercaps, object_id.id);
2170
2171 info->DP_HBR2_CAP = (record->encodercaps &
2172 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
2173 info->DP_HBR2_EN = (record->encodercaps &
2174 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
2175 info->DP_HBR3_EN = (record->encodercaps &
2176 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
2177 info->HDMI_6GB_EN = (record->encodercaps &
2178 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
2179 info->IS_DP2_CAPABLE = (record->encodercaps &
2180 ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0;
2181 info->DP_UHBR10_EN = (record->encodercaps &
2182 ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0;
2183 info->DP_UHBR13_5_EN = (record->encodercaps &
2184 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0;
2185 info->DP_UHBR20_EN = (record->encodercaps &
2186 ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0;
2187 info->DP_IS_USB_C = (record->encodercaps &
2188 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
2189 DC_LOG_BIOS("\t info->DP_IS_USB_C %d", info->DP_IS_USB_C);
2190
2191 return BP_RESULT_OK;
2192 }
2193
2194
get_encoder_cap_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)2195 static struct atom_encoder_caps_record *get_encoder_cap_record(
2196 struct bios_parser *bp,
2197 struct atom_display_object_path_v2 *object)
2198 {
2199 struct atom_common_record_header *header;
2200 uint32_t offset;
2201 int i;
2202
2203 if (!object) {
2204 BREAK_TO_DEBUGGER(); /* Invalid object */
2205 return NULL;
2206 }
2207
2208 offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
2209
2210 for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
2211 header = GET_IMAGE(struct atom_common_record_header, offset);
2212
2213 if (!header)
2214 return NULL;
2215
2216 offset += header->record_size;
2217
2218 if (header->record_type == LAST_RECORD_TYPE ||
2219 !header->record_size)
2220 break;
2221
2222 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
2223 continue;
2224
2225 if (sizeof(struct atom_encoder_caps_record) <=
2226 header->record_size)
2227 return (struct atom_encoder_caps_record *)header;
2228 }
2229
2230 return NULL;
2231 }
2232
get_disp_connector_caps_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)2233 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record(
2234 struct bios_parser *bp,
2235 struct atom_display_object_path_v2 *object)
2236 {
2237 struct atom_common_record_header *header;
2238 uint32_t offset;
2239 int i;
2240
2241 if (!object) {
2242 BREAK_TO_DEBUGGER(); /* Invalid object */
2243 return NULL;
2244 }
2245
2246 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2247
2248 for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
2249 header = GET_IMAGE(struct atom_common_record_header, offset);
2250
2251 if (!header)
2252 return NULL;
2253
2254 offset += header->record_size;
2255
2256 if (header->record_type == LAST_RECORD_TYPE ||
2257 !header->record_size)
2258 break;
2259
2260 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE)
2261 continue;
2262
2263 if (sizeof(struct atom_disp_connector_caps_record) <=
2264 header->record_size)
2265 return (struct atom_disp_connector_caps_record *)header;
2266 }
2267
2268 return NULL;
2269 }
2270
get_connector_caps_record(struct bios_parser * bp,struct atom_display_object_path_v3 * object)2271 static struct atom_connector_caps_record *get_connector_caps_record(struct bios_parser *bp,
2272 struct atom_display_object_path_v3 *object)
2273 {
2274 struct atom_common_record_header *header;
2275 uint32_t offset;
2276 int i;
2277
2278 if (!object) {
2279 BREAK_TO_DEBUGGER(); /* Invalid object */
2280 return NULL;
2281 }
2282
2283 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2284
2285 for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
2286 header = GET_IMAGE(struct atom_common_record_header, offset);
2287
2288 if (!header)
2289 return NULL;
2290
2291 offset += header->record_size;
2292
2293 if (header->record_type == ATOM_RECORD_END_TYPE ||
2294 !header->record_size)
2295 break;
2296
2297 if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE)
2298 continue;
2299
2300 if (sizeof(struct atom_connector_caps_record) <= header->record_size)
2301 return (struct atom_connector_caps_record *)header;
2302 }
2303
2304 return NULL;
2305 }
2306
bios_parser_get_disp_connector_caps_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_disp_connector_caps_info * info)2307 static enum bp_result bios_parser_get_disp_connector_caps_info(
2308 struct dc_bios *dcb,
2309 struct graphics_object_id object_id,
2310 struct bp_disp_connector_caps_info *info)
2311 {
2312 struct bios_parser *bp = BP_FROM_DCB(dcb);
2313 struct atom_display_object_path_v2 *object;
2314 struct atom_display_object_path_v3 *object_path_v3;
2315 struct atom_connector_caps_record *record_path_v3;
2316 struct atom_disp_connector_caps_record *record = NULL;
2317
2318 if (!info)
2319 return BP_RESULT_BADINPUT;
2320
2321 switch (bp->object_info_tbl.revision.minor) {
2322 case 4:
2323 default:
2324 object = get_bios_object(bp, object_id);
2325
2326 if (!object)
2327 return BP_RESULT_BADINPUT;
2328
2329 record = get_disp_connector_caps_record(bp, object);
2330 if (!record)
2331 return BP_RESULT_NORECORD;
2332
2333 info->INTERNAL_DISPLAY =
2334 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0;
2335 info->INTERNAL_DISPLAY_BL =
2336 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0;
2337 break;
2338 case 5:
2339 object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
2340
2341 if (!object_path_v3)
2342 return BP_RESULT_BADINPUT;
2343
2344 record_path_v3 = get_connector_caps_record(bp, object_path_v3);
2345 if (!record_path_v3)
2346 return BP_RESULT_NORECORD;
2347
2348 info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY)
2349 ? 1 : 0;
2350 info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL)
2351 ? 1 : 0;
2352 break;
2353 }
2354
2355 return BP_RESULT_OK;
2356 }
2357
get_connector_speed_cap_record(struct bios_parser * bp,struct atom_display_object_path_v3 * object)2358 static struct atom_connector_speed_record *get_connector_speed_cap_record(struct bios_parser *bp,
2359 struct atom_display_object_path_v3 *object)
2360 {
2361 struct atom_common_record_header *header;
2362 uint32_t offset;
2363 int i;
2364
2365 if (!object) {
2366 BREAK_TO_DEBUGGER(); /* Invalid object */
2367 return NULL;
2368 }
2369
2370 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2371
2372 for (i = 0; i < BIOS_MAX_NUM_RECORD; i++) {
2373 header = GET_IMAGE(struct atom_common_record_header, offset);
2374
2375 if (!header)
2376 return NULL;
2377
2378 offset += header->record_size;
2379
2380 if (header->record_type == ATOM_RECORD_END_TYPE ||
2381 !header->record_size)
2382 break;
2383
2384 if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO)
2385 continue;
2386
2387 if (sizeof(struct atom_connector_speed_record) <= header->record_size)
2388 return (struct atom_connector_speed_record *)header;
2389 }
2390
2391 return NULL;
2392 }
2393
bios_parser_get_connector_speed_cap_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_connector_speed_cap_info * info)2394 static enum bp_result bios_parser_get_connector_speed_cap_info(
2395 struct dc_bios *dcb,
2396 struct graphics_object_id object_id,
2397 struct bp_connector_speed_cap_info *info)
2398 {
2399 struct bios_parser *bp = BP_FROM_DCB(dcb);
2400 struct atom_display_object_path_v3 *object_path_v3;
2401 //struct atom_connector_speed_record *record = NULL;
2402 struct atom_connector_speed_record *record;
2403
2404 if (!info)
2405 return BP_RESULT_BADINPUT;
2406
2407 object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
2408
2409 if (!object_path_v3)
2410 return BP_RESULT_BADINPUT;
2411
2412 record = get_connector_speed_cap_record(bp, object_path_v3);
2413 if (!record)
2414 return BP_RESULT_NORECORD;
2415
2416 info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0;
2417 info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0;
2418 info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0;
2419 info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0;
2420 info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0;
2421 info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0;
2422 return BP_RESULT_OK;
2423 }
2424
get_vram_info_v23(struct bios_parser * bp,struct dc_vram_info * info)2425 static enum bp_result get_vram_info_v23(
2426 struct bios_parser *bp,
2427 struct dc_vram_info *info)
2428 {
2429 struct atom_vram_info_header_v2_3 *info_v23;
2430 static enum bp_result result = BP_RESULT_OK;
2431
2432 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3,
2433 DATA_TABLES(vram_info));
2434
2435 if (info_v23 == NULL)
2436 return BP_RESULT_BADBIOSTABLE;
2437
2438 info->num_chans = info_v23->vram_module[0].channel_num;
2439 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8;
2440
2441 return result;
2442 }
2443
get_vram_info_v24(struct bios_parser * bp,struct dc_vram_info * info)2444 static enum bp_result get_vram_info_v24(
2445 struct bios_parser *bp,
2446 struct dc_vram_info *info)
2447 {
2448 struct atom_vram_info_header_v2_4 *info_v24;
2449 static enum bp_result result = BP_RESULT_OK;
2450
2451 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4,
2452 DATA_TABLES(vram_info));
2453
2454 if (info_v24 == NULL)
2455 return BP_RESULT_BADBIOSTABLE;
2456
2457 info->num_chans = info_v24->vram_module[0].channel_num;
2458 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8;
2459
2460 return result;
2461 }
2462
get_vram_info_v25(struct bios_parser * bp,struct dc_vram_info * info)2463 static enum bp_result get_vram_info_v25(
2464 struct bios_parser *bp,
2465 struct dc_vram_info *info)
2466 {
2467 struct atom_vram_info_header_v2_5 *info_v25;
2468 static enum bp_result result = BP_RESULT_OK;
2469
2470 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5,
2471 DATA_TABLES(vram_info));
2472
2473 if (info_v25 == NULL)
2474 return BP_RESULT_BADBIOSTABLE;
2475
2476 info->num_chans = info_v25->vram_module[0].channel_num;
2477 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8;
2478
2479 return result;
2480 }
2481
get_vram_info_v30(struct bios_parser * bp,struct dc_vram_info * info)2482 static enum bp_result get_vram_info_v30(
2483 struct bios_parser *bp,
2484 struct dc_vram_info *info)
2485 {
2486 struct atom_vram_info_header_v3_0 *info_v30;
2487 enum bp_result result = BP_RESULT_OK;
2488
2489 info_v30 = GET_IMAGE(struct atom_vram_info_header_v3_0,
2490 DATA_TABLES(vram_info));
2491
2492 if (info_v30 == NULL)
2493 return BP_RESULT_BADBIOSTABLE;
2494
2495 info->num_chans = info_v30->channel_num;
2496 info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8;
2497
2498 return result;
2499 }
2500
get_vram_info_from_umc_info_v40(struct bios_parser * bp,struct dc_vram_info * info)2501 static enum bp_result get_vram_info_from_umc_info_v40(
2502 struct bios_parser *bp,
2503 struct dc_vram_info *info)
2504 {
2505 struct atom_umc_info_v4_0 *info_v40;
2506 enum bp_result result = BP_RESULT_OK;
2507
2508 info_v40 = GET_IMAGE(struct atom_umc_info_v4_0,
2509 DATA_TABLES(umc_info));
2510
2511 if (info_v40 == NULL)
2512 return BP_RESULT_BADBIOSTABLE;
2513
2514 info->num_chans = info_v40->channel_num;
2515 info->dram_channel_width_bytes = (1 << info_v40->channel_width) / 8;
2516
2517 return result;
2518 }
2519
2520 /*
2521 * get_integrated_info_v11
2522 *
2523 * @brief
2524 * Get V8 integrated BIOS information
2525 *
2526 * @param
2527 * bios_parser *bp - [in]BIOS parser handler to get master data table
2528 * integrated_info *info - [out] store and output integrated info
2529 *
2530 * @return
2531 * static enum bp_result - BP_RESULT_OK if information is available,
2532 * BP_RESULT_BADBIOSTABLE otherwise.
2533 */
get_integrated_info_v11(struct bios_parser * bp,struct integrated_info * info)2534 static enum bp_result get_integrated_info_v11(
2535 struct bios_parser *bp,
2536 struct integrated_info *info)
2537 {
2538 struct atom_integrated_system_info_v1_11 *info_v11;
2539 uint32_t i;
2540
2541 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
2542 DATA_TABLES(integratedsysteminfo));
2543
2544 if (info_v11 == NULL)
2545 return BP_RESULT_BADBIOSTABLE;
2546
2547 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v11->gpuclk_ss_percentage);
2548
2549 info->gpu_cap_info =
2550 le32_to_cpu(info_v11->gpucapinfo);
2551 /*
2552 * system_config: Bit[0] = 0 : PCIE power gating disabled
2553 * = 1 : PCIE power gating enabled
2554 * Bit[1] = 0 : DDR-PLL shut down disabled
2555 * = 1 : DDR-PLL shut down enabled
2556 * Bit[2] = 0 : DDR-PLL power down disabled
2557 * = 1 : DDR-PLL power down enabled
2558 */
2559 info->system_config = le32_to_cpu(info_v11->system_config);
2560 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
2561 info->memory_type = info_v11->memorytype;
2562 info->ma_channel_number = info_v11->umachannelnumber;
2563 info->lvds_ss_percentage =
2564 le16_to_cpu(info_v11->lvds_ss_percentage);
2565 info->dp_ss_control =
2566 le16_to_cpu(info_v11->reserved1);
2567 info->lvds_sspread_rate_in_10hz =
2568 le16_to_cpu(info_v11->lvds_ss_rate_10hz);
2569 info->hdmi_ss_percentage =
2570 le16_to_cpu(info_v11->hdmi_ss_percentage);
2571 info->hdmi_sspread_rate_in_10hz =
2572 le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
2573 info->dvi_ss_percentage =
2574 le16_to_cpu(info_v11->dvi_ss_percentage);
2575 info->dvi_sspread_rate_in_10_hz =
2576 le16_to_cpu(info_v11->dvi_ss_rate_10hz);
2577 info->lvds_misc = info_v11->lvds_misc;
2578 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2579 info->ext_disp_conn_info.gu_id[i] =
2580 info_v11->extdispconninfo.guid[i];
2581 }
2582
2583 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2584 info->ext_disp_conn_info.path[i].device_connector_id =
2585 object_id_from_bios_object_id(
2586 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
2587
2588 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2589 object_id_from_bios_object_id(
2590 le16_to_cpu(
2591 info_v11->extdispconninfo.path[i].ext_encoder_objid));
2592
2593 info->ext_disp_conn_info.path[i].device_tag =
2594 le16_to_cpu(
2595 info_v11->extdispconninfo.path[i].device_tag);
2596 info->ext_disp_conn_info.path[i].device_acpi_enum =
2597 le16_to_cpu(
2598 info_v11->extdispconninfo.path[i].device_acpi_enum);
2599 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2600 info_v11->extdispconninfo.path[i].auxddclut_index;
2601 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2602 info_v11->extdispconninfo.path[i].hpdlut_index;
2603 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2604 info_v11->extdispconninfo.path[i].channelmapping;
2605 info->ext_disp_conn_info.path[i].caps =
2606 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
2607 }
2608 info->ext_disp_conn_info.checksum =
2609 info_v11->extdispconninfo.checksum;
2610
2611 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
2612 info->dp0_ext_hdmi_reg_num = min_t(u8, info_v11->dp0_retimer_set.HdmiRegNum,
2613 ARRAY_SIZE(info->dp0_ext_hdmi_reg_settings));
2614 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
2615 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
2616 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2617 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
2618 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2619 }
2620 info->dp0_ext_hdmi_6g_reg_num = min_t(u8, info_v11->dp0_retimer_set.Hdmi6GRegNum,
2621 ARRAY_SIZE(info->dp0_ext_hdmi_6g_reg_settings));
2622 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
2623 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2624 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2625 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2626 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2627 }
2628
2629 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
2630 info->dp1_ext_hdmi_reg_num = min_t(u8, info_v11->dp1_retimer_set.HdmiRegNum,
2631 ARRAY_SIZE(info->dp1_ext_hdmi_reg_settings));
2632 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
2633 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
2634 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2635 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
2636 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2637 }
2638 info->dp1_ext_hdmi_6g_reg_num = min_t(u8, info_v11->dp1_retimer_set.Hdmi6GRegNum,
2639 ARRAY_SIZE(info->dp1_ext_hdmi_6g_reg_settings));
2640 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
2641 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2642 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2643 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2644 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2645 }
2646
2647 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
2648 info->dp2_ext_hdmi_reg_num = min_t(u8, info_v11->dp2_retimer_set.HdmiRegNum,
2649 ARRAY_SIZE(info->dp2_ext_hdmi_reg_settings));
2650 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
2651 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
2652 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2653 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
2654 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2655 }
2656 info->dp2_ext_hdmi_6g_reg_num = min_t(u8, info_v11->dp2_retimer_set.Hdmi6GRegNum,
2657 ARRAY_SIZE(info->dp2_ext_hdmi_6g_reg_settings));
2658 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
2659 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2660 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2661 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2662 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2663 }
2664
2665 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
2666 info->dp3_ext_hdmi_reg_num = min_t(u8, info_v11->dp3_retimer_set.HdmiRegNum,
2667 ARRAY_SIZE(info->dp3_ext_hdmi_reg_settings));
2668 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
2669 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
2670 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2671 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
2672 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2673 }
2674 info->dp3_ext_hdmi_6g_reg_num = min_t(u8, info_v11->dp3_retimer_set.Hdmi6GRegNum,
2675 ARRAY_SIZE(info->dp3_ext_hdmi_6g_reg_settings));
2676 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
2677 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2678 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2679 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2680 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2681 }
2682
2683
2684 /** TODO - review **/
2685 #if 0
2686 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
2687 * 10;
2688 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
2689 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
2690
2691 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
2692 /* Convert [10KHz] into [KHz] */
2693 info->disp_clk_voltage[i].max_supported_clk =
2694 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
2695 ulMaximumSupportedCLK) * 10;
2696 info->disp_clk_voltage[i].voltage_index =
2697 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
2698 }
2699
2700 info->boot_up_req_display_vector =
2701 le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
2702 info->boot_up_nb_voltage =
2703 le16_to_cpu(info_v11->usBootUpNBVoltage);
2704 info->ext_disp_conn_info_offset =
2705 le16_to_cpu(info_v11->usExtDispConnInfoOffset);
2706 info->gmc_restore_reset_time =
2707 le32_to_cpu(info_v11->ulGMCRestoreResetTime);
2708 info->minimum_n_clk =
2709 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
2710 for (i = 1; i < 4; ++i)
2711 info->minimum_n_clk =
2712 info->minimum_n_clk <
2713 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
2714 info->minimum_n_clk : le32_to_cpu(
2715 info_v11->ulNbpStateNClkFreq[i]);
2716
2717 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
2718 info->ddr_dll_power_up_time =
2719 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
2720 info->ddr_pll_power_up_time =
2721 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
2722 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
2723 info->max_lvds_pclk_freq_in_single_link =
2724 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
2725 info->max_lvds_pclk_freq_in_single_link =
2726 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
2727 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
2728 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
2729 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
2730 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
2731 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
2732 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
2733 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
2734 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
2735 info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
2736 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
2737 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
2738 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
2739 info->lvds_off_to_on_delay_in_4ms =
2740 info_v11->ucLVDSOffToOnDelay_in4Ms;
2741 info->lvds_bit_depth_control_val =
2742 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
2743
2744 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
2745 /* Convert [10KHz] into [KHz] */
2746 info->avail_s_clk[i].supported_s_clk =
2747 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
2748 * 10;
2749 info->avail_s_clk[i].voltage_index =
2750 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
2751 info->avail_s_clk[i].voltage_id =
2752 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
2753 }
2754 #endif /* TODO*/
2755
2756 return BP_RESULT_OK;
2757 }
2758
get_integrated_info_v2_1(struct bios_parser * bp,struct integrated_info * info)2759 static enum bp_result get_integrated_info_v2_1(
2760 struct bios_parser *bp,
2761 struct integrated_info *info)
2762 {
2763 struct atom_integrated_system_info_v2_1 *info_v2_1;
2764 uint32_t i;
2765
2766 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1,
2767 DATA_TABLES(integratedsysteminfo));
2768
2769 if (info_v2_1 == NULL)
2770 return BP_RESULT_BADBIOSTABLE;
2771
2772 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_1->gpuclk_ss_percentage);
2773
2774 info->gpu_cap_info =
2775 le32_to_cpu(info_v2_1->gpucapinfo);
2776 /*
2777 * system_config: Bit[0] = 0 : PCIE power gating disabled
2778 * = 1 : PCIE power gating enabled
2779 * Bit[1] = 0 : DDR-PLL shut down disabled
2780 * = 1 : DDR-PLL shut down enabled
2781 * Bit[2] = 0 : DDR-PLL power down disabled
2782 * = 1 : DDR-PLL power down enabled
2783 */
2784 info->system_config = le32_to_cpu(info_v2_1->system_config);
2785 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo);
2786 info->memory_type = info_v2_1->memorytype;
2787 info->ma_channel_number = info_v2_1->umachannelnumber;
2788 info->dp_ss_control =
2789 le16_to_cpu(info_v2_1->reserved1);
2790
2791 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2792 info->ext_disp_conn_info.gu_id[i] =
2793 info_v2_1->extdispconninfo.guid[i];
2794 }
2795
2796 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2797 info->ext_disp_conn_info.path[i].device_connector_id =
2798 object_id_from_bios_object_id(
2799 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid));
2800
2801 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2802 object_id_from_bios_object_id(
2803 le16_to_cpu(
2804 info_v2_1->extdispconninfo.path[i].ext_encoder_objid));
2805
2806 info->ext_disp_conn_info.path[i].device_tag =
2807 le16_to_cpu(
2808 info_v2_1->extdispconninfo.path[i].device_tag);
2809 info->ext_disp_conn_info.path[i].device_acpi_enum =
2810 le16_to_cpu(
2811 info_v2_1->extdispconninfo.path[i].device_acpi_enum);
2812 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2813 info_v2_1->extdispconninfo.path[i].auxddclut_index;
2814 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2815 info_v2_1->extdispconninfo.path[i].hpdlut_index;
2816 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2817 info_v2_1->extdispconninfo.path[i].channelmapping;
2818 info->ext_disp_conn_info.path[i].caps =
2819 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
2820 }
2821
2822 info->ext_disp_conn_info.checksum =
2823 info_v2_1->extdispconninfo.checksum;
2824 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr;
2825 info->dp0_ext_hdmi_reg_num = min_t(u8, info_v2_1->dp0_retimer_set.HdmiRegNum,
2826 ARRAY_SIZE(info->dp0_ext_hdmi_reg_settings));
2827 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
2828 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
2829 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2830 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
2831 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2832 }
2833 info->dp0_ext_hdmi_6g_reg_num = min_t(u8, info_v2_1->dp0_retimer_set.Hdmi6GRegNum,
2834 ARRAY_SIZE(info->dp0_ext_hdmi_6g_reg_settings));
2835 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
2836 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2837 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2838 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2839 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2840 }
2841 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr;
2842 info->dp1_ext_hdmi_reg_num = min_t(u8, info_v2_1->dp1_retimer_set.HdmiRegNum,
2843 ARRAY_SIZE(info->dp1_ext_hdmi_reg_settings));
2844 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
2845 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
2846 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2847 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
2848 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2849 }
2850 info->dp1_ext_hdmi_6g_reg_num = min_t(u8, info_v2_1->dp1_retimer_set.Hdmi6GRegNum,
2851 ARRAY_SIZE(info->dp1_ext_hdmi_6g_reg_settings));
2852 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
2853 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2854 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2855 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2856 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2857 }
2858 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr;
2859 info->dp2_ext_hdmi_reg_num = min_t(u8, info_v2_1->dp2_retimer_set.HdmiRegNum,
2860 ARRAY_SIZE(info->dp2_ext_hdmi_reg_settings));
2861 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
2862 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
2863 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2864 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
2865 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2866 }
2867 info->dp2_ext_hdmi_6g_reg_num = min_t(u8, info_v2_1->dp2_retimer_set.Hdmi6GRegNum,
2868 ARRAY_SIZE(info->dp2_ext_hdmi_6g_reg_settings));
2869 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
2870 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2871 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2872 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2873 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2874 }
2875 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr;
2876 info->dp3_ext_hdmi_reg_num = min_t(u8, info_v2_1->dp3_retimer_set.HdmiRegNum,
2877 ARRAY_SIZE(info->dp3_ext_hdmi_reg_settings));
2878 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
2879 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
2880 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2881 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
2882 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2883 }
2884 info->dp3_ext_hdmi_6g_reg_num = min_t(u8, info_v2_1->dp3_retimer_set.Hdmi6GRegNum,
2885 ARRAY_SIZE(info->dp3_ext_hdmi_6g_reg_settings));
2886 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
2887 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2888 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2889 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2890 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2891 }
2892
2893 info->edp1_info.edp_backlight_pwm_hz =
2894 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz);
2895 info->edp1_info.edp_ss_percentage =
2896 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage);
2897 info->edp1_info.edp_ss_rate_10hz =
2898 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz);
2899 info->edp1_info.edp_pwr_on_off_delay =
2900 info_v2_1->edp1_info.edp_pwr_on_off_delay;
2901 info->edp1_info.edp_pwr_on_vary_bl_to_blon =
2902 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon;
2903 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
2904 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
2905 info->edp1_info.edp_panel_bpc =
2906 info_v2_1->edp1_info.edp_panel_bpc;
2907 info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level;
2908
2909 info->edp2_info.edp_backlight_pwm_hz =
2910 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz);
2911 info->edp2_info.edp_ss_percentage =
2912 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage);
2913 info->edp2_info.edp_ss_rate_10hz =
2914 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz);
2915 info->edp2_info.edp_pwr_on_off_delay =
2916 info_v2_1->edp2_info.edp_pwr_on_off_delay;
2917 info->edp2_info.edp_pwr_on_vary_bl_to_blon =
2918 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon;
2919 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
2920 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
2921 info->edp2_info.edp_panel_bpc =
2922 info_v2_1->edp2_info.edp_panel_bpc;
2923 info->edp2_info.edp_bootup_bl_level =
2924 info_v2_1->edp2_info.edp_bootup_bl_level;
2925
2926 return BP_RESULT_OK;
2927 }
2928
get_integrated_info_v2_2(struct bios_parser * bp,struct integrated_info * info)2929 static enum bp_result get_integrated_info_v2_2(
2930 struct bios_parser *bp,
2931 struct integrated_info *info)
2932 {
2933 struct atom_integrated_system_info_v2_2 *info_v2_2;
2934 uint32_t i;
2935
2936 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2,
2937 DATA_TABLES(integratedsysteminfo));
2938
2939 if (info_v2_2 == NULL)
2940 return BP_RESULT_BADBIOSTABLE;
2941
2942 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_2->gpuclk_ss_percentage);
2943
2944 info->gpu_cap_info =
2945 le32_to_cpu(info_v2_2->gpucapinfo);
2946 /*
2947 * system_config: Bit[0] = 0 : PCIE power gating disabled
2948 * = 1 : PCIE power gating enabled
2949 * Bit[1] = 0 : DDR-PLL shut down disabled
2950 * = 1 : DDR-PLL shut down enabled
2951 * Bit[2] = 0 : DDR-PLL power down disabled
2952 * = 1 : DDR-PLL power down enabled
2953 */
2954 info->system_config = le32_to_cpu(info_v2_2->system_config);
2955 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo);
2956 info->memory_type = info_v2_2->memorytype;
2957 info->ma_channel_number = info_v2_2->umachannelnumber;
2958 info->dp_ss_control =
2959 le16_to_cpu(info_v2_2->reserved1);
2960 info->gpuclk_ss_percentage = info_v2_2->gpuclk_ss_percentage;
2961 info->gpuclk_ss_type = info_v2_2->gpuclk_ss_type;
2962
2963 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2964 info->ext_disp_conn_info.gu_id[i] =
2965 info_v2_2->extdispconninfo.guid[i];
2966 }
2967
2968 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2969 info->ext_disp_conn_info.path[i].device_connector_id =
2970 object_id_from_bios_object_id(
2971 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid));
2972
2973 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2974 object_id_from_bios_object_id(
2975 le16_to_cpu(
2976 info_v2_2->extdispconninfo.path[i].ext_encoder_objid));
2977
2978 info->ext_disp_conn_info.path[i].device_tag =
2979 le16_to_cpu(
2980 info_v2_2->extdispconninfo.path[i].device_tag);
2981 info->ext_disp_conn_info.path[i].device_acpi_enum =
2982 le16_to_cpu(
2983 info_v2_2->extdispconninfo.path[i].device_acpi_enum);
2984 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2985 info_v2_2->extdispconninfo.path[i].auxddclut_index;
2986 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2987 info_v2_2->extdispconninfo.path[i].hpdlut_index;
2988 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2989 info_v2_2->extdispconninfo.path[i].channelmapping;
2990 info->ext_disp_conn_info.path[i].caps =
2991 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
2992 }
2993
2994 info->ext_disp_conn_info.checksum =
2995 info_v2_2->extdispconninfo.checksum;
2996 info->ext_disp_conn_info.fixdpvoltageswing =
2997 info_v2_2->extdispconninfo.fixdpvoltageswing;
2998
2999 info->edp1_info.edp_backlight_pwm_hz =
3000 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz);
3001 info->edp1_info.edp_ss_percentage =
3002 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage);
3003 info->edp1_info.edp_ss_rate_10hz =
3004 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz);
3005 info->edp1_info.edp_pwr_on_off_delay =
3006 info_v2_2->edp1_info.edp_pwr_on_off_delay;
3007 info->edp1_info.edp_pwr_on_vary_bl_to_blon =
3008 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon;
3009 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
3010 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
3011 info->edp1_info.edp_panel_bpc =
3012 info_v2_2->edp1_info.edp_panel_bpc;
3013 info->edp1_info.edp_bootup_bl_level =
3014
3015 info->edp2_info.edp_backlight_pwm_hz =
3016 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz);
3017 info->edp2_info.edp_ss_percentage =
3018 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage);
3019 info->edp2_info.edp_ss_rate_10hz =
3020 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz);
3021 info->edp2_info.edp_pwr_on_off_delay =
3022 info_v2_2->edp2_info.edp_pwr_on_off_delay;
3023 info->edp2_info.edp_pwr_on_vary_bl_to_blon =
3024 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon;
3025 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
3026 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
3027 info->edp2_info.edp_panel_bpc =
3028 info_v2_2->edp2_info.edp_panel_bpc;
3029 info->edp2_info.edp_bootup_bl_level =
3030 info_v2_2->edp2_info.edp_bootup_bl_level;
3031
3032 return BP_RESULT_OK;
3033 }
3034
3035 /*
3036 * construct_integrated_info
3037 *
3038 * @brief
3039 * Get integrated BIOS information based on table revision
3040 *
3041 * @param
3042 * bios_parser *bp - [in]BIOS parser handler to get master data table
3043 * integrated_info *info - [out] store and output integrated info
3044 *
3045 * @return
3046 * static enum bp_result - BP_RESULT_OK if information is available,
3047 * BP_RESULT_BADBIOSTABLE otherwise.
3048 */
construct_integrated_info(struct bios_parser * bp,struct integrated_info * info)3049 static enum bp_result construct_integrated_info(
3050 struct bios_parser *bp,
3051 struct integrated_info *info)
3052 {
3053 static enum bp_result result = BP_RESULT_BADBIOSTABLE;
3054
3055 struct atom_common_table_header *header;
3056 struct atom_data_revision revision;
3057
3058 int32_t i;
3059 int32_t j;
3060
3061 if (!info)
3062 return result;
3063
3064 if (info && DATA_TABLES(integratedsysteminfo)) {
3065 header = GET_IMAGE(struct atom_common_table_header,
3066 DATA_TABLES(integratedsysteminfo));
3067
3068 get_atom_data_table_revision(header, &revision);
3069
3070 switch (revision.major) {
3071 case 1:
3072 switch (revision.minor) {
3073 case 11:
3074 case 12:
3075 result = get_integrated_info_v11(bp, info);
3076 break;
3077 default:
3078 return result;
3079 }
3080 break;
3081 case 2:
3082 switch (revision.minor) {
3083 case 1:
3084 result = get_integrated_info_v2_1(bp, info);
3085 break;
3086 case 2:
3087 case 3:
3088 result = get_integrated_info_v2_2(bp, info);
3089 break;
3090 default:
3091 return result;
3092 }
3093 break;
3094 default:
3095 return result;
3096 }
3097 if (result == BP_RESULT_OK) {
3098
3099 DC_LOG_BIOS("edp1:\n"
3100 "\tedp_pwr_on_off_delay = %d\n"
3101 "\tedp_pwr_on_vary_bl_to_blon = %d\n"
3102 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n"
3103 "\tedp_bootup_bl_level = %d\n",
3104 info->edp1_info.edp_pwr_on_off_delay,
3105 info->edp1_info.edp_pwr_on_vary_bl_to_blon,
3106 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff,
3107 info->edp1_info.edp_bootup_bl_level);
3108 DC_LOG_BIOS("edp2:\n"
3109 "\tedp_pwr_on_off_delayv = %d\n"
3110 "\tedp_pwr_on_vary_bl_to_blon = %d\n"
3111 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n"
3112 "\tedp_bootup_bl_level = %d\n",
3113 info->edp2_info.edp_pwr_on_off_delay,
3114 info->edp2_info.edp_pwr_on_vary_bl_to_blon,
3115 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff,
3116 info->edp2_info.edp_bootup_bl_level);
3117 }
3118 }
3119
3120 if (result != BP_RESULT_OK)
3121 return result;
3122 else {
3123 // Log each external path
3124 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
3125 if (info->ext_disp_conn_info.path[i].device_tag != 0)
3126 DC_LOG_BIOS("integrated_info:For EXTERNAL DISPLAY PATH %d --------------\n"
3127 "DEVICE_TAG: 0x%x\n"
3128 "DEVICE_ACPI_ENUM: 0x%x\n"
3129 "DEVICE_CONNECTOR_ID: 0x%x\n"
3130 "EXT_AUX_DDC_LUT_INDEX: %d\n"
3131 "EXT_HPD_PIN_LUT_INDEX: %d\n"
3132 "EXT_ENCODER_OBJ_ID: 0x%x\n"
3133 "Encoder CAPS: 0x%x\n",
3134 i,
3135 info->ext_disp_conn_info.path[i].device_tag,
3136 info->ext_disp_conn_info.path[i].device_acpi_enum,
3137 info->ext_disp_conn_info.path[i].device_connector_id.id,
3138 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index,
3139 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index,
3140 info->ext_disp_conn_info.path[i].ext_encoder_obj_id.id,
3141 info->ext_disp_conn_info.path[i].caps
3142 );
3143 if ((info->ext_disp_conn_info.path[i].caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)
3144 DC_LOG_BIOS("BIOS AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
3145 else if (bp->base.ctx->dc->config.force_bios_fixed_vs) {
3146 info->ext_disp_conn_info.path[i].caps &= ~AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
3147 info->ext_disp_conn_info.path[i].caps |= AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN;
3148 DC_LOG_BIOS("driver forced AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
3149 }
3150 }
3151 // Log the Checksum and Voltage Swing
3152 DC_LOG_BIOS("Integrated info table CHECKSUM: %d\n"
3153 "Integrated info table FIX_DP_VOLTAGE_SWING: %d\n",
3154 info->ext_disp_conn_info.checksum,
3155 info->ext_disp_conn_info.fixdpvoltageswing);
3156 if (bp->base.ctx->dc->config.force_bios_fixed_vs && info->ext_disp_conn_info.fixdpvoltageswing == 0) {
3157 info->ext_disp_conn_info.fixdpvoltageswing = bp->base.ctx->dc->config.force_bios_fixed_vs & 0xF;
3158 DC_LOG_BIOS("driver forced fixdpvoltageswing = %d\n", info->ext_disp_conn_info.fixdpvoltageswing);
3159 }
3160 }
3161 /* Sort voltage table from low to high*/
3162 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
3163 for (j = i; j > 0; --j) {
3164 if (info->disp_clk_voltage[j].max_supported_clk <
3165 info->disp_clk_voltage[j-1].max_supported_clk)
3166 swap(info->disp_clk_voltage[j-1], info->disp_clk_voltage[j]);
3167 }
3168 }
3169
3170 return result;
3171 }
3172
bios_parser_get_vram_info(struct dc_bios * dcb,struct dc_vram_info * info)3173 static enum bp_result bios_parser_get_vram_info(
3174 struct dc_bios *dcb,
3175 struct dc_vram_info *info)
3176 {
3177 struct bios_parser *bp = BP_FROM_DCB(dcb);
3178 enum bp_result result = BP_RESULT_BADBIOSTABLE;
3179 struct atom_common_table_header *header;
3180 struct atom_data_revision revision;
3181
3182 // vram info moved to umc_info for DCN4x
3183 if (info && DATA_TABLES(umc_info)) {
3184 header = GET_IMAGE(struct atom_common_table_header,
3185 DATA_TABLES(umc_info));
3186
3187 get_atom_data_table_revision(header, &revision);
3188
3189 switch (revision.major) {
3190 case 4:
3191 switch (revision.minor) {
3192 case 0:
3193 result = get_vram_info_from_umc_info_v40(bp, info);
3194 break;
3195 default:
3196 break;
3197 }
3198 break;
3199 default:
3200 break;
3201 }
3202 }
3203
3204 if (result != BP_RESULT_OK && info && DATA_TABLES(vram_info)) {
3205 header = GET_IMAGE(struct atom_common_table_header,
3206 DATA_TABLES(vram_info));
3207
3208 get_atom_data_table_revision(header, &revision);
3209
3210 switch (revision.major) {
3211 case 2:
3212 switch (revision.minor) {
3213 case 3:
3214 result = get_vram_info_v23(bp, info);
3215 break;
3216 case 4:
3217 result = get_vram_info_v24(bp, info);
3218 break;
3219 case 5:
3220 result = get_vram_info_v25(bp, info);
3221 break;
3222 default:
3223 break;
3224 }
3225 break;
3226
3227 case 3:
3228 switch (revision.minor) {
3229 case 0:
3230 result = get_vram_info_v30(bp, info);
3231 break;
3232 default:
3233 break;
3234 }
3235 break;
3236
3237 default:
3238 return result;
3239 }
3240
3241 }
3242 return result;
3243 }
3244
bios_parser_create_integrated_info(struct dc_bios * dcb)3245 static struct integrated_info *bios_parser_create_integrated_info(
3246 struct dc_bios *dcb)
3247 {
3248 struct bios_parser *bp = BP_FROM_DCB(dcb);
3249 struct integrated_info *info;
3250
3251 info = kzalloc_obj(struct integrated_info);
3252
3253 if (info == NULL) {
3254 ASSERT_CRITICAL(0);
3255 return NULL;
3256 }
3257
3258 if (construct_integrated_info(bp, info) == BP_RESULT_OK)
3259 return info;
3260
3261 kfree(info);
3262
3263 return NULL;
3264 }
3265
update_slot_layout_info(struct dc_bios * dcb,unsigned int i,struct slot_layout_info * slot_layout_info)3266 static enum bp_result update_slot_layout_info(
3267 struct dc_bios *dcb,
3268 unsigned int i,
3269 struct slot_layout_info *slot_layout_info)
3270 {
3271 unsigned int record_offset;
3272 unsigned int j;
3273 unsigned int n;
3274 struct atom_display_object_path_v2 *object;
3275 struct atom_bracket_layout_record *record;
3276 struct atom_common_record_header *record_header;
3277 static enum bp_result result;
3278 struct bios_parser *bp;
3279 struct object_info_table *tbl;
3280 struct display_object_info_table_v1_4 *v1_4;
3281
3282 record = NULL;
3283 record_header = NULL;
3284 result = BP_RESULT_NORECORD;
3285
3286 bp = BP_FROM_DCB(dcb);
3287 tbl = &bp->object_info_tbl;
3288 v1_4 = tbl->v1_4;
3289
3290 object = &v1_4->display_path[i];
3291 record_offset = (unsigned int)
3292 (object->disp_recordoffset) +
3293 (unsigned int)(bp->object_info_tbl_offset);
3294
3295 for (n = 0; n < BIOS_MAX_NUM_RECORD; n++) {
3296
3297 record_header = (struct atom_common_record_header *)
3298 GET_IMAGE(struct atom_common_record_header,
3299 record_offset);
3300 if (record_header == NULL) {
3301 result = BP_RESULT_BADBIOSTABLE;
3302 break;
3303 }
3304
3305 /* the end of the list */
3306 if (record_header->record_type == 0xff ||
3307 record_header->record_size == 0) {
3308 break;
3309 }
3310
3311 if (record_header->record_type ==
3312 ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
3313 sizeof(struct atom_bracket_layout_record)
3314 <= record_header->record_size) {
3315 record = (struct atom_bracket_layout_record *)
3316 (record_header);
3317 result = BP_RESULT_OK;
3318 break;
3319 }
3320
3321 record_offset += record_header->record_size;
3322 }
3323
3324 /* return if the record not found */
3325 if (result != BP_RESULT_OK)
3326 return result;
3327
3328 /* get slot sizes */
3329 slot_layout_info->length = record->bracketlen;
3330 slot_layout_info->width = record->bracketwidth;
3331
3332 /* get info for each connector in the slot */
3333 slot_layout_info->num_of_connectors = record->conn_num;
3334 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
3335 slot_layout_info->connectors[j].connector_type =
3336 (enum connector_layout_type)
3337 (record->conn_info[j].connector_type);
3338 switch (record->conn_info[j].connector_type) {
3339 case CONNECTOR_TYPE_DVI_D:
3340 slot_layout_info->connectors[j].connector_type =
3341 CONNECTOR_LAYOUT_TYPE_DVI_D;
3342 slot_layout_info->connectors[j].length =
3343 CONNECTOR_SIZE_DVI;
3344 break;
3345
3346 case CONNECTOR_TYPE_HDMI:
3347 slot_layout_info->connectors[j].connector_type =
3348 CONNECTOR_LAYOUT_TYPE_HDMI;
3349 slot_layout_info->connectors[j].length =
3350 CONNECTOR_SIZE_HDMI;
3351 break;
3352
3353 case CONNECTOR_TYPE_DISPLAY_PORT:
3354 slot_layout_info->connectors[j].connector_type =
3355 CONNECTOR_LAYOUT_TYPE_DP;
3356 slot_layout_info->connectors[j].length =
3357 CONNECTOR_SIZE_DP;
3358 break;
3359
3360 case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
3361 slot_layout_info->connectors[j].connector_type =
3362 CONNECTOR_LAYOUT_TYPE_MINI_DP;
3363 slot_layout_info->connectors[j].length =
3364 CONNECTOR_SIZE_MINI_DP;
3365 break;
3366
3367 default:
3368 slot_layout_info->connectors[j].connector_type =
3369 CONNECTOR_LAYOUT_TYPE_UNKNOWN;
3370 slot_layout_info->connectors[j].length =
3371 CONNECTOR_SIZE_UNKNOWN;
3372 }
3373
3374 slot_layout_info->connectors[j].position =
3375 record->conn_info[j].position;
3376 slot_layout_info->connectors[j].connector_id =
3377 object_id_from_bios_object_id(
3378 record->conn_info[j].connectorobjid);
3379 }
3380 return result;
3381 }
3382
update_slot_layout_info_v2(struct dc_bios * dcb,unsigned int i,struct slot_layout_info * slot_layout_info)3383 static enum bp_result update_slot_layout_info_v2(
3384 struct dc_bios *dcb,
3385 unsigned int i,
3386 struct slot_layout_info *slot_layout_info)
3387 {
3388 unsigned int record_offset;
3389 unsigned int n;
3390 struct atom_display_object_path_v3 *object;
3391 struct atom_bracket_layout_record_v2 *record;
3392 struct atom_common_record_header *record_header;
3393 static enum bp_result result;
3394 struct bios_parser *bp;
3395 struct object_info_table *tbl;
3396 struct display_object_info_table_v1_5 *v1_5;
3397 struct graphics_object_id connector_id;
3398
3399 record = NULL;
3400 record_header = NULL;
3401 result = BP_RESULT_NORECORD;
3402
3403 bp = BP_FROM_DCB(dcb);
3404 tbl = &bp->object_info_tbl;
3405 v1_5 = tbl->v1_5;
3406
3407 object = &v1_5->display_path[i];
3408 record_offset = (unsigned int)
3409 (object->disp_recordoffset) +
3410 (unsigned int)(bp->object_info_tbl_offset);
3411
3412 for (n = 0; n < BIOS_MAX_NUM_RECORD; n++) {
3413
3414 record_header = (struct atom_common_record_header *)
3415 GET_IMAGE(struct atom_common_record_header,
3416 record_offset);
3417 if (record_header == NULL) {
3418 result = BP_RESULT_BADBIOSTABLE;
3419 break;
3420 }
3421
3422 /* the end of the list */
3423 if (record_header->record_type == ATOM_RECORD_END_TYPE ||
3424 record_header->record_size == 0) {
3425 break;
3426 }
3427
3428 if (record_header->record_type ==
3429 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE &&
3430 sizeof(struct atom_bracket_layout_record_v2)
3431 <= record_header->record_size) {
3432 record = (struct atom_bracket_layout_record_v2 *)
3433 (record_header);
3434 result = BP_RESULT_OK;
3435 break;
3436 }
3437
3438 record_offset += record_header->record_size;
3439 }
3440
3441 /* return if the record not found */
3442 if (result != BP_RESULT_OK)
3443 return result;
3444
3445 /* get slot sizes */
3446 connector_id = object_id_from_bios_object_id(object->display_objid);
3447
3448 slot_layout_info->length = record->bracketlen;
3449 slot_layout_info->width = record->bracketwidth;
3450 slot_layout_info->num_of_connectors = v1_5->number_of_path;
3451 slot_layout_info->connectors[i].position = record->conn_num;
3452 slot_layout_info->connectors[i].connector_id = connector_id;
3453
3454 switch (connector_id.id) {
3455 case CONNECTOR_ID_SINGLE_LINK_DVID:
3456 case CONNECTOR_ID_DUAL_LINK_DVID:
3457 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D;
3458 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI;
3459 break;
3460
3461 case CONNECTOR_ID_HDMI_TYPE_A:
3462 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI;
3463 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI;
3464 break;
3465
3466 case CONNECTOR_ID_DISPLAY_PORT:
3467 case CONNECTOR_ID_USBC:
3468 if (record->mini_type == MINI_TYPE_NORMAL) {
3469 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP;
3470 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP;
3471 } else {
3472 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP;
3473 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP;
3474 }
3475 break;
3476
3477 default:
3478 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN;
3479 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN;
3480 }
3481 return result;
3482 }
3483
get_bracket_layout_record(struct dc_bios * dcb,unsigned int bracket_layout_id,struct slot_layout_info * slot_layout_info)3484 static enum bp_result get_bracket_layout_record(
3485 struct dc_bios *dcb,
3486 unsigned int bracket_layout_id,
3487 struct slot_layout_info *slot_layout_info)
3488 {
3489 unsigned int i;
3490 struct bios_parser *bp = BP_FROM_DCB(dcb);
3491 static enum bp_result result;
3492 struct object_info_table *tbl;
3493 struct display_object_info_table_v1_4 *v1_4;
3494 struct display_object_info_table_v1_5 *v1_5;
3495
3496 if (slot_layout_info == NULL) {
3497 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
3498 return BP_RESULT_BADINPUT;
3499 }
3500
3501 tbl = &bp->object_info_tbl;
3502 v1_4 = tbl->v1_4;
3503 v1_5 = tbl->v1_5;
3504
3505 result = BP_RESULT_NORECORD;
3506 switch (bp->object_info_tbl.revision.minor) {
3507 case 4:
3508 default:
3509 for (i = 0; i < v1_4->number_of_path; ++i) {
3510 if (bracket_layout_id == v1_4->display_path[i].display_objid) {
3511 result = update_slot_layout_info(dcb, i, slot_layout_info);
3512 break;
3513 }
3514 }
3515 break;
3516 case 5:
3517 for (i = 0; i < v1_5->number_of_path; ++i)
3518 result = update_slot_layout_info_v2(dcb, i, slot_layout_info);
3519 break;
3520 }
3521
3522 return result;
3523 }
3524
bios_get_board_layout_info(struct dc_bios * dcb,struct board_layout_info * board_layout_info)3525 static enum bp_result bios_get_board_layout_info(
3526 struct dc_bios *dcb,
3527 struct board_layout_info *board_layout_info)
3528 {
3529 unsigned int i;
3530 struct bios_parser *bp;
3531 static enum bp_result record_result;
3532 unsigned int max_slots;
3533
3534 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
3535 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
3536 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
3537 0, 0
3538 };
3539
3540 bp = BP_FROM_DCB(dcb);
3541
3542 if (board_layout_info == NULL) {
3543 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
3544 return BP_RESULT_BADINPUT;
3545 }
3546
3547 board_layout_info->num_of_slots = 0;
3548 max_slots = MAX_BOARD_SLOTS;
3549
3550 // Assume single slot on v1_5
3551 if (bp->object_info_tbl.revision.minor == 5) {
3552 max_slots = 1;
3553 }
3554
3555 for (i = 0; i < max_slots; ++i) {
3556 record_result = get_bracket_layout_record(dcb,
3557 slot_index_to_vbios_id[i],
3558 &board_layout_info->slots[i]);
3559
3560 if (record_result == BP_RESULT_NORECORD && i > 0)
3561 break; /* no more slots present in bios */
3562 else if (record_result != BP_RESULT_OK)
3563 return record_result; /* fail */
3564
3565 ++board_layout_info->num_of_slots;
3566 }
3567
3568 /* all data is valid */
3569 board_layout_info->is_number_of_slots_valid = 1;
3570 board_layout_info->is_slots_size_valid = 1;
3571 board_layout_info->is_connector_offsets_valid = 1;
3572 board_layout_info->is_connector_lengths_valid = 1;
3573
3574 return BP_RESULT_OK;
3575 }
3576
3577
bios_parser_pack_data_tables(struct dc_bios * dcb,void * dst)3578 static uint16_t bios_parser_pack_data_tables(
3579 struct dc_bios *dcb,
3580 void *dst)
3581 {
3582 (void)dcb;
3583 (void)dst;
3584 // TODO: There is data bytes alignment issue, disable it for now.
3585 return 0;
3586 }
3587
bios_get_golden_table(struct bios_parser * bp,uint32_t rev_major,uint32_t rev_minor,uint16_t * dc_golden_table_ver)3588 static struct atom_dc_golden_table_v1 *bios_get_golden_table(
3589 struct bios_parser *bp,
3590 uint32_t rev_major,
3591 uint32_t rev_minor,
3592 uint16_t *dc_golden_table_ver)
3593 {
3594 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL;
3595 uint32_t dc_golden_offset = 0;
3596 *dc_golden_table_ver = 0;
3597
3598 if (!DATA_TABLES(dce_info))
3599 return NULL;
3600
3601 /* ver.4.4 or higher */
3602 switch (rev_major) {
3603 case 4:
3604 switch (rev_minor) {
3605 case 4:
3606 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
3607 DATA_TABLES(dce_info));
3608 if (!disp_cntl_tbl_4_4)
3609 return NULL;
3610 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset;
3611 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver;
3612 break;
3613 case 5:
3614 default:
3615 /* For atom_display_controller_info_v4_5 there is no need to get golden table from
3616 * dc_golden_table_offset as all these fields previously in golden table used for AUX
3617 * pre-charge settings are now available directly in atom_display_controller_info_v4_5.
3618 */
3619 break;
3620 }
3621 break;
3622 }
3623
3624 if (!dc_golden_offset)
3625 return NULL;
3626
3627 if (*dc_golden_table_ver != 1)
3628 return NULL;
3629
3630 return GET_IMAGE(struct atom_dc_golden_table_v1,
3631 dc_golden_offset);
3632 }
3633
bios_get_atom_dc_golden_table(struct dc_bios * dcb)3634 static enum bp_result bios_get_atom_dc_golden_table(
3635 struct dc_bios *dcb)
3636 {
3637 struct bios_parser *bp = BP_FROM_DCB(dcb);
3638 enum bp_result result = BP_RESULT_OK;
3639 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL;
3640 struct atom_common_table_header *header;
3641 struct atom_data_revision tbl_revision;
3642 uint16_t dc_golden_table_ver = 0;
3643
3644 header = GET_IMAGE(struct atom_common_table_header,
3645 DATA_TABLES(dce_info));
3646 if (!header)
3647 return BP_RESULT_UNSUPPORTED;
3648
3649 get_atom_data_table_revision(header, &tbl_revision);
3650
3651 atom_dc_golden_table = bios_get_golden_table(bp,
3652 tbl_revision.major,
3653 tbl_revision.minor,
3654 &dc_golden_table_ver);
3655
3656 if (!atom_dc_golden_table)
3657 return BP_RESULT_UNSUPPORTED;
3658
3659 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver;
3660 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val;
3661 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val;
3662 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val;
3663 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val;
3664 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val;
3665 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val;
3666 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val;
3667 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val;
3668 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val;
3669
3670 return result;
3671 }
3672
3673
3674 static const struct dc_vbios_funcs vbios_funcs = {
3675 .get_connectors_number = bios_parser_get_connectors_number,
3676
3677 .get_connector_id = bios_parser_get_connector_id,
3678
3679 .get_src_obj = bios_parser_get_src_obj,
3680
3681 .get_i2c_info = bios_parser_get_i2c_info,
3682
3683 .get_hpd_info = bios_parser_get_hpd_info,
3684
3685 .get_device_tag = bios_parser_get_device_tag,
3686
3687 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
3688
3689 .get_ss_entry_number = bios_parser_get_ss_entry_number,
3690
3691 .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
3692
3693 .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
3694
3695 .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
3696
3697 .is_device_id_supported = bios_parser_is_device_id_supported,
3698
3699 .is_accelerated_mode = bios_parser_is_accelerated_mode,
3700
3701 .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
3702
3703
3704 /* COMMANDS */
3705 .encoder_control = bios_parser_encoder_control,
3706
3707 .transmitter_control = bios_parser_transmitter_control,
3708
3709 .enable_crtc = bios_parser_enable_crtc,
3710
3711 .set_pixel_clock = bios_parser_set_pixel_clock,
3712
3713 .set_dce_clock = bios_parser_set_dce_clock,
3714
3715 .program_crtc_timing = bios_parser_program_crtc_timing,
3716
3717 .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
3718
3719 .bios_parser_destroy = firmware_parser_destroy,
3720
3721 .get_board_layout_info = bios_get_board_layout_info,
3722 .pack_data_tables = bios_parser_pack_data_tables,
3723
3724 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
3725
3726 .enable_lvtma_control = bios_parser_enable_lvtma_control,
3727
3728 .get_soc_bb_info = bios_parser_get_soc_bb_info,
3729
3730 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info,
3731
3732 .get_lttpr_caps = bios_parser_get_lttpr_caps,
3733
3734 .get_lttpr_interop = bios_parser_get_lttpr_interop,
3735
3736 .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info,
3737 };
3738
bios_parser2_construct(struct bios_parser * bp,struct bp_init_data * init,enum dce_version dce_version)3739 static bool bios_parser2_construct(
3740 struct bios_parser *bp,
3741 struct bp_init_data *init,
3742 enum dce_version dce_version)
3743 {
3744 uint16_t *rom_header_offset = NULL;
3745 struct atom_rom_header_v2_2 *rom_header = NULL;
3746 struct display_object_info_table_v1_4 *object_info_tbl;
3747 struct atom_data_revision tbl_rev = {0};
3748
3749 if (!init)
3750 return false;
3751
3752 if (!init->bios)
3753 return false;
3754
3755 bp->base.funcs = &vbios_funcs;
3756 bp->base.bios = init->bios;
3757 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
3758
3759 bp->base.ctx = init->ctx;
3760
3761 bp->base.bios_local_image = NULL;
3762
3763 rom_header_offset =
3764 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
3765
3766 if (!rom_header_offset)
3767 return false;
3768
3769 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
3770
3771 if (!rom_header)
3772 return false;
3773
3774 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
3775 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
3776 return false;
3777
3778 bp->master_data_tbl =
3779 GET_IMAGE(struct atom_master_data_table_v2_1,
3780 rom_header->masterdatatable_offset);
3781
3782 if (!bp->master_data_tbl)
3783 return false;
3784
3785 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
3786
3787 if (!bp->object_info_tbl_offset)
3788 return false;
3789
3790 object_info_tbl =
3791 GET_IMAGE(struct display_object_info_table_v1_4,
3792 bp->object_info_tbl_offset);
3793
3794 if (!object_info_tbl)
3795 return false;
3796
3797 get_atom_data_table_revision(&object_info_tbl->table_header,
3798 &bp->object_info_tbl.revision);
3799
3800 if (bp->object_info_tbl.revision.major == 1
3801 && bp->object_info_tbl.revision.minor == 4) {
3802 struct display_object_info_table_v1_4 *tbl_v1_4;
3803
3804 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
3805 bp->object_info_tbl_offset);
3806 if (!tbl_v1_4)
3807 return false;
3808
3809 bp->object_info_tbl.v1_4 = tbl_v1_4;
3810 } else if (bp->object_info_tbl.revision.major == 1
3811 && bp->object_info_tbl.revision.minor == 5) {
3812 struct display_object_info_table_v1_5 *tbl_v1_5;
3813
3814 tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5,
3815 bp->object_info_tbl_offset);
3816 if (!tbl_v1_5)
3817 return false;
3818
3819 bp->object_info_tbl.v1_5 = tbl_v1_5;
3820 } else {
3821 ASSERT(0);
3822 return false;
3823 }
3824
3825 dal_firmware_parser_init_cmd_tbl(bp);
3826 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
3827
3828 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
3829 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
3830 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info);
3831 bios_parser_get_soc_bb_info(&bp->base, &bp->base.bb_info);
3832 return true;
3833 }
3834
firmware_parser_create(struct bp_init_data * init,enum dce_version dce_version)3835 struct dc_bios *firmware_parser_create(
3836 struct bp_init_data *init,
3837 enum dce_version dce_version)
3838 {
3839 struct bios_parser *bp;
3840
3841 bp = kzalloc_obj(struct bios_parser);
3842 if (!bp)
3843 return NULL;
3844
3845 if (bios_parser2_construct(bp, init, dce_version))
3846 return &bp->base;
3847
3848 kfree(bp);
3849 return NULL;
3850 }
3851
3852
3853