1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 /* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7 #include <linux/types.h> 8 #include <asm/byteorder.h> 9 #include <linux/io.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/errno.h> 13 #include <linux/kernel.h> 14 #include <linux/mutex.h> 15 #include <linux/pci.h> 16 #include <linux/slab.h> 17 #include <linux/string.h> 18 #include <linux/vmalloc.h> 19 #include <linux/etherdevice.h> 20 #include <linux/qed/qed_chain.h> 21 #include <linux/qed/qed_if.h> 22 #include "qed.h" 23 #include "qed_cxt.h" 24 #include "qed_dcbx.h" 25 #include "qed_dev_api.h" 26 #include "qed_fcoe.h" 27 #include "qed_hsi.h" 28 #include "qed_iro_hsi.h" 29 #include "qed_hw.h" 30 #include "qed_init_ops.h" 31 #include "qed_int.h" 32 #include "qed_iscsi.h" 33 #include "qed_ll2.h" 34 #include "qed_mcp.h" 35 #include "qed_ooo.h" 36 #include "qed_reg_addr.h" 37 #include "qed_sp.h" 38 #include "qed_sriov.h" 39 #include "qed_vf.h" 40 #include "qed_rdma.h" 41 #include "qed_nvmetcp.h" 42 43 static DEFINE_SPINLOCK(qm_lock); 44 45 /******************** Doorbell Recovery *******************/ 46 /* The doorbell recovery mechanism consists of a list of entries which represent 47 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each 48 * entity needs to register with the mechanism and provide the parameters 49 * describing it's doorbell, including a location where last used doorbell data 50 * can be found. The doorbell execute function will traverse the list and 51 * doorbell all of the registered entries. 52 */ 53 struct qed_db_recovery_entry { 54 struct list_head list_entry; 55 void __iomem *db_addr; 56 void *db_data; 57 enum qed_db_rec_width db_width; 58 enum qed_db_rec_space db_space; 59 u8 hwfn_idx; 60 }; 61 62 /* Display a single doorbell recovery entry */ 63 static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn, 64 struct qed_db_recovery_entry *db_entry, 65 char *action) 66 { 67 DP_VERBOSE(p_hwfn, 68 QED_MSG_SPQ, 69 "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n", 70 action, 71 db_entry, 72 db_entry->db_addr, 73 db_entry->db_data, 74 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b", 75 db_entry->db_space == DB_REC_USER ? "user" : "kernel", 76 db_entry->hwfn_idx); 77 } 78 79 /* Doorbell address sanity (address within doorbell bar range) */ 80 static bool qed_db_rec_sanity(struct qed_dev *cdev, 81 void __iomem *db_addr, 82 enum qed_db_rec_width db_width, 83 void *db_data) 84 { 85 u32 width = (db_width == DB_REC_WIDTH_32B) ? 32 : 64; 86 87 /* Make sure doorbell address is within the doorbell bar */ 88 if (db_addr < cdev->doorbells || 89 (u8 __iomem *)db_addr + width > 90 (u8 __iomem *)cdev->doorbells + cdev->db_size) { 91 WARN(true, 92 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n", 93 db_addr, 94 cdev->doorbells, 95 (u8 __iomem *)cdev->doorbells + cdev->db_size); 96 return false; 97 } 98 99 /* ake sure doorbell data pointer is not null */ 100 if (!db_data) { 101 WARN(true, "Illegal doorbell data pointer: %p", db_data); 102 return false; 103 } 104 105 return true; 106 } 107 108 /* Find hwfn according to the doorbell address */ 109 static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev, 110 void __iomem *db_addr) 111 { 112 struct qed_hwfn *p_hwfn; 113 114 /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */ 115 if (cdev->num_hwfns > 1) 116 p_hwfn = db_addr < cdev->hwfns[1].doorbells ? 117 &cdev->hwfns[0] : &cdev->hwfns[1]; 118 else 119 p_hwfn = QED_LEADING_HWFN(cdev); 120 121 return p_hwfn; 122 } 123 124 /* Add a new entry to the doorbell recovery mechanism */ 125 int qed_db_recovery_add(struct qed_dev *cdev, 126 void __iomem *db_addr, 127 void *db_data, 128 enum qed_db_rec_width db_width, 129 enum qed_db_rec_space db_space) 130 { 131 struct qed_db_recovery_entry *db_entry; 132 struct qed_hwfn *p_hwfn; 133 134 /* Shortcircuit VFs, for now */ 135 if (IS_VF(cdev)) { 136 DP_VERBOSE(cdev, 137 QED_MSG_IOV, "db recovery - skipping VF doorbell\n"); 138 return 0; 139 } 140 141 /* Sanitize doorbell address */ 142 if (!qed_db_rec_sanity(cdev, db_addr, db_width, db_data)) 143 return -EINVAL; 144 145 /* Obtain hwfn from doorbell address */ 146 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr); 147 148 /* Create entry */ 149 db_entry = kzalloc_obj(*db_entry); 150 if (!db_entry) { 151 DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n"); 152 return -ENOMEM; 153 } 154 155 /* Populate entry */ 156 db_entry->db_addr = db_addr; 157 db_entry->db_data = db_data; 158 db_entry->db_width = db_width; 159 db_entry->db_space = db_space; 160 db_entry->hwfn_idx = p_hwfn->my_id; 161 162 /* Display */ 163 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding"); 164 165 /* Protect the list */ 166 spin_lock_bh(&p_hwfn->db_recovery_info.lock); 167 list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list); 168 spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 169 170 return 0; 171 } 172 173 /* Remove an entry from the doorbell recovery mechanism */ 174 int qed_db_recovery_del(struct qed_dev *cdev, 175 void __iomem *db_addr, void *db_data) 176 { 177 struct qed_db_recovery_entry *db_entry = NULL; 178 struct qed_hwfn *p_hwfn; 179 int rc = -EINVAL; 180 181 /* Shortcircuit VFs, for now */ 182 if (IS_VF(cdev)) { 183 DP_VERBOSE(cdev, 184 QED_MSG_IOV, "db recovery - skipping VF doorbell\n"); 185 return 0; 186 } 187 188 /* Obtain hwfn from doorbell address */ 189 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr); 190 191 /* Protect the list */ 192 spin_lock_bh(&p_hwfn->db_recovery_info.lock); 193 list_for_each_entry(db_entry, 194 &p_hwfn->db_recovery_info.list, list_entry) { 195 /* search according to db_data addr since db_addr is not unique (roce) */ 196 if (db_entry->db_data == db_data) { 197 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting"); 198 list_del(&db_entry->list_entry); 199 rc = 0; 200 break; 201 } 202 } 203 204 spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 205 206 if (rc == -EINVAL) 207 208 DP_NOTICE(p_hwfn, 209 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n", 210 db_data, db_addr); 211 else 212 kfree(db_entry); 213 214 return rc; 215 } 216 217 /* Initialize the doorbell recovery mechanism */ 218 static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn) 219 { 220 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n"); 221 222 /* Make sure db_size was set in cdev */ 223 if (!p_hwfn->cdev->db_size) { 224 DP_ERR(p_hwfn->cdev, "db_size not set\n"); 225 return -EINVAL; 226 } 227 228 INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list); 229 spin_lock_init(&p_hwfn->db_recovery_info.lock); 230 p_hwfn->db_recovery_info.db_recovery_counter = 0; 231 232 return 0; 233 } 234 235 /* Destroy the doorbell recovery mechanism */ 236 static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn) 237 { 238 struct qed_db_recovery_entry *db_entry = NULL; 239 240 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n"); 241 if (!list_empty(&p_hwfn->db_recovery_info.list)) { 242 DP_VERBOSE(p_hwfn, 243 QED_MSG_SPQ, 244 "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n"); 245 while (!list_empty(&p_hwfn->db_recovery_info.list)) { 246 db_entry = 247 list_first_entry(&p_hwfn->db_recovery_info.list, 248 struct qed_db_recovery_entry, 249 list_entry); 250 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging"); 251 list_del(&db_entry->list_entry); 252 kfree(db_entry); 253 } 254 } 255 p_hwfn->db_recovery_info.db_recovery_counter = 0; 256 } 257 258 /* Ring the doorbell of a single doorbell recovery entry */ 259 static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn, 260 struct qed_db_recovery_entry *db_entry) 261 { 262 /* Print according to width */ 263 if (db_entry->db_width == DB_REC_WIDTH_32B) { 264 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 265 "ringing doorbell address %p data %x\n", 266 db_entry->db_addr, 267 *(u32 *)db_entry->db_data); 268 } else { 269 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 270 "ringing doorbell address %p data %llx\n", 271 db_entry->db_addr, 272 *(u64 *)(db_entry->db_data)); 273 } 274 275 /* Sanity */ 276 if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr, 277 db_entry->db_width, db_entry->db_data)) 278 return; 279 280 /* Flush the write combined buffer. Since there are multiple doorbelling 281 * entities using the same address, if we don't flush, a transaction 282 * could be lost. 283 */ 284 wmb(); 285 286 /* Ring the doorbell */ 287 if (db_entry->db_width == DB_REC_WIDTH_32B) 288 DIRECT_REG_WR(db_entry->db_addr, 289 *(u32 *)(db_entry->db_data)); 290 else 291 DIRECT_REG_WR64(db_entry->db_addr, 292 *(u64 *)(db_entry->db_data)); 293 294 /* Flush the write combined buffer. Next doorbell may come from a 295 * different entity to the same address... 296 */ 297 wmb(); 298 } 299 300 /* Traverse the doorbell recovery entry list and ring all the doorbells */ 301 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn) 302 { 303 struct qed_db_recovery_entry *db_entry = NULL; 304 305 DP_NOTICE(p_hwfn, "Executing doorbell recovery. Counter was %d\n", 306 p_hwfn->db_recovery_info.db_recovery_counter); 307 308 /* Track amount of times recovery was executed */ 309 p_hwfn->db_recovery_info.db_recovery_counter++; 310 311 /* Protect the list */ 312 spin_lock_bh(&p_hwfn->db_recovery_info.lock); 313 list_for_each_entry(db_entry, 314 &p_hwfn->db_recovery_info.list, list_entry) 315 qed_db_recovery_ring(p_hwfn, db_entry); 316 spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 317 } 318 319 /******************** Doorbell Recovery end ****************/ 320 321 /********************************** NIG LLH ***********************************/ 322 323 enum qed_llh_filter_type { 324 QED_LLH_FILTER_TYPE_MAC, 325 QED_LLH_FILTER_TYPE_PROTOCOL, 326 }; 327 328 struct qed_llh_mac_filter { 329 u8 addr[ETH_ALEN]; 330 }; 331 332 struct qed_llh_protocol_filter { 333 enum qed_llh_prot_filter_type_t type; 334 u16 source_port_or_eth_type; 335 u16 dest_port; 336 }; 337 338 union qed_llh_filter { 339 struct qed_llh_mac_filter mac; 340 struct qed_llh_protocol_filter protocol; 341 }; 342 343 struct qed_llh_filter_info { 344 bool b_enabled; 345 u32 ref_cnt; 346 enum qed_llh_filter_type type; 347 union qed_llh_filter filter; 348 }; 349 350 struct qed_llh_info { 351 /* Number of LLH filters banks */ 352 u8 num_ppfid; 353 354 #define MAX_NUM_PPFID 8 355 u8 ppfid_array[MAX_NUM_PPFID]; 356 357 /* Array of filters arrays: 358 * "num_ppfid" elements of filters banks, where each is an array of 359 * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters. 360 */ 361 struct qed_llh_filter_info **pp_filters; 362 }; 363 364 static void qed_llh_free(struct qed_dev *cdev) 365 { 366 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 367 u32 i; 368 369 if (p_llh_info) { 370 if (p_llh_info->pp_filters) 371 for (i = 0; i < p_llh_info->num_ppfid; i++) 372 kfree(p_llh_info->pp_filters[i]); 373 374 kfree(p_llh_info->pp_filters); 375 } 376 377 kfree(p_llh_info); 378 cdev->p_llh_info = NULL; 379 } 380 381 static int qed_llh_alloc(struct qed_dev *cdev) 382 { 383 struct qed_llh_info *p_llh_info; 384 u32 size, i; 385 386 p_llh_info = kzalloc_obj(*p_llh_info); 387 if (!p_llh_info) 388 return -ENOMEM; 389 cdev->p_llh_info = p_llh_info; 390 391 for (i = 0; i < MAX_NUM_PPFID; i++) { 392 if (!(cdev->ppfid_bitmap & (0x1 << i))) 393 continue; 394 395 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i; 396 DP_VERBOSE(cdev, QED_MSG_SP, "ppfid_array[%d] = %u\n", 397 p_llh_info->num_ppfid, i); 398 p_llh_info->num_ppfid++; 399 } 400 401 size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters); 402 p_llh_info->pp_filters = kzalloc(size, GFP_KERNEL); 403 if (!p_llh_info->pp_filters) 404 return -ENOMEM; 405 406 size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE * 407 sizeof(**p_llh_info->pp_filters); 408 for (i = 0; i < p_llh_info->num_ppfid; i++) { 409 p_llh_info->pp_filters[i] = kzalloc(size, GFP_KERNEL); 410 if (!p_llh_info->pp_filters[i]) 411 return -ENOMEM; 412 } 413 414 return 0; 415 } 416 417 static int qed_llh_shadow_sanity(struct qed_dev *cdev, 418 u8 ppfid, u8 filter_idx, const char *action) 419 { 420 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 421 422 if (ppfid >= p_llh_info->num_ppfid) { 423 DP_NOTICE(cdev, 424 "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n", 425 action, ppfid, p_llh_info->num_ppfid); 426 return -EINVAL; 427 } 428 429 if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 430 DP_NOTICE(cdev, 431 "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n", 432 action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE); 433 return -EINVAL; 434 } 435 436 return 0; 437 } 438 439 #define QED_LLH_INVALID_FILTER_IDX 0xff 440 441 static int 442 qed_llh_shadow_search_filter(struct qed_dev *cdev, 443 u8 ppfid, 444 union qed_llh_filter *p_filter, u8 *p_filter_idx) 445 { 446 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 447 struct qed_llh_filter_info *p_filters; 448 int rc; 449 u8 i; 450 451 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "search"); 452 if (rc) 453 return rc; 454 455 *p_filter_idx = QED_LLH_INVALID_FILTER_IDX; 456 457 p_filters = p_llh_info->pp_filters[ppfid]; 458 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 459 if (!memcmp(p_filter, &p_filters[i].filter, 460 sizeof(*p_filter))) { 461 *p_filter_idx = i; 462 break; 463 } 464 } 465 466 return 0; 467 } 468 469 static int 470 qed_llh_shadow_get_free_idx(struct qed_dev *cdev, u8 ppfid, u8 *p_filter_idx) 471 { 472 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 473 struct qed_llh_filter_info *p_filters; 474 int rc; 475 u8 i; 476 477 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "get_free_idx"); 478 if (rc) 479 return rc; 480 481 *p_filter_idx = QED_LLH_INVALID_FILTER_IDX; 482 483 p_filters = p_llh_info->pp_filters[ppfid]; 484 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 485 if (!p_filters[i].b_enabled) { 486 *p_filter_idx = i; 487 break; 488 } 489 } 490 491 return 0; 492 } 493 494 static int 495 __qed_llh_shadow_add_filter(struct qed_dev *cdev, 496 u8 ppfid, 497 u8 filter_idx, 498 enum qed_llh_filter_type type, 499 union qed_llh_filter *p_filter, u32 *p_ref_cnt) 500 { 501 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 502 struct qed_llh_filter_info *p_filters; 503 int rc; 504 505 rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "add"); 506 if (rc) 507 return rc; 508 509 p_filters = p_llh_info->pp_filters[ppfid]; 510 if (!p_filters[filter_idx].ref_cnt) { 511 p_filters[filter_idx].b_enabled = true; 512 p_filters[filter_idx].type = type; 513 memcpy(&p_filters[filter_idx].filter, p_filter, 514 sizeof(p_filters[filter_idx].filter)); 515 } 516 517 *p_ref_cnt = ++p_filters[filter_idx].ref_cnt; 518 519 return 0; 520 } 521 522 static int 523 qed_llh_shadow_add_filter(struct qed_dev *cdev, 524 u8 ppfid, 525 enum qed_llh_filter_type type, 526 union qed_llh_filter *p_filter, 527 u8 *p_filter_idx, u32 *p_ref_cnt) 528 { 529 int rc; 530 531 /* Check if the same filter already exist */ 532 rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx); 533 if (rc) 534 return rc; 535 536 /* Find a new entry in case of a new filter */ 537 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) { 538 rc = qed_llh_shadow_get_free_idx(cdev, ppfid, p_filter_idx); 539 if (rc) 540 return rc; 541 } 542 543 /* No free entry was found */ 544 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) { 545 DP_NOTICE(cdev, 546 "Failed to find an empty LLH filter to utilize [ppfid %d]\n", 547 ppfid); 548 return -EINVAL; 549 } 550 551 return __qed_llh_shadow_add_filter(cdev, ppfid, *p_filter_idx, type, 552 p_filter, p_ref_cnt); 553 } 554 555 static int 556 __qed_llh_shadow_remove_filter(struct qed_dev *cdev, 557 u8 ppfid, u8 filter_idx, u32 *p_ref_cnt) 558 { 559 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 560 struct qed_llh_filter_info *p_filters; 561 int rc; 562 563 rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "remove"); 564 if (rc) 565 return rc; 566 567 p_filters = p_llh_info->pp_filters[ppfid]; 568 if (!p_filters[filter_idx].ref_cnt) { 569 DP_NOTICE(cdev, 570 "LLH shadow: trying to remove a filter with ref_cnt=0\n"); 571 return -EINVAL; 572 } 573 574 *p_ref_cnt = --p_filters[filter_idx].ref_cnt; 575 if (!p_filters[filter_idx].ref_cnt) 576 memset(&p_filters[filter_idx], 577 0, sizeof(p_filters[filter_idx])); 578 579 return 0; 580 } 581 582 static int 583 qed_llh_shadow_remove_filter(struct qed_dev *cdev, 584 u8 ppfid, 585 union qed_llh_filter *p_filter, 586 u8 *p_filter_idx, u32 *p_ref_cnt) 587 { 588 int rc; 589 590 rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx); 591 if (rc) 592 return rc; 593 594 /* No matching filter was found */ 595 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) { 596 DP_NOTICE(cdev, "Failed to find a filter in the LLH shadow\n"); 597 return -EINVAL; 598 } 599 600 return __qed_llh_shadow_remove_filter(cdev, ppfid, *p_filter_idx, 601 p_ref_cnt); 602 } 603 604 static int qed_llh_abs_ppfid(struct qed_dev *cdev, u8 ppfid, u8 *p_abs_ppfid) 605 { 606 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 607 608 if (ppfid >= p_llh_info->num_ppfid) { 609 DP_NOTICE(cdev, 610 "ppfid %d is not valid, available indices are 0..%d\n", 611 ppfid, p_llh_info->num_ppfid - 1); 612 *p_abs_ppfid = 0; 613 return -EINVAL; 614 } 615 616 *p_abs_ppfid = p_llh_info->ppfid_array[ppfid]; 617 618 return 0; 619 } 620 621 static int 622 qed_llh_set_engine_affin(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 623 { 624 struct qed_dev *cdev = p_hwfn->cdev; 625 enum qed_eng eng; 626 u8 ppfid; 627 int rc; 628 629 rc = qed_mcp_get_engine_config(p_hwfn, p_ptt); 630 if (rc != 0 && rc != -EOPNOTSUPP) { 631 DP_NOTICE(p_hwfn, 632 "Failed to get the engine affinity configuration\n"); 633 return rc; 634 } 635 636 /* RoCE PF is bound to a single engine */ 637 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) { 638 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0; 639 rc = qed_llh_set_roce_affinity(cdev, eng); 640 if (rc) { 641 DP_NOTICE(cdev, 642 "Failed to set the RoCE engine affinity\n"); 643 return rc; 644 } 645 646 DP_VERBOSE(cdev, 647 QED_MSG_SP, 648 "LLH: Set the engine affinity of RoCE packets as %d\n", 649 eng); 650 } 651 652 /* Storage PF is bound to a single engine while L2 PF uses both */ 653 if (QED_IS_FCOE_PERSONALITY(p_hwfn) || QED_IS_ISCSI_PERSONALITY(p_hwfn) || 654 QED_IS_NVMETCP_PERSONALITY(p_hwfn)) 655 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0; 656 else /* L2_PERSONALITY */ 657 eng = QED_BOTH_ENG; 658 659 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) { 660 rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng); 661 if (rc) { 662 DP_NOTICE(cdev, 663 "Failed to set the engine affinity of ppfid %d\n", 664 ppfid); 665 return rc; 666 } 667 } 668 669 DP_VERBOSE(cdev, QED_MSG_SP, 670 "LLH: Set the engine affinity of non-RoCE packets as %d\n", 671 eng); 672 673 return 0; 674 } 675 676 static int qed_llh_hw_init_pf(struct qed_hwfn *p_hwfn, 677 struct qed_ptt *p_ptt) 678 { 679 struct qed_dev *cdev = p_hwfn->cdev; 680 u8 ppfid, abs_ppfid; 681 int rc; 682 683 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) { 684 u32 addr; 685 686 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 687 if (rc) 688 return rc; 689 690 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4; 691 qed_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id); 692 } 693 694 if (test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) && 695 !QED_IS_FCOE_PERSONALITY(p_hwfn)) { 696 rc = qed_llh_add_mac_filter(cdev, 0, 697 p_hwfn->hw_info.hw_mac_addr); 698 if (rc) 699 DP_NOTICE(cdev, 700 "Failed to add an LLH filter with the primary MAC\n"); 701 } 702 703 if (QED_IS_CMT(cdev)) { 704 rc = qed_llh_set_engine_affin(p_hwfn, p_ptt); 705 if (rc) 706 return rc; 707 } 708 709 return 0; 710 } 711 712 u8 qed_llh_get_num_ppfid(struct qed_dev *cdev) 713 { 714 return cdev->p_llh_info->num_ppfid; 715 } 716 717 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK 0x3 718 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT 0 719 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK 0x3 720 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT 2 721 722 int qed_llh_set_ppfid_affinity(struct qed_dev *cdev, u8 ppfid, enum qed_eng eng) 723 { 724 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 725 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 726 u32 addr, val, eng_sel; 727 u8 abs_ppfid; 728 int rc = 0; 729 730 if (!p_ptt) 731 return -EAGAIN; 732 733 if (!QED_IS_CMT(cdev)) 734 goto out; 735 736 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 737 if (rc) 738 goto out; 739 740 switch (eng) { 741 case QED_ENG0: 742 eng_sel = 0; 743 break; 744 case QED_ENG1: 745 eng_sel = 1; 746 break; 747 case QED_BOTH_ENG: 748 eng_sel = 2; 749 break; 750 default: 751 DP_NOTICE(cdev, "Invalid affinity value for ppfid [%d]\n", eng); 752 rc = -EINVAL; 753 goto out; 754 } 755 756 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4; 757 val = qed_rd(p_hwfn, p_ptt, addr); 758 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel); 759 qed_wr(p_hwfn, p_ptt, addr, val); 760 761 /* The iWARP affinity is set as the affinity of ppfid 0 */ 762 if (!ppfid && QED_IS_IWARP_PERSONALITY(p_hwfn)) 763 cdev->iwarp_affin = (eng == QED_ENG1) ? 1 : 0; 764 out: 765 qed_ptt_release(p_hwfn, p_ptt); 766 767 return rc; 768 } 769 770 int qed_llh_set_roce_affinity(struct qed_dev *cdev, enum qed_eng eng) 771 { 772 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 773 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 774 u32 addr, val, eng_sel; 775 u8 ppfid, abs_ppfid; 776 int rc = 0; 777 778 if (!p_ptt) 779 return -EAGAIN; 780 781 if (!QED_IS_CMT(cdev)) 782 goto out; 783 784 switch (eng) { 785 case QED_ENG0: 786 eng_sel = 0; 787 break; 788 case QED_ENG1: 789 eng_sel = 1; 790 break; 791 case QED_BOTH_ENG: 792 eng_sel = 2; 793 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL, 794 0xf); /* QP bit 15 */ 795 break; 796 default: 797 DP_NOTICE(cdev, "Invalid affinity value for RoCE [%d]\n", eng); 798 rc = -EINVAL; 799 goto out; 800 } 801 802 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) { 803 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 804 if (rc) 805 goto out; 806 807 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4; 808 val = qed_rd(p_hwfn, p_ptt, addr); 809 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel); 810 qed_wr(p_hwfn, p_ptt, addr, val); 811 } 812 out: 813 qed_ptt_release(p_hwfn, p_ptt); 814 815 return rc; 816 } 817 818 struct qed_llh_filter_details { 819 u64 value; 820 u32 mode; 821 u32 protocol_type; 822 u32 hdr_sel; 823 u32 enable; 824 }; 825 826 static int 827 qed_llh_access_filter(struct qed_hwfn *p_hwfn, 828 struct qed_ptt *p_ptt, 829 u8 abs_ppfid, 830 u8 filter_idx, 831 struct qed_llh_filter_details *p_details) 832 { 833 struct qed_dmae_params params = {0}; 834 u32 addr; 835 u8 pfid; 836 int rc; 837 838 /* The NIG/LLH registers that are accessed in this function have only 16 839 * rows which are exposed to a PF. I.e. only the 16 filters of its 840 * default ppfid. Accessing filters of other ppfids requires pretending 841 * to another PFs. 842 * The calculation of PPFID->PFID in AH is based on the relative index 843 * of a PF on its port. 844 * For BB the pfid is actually the abs_ppfid. 845 */ 846 if (QED_IS_BB(p_hwfn->cdev)) 847 pfid = abs_ppfid; 848 else 849 pfid = abs_ppfid * p_hwfn->cdev->num_ports_in_engine + 850 MFW_PORT(p_hwfn); 851 852 /* Filter enable - should be done first when removing a filter */ 853 if (!p_details->enable) { 854 qed_fid_pretend(p_hwfn, p_ptt, 855 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); 856 857 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4; 858 qed_wr(p_hwfn, p_ptt, addr, p_details->enable); 859 860 qed_fid_pretend(p_hwfn, p_ptt, 861 p_hwfn->rel_pf_id << 862 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); 863 } 864 865 /* Filter value */ 866 addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4; 867 868 SET_FIELD(params.flags, QED_DMAE_PARAMS_DST_PF_VALID, 0x1); 869 params.dst_pfid = pfid; 870 rc = qed_dmae_host2grc(p_hwfn, 871 p_ptt, 872 (u64)(uintptr_t)&p_details->value, 873 addr, 2 /* size_in_dwords */, 874 ¶ms); 875 if (rc) 876 return rc; 877 878 qed_fid_pretend(p_hwfn, p_ptt, 879 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); 880 881 /* Filter mode */ 882 addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4; 883 qed_wr(p_hwfn, p_ptt, addr, p_details->mode); 884 885 /* Filter protocol type */ 886 addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4; 887 qed_wr(p_hwfn, p_ptt, addr, p_details->protocol_type); 888 889 /* Filter header select */ 890 addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4; 891 qed_wr(p_hwfn, p_ptt, addr, p_details->hdr_sel); 892 893 /* Filter enable - should be done last when adding a filter */ 894 if (p_details->enable) { 895 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4; 896 qed_wr(p_hwfn, p_ptt, addr, p_details->enable); 897 } 898 899 qed_fid_pretend(p_hwfn, p_ptt, 900 p_hwfn->rel_pf_id << 901 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); 902 903 return 0; 904 } 905 906 static int 907 qed_llh_add_filter(struct qed_hwfn *p_hwfn, 908 struct qed_ptt *p_ptt, 909 u8 abs_ppfid, 910 u8 filter_idx, u8 filter_prot_type, u32 high, u32 low) 911 { 912 struct qed_llh_filter_details filter_details; 913 914 filter_details.enable = 1; 915 filter_details.value = ((u64)high << 32) | low; 916 filter_details.hdr_sel = 0; 917 filter_details.protocol_type = filter_prot_type; 918 /* Mode: 0: MAC-address classification 1: protocol classification */ 919 filter_details.mode = filter_prot_type ? 1 : 0; 920 921 return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx, 922 &filter_details); 923 } 924 925 static int 926 qed_llh_remove_filter(struct qed_hwfn *p_hwfn, 927 struct qed_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx) 928 { 929 struct qed_llh_filter_details filter_details = {0}; 930 931 return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx, 932 &filter_details); 933 } 934 935 int qed_llh_add_mac_filter(struct qed_dev *cdev, 936 u8 ppfid, const u8 mac_addr[ETH_ALEN]) 937 { 938 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 939 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 940 union qed_llh_filter filter = {}; 941 u8 filter_idx, abs_ppfid = 0; 942 u32 high, low, ref_cnt; 943 int rc = 0; 944 945 if (!p_ptt) 946 return -EAGAIN; 947 948 if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits)) 949 goto out; 950 951 memcpy(filter.mac.addr, mac_addr, ETH_ALEN); 952 rc = qed_llh_shadow_add_filter(cdev, ppfid, 953 QED_LLH_FILTER_TYPE_MAC, 954 &filter, &filter_idx, &ref_cnt); 955 if (rc) 956 goto err; 957 958 /* Configure the LLH only in case of a new the filter */ 959 if (ref_cnt == 1) { 960 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 961 if (rc) 962 goto err; 963 964 high = mac_addr[1] | (mac_addr[0] << 8); 965 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) | 966 (mac_addr[2] << 24); 967 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx, 968 0, high, low); 969 if (rc) 970 goto err; 971 } 972 973 DP_VERBOSE(cdev, 974 QED_MSG_SP, 975 "LLH: Added MAC filter [%pM] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 976 mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt); 977 978 goto out; 979 980 err: DP_NOTICE(cdev, 981 "LLH: Failed to add MAC filter [%pM] to ppfid %hhd\n", 982 mac_addr, ppfid); 983 out: 984 qed_ptt_release(p_hwfn, p_ptt); 985 986 return rc; 987 } 988 989 static int 990 qed_llh_protocol_filter_stringify(struct qed_dev *cdev, 991 enum qed_llh_prot_filter_type_t type, 992 u16 source_port_or_eth_type, 993 u16 dest_port, u8 *str, size_t str_len) 994 { 995 switch (type) { 996 case QED_LLH_FILTER_ETHERTYPE: 997 snprintf(str, str_len, "Ethertype 0x%04x", 998 source_port_or_eth_type); 999 break; 1000 case QED_LLH_FILTER_TCP_SRC_PORT: 1001 snprintf(str, str_len, "TCP src port 0x%04x", 1002 source_port_or_eth_type); 1003 break; 1004 case QED_LLH_FILTER_UDP_SRC_PORT: 1005 snprintf(str, str_len, "UDP src port 0x%04x", 1006 source_port_or_eth_type); 1007 break; 1008 case QED_LLH_FILTER_TCP_DEST_PORT: 1009 snprintf(str, str_len, "TCP dst port 0x%04x", dest_port); 1010 break; 1011 case QED_LLH_FILTER_UDP_DEST_PORT: 1012 snprintf(str, str_len, "UDP dst port 0x%04x", dest_port); 1013 break; 1014 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 1015 snprintf(str, str_len, "TCP src/dst ports 0x%04x/0x%04x", 1016 source_port_or_eth_type, dest_port); 1017 break; 1018 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 1019 snprintf(str, str_len, "UDP src/dst ports 0x%04x/0x%04x", 1020 source_port_or_eth_type, dest_port); 1021 break; 1022 default: 1023 DP_NOTICE(cdev, 1024 "Non valid LLH protocol filter type %d\n", type); 1025 return -EINVAL; 1026 } 1027 1028 return 0; 1029 } 1030 1031 static int 1032 qed_llh_protocol_filter_to_hilo(struct qed_dev *cdev, 1033 enum qed_llh_prot_filter_type_t type, 1034 u16 source_port_or_eth_type, 1035 u16 dest_port, u32 *p_high, u32 *p_low) 1036 { 1037 *p_high = 0; 1038 *p_low = 0; 1039 1040 switch (type) { 1041 case QED_LLH_FILTER_ETHERTYPE: 1042 *p_high = source_port_or_eth_type; 1043 break; 1044 case QED_LLH_FILTER_TCP_SRC_PORT: 1045 case QED_LLH_FILTER_UDP_SRC_PORT: 1046 *p_low = source_port_or_eth_type << 16; 1047 break; 1048 case QED_LLH_FILTER_TCP_DEST_PORT: 1049 case QED_LLH_FILTER_UDP_DEST_PORT: 1050 *p_low = dest_port; 1051 break; 1052 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 1053 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 1054 *p_low = (source_port_or_eth_type << 16) | dest_port; 1055 break; 1056 default: 1057 DP_NOTICE(cdev, 1058 "Non valid LLH protocol filter type %d\n", type); 1059 return -EINVAL; 1060 } 1061 1062 return 0; 1063 } 1064 1065 int 1066 qed_llh_add_protocol_filter(struct qed_dev *cdev, 1067 u8 ppfid, 1068 enum qed_llh_prot_filter_type_t type, 1069 u16 source_port_or_eth_type, u16 dest_port) 1070 { 1071 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1072 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 1073 u8 filter_idx, abs_ppfid, str[32], type_bitmap; 1074 union qed_llh_filter filter = {}; 1075 u32 high, low, ref_cnt; 1076 int rc = 0; 1077 1078 if (!p_ptt) 1079 return -EAGAIN; 1080 1081 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits)) 1082 goto out; 1083 1084 rc = qed_llh_protocol_filter_stringify(cdev, type, 1085 source_port_or_eth_type, 1086 dest_port, str, sizeof(str)); 1087 if (rc) 1088 goto err; 1089 1090 filter.protocol.type = type; 1091 filter.protocol.source_port_or_eth_type = source_port_or_eth_type; 1092 filter.protocol.dest_port = dest_port; 1093 rc = qed_llh_shadow_add_filter(cdev, 1094 ppfid, 1095 QED_LLH_FILTER_TYPE_PROTOCOL, 1096 &filter, &filter_idx, &ref_cnt); 1097 if (rc) 1098 goto err; 1099 1100 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 1101 if (rc) 1102 goto err; 1103 1104 /* Configure the LLH only in case of a new the filter */ 1105 if (ref_cnt == 1) { 1106 rc = qed_llh_protocol_filter_to_hilo(cdev, type, 1107 source_port_or_eth_type, 1108 dest_port, &high, &low); 1109 if (rc) 1110 goto err; 1111 1112 type_bitmap = 0x1 << type; 1113 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, 1114 filter_idx, type_bitmap, high, low); 1115 if (rc) 1116 goto err; 1117 } 1118 1119 DP_VERBOSE(cdev, 1120 QED_MSG_SP, 1121 "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 1122 str, ppfid, abs_ppfid, filter_idx, ref_cnt); 1123 1124 goto out; 1125 1126 err: DP_NOTICE(p_hwfn, 1127 "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n", 1128 str, ppfid); 1129 out: 1130 qed_ptt_release(p_hwfn, p_ptt); 1131 1132 return rc; 1133 } 1134 1135 void qed_llh_remove_mac_filter(struct qed_dev *cdev, 1136 u8 ppfid, u8 mac_addr[ETH_ALEN]) 1137 { 1138 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1139 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 1140 union qed_llh_filter filter = {}; 1141 u8 filter_idx, abs_ppfid; 1142 int rc = 0; 1143 u32 ref_cnt; 1144 1145 if (!p_ptt) 1146 return; 1147 1148 if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits)) 1149 goto out; 1150 1151 if (QED_IS_NVMETCP_PERSONALITY(p_hwfn)) 1152 return; 1153 1154 ether_addr_copy(filter.mac.addr, mac_addr); 1155 rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx, 1156 &ref_cnt); 1157 if (rc) 1158 goto err; 1159 1160 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 1161 if (rc) 1162 goto err; 1163 1164 /* Remove from the LLH in case the filter is not in use */ 1165 if (!ref_cnt) { 1166 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid, 1167 filter_idx); 1168 if (rc) 1169 goto err; 1170 } 1171 1172 DP_VERBOSE(cdev, 1173 QED_MSG_SP, 1174 "LLH: Removed MAC filter [%pM] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 1175 mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt); 1176 1177 goto out; 1178 1179 err: DP_NOTICE(cdev, 1180 "LLH: Failed to remove MAC filter [%pM] from ppfid %hhd\n", 1181 mac_addr, ppfid); 1182 out: 1183 qed_ptt_release(p_hwfn, p_ptt); 1184 } 1185 1186 void qed_llh_remove_protocol_filter(struct qed_dev *cdev, 1187 u8 ppfid, 1188 enum qed_llh_prot_filter_type_t type, 1189 u16 source_port_or_eth_type, u16 dest_port) 1190 { 1191 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1192 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 1193 u8 filter_idx, abs_ppfid, str[32]; 1194 union qed_llh_filter filter = {}; 1195 int rc = 0; 1196 u32 ref_cnt; 1197 1198 if (!p_ptt) 1199 return; 1200 1201 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits)) 1202 goto out; 1203 1204 rc = qed_llh_protocol_filter_stringify(cdev, type, 1205 source_port_or_eth_type, 1206 dest_port, str, sizeof(str)); 1207 if (rc) 1208 goto err; 1209 1210 filter.protocol.type = type; 1211 filter.protocol.source_port_or_eth_type = source_port_or_eth_type; 1212 filter.protocol.dest_port = dest_port; 1213 rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx, 1214 &ref_cnt); 1215 if (rc) 1216 goto err; 1217 1218 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 1219 if (rc) 1220 goto err; 1221 1222 /* Remove from the LLH in case the filter is not in use */ 1223 if (!ref_cnt) { 1224 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid, 1225 filter_idx); 1226 if (rc) 1227 goto err; 1228 } 1229 1230 DP_VERBOSE(cdev, 1231 QED_MSG_SP, 1232 "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 1233 str, ppfid, abs_ppfid, filter_idx, ref_cnt); 1234 1235 goto out; 1236 1237 err: DP_NOTICE(cdev, 1238 "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n", 1239 str, ppfid); 1240 out: 1241 qed_ptt_release(p_hwfn, p_ptt); 1242 } 1243 1244 /******************************* NIG LLH - End ********************************/ 1245 1246 #define QED_MIN_DPIS (4) 1247 #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS) 1248 1249 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, 1250 struct qed_ptt *p_ptt, enum BAR_ID bar_id) 1251 { 1252 u32 bar_reg = (bar_id == BAR_ID_0 ? 1253 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 1254 u32 val; 1255 1256 if (IS_VF(p_hwfn->cdev)) 1257 return qed_vf_hw_bar_size(p_hwfn, bar_id); 1258 1259 val = qed_rd(p_hwfn, p_ptt, bar_reg); 1260 if (val) 1261 return 1 << (val + 15); 1262 1263 /* Old MFW initialized above registered only conditionally */ 1264 if (p_hwfn->cdev->num_hwfns > 1) { 1265 DP_INFO(p_hwfn, 1266 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 1267 return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 1268 } else { 1269 DP_INFO(p_hwfn, 1270 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 1271 return 512 * 1024; 1272 } 1273 } 1274 1275 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level) 1276 { 1277 u32 i; 1278 1279 cdev->dp_level = dp_level; 1280 cdev->dp_module = dp_module; 1281 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 1282 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1283 1284 p_hwfn->dp_level = dp_level; 1285 p_hwfn->dp_module = dp_module; 1286 } 1287 } 1288 1289 void qed_init_struct(struct qed_dev *cdev) 1290 { 1291 u8 i; 1292 1293 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 1294 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1295 1296 p_hwfn->cdev = cdev; 1297 p_hwfn->my_id = i; 1298 p_hwfn->b_active = false; 1299 1300 mutex_init(&p_hwfn->dmae_info.mutex); 1301 } 1302 1303 /* hwfn 0 is always active */ 1304 cdev->hwfns[0].b_active = true; 1305 1306 /* set the default cache alignment to 128 */ 1307 cdev->cache_shift = 7; 1308 } 1309 1310 static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 1311 { 1312 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1313 1314 kfree(qm_info->qm_pq_params); 1315 qm_info->qm_pq_params = NULL; 1316 kfree(qm_info->qm_vport_params); 1317 qm_info->qm_vport_params = NULL; 1318 kfree(qm_info->qm_port_params); 1319 qm_info->qm_port_params = NULL; 1320 kfree(qm_info->wfq_data); 1321 qm_info->wfq_data = NULL; 1322 } 1323 1324 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn) 1325 { 1326 kfree(p_hwfn->dbg_user_info); 1327 p_hwfn->dbg_user_info = NULL; 1328 } 1329 1330 void qed_resc_free(struct qed_dev *cdev) 1331 { 1332 struct qed_rdma_info *rdma_info; 1333 struct qed_hwfn *p_hwfn; 1334 int i; 1335 1336 if (IS_VF(cdev)) { 1337 for_each_hwfn(cdev, i) 1338 qed_l2_free(&cdev->hwfns[i]); 1339 return; 1340 } 1341 1342 kfree(cdev->fw_data); 1343 cdev->fw_data = NULL; 1344 1345 kfree(cdev->reset_stats); 1346 cdev->reset_stats = NULL; 1347 1348 qed_llh_free(cdev); 1349 1350 for_each_hwfn(cdev, i) { 1351 p_hwfn = cdev->hwfns + i; 1352 rdma_info = p_hwfn->p_rdma_info; 1353 1354 qed_cxt_mngr_free(p_hwfn); 1355 qed_qm_info_free(p_hwfn); 1356 qed_spq_free(p_hwfn); 1357 qed_eq_free(p_hwfn); 1358 qed_consq_free(p_hwfn); 1359 qed_int_free(p_hwfn); 1360 #ifdef CONFIG_QED_LL2 1361 qed_ll2_free(p_hwfn); 1362 #endif 1363 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 1364 qed_fcoe_free(p_hwfn); 1365 1366 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 1367 qed_iscsi_free(p_hwfn); 1368 qed_ooo_free(p_hwfn); 1369 } 1370 1371 if (p_hwfn->hw_info.personality == QED_PCI_NVMETCP) { 1372 qed_nvmetcp_free(p_hwfn); 1373 qed_ooo_free(p_hwfn); 1374 } 1375 1376 if (QED_IS_RDMA_PERSONALITY(p_hwfn) && rdma_info) { 1377 qed_spq_unregister_async_cb(p_hwfn, rdma_info->proto); 1378 qed_rdma_info_free(p_hwfn); 1379 } 1380 1381 qed_spq_unregister_async_cb(p_hwfn, PROTOCOLID_COMMON); 1382 qed_iov_free(p_hwfn); 1383 qed_l2_free(p_hwfn); 1384 qed_dmae_info_free(p_hwfn); 1385 qed_dcbx_info_free(p_hwfn); 1386 qed_dbg_user_data_free(p_hwfn); 1387 qed_fw_overlay_mem_free(p_hwfn, &p_hwfn->fw_overlay_mem); 1388 1389 /* Destroy doorbell recovery mechanism */ 1390 qed_db_recovery_teardown(p_hwfn); 1391 } 1392 } 1393 1394 /******************** QM initialization *******************/ 1395 #define ACTIVE_TCS_BMAP 0x9f 1396 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf 1397 1398 /* determines the physical queue flags for a given PF. */ 1399 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn) 1400 { 1401 u32 flags; 1402 1403 /* common flags */ 1404 flags = PQ_FLAGS_LB; 1405 1406 /* feature flags */ 1407 if (IS_QED_SRIOV(p_hwfn->cdev)) 1408 flags |= PQ_FLAGS_VFS; 1409 1410 /* protocol flags */ 1411 switch (p_hwfn->hw_info.personality) { 1412 case QED_PCI_ETH: 1413 flags |= PQ_FLAGS_MCOS; 1414 break; 1415 case QED_PCI_FCOE: 1416 flags |= PQ_FLAGS_OFLD; 1417 break; 1418 case QED_PCI_ISCSI: 1419 case QED_PCI_NVMETCP: 1420 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD; 1421 break; 1422 case QED_PCI_ETH_ROCE: 1423 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT; 1424 if (IS_QED_MULTI_TC_ROCE(p_hwfn)) 1425 flags |= PQ_FLAGS_MTC; 1426 break; 1427 case QED_PCI_ETH_IWARP: 1428 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO | 1429 PQ_FLAGS_OFLD; 1430 break; 1431 default: 1432 DP_ERR(p_hwfn, 1433 "unknown personality %d\n", p_hwfn->hw_info.personality); 1434 return 0; 1435 } 1436 1437 return flags; 1438 } 1439 1440 /* Getters for resource amounts necessary for qm initialization */ 1441 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn) 1442 { 1443 return p_hwfn->hw_info.num_hw_tc; 1444 } 1445 1446 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn) 1447 { 1448 return IS_QED_SRIOV(p_hwfn->cdev) ? 1449 p_hwfn->cdev->p_iov_info->total_vfs : 0; 1450 } 1451 1452 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn) 1453 { 1454 u32 pq_flags = qed_get_pq_flags(p_hwfn); 1455 1456 if (!(PQ_FLAGS_MTC & pq_flags)) 1457 return 1; 1458 1459 return qed_init_qm_get_num_tcs(p_hwfn); 1460 } 1461 1462 #define NUM_DEFAULT_RLS 1 1463 1464 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn) 1465 { 1466 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 1467 1468 /* num RLs can't exceed resource amount of rls or vports */ 1469 num_pf_rls = (u16)min_t(u32, RESC_NUM(p_hwfn, QED_RL), 1470 RESC_NUM(p_hwfn, QED_VPORT)); 1471 1472 /* Make sure after we reserve there's something left */ 1473 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) 1474 return 0; 1475 1476 /* subtract rls necessary for VFs and one default one for the PF */ 1477 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS; 1478 1479 return num_pf_rls; 1480 } 1481 1482 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn) 1483 { 1484 u32 pq_flags = qed_get_pq_flags(p_hwfn); 1485 1486 /* all pqs share the same vport, except for vfs and pf_rl pqs */ 1487 return (!!(PQ_FLAGS_RLS & pq_flags)) * 1488 qed_init_qm_get_num_pf_rls(p_hwfn) + 1489 (!!(PQ_FLAGS_VFS & pq_flags)) * 1490 qed_init_qm_get_num_vfs(p_hwfn) + 1; 1491 } 1492 1493 /* calc amount of PQs according to the requested flags */ 1494 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn) 1495 { 1496 u32 pq_flags = qed_get_pq_flags(p_hwfn); 1497 1498 return (!!(PQ_FLAGS_RLS & pq_flags)) * 1499 qed_init_qm_get_num_pf_rls(p_hwfn) + 1500 (!!(PQ_FLAGS_MCOS & pq_flags)) * 1501 qed_init_qm_get_num_tcs(p_hwfn) + 1502 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) + 1503 (!!(PQ_FLAGS_ACK & pq_flags)) + 1504 (!!(PQ_FLAGS_OFLD & pq_flags)) * 1505 qed_init_qm_get_num_mtc_tcs(p_hwfn) + 1506 (!!(PQ_FLAGS_LLT & pq_flags)) * 1507 qed_init_qm_get_num_mtc_tcs(p_hwfn) + 1508 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn); 1509 } 1510 1511 /* initialize the top level QM params */ 1512 static void qed_init_qm_params(struct qed_hwfn *p_hwfn) 1513 { 1514 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1515 bool four_port; 1516 1517 /* pq and vport bases for this PF */ 1518 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ); 1519 qm_info->start_vport = (u8)RESC_START(p_hwfn, QED_VPORT); 1520 1521 /* rate limiting and weighted fair queueing are always enabled */ 1522 qm_info->vport_rl_en = true; 1523 qm_info->vport_wfq_en = true; 1524 1525 /* TC config is different for AH 4 port */ 1526 four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2; 1527 1528 /* in AH 4 port we have fewer TCs per port */ 1529 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 : 1530 NUM_OF_PHYS_TCS; 1531 1532 /* unless MFW indicated otherwise, ooo_tc == 3 for 1533 * AH 4-port and 4 otherwise. 1534 */ 1535 if (!qm_info->ooo_tc) 1536 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC : 1537 DCBX_TCP_OOO_TC; 1538 } 1539 1540 /* initialize qm vport params */ 1541 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn) 1542 { 1543 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1544 u8 i; 1545 1546 /* all vports participate in weighted fair queueing */ 1547 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++) 1548 qm_info->qm_vport_params[i].wfq = 1; 1549 } 1550 1551 /* initialize qm port params */ 1552 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn) 1553 { 1554 /* Initialize qm port parameters */ 1555 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine; 1556 struct qed_dev *cdev = p_hwfn->cdev; 1557 1558 /* indicate how ooo and high pri traffic is dealt with */ 1559 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ? 1560 ACTIVE_TCS_BMAP_4PORT_K2 : 1561 ACTIVE_TCS_BMAP; 1562 1563 for (i = 0; i < num_ports; i++) { 1564 struct init_qm_port_params *p_qm_port = 1565 &p_hwfn->qm_info.qm_port_params[i]; 1566 u16 pbf_max_cmd_lines; 1567 1568 p_qm_port->active = 1; 1569 p_qm_port->active_phys_tcs = active_phys_tcs; 1570 pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(cdev); 1571 p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports; 1572 p_qm_port->num_btb_blocks = NUM_OF_BTB_BLOCKS(cdev) / num_ports; 1573 } 1574 } 1575 1576 /* Reset the params which must be reset for qm init. QM init may be called as 1577 * a result of flows other than driver load (e.g. dcbx renegotiation). Other 1578 * params may be affected by the init but would simply recalculate to the same 1579 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not 1580 * affected as these amounts stay the same. 1581 */ 1582 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn) 1583 { 1584 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1585 1586 qm_info->num_pqs = 0; 1587 qm_info->num_vports = 0; 1588 qm_info->num_pf_rls = 0; 1589 qm_info->num_vf_pqs = 0; 1590 qm_info->first_vf_pq = 0; 1591 qm_info->first_mcos_pq = 0; 1592 qm_info->first_rl_pq = 0; 1593 } 1594 1595 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn) 1596 { 1597 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1598 1599 qm_info->num_vports++; 1600 1601 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 1602 DP_ERR(p_hwfn, 1603 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 1604 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 1605 } 1606 1607 /* initialize a single pq and manage qm_info resources accounting. 1608 * The pq_init_flags param determines whether the PQ is rate limited 1609 * (for VF or PF) and whether a new vport is allocated to the pq or not 1610 * (i.e. vport will be shared). 1611 */ 1612 1613 /* flags for pq init */ 1614 #define PQ_INIT_SHARE_VPORT BIT(0) 1615 #define PQ_INIT_PF_RL BIT(1) 1616 #define PQ_INIT_VF_RL BIT(2) 1617 1618 /* defines for pq init */ 1619 #define PQ_INIT_DEFAULT_WRR_GROUP 1 1620 #define PQ_INIT_DEFAULT_TC 0 1621 1622 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc) 1623 { 1624 p_info->offload_tc = tc; 1625 p_info->offload_tc_set = true; 1626 } 1627 1628 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn) 1629 { 1630 return p_hwfn->hw_info.offload_tc_set; 1631 } 1632 1633 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn) 1634 { 1635 if (qed_is_offload_tc_set(p_hwfn)) 1636 return p_hwfn->hw_info.offload_tc; 1637 1638 return PQ_INIT_DEFAULT_TC; 1639 } 1640 1641 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn, 1642 struct qed_qm_info *qm_info, 1643 u8 tc, u32 pq_init_flags) 1644 { 1645 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn); 1646 1647 if (pq_idx > max_pq) 1648 DP_ERR(p_hwfn, 1649 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq); 1650 1651 /* init pq params */ 1652 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id; 1653 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport + 1654 qm_info->num_vports; 1655 qm_info->qm_pq_params[pq_idx].tc_id = tc; 1656 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP; 1657 qm_info->qm_pq_params[pq_idx].rl_valid = 1658 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL); 1659 1660 /* qm params accounting */ 1661 qm_info->num_pqs++; 1662 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT)) 1663 qm_info->num_vports++; 1664 1665 if (pq_init_flags & PQ_INIT_PF_RL) 1666 qm_info->num_pf_rls++; 1667 1668 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 1669 DP_ERR(p_hwfn, 1670 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 1671 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 1672 1673 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn)) 1674 DP_ERR(p_hwfn, 1675 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n", 1676 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn)); 1677 } 1678 1679 /* get pq index according to PQ_FLAGS */ 1680 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn, 1681 unsigned long pq_flags) 1682 { 1683 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1684 1685 /* Can't have multiple flags set here */ 1686 if (bitmap_weight(&pq_flags, 1687 sizeof(pq_flags) * BITS_PER_BYTE) > 1) { 1688 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags); 1689 goto err; 1690 } 1691 1692 if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) { 1693 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags); 1694 goto err; 1695 } 1696 1697 switch (pq_flags) { 1698 case PQ_FLAGS_RLS: 1699 return &qm_info->first_rl_pq; 1700 case PQ_FLAGS_MCOS: 1701 return &qm_info->first_mcos_pq; 1702 case PQ_FLAGS_LB: 1703 return &qm_info->pure_lb_pq; 1704 case PQ_FLAGS_OOO: 1705 return &qm_info->ooo_pq; 1706 case PQ_FLAGS_ACK: 1707 return &qm_info->pure_ack_pq; 1708 case PQ_FLAGS_OFLD: 1709 return &qm_info->first_ofld_pq; 1710 case PQ_FLAGS_LLT: 1711 return &qm_info->first_llt_pq; 1712 case PQ_FLAGS_VFS: 1713 return &qm_info->first_vf_pq; 1714 default: 1715 goto err; 1716 } 1717 1718 err: 1719 return &qm_info->start_pq; 1720 } 1721 1722 /* save pq index in qm info */ 1723 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn, 1724 u32 pq_flags, u16 pq_val) 1725 { 1726 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 1727 1728 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val; 1729 } 1730 1731 /* get tx pq index, with the PQ TX base already set (ready for context init) */ 1732 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags) 1733 { 1734 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 1735 1736 return *base_pq_idx + CM_TX_PQ_BASE; 1737 } 1738 1739 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc) 1740 { 1741 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn); 1742 1743 if (max_tc == 0) { 1744 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n", 1745 PQ_FLAGS_MCOS); 1746 return p_hwfn->qm_info.start_pq; 1747 } 1748 1749 if (tc > max_tc) 1750 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc); 1751 1752 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc); 1753 } 1754 1755 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf) 1756 { 1757 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn); 1758 1759 if (max_vf == 0) { 1760 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n", 1761 PQ_FLAGS_VFS); 1762 return p_hwfn->qm_info.start_pq; 1763 } 1764 1765 if (vf > max_vf) 1766 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf); 1767 1768 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf); 1769 } 1770 1771 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc) 1772 { 1773 u16 first_ofld_pq, pq_offset; 1774 1775 first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 1776 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ? 1777 tc : PQ_INIT_DEFAULT_TC; 1778 1779 return first_ofld_pq + pq_offset; 1780 } 1781 1782 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc) 1783 { 1784 u16 first_llt_pq, pq_offset; 1785 1786 first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT); 1787 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ? 1788 tc : PQ_INIT_DEFAULT_TC; 1789 1790 return first_llt_pq + pq_offset; 1791 } 1792 1793 /* Functions for creating specific types of pqs */ 1794 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn) 1795 { 1796 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1797 1798 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB)) 1799 return; 1800 1801 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs); 1802 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT); 1803 } 1804 1805 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn) 1806 { 1807 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1808 1809 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO)) 1810 return; 1811 1812 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs); 1813 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT); 1814 } 1815 1816 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn) 1817 { 1818 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1819 1820 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK)) 1821 return; 1822 1823 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs); 1824 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn), 1825 PQ_INIT_SHARE_VPORT); 1826 } 1827 1828 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn) 1829 { 1830 u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn); 1831 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1832 u8 tc; 1833 1834 /* override pq's TC if offload TC is set */ 1835 for (tc = 0; tc < num_tcs; tc++) 1836 qed_init_qm_pq(p_hwfn, qm_info, 1837 qed_is_offload_tc_set(p_hwfn) ? 1838 p_hwfn->hw_info.offload_tc : tc, 1839 PQ_INIT_SHARE_VPORT); 1840 } 1841 1842 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn) 1843 { 1844 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1845 1846 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD)) 1847 return; 1848 1849 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs); 1850 qed_init_qm_mtc_pqs(p_hwfn); 1851 } 1852 1853 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn) 1854 { 1855 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1856 1857 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT)) 1858 return; 1859 1860 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs); 1861 qed_init_qm_mtc_pqs(p_hwfn); 1862 } 1863 1864 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn) 1865 { 1866 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1867 u8 tc_idx; 1868 1869 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS)) 1870 return; 1871 1872 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs); 1873 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++) 1874 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT); 1875 } 1876 1877 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn) 1878 { 1879 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1880 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 1881 1882 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS)) 1883 return; 1884 1885 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs); 1886 qm_info->num_vf_pqs = num_vfs; 1887 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) 1888 qed_init_qm_pq(p_hwfn, 1889 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL); 1890 } 1891 1892 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn) 1893 { 1894 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn); 1895 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1896 1897 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS)) 1898 return; 1899 1900 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs); 1901 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++) 1902 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn), 1903 PQ_INIT_PF_RL); 1904 } 1905 1906 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn) 1907 { 1908 /* rate limited pqs, must come first (FW assumption) */ 1909 qed_init_qm_rl_pqs(p_hwfn); 1910 1911 /* pqs for multi cos */ 1912 qed_init_qm_mcos_pqs(p_hwfn); 1913 1914 /* pure loopback pq */ 1915 qed_init_qm_lb_pq(p_hwfn); 1916 1917 /* out of order pq */ 1918 qed_init_qm_ooo_pq(p_hwfn); 1919 1920 /* pure ack pq */ 1921 qed_init_qm_pure_ack_pq(p_hwfn); 1922 1923 /* pq for offloaded protocol */ 1924 qed_init_qm_offload_pq(p_hwfn); 1925 1926 /* low latency pq */ 1927 qed_init_qm_low_latency_pq(p_hwfn); 1928 1929 /* done sharing vports */ 1930 qed_init_qm_advance_vport(p_hwfn); 1931 1932 /* pqs for vfs */ 1933 qed_init_qm_vf_pqs(p_hwfn); 1934 } 1935 1936 /* compare values of getters against resources amounts */ 1937 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn) 1938 { 1939 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) { 1940 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n"); 1941 return -EINVAL; 1942 } 1943 1944 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ)) 1945 return 0; 1946 1947 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) { 1948 p_hwfn->hw_info.multi_tc_roce_en = false; 1949 DP_NOTICE(p_hwfn, 1950 "multi-tc roce was disabled to reduce requested amount of pqs\n"); 1951 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ)) 1952 return 0; 1953 } 1954 1955 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n"); 1956 return -EINVAL; 1957 } 1958 1959 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn) 1960 { 1961 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1962 struct init_qm_vport_params *vport; 1963 struct init_qm_port_params *port; 1964 struct init_qm_pq_params *pq; 1965 int i, tc; 1966 1967 /* top level params */ 1968 DP_VERBOSE(p_hwfn, 1969 NETIF_MSG_HW, 1970 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n", 1971 qm_info->start_pq, 1972 qm_info->start_vport, 1973 qm_info->pure_lb_pq, 1974 qm_info->first_ofld_pq, 1975 qm_info->first_llt_pq, 1976 qm_info->pure_ack_pq); 1977 DP_VERBOSE(p_hwfn, 1978 NETIF_MSG_HW, 1979 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n", 1980 qm_info->ooo_pq, 1981 qm_info->first_vf_pq, 1982 qm_info->num_pqs, 1983 qm_info->num_vf_pqs, 1984 qm_info->num_vports, qm_info->max_phys_tcs_per_port); 1985 DP_VERBOSE(p_hwfn, 1986 NETIF_MSG_HW, 1987 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n", 1988 qm_info->pf_rl_en, 1989 qm_info->pf_wfq_en, 1990 qm_info->vport_rl_en, 1991 qm_info->vport_wfq_en, 1992 qm_info->pf_wfq, 1993 qm_info->pf_rl, 1994 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn)); 1995 1996 /* port table */ 1997 for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) { 1998 port = &(qm_info->qm_port_params[i]); 1999 DP_VERBOSE(p_hwfn, 2000 NETIF_MSG_HW, 2001 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n", 2002 i, 2003 port->active, 2004 port->active_phys_tcs, 2005 port->num_pbf_cmd_lines, 2006 port->num_btb_blocks, port->reserved); 2007 } 2008 2009 /* vport table */ 2010 for (i = 0; i < qm_info->num_vports; i++) { 2011 vport = &(qm_info->qm_vport_params[i]); 2012 DP_VERBOSE(p_hwfn, 2013 NETIF_MSG_HW, 2014 "vport idx %d, wfq %d, first_tx_pq_id [ ", 2015 qm_info->start_vport + i, vport->wfq); 2016 for (tc = 0; tc < NUM_OF_TCS; tc++) 2017 DP_VERBOSE(p_hwfn, 2018 NETIF_MSG_HW, 2019 "%d ", vport->first_tx_pq_id[tc]); 2020 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n"); 2021 } 2022 2023 /* pq table */ 2024 for (i = 0; i < qm_info->num_pqs; i++) { 2025 pq = &(qm_info->qm_pq_params[i]); 2026 DP_VERBOSE(p_hwfn, 2027 NETIF_MSG_HW, 2028 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d rl_id %d\n", 2029 qm_info->start_pq + i, 2030 pq->port_id, 2031 pq->vport_id, 2032 pq->tc_id, pq->wrr_group, pq->rl_valid, pq->rl_id); 2033 } 2034 } 2035 2036 static void qed_init_qm_info(struct qed_hwfn *p_hwfn) 2037 { 2038 /* reset params required for init run */ 2039 qed_init_qm_reset_params(p_hwfn); 2040 2041 /* init QM top level params */ 2042 qed_init_qm_params(p_hwfn); 2043 2044 /* init QM port params */ 2045 qed_init_qm_port_params(p_hwfn); 2046 2047 /* init QM vport params */ 2048 qed_init_qm_vport_params(p_hwfn); 2049 2050 /* init QM physical queue params */ 2051 qed_init_qm_pq_params(p_hwfn); 2052 2053 /* display all that init */ 2054 qed_dp_init_qm_params(p_hwfn); 2055 } 2056 2057 /* This function reconfigures the QM pf on the fly. 2058 * For this purpose we: 2059 * 1. reconfigure the QM database 2060 * 2. set new values to runtime array 2061 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 2062 * 4. activate init tool in QM_PF stage 2063 * 5. send an sdm_qm_cmd through rbc interface to release the QM 2064 */ 2065 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2066 { 2067 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 2068 bool b_rc; 2069 int rc; 2070 2071 /* initialize qed's qm data structure */ 2072 qed_init_qm_info(p_hwfn); 2073 2074 /* stop PF's qm queues */ 2075 spin_lock_bh(&qm_lock); 2076 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 2077 qm_info->start_pq, qm_info->num_pqs); 2078 spin_unlock_bh(&qm_lock); 2079 if (!b_rc) 2080 return -EINVAL; 2081 2082 /* prepare QM portion of runtime array */ 2083 qed_qm_init_pf(p_hwfn, p_ptt, false); 2084 2085 /* activate init tool on runtime array */ 2086 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 2087 p_hwfn->hw_info.hw_mode); 2088 if (rc) 2089 return rc; 2090 2091 /* start PF's qm queues */ 2092 spin_lock_bh(&qm_lock); 2093 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 2094 qm_info->start_pq, qm_info->num_pqs); 2095 spin_unlock_bh(&qm_lock); 2096 if (!b_rc) 2097 return -EINVAL; 2098 2099 return 0; 2100 } 2101 2102 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn) 2103 { 2104 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 2105 int rc; 2106 2107 rc = qed_init_qm_sanity(p_hwfn); 2108 if (rc) 2109 goto alloc_err; 2110 2111 qm_info->qm_pq_params = kzalloc_objs(*qm_info->qm_pq_params, 2112 qed_init_qm_get_num_pqs(p_hwfn)); 2113 if (!qm_info->qm_pq_params) 2114 goto alloc_err; 2115 2116 qm_info->qm_vport_params = kzalloc_objs(*qm_info->qm_vport_params, 2117 qed_init_qm_get_num_vports(p_hwfn)); 2118 if (!qm_info->qm_vport_params) 2119 goto alloc_err; 2120 2121 qm_info->qm_port_params = kzalloc_objs(*qm_info->qm_port_params, 2122 p_hwfn->cdev->num_ports_in_engine); 2123 if (!qm_info->qm_port_params) 2124 goto alloc_err; 2125 2126 qm_info->wfq_data = kzalloc_objs(*qm_info->wfq_data, 2127 qed_init_qm_get_num_vports(p_hwfn)); 2128 if (!qm_info->wfq_data) 2129 goto alloc_err; 2130 2131 return 0; 2132 2133 alloc_err: 2134 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); 2135 qed_qm_info_free(p_hwfn); 2136 return -ENOMEM; 2137 } 2138 2139 int qed_resc_alloc(struct qed_dev *cdev) 2140 { 2141 u32 rdma_tasks, excess_tasks; 2142 u32 line_count; 2143 int i, rc = 0; 2144 2145 if (IS_VF(cdev)) { 2146 for_each_hwfn(cdev, i) { 2147 rc = qed_l2_alloc(&cdev->hwfns[i]); 2148 if (rc) 2149 return rc; 2150 } 2151 return rc; 2152 } 2153 2154 cdev->fw_data = kzalloc_obj(*cdev->fw_data); 2155 if (!cdev->fw_data) 2156 return -ENOMEM; 2157 2158 for_each_hwfn(cdev, i) { 2159 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2160 u32 n_eqes, num_cons; 2161 2162 /* Initialize the doorbell recovery mechanism */ 2163 rc = qed_db_recovery_setup(p_hwfn); 2164 if (rc) 2165 goto alloc_err; 2166 2167 /* First allocate the context manager structure */ 2168 rc = qed_cxt_mngr_alloc(p_hwfn); 2169 if (rc) 2170 goto alloc_err; 2171 2172 /* Set the HW cid/tid numbers (in the contest manager) 2173 * Must be done prior to any further computations. 2174 */ 2175 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS); 2176 if (rc) 2177 goto alloc_err; 2178 2179 rc = qed_alloc_qm_data(p_hwfn); 2180 if (rc) 2181 goto alloc_err; 2182 2183 /* init qm info */ 2184 qed_init_qm_info(p_hwfn); 2185 2186 /* Compute the ILT client partition */ 2187 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 2188 if (rc) { 2189 DP_NOTICE(p_hwfn, 2190 "too many ILT lines; re-computing with less lines\n"); 2191 /* In case there are not enough ILT lines we reduce the 2192 * number of RDMA tasks and re-compute. 2193 */ 2194 excess_tasks = 2195 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count); 2196 if (!excess_tasks) 2197 goto alloc_err; 2198 2199 rdma_tasks = RDMA_MAX_TIDS - excess_tasks; 2200 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks); 2201 if (rc) 2202 goto alloc_err; 2203 2204 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 2205 if (rc) { 2206 DP_ERR(p_hwfn, 2207 "failed ILT compute. Requested too many lines: %u\n", 2208 line_count); 2209 2210 goto alloc_err; 2211 } 2212 } 2213 2214 /* CID map / ILT shadow table / T2 2215 * The table sizes are determined by the computations above 2216 */ 2217 rc = qed_cxt_tables_alloc(p_hwfn); 2218 if (rc) 2219 goto alloc_err; 2220 2221 /* SPQ, must follow ILT because initializes SPQ context */ 2222 rc = qed_spq_alloc(p_hwfn); 2223 if (rc) 2224 goto alloc_err; 2225 2226 /* SP status block allocation */ 2227 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 2228 RESERVED_PTT_DPC); 2229 2230 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 2231 if (rc) 2232 goto alloc_err; 2233 2234 rc = qed_iov_alloc(p_hwfn); 2235 if (rc) 2236 goto alloc_err; 2237 2238 /* EQ */ 2239 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 2240 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) { 2241 u32 n_srq = qed_cxt_get_total_srq_count(p_hwfn); 2242 enum protocol_type rdma_proto; 2243 2244 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) 2245 rdma_proto = PROTOCOLID_ROCE; 2246 else 2247 rdma_proto = PROTOCOLID_IWARP; 2248 2249 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 2250 rdma_proto, 2251 NULL) * 2; 2252 /* EQ should be able to get events from all SRQ's 2253 * at the same time 2254 */ 2255 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB + n_srq; 2256 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI || 2257 p_hwfn->hw_info.personality == QED_PCI_NVMETCP) { 2258 num_cons = 2259 qed_cxt_get_proto_cid_count(p_hwfn, 2260 PROTOCOLID_TCP_ULP, 2261 NULL); 2262 n_eqes += 2 * num_cons; 2263 } 2264 2265 if (n_eqes > 0xFFFF) { 2266 DP_ERR(p_hwfn, 2267 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 2268 n_eqes, 0xFFFF); 2269 goto alloc_no_mem; 2270 } 2271 2272 rc = qed_eq_alloc(p_hwfn, (u16)n_eqes); 2273 if (rc) 2274 goto alloc_err; 2275 2276 rc = qed_consq_alloc(p_hwfn); 2277 if (rc) 2278 goto alloc_err; 2279 2280 rc = qed_l2_alloc(p_hwfn); 2281 if (rc) 2282 goto alloc_err; 2283 2284 #ifdef CONFIG_QED_LL2 2285 if (p_hwfn->using_ll2) { 2286 rc = qed_ll2_alloc(p_hwfn); 2287 if (rc) 2288 goto alloc_err; 2289 } 2290 #endif 2291 2292 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 2293 rc = qed_fcoe_alloc(p_hwfn); 2294 if (rc) 2295 goto alloc_err; 2296 } 2297 2298 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 2299 rc = qed_iscsi_alloc(p_hwfn); 2300 if (rc) 2301 goto alloc_err; 2302 rc = qed_ooo_alloc(p_hwfn); 2303 if (rc) 2304 goto alloc_err; 2305 } 2306 2307 if (p_hwfn->hw_info.personality == QED_PCI_NVMETCP) { 2308 rc = qed_nvmetcp_alloc(p_hwfn); 2309 if (rc) 2310 goto alloc_err; 2311 rc = qed_ooo_alloc(p_hwfn); 2312 if (rc) 2313 goto alloc_err; 2314 } 2315 2316 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) { 2317 rc = qed_rdma_info_alloc(p_hwfn); 2318 if (rc) 2319 goto alloc_err; 2320 } 2321 2322 /* DMA info initialization */ 2323 rc = qed_dmae_info_alloc(p_hwfn); 2324 if (rc) 2325 goto alloc_err; 2326 2327 /* DCBX initialization */ 2328 rc = qed_dcbx_info_alloc(p_hwfn); 2329 if (rc) 2330 goto alloc_err; 2331 2332 rc = qed_dbg_alloc_user_data(p_hwfn, &p_hwfn->dbg_user_info); 2333 if (rc) 2334 goto alloc_err; 2335 } 2336 2337 rc = qed_llh_alloc(cdev); 2338 if (rc) { 2339 DP_NOTICE(cdev, 2340 "Failed to allocate memory for the llh_info structure\n"); 2341 goto alloc_err; 2342 } 2343 2344 cdev->reset_stats = kzalloc_obj(*cdev->reset_stats); 2345 if (!cdev->reset_stats) 2346 goto alloc_no_mem; 2347 2348 return 0; 2349 2350 alloc_no_mem: 2351 rc = -ENOMEM; 2352 alloc_err: 2353 qed_resc_free(cdev); 2354 return rc; 2355 } 2356 2357 static int qed_fw_err_handler(struct qed_hwfn *p_hwfn, 2358 u8 opcode, 2359 u16 echo, 2360 union event_ring_data *data, u8 fw_return_code) 2361 { 2362 if (fw_return_code != COMMON_ERR_CODE_ERROR) 2363 goto eqe_unexpected; 2364 2365 if (data->err_data.recovery_scope == ERR_SCOPE_FUNC && 2366 le16_to_cpu(data->err_data.entity_id) >= MAX_NUM_PFS) { 2367 qed_sriov_vfpf_malicious(p_hwfn, &data->err_data); 2368 return 0; 2369 } 2370 2371 eqe_unexpected: 2372 DP_ERR(p_hwfn, 2373 "Skipping unexpected eqe 0x%02x, FW return code 0x%x, echo 0x%x\n", 2374 opcode, fw_return_code, echo); 2375 return -EINVAL; 2376 } 2377 2378 static int qed_common_eqe_event(struct qed_hwfn *p_hwfn, 2379 u8 opcode, 2380 __le16 echo, 2381 union event_ring_data *data, 2382 u8 fw_return_code) 2383 { 2384 switch (opcode) { 2385 case COMMON_EVENT_VF_PF_CHANNEL: 2386 case COMMON_EVENT_VF_FLR: 2387 return qed_sriov_eqe_event(p_hwfn, opcode, echo, data, 2388 fw_return_code); 2389 case COMMON_EVENT_FW_ERROR: 2390 return qed_fw_err_handler(p_hwfn, opcode, 2391 le16_to_cpu(echo), data, 2392 fw_return_code); 2393 default: 2394 DP_INFO(p_hwfn->cdev, "Unknown eqe event 0x%02x, echo 0x%x\n", 2395 opcode, echo); 2396 return -EINVAL; 2397 } 2398 } 2399 2400 void qed_resc_setup(struct qed_dev *cdev) 2401 { 2402 int i; 2403 2404 if (IS_VF(cdev)) { 2405 for_each_hwfn(cdev, i) 2406 qed_l2_setup(&cdev->hwfns[i]); 2407 return; 2408 } 2409 2410 for_each_hwfn(cdev, i) { 2411 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2412 2413 qed_cxt_mngr_setup(p_hwfn); 2414 qed_spq_setup(p_hwfn); 2415 qed_eq_setup(p_hwfn); 2416 qed_consq_setup(p_hwfn); 2417 2418 /* Read shadow of current MFW mailbox */ 2419 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 2420 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 2421 p_hwfn->mcp_info->mfw_mb_cur, 2422 p_hwfn->mcp_info->mfw_mb_length); 2423 2424 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 2425 2426 qed_l2_setup(p_hwfn); 2427 qed_iov_setup(p_hwfn); 2428 qed_spq_register_async_cb(p_hwfn, PROTOCOLID_COMMON, 2429 qed_common_eqe_event); 2430 #ifdef CONFIG_QED_LL2 2431 if (p_hwfn->using_ll2) 2432 qed_ll2_setup(p_hwfn); 2433 #endif 2434 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 2435 qed_fcoe_setup(p_hwfn); 2436 2437 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 2438 qed_iscsi_setup(p_hwfn); 2439 qed_ooo_setup(p_hwfn); 2440 } 2441 2442 if (p_hwfn->hw_info.personality == QED_PCI_NVMETCP) { 2443 qed_nvmetcp_setup(p_hwfn); 2444 qed_ooo_setup(p_hwfn); 2445 } 2446 } 2447 } 2448 2449 #define FINAL_CLEANUP_POLL_CNT (100) 2450 #define FINAL_CLEANUP_POLL_TIME (10) 2451 int qed_final_cleanup(struct qed_hwfn *p_hwfn, 2452 struct qed_ptt *p_ptt, u16 id, bool is_vf) 2453 { 2454 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 2455 int rc = -EBUSY; 2456 2457 addr = GET_GTT_REG_ADDR(GTT_BAR0_MAP_REG_USDM_RAM, 2458 USTORM_FLR_FINAL_ACK, p_hwfn->rel_pf_id); 2459 if (is_vf) 2460 id += 0x10; 2461 2462 command |= X_FINAL_CLEANUP_AGG_INT << 2463 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 2464 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 2465 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 2466 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 2467 2468 /* Make sure notification is not set before initiating final cleanup */ 2469 if (REG_RD(p_hwfn, addr)) { 2470 DP_NOTICE(p_hwfn, 2471 "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 2472 REG_WR(p_hwfn, addr, 0); 2473 } 2474 2475 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 2476 "Sending final cleanup for PFVF[%d] [Command %08x]\n", 2477 id, command); 2478 2479 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 2480 2481 /* Poll until completion */ 2482 while (!REG_RD(p_hwfn, addr) && count--) 2483 msleep(FINAL_CLEANUP_POLL_TIME); 2484 2485 if (REG_RD(p_hwfn, addr)) 2486 rc = 0; 2487 else 2488 DP_NOTICE(p_hwfn, 2489 "Failed to receive FW final cleanup notification\n"); 2490 2491 /* Cleanup afterwards */ 2492 REG_WR(p_hwfn, addr, 0); 2493 2494 return rc; 2495 } 2496 2497 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 2498 { 2499 int hw_mode = 0; 2500 2501 if (QED_IS_BB_B0(p_hwfn->cdev)) { 2502 hw_mode |= 1 << MODE_BB; 2503 } else if (QED_IS_AH(p_hwfn->cdev)) { 2504 hw_mode |= 1 << MODE_K2; 2505 } else { 2506 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n", 2507 p_hwfn->cdev->type); 2508 return -EINVAL; 2509 } 2510 2511 switch (p_hwfn->cdev->num_ports_in_engine) { 2512 case 1: 2513 hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 2514 break; 2515 case 2: 2516 hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 2517 break; 2518 case 4: 2519 hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 2520 break; 2521 default: 2522 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 2523 p_hwfn->cdev->num_ports_in_engine); 2524 return -EINVAL; 2525 } 2526 2527 if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) 2528 hw_mode |= 1 << MODE_MF_SD; 2529 else 2530 hw_mode |= 1 << MODE_MF_SI; 2531 2532 hw_mode |= 1 << MODE_ASIC; 2533 2534 if (p_hwfn->cdev->num_hwfns > 1) 2535 hw_mode |= 1 << MODE_100G; 2536 2537 p_hwfn->hw_info.hw_mode = hw_mode; 2538 2539 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 2540 "Configuring function for hw_mode: 0x%08x\n", 2541 p_hwfn->hw_info.hw_mode); 2542 2543 return 0; 2544 } 2545 2546 /* Init run time data for all PFs on an engine. */ 2547 static void qed_init_cau_rt_data(struct qed_dev *cdev) 2548 { 2549 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 2550 int i, igu_sb_id; 2551 2552 for_each_hwfn(cdev, i) { 2553 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2554 struct qed_igu_info *p_igu_info; 2555 struct qed_igu_block *p_block; 2556 struct cau_sb_entry sb_entry; 2557 2558 p_igu_info = p_hwfn->hw_info.p_igu_info; 2559 2560 for (igu_sb_id = 0; 2561 igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) { 2562 p_block = &p_igu_info->entry[igu_sb_id]; 2563 2564 if (!p_block->is_pf) 2565 continue; 2566 2567 qed_init_cau_sb_entry(p_hwfn, &sb_entry, 2568 p_block->function_id, 0, 0); 2569 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2, 2570 sb_entry); 2571 } 2572 } 2573 } 2574 2575 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn, 2576 struct qed_ptt *p_ptt) 2577 { 2578 u32 val, wr_mbs, cache_line_size; 2579 2580 val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0); 2581 switch (val) { 2582 case 0: 2583 wr_mbs = 128; 2584 break; 2585 case 1: 2586 wr_mbs = 256; 2587 break; 2588 case 2: 2589 wr_mbs = 512; 2590 break; 2591 default: 2592 DP_INFO(p_hwfn, 2593 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 2594 val); 2595 return; 2596 } 2597 2598 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs); 2599 switch (cache_line_size) { 2600 case 32: 2601 val = 0; 2602 break; 2603 case 64: 2604 val = 1; 2605 break; 2606 case 128: 2607 val = 2; 2608 break; 2609 case 256: 2610 val = 3; 2611 break; 2612 default: 2613 DP_INFO(p_hwfn, 2614 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 2615 cache_line_size); 2616 } 2617 2618 if (wr_mbs < L1_CACHE_BYTES) 2619 DP_INFO(p_hwfn, 2620 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n", 2621 L1_CACHE_BYTES, wr_mbs); 2622 2623 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val); 2624 if (val > 0) { 2625 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val); 2626 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val); 2627 } 2628 } 2629 2630 static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 2631 struct qed_ptt *p_ptt, int hw_mode) 2632 { 2633 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 2634 struct qed_qm_common_rt_init_params *params; 2635 struct qed_dev *cdev = p_hwfn->cdev; 2636 u8 vf_id, max_num_vfs; 2637 u16 num_pfs, pf_id; 2638 u32 concrete_fid; 2639 int rc = 0; 2640 2641 params = kzalloc_obj(*params); 2642 if (!params) { 2643 DP_NOTICE(p_hwfn->cdev, 2644 "Failed to allocate common init params\n"); 2645 2646 return -ENOMEM; 2647 } 2648 2649 qed_init_cau_rt_data(cdev); 2650 2651 /* Program GTT windows */ 2652 qed_gtt_init(p_hwfn); 2653 2654 if (p_hwfn->mcp_info) { 2655 if (p_hwfn->mcp_info->func_info.bandwidth_max) 2656 qm_info->pf_rl_en = true; 2657 if (p_hwfn->mcp_info->func_info.bandwidth_min) 2658 qm_info->pf_wfq_en = true; 2659 } 2660 2661 params->max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine; 2662 params->max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 2663 params->pf_rl_en = qm_info->pf_rl_en; 2664 params->pf_wfq_en = qm_info->pf_wfq_en; 2665 params->global_rl_en = qm_info->vport_rl_en; 2666 params->vport_wfq_en = qm_info->vport_wfq_en; 2667 params->port_params = qm_info->qm_port_params; 2668 2669 qed_qm_common_rt_init(p_hwfn, params); 2670 2671 qed_cxt_hw_init_common(p_hwfn); 2672 2673 qed_init_cache_line_size(p_hwfn, p_ptt); 2674 2675 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 2676 if (rc) 2677 goto out; 2678 2679 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 2680 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 2681 2682 if (QED_IS_BB(p_hwfn->cdev)) { 2683 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 2684 for (pf_id = 0; pf_id < num_pfs; pf_id++) { 2685 qed_fid_pretend(p_hwfn, p_ptt, pf_id); 2686 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 2687 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 2688 } 2689 /* pretend to original PF */ 2690 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 2691 } 2692 2693 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB; 2694 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) { 2695 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 2696 qed_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid); 2697 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 2698 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 2699 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 2700 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 2701 } 2702 /* pretend to original PF */ 2703 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 2704 2705 out: 2706 kfree(params); 2707 2708 return rc; 2709 } 2710 2711 static int 2712 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn, 2713 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 2714 { 2715 u32 dpi_bit_shift, dpi_count, dpi_page_size; 2716 u32 min_dpis; 2717 u32 n_wids; 2718 2719 /* Calculate DPI size */ 2720 n_wids = max_t(u32, QED_MIN_WIDS, n_cpus); 2721 dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids); 2722 dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1); 2723 dpi_bit_shift = ilog2(dpi_page_size / 4096); 2724 dpi_count = pwm_region_size / dpi_page_size; 2725 2726 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 2727 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis); 2728 2729 p_hwfn->dpi_size = dpi_page_size; 2730 p_hwfn->dpi_count = dpi_count; 2731 2732 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 2733 2734 if (dpi_count < min_dpis) 2735 return -EINVAL; 2736 2737 return 0; 2738 } 2739 2740 enum QED_ROCE_EDPM_MODE { 2741 QED_ROCE_EDPM_MODE_ENABLE = 0, 2742 QED_ROCE_EDPM_MODE_FORCE_ON = 1, 2743 QED_ROCE_EDPM_MODE_DISABLE = 2, 2744 }; 2745 2746 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn) 2747 { 2748 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) 2749 return false; 2750 2751 return true; 2752 } 2753 2754 static int 2755 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2756 { 2757 u32 pwm_regsize, norm_regsize; 2758 u32 non_pwm_conn, min_addr_reg1; 2759 u32 db_bar_size, n_cpus = 1; 2760 u32 roce_edpm_mode; 2761 u32 pf_dems_shift; 2762 int rc = 0; 2763 u8 cond; 2764 2765 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1); 2766 if (p_hwfn->cdev->num_hwfns > 1) 2767 db_bar_size /= 2; 2768 2769 /* Calculate doorbell regions */ 2770 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 2771 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 2772 NULL) + 2773 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 2774 NULL); 2775 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE); 2776 min_addr_reg1 = norm_regsize / 4096; 2777 pwm_regsize = db_bar_size - norm_regsize; 2778 2779 /* Check that the normal and PWM sizes are valid */ 2780 if (db_bar_size < norm_regsize) { 2781 DP_ERR(p_hwfn->cdev, 2782 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 2783 db_bar_size, norm_regsize); 2784 return -EINVAL; 2785 } 2786 2787 if (pwm_regsize < QED_MIN_PWM_REGION) { 2788 DP_ERR(p_hwfn->cdev, 2789 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 2790 pwm_regsize, 2791 QED_MIN_PWM_REGION, db_bar_size, norm_regsize); 2792 return -EINVAL; 2793 } 2794 2795 /* Calculate number of DPIs */ 2796 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 2797 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) || 2798 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) { 2799 /* Either EDPM is mandatory, or we are attempting to allocate a 2800 * WID per CPU. 2801 */ 2802 n_cpus = num_present_cpus(); 2803 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 2804 } 2805 2806 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) || 2807 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE); 2808 if (cond || p_hwfn->dcbx_no_edpm) { 2809 /* Either EDPM is disabled from user configuration, or it is 2810 * disabled via DCBx, or it is not mandatory and we failed to 2811 * allocated a WID per CPU. 2812 */ 2813 n_cpus = 1; 2814 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 2815 2816 if (cond) 2817 qed_rdma_dpm_bar(p_hwfn, p_ptt); 2818 } 2819 2820 p_hwfn->wid_count = (u16)n_cpus; 2821 2822 DP_INFO(p_hwfn, 2823 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n", 2824 norm_regsize, 2825 pwm_regsize, 2826 p_hwfn->dpi_size, 2827 p_hwfn->dpi_count, 2828 (!qed_edpm_enabled(p_hwfn)) ? 2829 "disabled" : "enabled", PAGE_SIZE); 2830 2831 if (rc) { 2832 DP_ERR(p_hwfn, 2833 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n", 2834 p_hwfn->dpi_count, 2835 p_hwfn->pf_params.rdma_pf_params.min_dpis); 2836 return -EINVAL; 2837 } 2838 2839 p_hwfn->dpi_start_offset = norm_regsize; 2840 2841 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 2842 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4); 2843 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 2844 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 2845 2846 return 0; 2847 } 2848 2849 static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 2850 struct qed_ptt *p_ptt, int hw_mode) 2851 { 2852 int rc = 0; 2853 2854 /* In CMT the gate should be cleared by the 2nd hwfn */ 2855 if (!QED_IS_CMT(p_hwfn->cdev) || !IS_LEAD_HWFN(p_hwfn)) 2856 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0); 2857 2858 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode); 2859 if (rc) 2860 return rc; 2861 2862 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0); 2863 2864 return 0; 2865 } 2866 2867 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 2868 struct qed_ptt *p_ptt, 2869 struct qed_tunnel_info *p_tunn, 2870 int hw_mode, 2871 bool b_hw_start, 2872 enum qed_int_mode int_mode, 2873 bool allow_npar_tx_switch) 2874 { 2875 u8 rel_pf_id = p_hwfn->rel_pf_id; 2876 int rc = 0; 2877 2878 if (p_hwfn->mcp_info) { 2879 struct qed_mcp_function_info *p_info; 2880 2881 p_info = &p_hwfn->mcp_info->func_info; 2882 if (p_info->bandwidth_min) 2883 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 2884 2885 /* Update rate limit once we'll actually have a link */ 2886 p_hwfn->qm_info.pf_rl = 100000; 2887 } 2888 2889 qed_cxt_hw_init_pf(p_hwfn, p_ptt); 2890 2891 qed_int_igu_init_rt(p_hwfn); 2892 2893 /* Set VLAN in NIG if needed */ 2894 if (hw_mode & BIT(MODE_MF_SD)) { 2895 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 2896 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 2897 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 2898 p_hwfn->hw_info.ovlan); 2899 2900 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 2901 "Configuring LLH_FUNC_FILTER_HDR_SEL\n"); 2902 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET, 2903 1); 2904 } 2905 2906 /* Enable classification by MAC if needed */ 2907 if (hw_mode & BIT(MODE_MF_SI)) { 2908 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 2909 "Configuring TAGMAC_CLS_TYPE\n"); 2910 STORE_RT_REG(p_hwfn, 2911 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 2912 } 2913 2914 /* Protocol Configuration */ 2915 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 2916 ((p_hwfn->hw_info.personality == QED_PCI_ISCSI) || 2917 (p_hwfn->hw_info.personality == QED_PCI_NVMETCP)) ? 1 : 0); 2918 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 2919 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0); 2920 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 2921 2922 /* Sanity check before the PF init sequence that uses DMAE */ 2923 rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase"); 2924 if (rc) 2925 return rc; 2926 2927 /* PF Init sequence */ 2928 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 2929 if (rc) 2930 return rc; 2931 2932 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 2933 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 2934 if (rc) 2935 return rc; 2936 2937 qed_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem); 2938 2939 /* Pure runtime initializations - directly to the HW */ 2940 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 2941 2942 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 2943 if (rc) 2944 return rc; 2945 2946 /* Use the leading hwfn since in CMT only NIG #0 is operational */ 2947 if (IS_LEAD_HWFN(p_hwfn)) { 2948 rc = qed_llh_hw_init_pf(p_hwfn, p_ptt); 2949 if (rc) 2950 return rc; 2951 } 2952 2953 if (b_hw_start) { 2954 /* enable interrupts */ 2955 qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 2956 2957 /* send function start command */ 2958 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn, 2959 allow_npar_tx_switch); 2960 if (rc) { 2961 DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 2962 return rc; 2963 } 2964 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 2965 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2)); 2966 qed_wr(p_hwfn, p_ptt, 2967 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST, 2968 0x100); 2969 } 2970 } 2971 return rc; 2972 } 2973 2974 int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn, 2975 struct qed_ptt *p_ptt, bool b_enable) 2976 { 2977 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0; 2978 2979 /* Configure the PF's internal FID_enable for master transactions */ 2980 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 2981 2982 /* Wait until value is set - try for 1 second every 50us */ 2983 for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 2984 val = qed_rd(p_hwfn, p_ptt, 2985 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 2986 if (val == set_val) 2987 break; 2988 2989 usleep_range(50, 60); 2990 } 2991 2992 if (val != set_val) { 2993 DP_NOTICE(p_hwfn, 2994 "PFID_ENABLE_MASTER wasn't changed after a second\n"); 2995 return -EAGAIN; 2996 } 2997 2998 return 0; 2999 } 3000 3001 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 3002 struct qed_ptt *p_main_ptt) 3003 { 3004 /* Read shadow of current MFW mailbox */ 3005 qed_mcp_read_mb(p_hwfn, p_main_ptt); 3006 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 3007 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length); 3008 } 3009 3010 static void 3011 qed_fill_load_req_params(struct qed_load_req_params *p_load_req, 3012 struct qed_drv_load_params *p_drv_load) 3013 { 3014 memset(p_load_req, 0, sizeof(*p_load_req)); 3015 3016 p_load_req->drv_role = p_drv_load->is_crash_kernel ? 3017 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS; 3018 p_load_req->timeout_val = p_drv_load->mfw_timeout_val; 3019 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset; 3020 p_load_req->override_force_load = p_drv_load->override_force_load; 3021 } 3022 3023 static int qed_vf_start(struct qed_hwfn *p_hwfn, 3024 struct qed_hw_init_params *p_params) 3025 { 3026 if (p_params->p_tunn) { 3027 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn); 3028 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn); 3029 } 3030 3031 p_hwfn->b_int_enabled = true; 3032 3033 return 0; 3034 } 3035 3036 static void qed_pglueb_clear_err(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3037 { 3038 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 3039 BIT(p_hwfn->abs_pf_id)); 3040 } 3041 3042 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params) 3043 { 3044 struct qed_load_req_params load_req_params; 3045 u32 load_code, resp, param, drv_mb_param; 3046 bool b_default_mtu = true; 3047 struct qed_hwfn *p_hwfn; 3048 const u32 *fw_overlays; 3049 u32 fw_overlays_len; 3050 u16 ether_type; 3051 int rc = 0, i; 3052 3053 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 3054 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 3055 return -EINVAL; 3056 } 3057 3058 if (IS_PF(cdev)) { 3059 rc = qed_init_fw_data(cdev, p_params->bin_fw_data); 3060 if (rc) 3061 return rc; 3062 } 3063 3064 for_each_hwfn(cdev, i) { 3065 p_hwfn = &cdev->hwfns[i]; 3066 3067 /* If management didn't provide a default, set one of our own */ 3068 if (!p_hwfn->hw_info.mtu) { 3069 p_hwfn->hw_info.mtu = 1500; 3070 b_default_mtu = false; 3071 } 3072 3073 if (IS_VF(cdev)) { 3074 qed_vf_start(p_hwfn, p_params); 3075 continue; 3076 } 3077 3078 /* Some flows may keep variable set */ 3079 p_hwfn->mcp_info->mcp_handling_status = 0; 3080 3081 rc = qed_calc_hw_mode(p_hwfn); 3082 if (rc) 3083 return rc; 3084 3085 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING, 3086 &cdev->mf_bits) || 3087 test_bit(QED_MF_8021AD_TAGGING, 3088 &cdev->mf_bits))) { 3089 if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits)) 3090 ether_type = ETH_P_8021Q; 3091 else 3092 ether_type = ETH_P_8021AD; 3093 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET, 3094 ether_type); 3095 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET, 3096 ether_type); 3097 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET, 3098 ether_type); 3099 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, 3100 ether_type); 3101 } 3102 3103 qed_fill_load_req_params(&load_req_params, 3104 p_params->p_drv_load_params); 3105 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, 3106 &load_req_params); 3107 if (rc) { 3108 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n"); 3109 return rc; 3110 } 3111 3112 load_code = load_req_params.load_code; 3113 DP_VERBOSE(p_hwfn, QED_MSG_SP, 3114 "Load request was sent. Load code: 0x%x\n", 3115 load_code); 3116 3117 /* Only relevant for recovery: 3118 * Clear the indication after LOAD_REQ is responded by the MFW. 3119 */ 3120 cdev->recov_in_prog = false; 3121 3122 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt); 3123 3124 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 3125 3126 /* Clean up chip from previous driver if such remains exist. 3127 * This is not needed when the PF is the first one on the 3128 * engine, since afterwards we are going to init the FW. 3129 */ 3130 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) { 3131 rc = qed_final_cleanup(p_hwfn, p_hwfn->p_main_ptt, 3132 p_hwfn->rel_pf_id, false); 3133 if (rc) { 3134 qed_hw_err_notify(p_hwfn, p_hwfn->p_main_ptt, 3135 QED_HW_ERR_RAMROD_FAIL, 3136 "Final cleanup failed\n"); 3137 goto load_err; 3138 } 3139 } 3140 3141 /* Log and clear previous pglue_b errors if such exist */ 3142 qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true); 3143 3144 /* Enable the PF's internal FID_enable in the PXP */ 3145 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt, 3146 true); 3147 if (rc) 3148 goto load_err; 3149 3150 /* Clear the pglue_b was_error indication. 3151 * In E4 it must be done after the BME and the internal 3152 * FID_enable for the PF are set, since VDMs may cause the 3153 * indication to be set again. 3154 */ 3155 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); 3156 3157 fw_overlays = cdev->fw_data->fw_overlays; 3158 fw_overlays_len = cdev->fw_data->fw_overlays_len; 3159 p_hwfn->fw_overlay_mem = 3160 qed_fw_overlay_mem_alloc(p_hwfn, fw_overlays, 3161 fw_overlays_len); 3162 if (!p_hwfn->fw_overlay_mem) { 3163 DP_NOTICE(p_hwfn, 3164 "Failed to allocate fw overlay memory\n"); 3165 rc = -ENOMEM; 3166 goto load_err; 3167 } 3168 3169 switch (load_code) { 3170 case FW_MSG_CODE_DRV_LOAD_ENGINE: 3171 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 3172 p_hwfn->hw_info.hw_mode); 3173 if (rc) 3174 break; 3175 fallthrough; 3176 case FW_MSG_CODE_DRV_LOAD_PORT: 3177 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 3178 p_hwfn->hw_info.hw_mode); 3179 if (rc) 3180 break; 3181 3182 fallthrough; 3183 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 3184 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 3185 p_params->p_tunn, 3186 p_hwfn->hw_info.hw_mode, 3187 p_params->b_hw_start, 3188 p_params->int_mode, 3189 p_params->allow_npar_tx_switch); 3190 break; 3191 default: 3192 DP_NOTICE(p_hwfn, 3193 "Unexpected load code [0x%08x]", load_code); 3194 rc = -EINVAL; 3195 break; 3196 } 3197 3198 if (rc) { 3199 DP_NOTICE(p_hwfn, 3200 "init phase failed for loadcode 0x%x (rc %d)\n", 3201 load_code, rc); 3202 goto load_err; 3203 } 3204 3205 rc = qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); 3206 if (rc) 3207 return rc; 3208 3209 /* send DCBX attention request command */ 3210 DP_VERBOSE(p_hwfn, 3211 QED_MSG_DCB, 3212 "sending phony dcbx set command to trigger DCBx attention handling\n"); 3213 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 3214 DRV_MSG_CODE_SET_DCBX, 3215 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 3216 &resp, ¶m); 3217 if (rc) { 3218 DP_NOTICE(p_hwfn, 3219 "Failed to send DCBX attention request\n"); 3220 return rc; 3221 } 3222 3223 p_hwfn->hw_init_done = true; 3224 } 3225 3226 if (IS_PF(cdev)) { 3227 p_hwfn = QED_LEADING_HWFN(cdev); 3228 3229 /* Get pre-negotiated values for stag, bandwidth etc. */ 3230 DP_VERBOSE(p_hwfn, 3231 QED_MSG_SPQ, 3232 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n"); 3233 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET; 3234 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 3235 DRV_MSG_CODE_GET_OEM_UPDATES, 3236 drv_mb_param, &resp, ¶m); 3237 if (rc) 3238 DP_NOTICE(p_hwfn, 3239 "Failed to send GET_OEM_UPDATES attention request\n"); 3240 3241 drv_mb_param = STORM_FW_VERSION; 3242 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 3243 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, 3244 drv_mb_param, &load_code, ¶m); 3245 if (rc) 3246 DP_INFO(p_hwfn, "Failed to update firmware version\n"); 3247 3248 if (!b_default_mtu) { 3249 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt, 3250 p_hwfn->hw_info.mtu); 3251 if (rc) 3252 DP_INFO(p_hwfn, 3253 "Failed to update default mtu\n"); 3254 } 3255 3256 rc = qed_mcp_ov_update_driver_state(p_hwfn, 3257 p_hwfn->p_main_ptt, 3258 QED_OV_DRIVER_STATE_DISABLED); 3259 if (rc) 3260 DP_INFO(p_hwfn, "Failed to update driver state\n"); 3261 3262 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt, 3263 QED_OV_ESWITCH_NONE); 3264 if (rc) 3265 DP_INFO(p_hwfn, "Failed to update eswitch mode\n"); 3266 } 3267 3268 return 0; 3269 3270 load_err: 3271 /* The MFW load lock should be released also when initialization fails. 3272 */ 3273 qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); 3274 return rc; 3275 } 3276 3277 #define QED_HW_STOP_RETRY_LIMIT (10) 3278 static void qed_hw_timers_stop(struct qed_dev *cdev, 3279 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3280 { 3281 int i; 3282 3283 /* close timers */ 3284 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 3285 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 3286 3287 if (cdev->recov_in_prog) 3288 return; 3289 3290 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 3291 if ((!qed_rd(p_hwfn, p_ptt, 3292 TM_REG_PF_SCAN_ACTIVE_CONN)) && 3293 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 3294 break; 3295 3296 /* Dependent on number of connection/tasks, possibly 3297 * 1ms sleep is required between polls 3298 */ 3299 usleep_range(1000, 2000); 3300 } 3301 3302 if (i < QED_HW_STOP_RETRY_LIMIT) 3303 return; 3304 3305 DP_NOTICE(p_hwfn, 3306 "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 3307 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 3308 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 3309 } 3310 3311 void qed_hw_timers_stop_all(struct qed_dev *cdev) 3312 { 3313 int j; 3314 3315 for_each_hwfn(cdev, j) { 3316 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 3317 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 3318 3319 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 3320 } 3321 } 3322 3323 int qed_hw_stop(struct qed_dev *cdev) 3324 { 3325 struct qed_hwfn *p_hwfn; 3326 struct qed_ptt *p_ptt; 3327 int rc, rc2 = 0; 3328 int j; 3329 3330 for_each_hwfn(cdev, j) { 3331 p_hwfn = &cdev->hwfns[j]; 3332 p_ptt = p_hwfn->p_main_ptt; 3333 3334 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 3335 3336 if (IS_VF(cdev)) { 3337 qed_vf_pf_int_cleanup(p_hwfn); 3338 rc = qed_vf_pf_reset(p_hwfn); 3339 if (rc) { 3340 DP_NOTICE(p_hwfn, 3341 "qed_vf_pf_reset failed. rc = %d.\n", 3342 rc); 3343 rc2 = -EINVAL; 3344 } 3345 continue; 3346 } 3347 3348 /* mark the hw as uninitialized... */ 3349 p_hwfn->hw_init_done = false; 3350 3351 /* Send unload command to MCP */ 3352 if (!cdev->recov_in_prog) { 3353 rc = qed_mcp_unload_req(p_hwfn, p_ptt); 3354 if (rc) { 3355 DP_NOTICE(p_hwfn, 3356 "Failed sending a UNLOAD_REQ command. rc = %d.\n", 3357 rc); 3358 rc2 = -EINVAL; 3359 } 3360 } 3361 3362 qed_slowpath_irq_sync(p_hwfn); 3363 3364 /* After this point no MFW attentions are expected, e.g. prevent 3365 * race between pf stop and dcbx pf update. 3366 */ 3367 rc = qed_sp_pf_stop(p_hwfn); 3368 if (rc) { 3369 DP_NOTICE(p_hwfn, 3370 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n", 3371 rc); 3372 rc2 = -EINVAL; 3373 } 3374 3375 qed_wr(p_hwfn, p_ptt, 3376 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 3377 3378 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 3379 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 3380 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 3381 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 3382 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 3383 3384 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 3385 3386 /* Disable Attention Generation */ 3387 qed_int_igu_disable_int(p_hwfn, p_ptt); 3388 3389 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 3390 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 3391 3392 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 3393 3394 /* Need to wait 1ms to guarantee SBs are cleared */ 3395 usleep_range(1000, 2000); 3396 3397 /* Disable PF in HW blocks */ 3398 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0); 3399 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0); 3400 3401 if (IS_LEAD_HWFN(p_hwfn) && 3402 test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) && 3403 !QED_IS_FCOE_PERSONALITY(p_hwfn)) 3404 qed_llh_remove_mac_filter(cdev, 0, 3405 p_hwfn->hw_info.hw_mac_addr); 3406 3407 if (!cdev->recov_in_prog) { 3408 rc = qed_mcp_unload_done(p_hwfn, p_ptt); 3409 if (rc) { 3410 DP_NOTICE(p_hwfn, 3411 "Failed sending a UNLOAD_DONE command. rc = %d.\n", 3412 rc); 3413 rc2 = -EINVAL; 3414 } 3415 } 3416 } 3417 3418 if (IS_PF(cdev) && !cdev->recov_in_prog) { 3419 p_hwfn = QED_LEADING_HWFN(cdev); 3420 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt; 3421 3422 /* Clear the PF's internal FID_enable in the PXP. 3423 * In CMT this should only be done for first hw-function, and 3424 * only after all transactions have stopped for all active 3425 * hw-functions. 3426 */ 3427 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false); 3428 if (rc) { 3429 DP_NOTICE(p_hwfn, 3430 "qed_pglueb_set_pfid_enable() failed. rc = %d.\n", 3431 rc); 3432 rc2 = -EINVAL; 3433 } 3434 } 3435 3436 return rc2; 3437 } 3438 3439 int qed_hw_stop_fastpath(struct qed_dev *cdev) 3440 { 3441 int j; 3442 3443 for_each_hwfn(cdev, j) { 3444 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 3445 struct qed_ptt *p_ptt; 3446 3447 if (IS_VF(cdev)) { 3448 qed_vf_pf_int_cleanup(p_hwfn); 3449 continue; 3450 } 3451 p_ptt = qed_ptt_acquire(p_hwfn); 3452 if (!p_ptt) 3453 return -EAGAIN; 3454 3455 DP_VERBOSE(p_hwfn, 3456 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n"); 3457 3458 qed_wr(p_hwfn, p_ptt, 3459 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 3460 3461 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 3462 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 3463 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 3464 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 3465 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 3466 3467 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 3468 3469 /* Need to wait 1ms to guarantee SBs are cleared */ 3470 usleep_range(1000, 2000); 3471 qed_ptt_release(p_hwfn, p_ptt); 3472 } 3473 3474 return 0; 3475 } 3476 3477 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 3478 { 3479 struct qed_ptt *p_ptt; 3480 3481 if (IS_VF(p_hwfn->cdev)) 3482 return 0; 3483 3484 p_ptt = qed_ptt_acquire(p_hwfn); 3485 if (!p_ptt) 3486 return -EAGAIN; 3487 3488 if (p_hwfn->p_rdma_info && 3489 p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs) 3490 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1); 3491 3492 /* Re-open incoming traffic */ 3493 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 3494 qed_ptt_release(p_hwfn, p_ptt); 3495 3496 return 0; 3497 } 3498 3499 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 3500 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 3501 { 3502 qed_ptt_pool_free(p_hwfn); 3503 kfree(p_hwfn->hw_info.p_igu_info); 3504 p_hwfn->hw_info.p_igu_info = NULL; 3505 } 3506 3507 /* Setup bar access */ 3508 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 3509 { 3510 /* clear indirect access */ 3511 if (QED_IS_AH(p_hwfn->cdev)) { 3512 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3513 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0); 3514 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3515 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0); 3516 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3517 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0); 3518 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3519 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0); 3520 } else { 3521 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3522 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0); 3523 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3524 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0); 3525 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3526 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0); 3527 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3528 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0); 3529 } 3530 3531 /* Clean previous pglue_b errors if such exist */ 3532 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); 3533 3534 /* enable internal target-read */ 3535 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3536 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 3537 } 3538 3539 static void get_function_id(struct qed_hwfn *p_hwfn) 3540 { 3541 /* ME Register */ 3542 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, 3543 PXP_PF_ME_OPAQUE_ADDR); 3544 3545 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 3546 3547 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 3548 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 3549 PXP_CONCRETE_FID_PFID); 3550 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 3551 PXP_CONCRETE_FID_PORT); 3552 3553 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 3554 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 3555 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 3556 } 3557 3558 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 3559 { 3560 u32 *feat_num = p_hwfn->hw_info.feat_num; 3561 struct qed_sb_cnt_info sb_cnt; 3562 u32 non_l2_sbs = 0; 3563 3564 memset(&sb_cnt, 0, sizeof(sb_cnt)); 3565 qed_int_get_num_sbs(p_hwfn, &sb_cnt); 3566 3567 if (IS_ENABLED(CONFIG_QED_RDMA) && 3568 QED_IS_RDMA_PERSONALITY(p_hwfn)) { 3569 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide 3570 * the status blocks equally between L2 / RoCE but with 3571 * consideration as to how many l2 queues / cnqs we have. 3572 */ 3573 feat_num[QED_RDMA_CNQ] = 3574 min_t(u32, sb_cnt.cnt / 2, 3575 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM)); 3576 3577 non_l2_sbs = feat_num[QED_RDMA_CNQ]; 3578 } 3579 if (QED_IS_L2_PERSONALITY(p_hwfn)) { 3580 /* Start by allocating VF queues, then PF's */ 3581 feat_num[QED_VF_L2_QUE] = min_t(u32, 3582 RESC_NUM(p_hwfn, QED_L2_QUEUE), 3583 sb_cnt.iov_cnt); 3584 feat_num[QED_PF_L2_QUE] = min_t(u32, 3585 sb_cnt.cnt - non_l2_sbs, 3586 RESC_NUM(p_hwfn, 3587 QED_L2_QUEUE) - 3588 FEAT_NUM(p_hwfn, 3589 QED_VF_L2_QUE)); 3590 } 3591 3592 if (QED_IS_FCOE_PERSONALITY(p_hwfn)) 3593 feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt, 3594 RESC_NUM(p_hwfn, 3595 QED_CMDQS_CQS)); 3596 3597 if (QED_IS_ISCSI_PERSONALITY(p_hwfn)) 3598 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt, 3599 RESC_NUM(p_hwfn, 3600 QED_CMDQS_CQS)); 3601 3602 if (QED_IS_NVMETCP_PERSONALITY(p_hwfn)) 3603 feat_num[QED_NVMETCP_CQ] = min_t(u32, sb_cnt.cnt, 3604 RESC_NUM(p_hwfn, 3605 QED_CMDQS_CQS)); 3606 3607 DP_VERBOSE(p_hwfn, 3608 NETIF_MSG_PROBE, 3609 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d NVMETCP_CQ=%d #SBS=%d\n", 3610 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE), 3611 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE), 3612 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ), 3613 (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ), 3614 (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ), 3615 (int)FEAT_NUM(p_hwfn, QED_NVMETCP_CQ), 3616 (int)sb_cnt.cnt); 3617 } 3618 3619 const char *qed_hw_get_resc_name(enum qed_resources res_id) 3620 { 3621 switch (res_id) { 3622 case QED_L2_QUEUE: 3623 return "L2_QUEUE"; 3624 case QED_VPORT: 3625 return "VPORT"; 3626 case QED_RSS_ENG: 3627 return "RSS_ENG"; 3628 case QED_PQ: 3629 return "PQ"; 3630 case QED_RL: 3631 return "RL"; 3632 case QED_MAC: 3633 return "MAC"; 3634 case QED_VLAN: 3635 return "VLAN"; 3636 case QED_RDMA_CNQ_RAM: 3637 return "RDMA_CNQ_RAM"; 3638 case QED_ILT: 3639 return "ILT"; 3640 case QED_LL2_RAM_QUEUE: 3641 return "LL2_RAM_QUEUE"; 3642 case QED_LL2_CTX_QUEUE: 3643 return "LL2_CTX_QUEUE"; 3644 case QED_CMDQS_CQS: 3645 return "CMDQS_CQS"; 3646 case QED_RDMA_STATS_QUEUE: 3647 return "RDMA_STATS_QUEUE"; 3648 case QED_BDQ: 3649 return "BDQ"; 3650 case QED_SB: 3651 return "SB"; 3652 default: 3653 return "UNKNOWN_RESOURCE"; 3654 } 3655 } 3656 3657 static int 3658 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, 3659 struct qed_ptt *p_ptt, 3660 enum qed_resources res_id, 3661 u32 resc_max_val, u32 *p_mcp_resp) 3662 { 3663 int rc; 3664 3665 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id, 3666 resc_max_val, p_mcp_resp); 3667 if (rc) { 3668 DP_NOTICE(p_hwfn, 3669 "MFW response failure for a max value setting of resource %d [%s]\n", 3670 res_id, qed_hw_get_resc_name(res_id)); 3671 return rc; 3672 } 3673 3674 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) 3675 DP_INFO(p_hwfn, 3676 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n", 3677 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp); 3678 3679 return 0; 3680 } 3681 3682 static u32 qed_hsi_def_val[][MAX_CHIP_IDS] = { 3683 {MAX_NUM_VFS_BB, MAX_NUM_VFS_K2}, 3684 {MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2}, 3685 {MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2}, 3686 {MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2,}, 3687 {MAX_NUM_PFS_BB, MAX_NUM_PFS_K2}, 3688 {MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2}, 3689 {ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2}, 3690 {MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2}, 3691 {PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2}, 3692 {RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2}, 3693 {MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS}, 3694 {PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES}, 3695 {BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2}, 3696 }; 3697 3698 u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type) 3699 { 3700 enum chip_ids chip_id = QED_IS_BB(cdev) ? CHIP_BB : CHIP_K2; 3701 3702 if (type >= QED_NUM_HSI_DEFS) { 3703 DP_ERR(cdev, "Unexpected HSI definition type [%d]\n", type); 3704 return 0; 3705 } 3706 3707 return qed_hsi_def_val[type][chip_id]; 3708 } 3709 3710 static int 3711 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3712 { 3713 u32 resc_max_val, mcp_resp; 3714 u8 res_id; 3715 int rc; 3716 3717 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 3718 switch (res_id) { 3719 case QED_LL2_RAM_QUEUE: 3720 resc_max_val = MAX_NUM_LL2_RX_RAM_QUEUES; 3721 break; 3722 case QED_LL2_CTX_QUEUE: 3723 resc_max_val = MAX_NUM_LL2_RX_CTX_QUEUES; 3724 break; 3725 case QED_RDMA_CNQ_RAM: 3726 /* No need for a case for QED_CMDQS_CQS since 3727 * CNQ/CMDQS are the same resource. 3728 */ 3729 resc_max_val = NUM_OF_GLOBAL_QUEUES; 3730 break; 3731 case QED_RDMA_STATS_QUEUE: 3732 resc_max_val = 3733 NUM_OF_RDMA_STATISTIC_COUNTERS(p_hwfn->cdev); 3734 break; 3735 case QED_BDQ: 3736 resc_max_val = BDQ_NUM_RESOURCES; 3737 break; 3738 default: 3739 continue; 3740 } 3741 3742 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id, 3743 resc_max_val, &mcp_resp); 3744 if (rc) 3745 return rc; 3746 3747 /* There's no point to continue to the next resource if the 3748 * command is not supported by the MFW. 3749 * We do continue if the command is supported but the resource 3750 * is unknown to the MFW. Such a resource will be later 3751 * configured with the default allocation values. 3752 */ 3753 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED) 3754 return -EINVAL; 3755 } 3756 3757 return 0; 3758 } 3759 3760 static 3761 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn, 3762 enum qed_resources res_id, 3763 u32 *p_resc_num, u32 *p_resc_start) 3764 { 3765 u8 num_funcs = p_hwfn->num_funcs_on_engine; 3766 struct qed_dev *cdev = p_hwfn->cdev; 3767 3768 switch (res_id) { 3769 case QED_L2_QUEUE: 3770 *p_resc_num = NUM_OF_L2_QUEUES(cdev) / num_funcs; 3771 break; 3772 case QED_VPORT: 3773 *p_resc_num = NUM_OF_VPORTS(cdev) / num_funcs; 3774 break; 3775 case QED_RSS_ENG: 3776 *p_resc_num = NUM_OF_RSS_ENGINES(cdev) / num_funcs; 3777 break; 3778 case QED_PQ: 3779 *p_resc_num = NUM_OF_QM_TX_QUEUES(cdev) / num_funcs; 3780 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */ 3781 break; 3782 case QED_RL: 3783 *p_resc_num = NUM_OF_QM_GLOBAL_RLS(cdev) / num_funcs; 3784 break; 3785 case QED_MAC: 3786 case QED_VLAN: 3787 /* Each VFC resource can accommodate both a MAC and a VLAN */ 3788 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 3789 break; 3790 case QED_ILT: 3791 *p_resc_num = NUM_OF_PXP_ILT_RECORDS(cdev) / num_funcs; 3792 break; 3793 case QED_LL2_RAM_QUEUE: 3794 *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs; 3795 break; 3796 case QED_LL2_CTX_QUEUE: 3797 *p_resc_num = MAX_NUM_LL2_RX_CTX_QUEUES / num_funcs; 3798 break; 3799 case QED_RDMA_CNQ_RAM: 3800 case QED_CMDQS_CQS: 3801 /* CNQ/CMDQS are the same resource */ 3802 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs; 3803 break; 3804 case QED_RDMA_STATS_QUEUE: 3805 *p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(cdev) / num_funcs; 3806 break; 3807 case QED_BDQ: 3808 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI && 3809 p_hwfn->hw_info.personality != QED_PCI_FCOE && 3810 p_hwfn->hw_info.personality != QED_PCI_NVMETCP) 3811 *p_resc_num = 0; 3812 else 3813 *p_resc_num = 1; 3814 break; 3815 case QED_SB: 3816 /* Since we want its value to reflect whether MFW supports 3817 * the new scheme, have a default of 0. 3818 */ 3819 *p_resc_num = 0; 3820 break; 3821 default: 3822 return -EINVAL; 3823 } 3824 3825 switch (res_id) { 3826 case QED_BDQ: 3827 if (!*p_resc_num) 3828 *p_resc_start = 0; 3829 else if (p_hwfn->cdev->num_ports_in_engine == 4) 3830 *p_resc_start = p_hwfn->port_id; 3831 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI || 3832 p_hwfn->hw_info.personality == QED_PCI_NVMETCP) 3833 *p_resc_start = p_hwfn->port_id; 3834 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 3835 *p_resc_start = p_hwfn->port_id + 2; 3836 break; 3837 default: 3838 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx; 3839 break; 3840 } 3841 3842 return 0; 3843 } 3844 3845 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn, 3846 enum qed_resources res_id) 3847 { 3848 u32 dflt_resc_num = 0, dflt_resc_start = 0; 3849 u32 mcp_resp, *p_resc_num, *p_resc_start; 3850 int rc; 3851 3852 p_resc_num = &RESC_NUM(p_hwfn, res_id); 3853 p_resc_start = &RESC_START(p_hwfn, res_id); 3854 3855 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num, 3856 &dflt_resc_start); 3857 if (rc) { 3858 DP_ERR(p_hwfn, 3859 "Failed to get default amount for resource %d [%s]\n", 3860 res_id, qed_hw_get_resc_name(res_id)); 3861 return rc; 3862 } 3863 3864 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id, 3865 &mcp_resp, p_resc_num, p_resc_start); 3866 if (rc) { 3867 DP_NOTICE(p_hwfn, 3868 "MFW response failure for an allocation request for resource %d [%s]\n", 3869 res_id, qed_hw_get_resc_name(res_id)); 3870 return rc; 3871 } 3872 3873 /* Default driver values are applied in the following cases: 3874 * - The resource allocation MB command is not supported by the MFW 3875 * - There is an internal error in the MFW while processing the request 3876 * - The resource ID is unknown to the MFW 3877 */ 3878 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) { 3879 DP_INFO(p_hwfn, 3880 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n", 3881 res_id, 3882 qed_hw_get_resc_name(res_id), 3883 mcp_resp, dflt_resc_num, dflt_resc_start); 3884 *p_resc_num = dflt_resc_num; 3885 *p_resc_start = dflt_resc_start; 3886 goto out; 3887 } 3888 3889 out: 3890 /* PQs have to divide by 8 [that's the HW granularity]. 3891 * Reduce number so it would fit. 3892 */ 3893 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) { 3894 DP_INFO(p_hwfn, 3895 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n", 3896 *p_resc_num, 3897 (*p_resc_num) & ~0x7, 3898 *p_resc_start, (*p_resc_start) & ~0x7); 3899 *p_resc_num &= ~0x7; 3900 *p_resc_start &= ~0x7; 3901 } 3902 3903 return 0; 3904 } 3905 3906 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn) 3907 { 3908 int rc; 3909 u8 res_id; 3910 3911 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 3912 rc = __qed_hw_set_resc_info(p_hwfn, res_id); 3913 if (rc) 3914 return rc; 3915 } 3916 3917 return 0; 3918 } 3919 3920 static int qed_hw_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, 3921 struct qed_ptt *p_ptt) 3922 { 3923 struct qed_dev *cdev = p_hwfn->cdev; 3924 u8 native_ppfid_idx; 3925 int rc; 3926 3927 /* Calculation of BB/AH is different for native_ppfid_idx */ 3928 if (QED_IS_BB(cdev)) 3929 native_ppfid_idx = p_hwfn->rel_pf_id; 3930 else 3931 native_ppfid_idx = p_hwfn->rel_pf_id / 3932 cdev->num_ports_in_engine; 3933 3934 rc = qed_mcp_get_ppfid_bitmap(p_hwfn, p_ptt); 3935 if (rc != 0 && rc != -EOPNOTSUPP) 3936 return rc; 3937 else if (rc == -EOPNOTSUPP) 3938 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx; 3939 3940 if (!(cdev->ppfid_bitmap & (0x1 << native_ppfid_idx))) { 3941 DP_INFO(p_hwfn, 3942 "Fix the PPFID bitmap to include the native PPFID [native_ppfid_idx %hhd, orig_bitmap 0x%hhx]\n", 3943 native_ppfid_idx, cdev->ppfid_bitmap); 3944 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx; 3945 } 3946 3947 return 0; 3948 } 3949 3950 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3951 { 3952 struct qed_resc_unlock_params resc_unlock_params; 3953 struct qed_resc_lock_params resc_lock_params; 3954 bool b_ah = QED_IS_AH(p_hwfn->cdev); 3955 u8 res_id; 3956 int rc; 3957 3958 /* Setting the max values of the soft resources and the following 3959 * resources allocation queries should be atomic. Since several PFs can 3960 * run in parallel - a resource lock is needed. 3961 * If either the resource lock or resource set value commands are not 3962 * supported - skip the max values setting, release the lock if 3963 * needed, and proceed to the queries. Other failures, including a 3964 * failure to acquire the lock, will cause this function to fail. 3965 */ 3966 qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params, 3967 QED_RESC_LOCK_RESC_ALLOC, false); 3968 3969 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params); 3970 if (rc && rc != -EINVAL) { 3971 return rc; 3972 } else if (rc == -EINVAL) { 3973 DP_INFO(p_hwfn, 3974 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n"); 3975 } else if (!resc_lock_params.b_granted) { 3976 DP_NOTICE(p_hwfn, 3977 "Failed to acquire the resource lock for the resource allocation commands\n"); 3978 return -EBUSY; 3979 } else { 3980 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt); 3981 if (rc && rc != -EINVAL) { 3982 DP_NOTICE(p_hwfn, 3983 "Failed to set the max values of the soft resources\n"); 3984 goto unlock_and_exit; 3985 } else if (rc == -EINVAL) { 3986 DP_INFO(p_hwfn, 3987 "Skip the max values setting of the soft resources since it is not supported by the MFW\n"); 3988 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, 3989 &resc_unlock_params); 3990 if (rc) 3991 DP_INFO(p_hwfn, 3992 "Failed to release the resource lock for the resource allocation commands\n"); 3993 } 3994 } 3995 3996 rc = qed_hw_set_resc_info(p_hwfn); 3997 if (rc) 3998 goto unlock_and_exit; 3999 4000 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) { 4001 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 4002 if (rc) 4003 DP_INFO(p_hwfn, 4004 "Failed to release the resource lock for the resource allocation commands\n"); 4005 } 4006 4007 /* PPFID bitmap */ 4008 if (IS_LEAD_HWFN(p_hwfn)) { 4009 rc = qed_hw_get_ppfid_bitmap(p_hwfn, p_ptt); 4010 if (rc) 4011 return rc; 4012 } 4013 4014 /* Sanity for ILT */ 4015 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) || 4016 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) { 4017 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 4018 RESC_START(p_hwfn, QED_ILT), 4019 RESC_END(p_hwfn, QED_ILT) - 1); 4020 return -EINVAL; 4021 } 4022 4023 /* This will also learn the number of SBs from MFW */ 4024 if (qed_int_igu_reset_cam(p_hwfn, p_ptt)) 4025 return -EINVAL; 4026 4027 qed_hw_set_feat(p_hwfn); 4028 4029 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) 4030 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n", 4031 qed_hw_get_resc_name(res_id), 4032 RESC_NUM(p_hwfn, res_id), 4033 RESC_START(p_hwfn, res_id)); 4034 4035 return 0; 4036 4037 unlock_and_exit: 4038 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) 4039 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 4040 return rc; 4041 } 4042 4043 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4044 { 4045 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities, fld; 4046 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 4047 struct qed_mcp_link_speed_params *ext_speed; 4048 struct qed_mcp_link_capabilities *p_caps; 4049 struct qed_mcp_link_params *link; 4050 int i; 4051 4052 /* Read global nvm_cfg address */ 4053 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 4054 4055 /* Verify MCP has initialized it */ 4056 if (!nvm_cfg_addr) { 4057 DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 4058 return -EINVAL; 4059 } 4060 4061 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 4062 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 4063 4064 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4065 offsetof(struct nvm_cfg1, glob) + 4066 offsetof(struct nvm_cfg1_glob, core_cfg); 4067 4068 core_cfg = qed_rd(p_hwfn, p_ptt, addr); 4069 4070 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 4071 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 4072 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 4073 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 4074 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 4075 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 4076 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 4077 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 4078 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 4079 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 4080 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G: 4081 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 4082 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G: 4083 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1: 4084 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1: 4085 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2: 4086 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2: 4087 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4: 4088 break; 4089 default: 4090 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg); 4091 break; 4092 } 4093 4094 /* Read default link configuration */ 4095 link = &p_hwfn->mcp_info->link_input; 4096 p_caps = &p_hwfn->mcp_info->link_capabilities; 4097 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4098 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 4099 link_temp = qed_rd(p_hwfn, p_ptt, 4100 port_cfg_addr + 4101 offsetof(struct nvm_cfg1_port, speed_cap_mask)); 4102 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 4103 link->speed.advertised_speeds = link_temp; 4104 4105 p_caps->speed_capabilities = link->speed.advertised_speeds; 4106 4107 link_temp = qed_rd(p_hwfn, p_ptt, 4108 port_cfg_addr + 4109 offsetof(struct nvm_cfg1_port, link_settings)); 4110 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 4111 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 4112 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 4113 link->speed.autoneg = true; 4114 break; 4115 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 4116 link->speed.forced_speed = 1000; 4117 break; 4118 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 4119 link->speed.forced_speed = 10000; 4120 break; 4121 case NVM_CFG1_PORT_DRV_LINK_SPEED_20G: 4122 link->speed.forced_speed = 20000; 4123 break; 4124 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 4125 link->speed.forced_speed = 25000; 4126 break; 4127 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 4128 link->speed.forced_speed = 40000; 4129 break; 4130 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 4131 link->speed.forced_speed = 50000; 4132 break; 4133 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 4134 link->speed.forced_speed = 100000; 4135 break; 4136 default: 4137 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp); 4138 } 4139 4140 p_caps->default_speed_autoneg = link->speed.autoneg; 4141 4142 fld = GET_MFW_FIELD(link_temp, NVM_CFG1_PORT_DRV_FLOW_CONTROL); 4143 link->pause.autoneg = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 4144 link->pause.forced_rx = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 4145 link->pause.forced_tx = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 4146 link->loopback_mode = 0; 4147 4148 if (p_hwfn->mcp_info->capabilities & 4149 FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) { 4150 switch (GET_MFW_FIELD(link_temp, 4151 NVM_CFG1_PORT_FEC_FORCE_MODE)) { 4152 case NVM_CFG1_PORT_FEC_FORCE_MODE_NONE: 4153 p_caps->fec_default |= QED_FEC_MODE_NONE; 4154 break; 4155 case NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE: 4156 p_caps->fec_default |= QED_FEC_MODE_FIRECODE; 4157 break; 4158 case NVM_CFG1_PORT_FEC_FORCE_MODE_RS: 4159 p_caps->fec_default |= QED_FEC_MODE_RS; 4160 break; 4161 case NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO: 4162 p_caps->fec_default |= QED_FEC_MODE_AUTO; 4163 break; 4164 default: 4165 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4166 "unknown FEC mode in 0x%08x\n", link_temp); 4167 } 4168 } else { 4169 p_caps->fec_default = QED_FEC_MODE_UNSUPPORTED; 4170 } 4171 4172 link->fec = p_caps->fec_default; 4173 4174 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) { 4175 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr + 4176 offsetof(struct nvm_cfg1_port, ext_phy)); 4177 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK; 4178 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET; 4179 p_caps->default_eee = QED_MCP_EEE_ENABLED; 4180 link->eee.enable = true; 4181 switch (link_temp) { 4182 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED: 4183 p_caps->default_eee = QED_MCP_EEE_DISABLED; 4184 link->eee.enable = false; 4185 break; 4186 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED: 4187 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME; 4188 break; 4189 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE: 4190 p_caps->eee_lpi_timer = 4191 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME; 4192 break; 4193 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY: 4194 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME; 4195 break; 4196 } 4197 4198 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer; 4199 link->eee.tx_lpi_enable = link->eee.enable; 4200 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV; 4201 } else { 4202 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED; 4203 } 4204 4205 if (p_hwfn->mcp_info->capabilities & 4206 FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL) { 4207 ext_speed = &link->ext_speed; 4208 4209 link_temp = qed_rd(p_hwfn, p_ptt, 4210 port_cfg_addr + 4211 offsetof(struct nvm_cfg1_port, 4212 extended_speed)); 4213 4214 fld = GET_MFW_FIELD(link_temp, NVM_CFG1_PORT_EXTENDED_SPEED); 4215 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_AN) 4216 ext_speed->autoneg = true; 4217 4218 ext_speed->forced_speed = 0; 4219 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G) 4220 ext_speed->forced_speed |= QED_EXT_SPEED_1G; 4221 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G) 4222 ext_speed->forced_speed |= QED_EXT_SPEED_10G; 4223 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_20G) 4224 ext_speed->forced_speed |= QED_EXT_SPEED_20G; 4225 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G) 4226 ext_speed->forced_speed |= QED_EXT_SPEED_25G; 4227 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G) 4228 ext_speed->forced_speed |= QED_EXT_SPEED_40G; 4229 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R) 4230 ext_speed->forced_speed |= QED_EXT_SPEED_50G_R; 4231 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2) 4232 ext_speed->forced_speed |= QED_EXT_SPEED_50G_R2; 4233 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2) 4234 ext_speed->forced_speed |= QED_EXT_SPEED_100G_R2; 4235 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4) 4236 ext_speed->forced_speed |= QED_EXT_SPEED_100G_R4; 4237 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4) 4238 ext_speed->forced_speed |= QED_EXT_SPEED_100G_P4; 4239 4240 fld = GET_MFW_FIELD(link_temp, 4241 NVM_CFG1_PORT_EXTENDED_SPEED_CAP); 4242 4243 ext_speed->advertised_speeds = 0; 4244 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_RESERVED) 4245 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_RES; 4246 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G) 4247 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_1G; 4248 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G) 4249 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_10G; 4250 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_20G) 4251 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_20G; 4252 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G) 4253 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_25G; 4254 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G) 4255 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_40G; 4256 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R) 4257 ext_speed->advertised_speeds |= 4258 QED_EXT_SPEED_MASK_50G_R; 4259 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2) 4260 ext_speed->advertised_speeds |= 4261 QED_EXT_SPEED_MASK_50G_R2; 4262 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2) 4263 ext_speed->advertised_speeds |= 4264 QED_EXT_SPEED_MASK_100G_R2; 4265 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4) 4266 ext_speed->advertised_speeds |= 4267 QED_EXT_SPEED_MASK_100G_R4; 4268 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4) 4269 ext_speed->advertised_speeds |= 4270 QED_EXT_SPEED_MASK_100G_P4; 4271 4272 link_temp = qed_rd(p_hwfn, p_ptt, 4273 port_cfg_addr + 4274 offsetof(struct nvm_cfg1_port, 4275 extended_fec_mode)); 4276 link->ext_fec_mode = link_temp; 4277 4278 p_caps->default_ext_speed_caps = ext_speed->advertised_speeds; 4279 p_caps->default_ext_speed = ext_speed->forced_speed; 4280 p_caps->default_ext_autoneg = ext_speed->autoneg; 4281 p_caps->default_ext_fec = link->ext_fec_mode; 4282 4283 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4284 "Read default extended link config: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, FEC: 0x%02x\n", 4285 ext_speed->forced_speed, 4286 ext_speed->advertised_speeds, ext_speed->autoneg, 4287 p_caps->default_ext_fec); 4288 } 4289 4290 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4291 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x, EEE: 0x%02x [0x%08x usec], FEC: 0x%02x\n", 4292 link->speed.forced_speed, link->speed.advertised_speeds, 4293 link->speed.autoneg, link->pause.autoneg, 4294 p_caps->default_eee, p_caps->eee_lpi_timer, 4295 p_caps->fec_default); 4296 4297 if (IS_LEAD_HWFN(p_hwfn)) { 4298 struct qed_dev *cdev = p_hwfn->cdev; 4299 4300 /* Read Multi-function information from shmem */ 4301 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4302 offsetof(struct nvm_cfg1, glob) + 4303 offsetof(struct nvm_cfg1_glob, generic_cont0); 4304 4305 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 4306 4307 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 4308 NVM_CFG1_GLOB_MF_MODE_OFFSET; 4309 4310 switch (mf_mode) { 4311 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 4312 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS); 4313 break; 4314 case NVM_CFG1_GLOB_MF_MODE_UFP: 4315 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | 4316 BIT(QED_MF_LLH_PROTO_CLSS) | 4317 BIT(QED_MF_UFP_SPECIFIC) | 4318 BIT(QED_MF_8021Q_TAGGING) | 4319 BIT(QED_MF_DONT_ADD_VLAN0_TAG); 4320 break; 4321 case NVM_CFG1_GLOB_MF_MODE_BD: 4322 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | 4323 BIT(QED_MF_LLH_PROTO_CLSS) | 4324 BIT(QED_MF_8021AD_TAGGING) | 4325 BIT(QED_MF_DONT_ADD_VLAN0_TAG); 4326 break; 4327 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 4328 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | 4329 BIT(QED_MF_LLH_PROTO_CLSS) | 4330 BIT(QED_MF_LL2_NON_UNICAST) | 4331 BIT(QED_MF_INTER_PF_SWITCH) | 4332 BIT(QED_MF_DISABLE_ARFS); 4333 break; 4334 case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 4335 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | 4336 BIT(QED_MF_LLH_PROTO_CLSS) | 4337 BIT(QED_MF_LL2_NON_UNICAST); 4338 if (QED_IS_BB(p_hwfn->cdev)) 4339 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF); 4340 break; 4341 } 4342 4343 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 4344 cdev->mf_bits); 4345 4346 /* In CMT the PF is unknown when the GFS block processes the 4347 * packet. Therefore cannot use searcher as it has a per PF 4348 * database, and thus ARFS must be disabled. 4349 * 4350 */ 4351 if (QED_IS_CMT(cdev)) 4352 cdev->mf_bits |= BIT(QED_MF_DISABLE_ARFS); 4353 } 4354 4355 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 4356 p_hwfn->cdev->mf_bits); 4357 4358 /* Read device capabilities information from shmem */ 4359 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4360 offsetof(struct nvm_cfg1, glob) + 4361 offsetof(struct nvm_cfg1_glob, device_capabilities); 4362 4363 device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 4364 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 4365 __set_bit(QED_DEV_CAP_ETH, 4366 &p_hwfn->hw_info.device_capabilities); 4367 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE) 4368 __set_bit(QED_DEV_CAP_FCOE, 4369 &p_hwfn->hw_info.device_capabilities); 4370 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 4371 __set_bit(QED_DEV_CAP_ISCSI, 4372 &p_hwfn->hw_info.device_capabilities); 4373 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 4374 __set_bit(QED_DEV_CAP_ROCE, 4375 &p_hwfn->hw_info.device_capabilities); 4376 4377 /* Read device serial number information from shmem */ 4378 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4379 offsetof(struct nvm_cfg1, glob) + 4380 offsetof(struct nvm_cfg1_glob, serial_number); 4381 4382 for (i = 0; i < 4; i++) 4383 p_hwfn->hw_info.part_num[i] = qed_rd(p_hwfn, p_ptt, addr + i * 4); 4384 4385 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 4386 } 4387 4388 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4389 { 4390 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 4391 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 4392 struct qed_dev *cdev = p_hwfn->cdev; 4393 4394 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB; 4395 4396 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 4397 * in the other bits are selected. 4398 * Bits 1-15 are for functions 1-15, respectively, and their value is 4399 * '0' only for enabled functions (function 0 always exists and 4400 * enabled). 4401 * In case of CMT, only the "even" functions are enabled, and thus the 4402 * number of functions for both hwfns is learnt from the same bits. 4403 */ 4404 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 4405 4406 if (reg_function_hide & 0x1) { 4407 if (QED_IS_BB(cdev)) { 4408 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) { 4409 num_funcs = 0; 4410 eng_mask = 0xaaaa; 4411 } else { 4412 num_funcs = 1; 4413 eng_mask = 0x5554; 4414 } 4415 } else { 4416 num_funcs = 1; 4417 eng_mask = 0xfffe; 4418 } 4419 4420 /* Get the number of the enabled functions on the engine */ 4421 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 4422 while (tmp) { 4423 if (tmp & 0x1) 4424 num_funcs++; 4425 tmp >>= 0x1; 4426 } 4427 4428 /* Get the PF index within the enabled functions */ 4429 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 4430 tmp = reg_function_hide & eng_mask & low_pfs_mask; 4431 while (tmp) { 4432 if (tmp & 0x1) 4433 enabled_func_idx--; 4434 tmp >>= 0x1; 4435 } 4436 } 4437 4438 p_hwfn->num_funcs_on_engine = num_funcs; 4439 p_hwfn->enabled_func_idx = enabled_func_idx; 4440 4441 DP_VERBOSE(p_hwfn, 4442 NETIF_MSG_PROBE, 4443 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 4444 p_hwfn->rel_pf_id, 4445 p_hwfn->abs_pf_id, 4446 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 4447 } 4448 4449 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4450 { 4451 u32 addr, global_offsize, global_addr, port_mode; 4452 struct qed_dev *cdev = p_hwfn->cdev; 4453 4454 /* In CMT there is always only one port */ 4455 if (cdev->num_hwfns > 1) { 4456 cdev->num_ports_in_engine = 1; 4457 cdev->num_ports = 1; 4458 return; 4459 } 4460 4461 /* Determine the number of ports per engine */ 4462 port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE); 4463 switch (port_mode) { 4464 case 0x0: 4465 cdev->num_ports_in_engine = 1; 4466 break; 4467 case 0x1: 4468 cdev->num_ports_in_engine = 2; 4469 break; 4470 case 0x2: 4471 cdev->num_ports_in_engine = 4; 4472 break; 4473 default: 4474 DP_NOTICE(p_hwfn, "Unknown port mode 0x%08x\n", port_mode); 4475 cdev->num_ports_in_engine = 1; /* Default to something */ 4476 break; 4477 } 4478 4479 /* Get the total number of ports of the device */ 4480 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 4481 PUBLIC_GLOBAL); 4482 global_offsize = qed_rd(p_hwfn, p_ptt, addr); 4483 global_addr = SECTION_ADDR(global_offsize, 0); 4484 addr = global_addr + offsetof(struct public_global, max_ports); 4485 cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr); 4486 } 4487 4488 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4489 { 4490 struct qed_mcp_link_capabilities *p_caps; 4491 u32 eee_status; 4492 4493 p_caps = &p_hwfn->mcp_info->link_capabilities; 4494 if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED) 4495 return; 4496 4497 p_caps->eee_speed_caps = 0; 4498 eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 4499 offsetof(struct public_port, eee_status)); 4500 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >> 4501 EEE_SUPPORTED_SPEED_OFFSET; 4502 4503 if (eee_status & EEE_1G_SUPPORTED) 4504 p_caps->eee_speed_caps |= QED_EEE_1G_ADV; 4505 if (eee_status & EEE_10G_ADV) 4506 p_caps->eee_speed_caps |= QED_EEE_10G_ADV; 4507 } 4508 4509 static int 4510 qed_get_hw_info(struct qed_hwfn *p_hwfn, 4511 struct qed_ptt *p_ptt, 4512 enum qed_pci_personality personality) 4513 { 4514 int rc; 4515 4516 /* Since all information is common, only first hwfns should do this */ 4517 if (IS_LEAD_HWFN(p_hwfn)) { 4518 rc = qed_iov_hw_info(p_hwfn); 4519 if (rc) 4520 return rc; 4521 } 4522 4523 if (IS_LEAD_HWFN(p_hwfn)) 4524 qed_hw_info_port_num(p_hwfn, p_ptt); 4525 4526 qed_mcp_get_capabilities(p_hwfn, p_ptt); 4527 4528 qed_hw_get_nvm_info(p_hwfn, p_ptt); 4529 4530 rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 4531 if (rc) 4532 return rc; 4533 4534 if (qed_mcp_is_init(p_hwfn)) 4535 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 4536 p_hwfn->mcp_info->func_info.mac); 4537 else 4538 eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 4539 4540 if (qed_mcp_is_init(p_hwfn)) { 4541 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 4542 p_hwfn->hw_info.ovlan = 4543 p_hwfn->mcp_info->func_info.ovlan; 4544 4545 qed_mcp_cmd_port_init(p_hwfn, p_ptt); 4546 4547 qed_get_eee_caps(p_hwfn, p_ptt); 4548 4549 qed_mcp_read_ufp_config(p_hwfn, p_ptt); 4550 } 4551 4552 if (qed_mcp_is_init(p_hwfn)) { 4553 enum qed_pci_personality protocol; 4554 4555 protocol = p_hwfn->mcp_info->func_info.protocol; 4556 p_hwfn->hw_info.personality = protocol; 4557 } 4558 4559 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) 4560 p_hwfn->hw_info.multi_tc_roce_en = true; 4561 4562 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2; 4563 p_hwfn->hw_info.num_active_tc = 1; 4564 4565 qed_get_num_funcs(p_hwfn, p_ptt); 4566 4567 if (qed_mcp_is_init(p_hwfn)) 4568 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu; 4569 4570 return qed_hw_get_resc(p_hwfn, p_ptt); 4571 } 4572 4573 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4574 { 4575 struct qed_dev *cdev = p_hwfn->cdev; 4576 u16 device_id_mask; 4577 u32 tmp; 4578 4579 /* Read Vendor Id / Device Id */ 4580 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id); 4581 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id); 4582 4583 /* Determine type */ 4584 device_id_mask = cdev->device_id & QED_DEV_ID_MASK; 4585 switch (device_id_mask) { 4586 case QED_DEV_ID_MASK_BB: 4587 cdev->type = QED_DEV_TYPE_BB; 4588 break; 4589 case QED_DEV_ID_MASK_AH: 4590 cdev->type = QED_DEV_TYPE_AH; 4591 break; 4592 default: 4593 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id); 4594 return -EBUSY; 4595 } 4596 4597 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM); 4598 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV); 4599 4600 MASK_FIELD(CHIP_REV, cdev->chip_rev); 4601 4602 /* Learn number of HW-functions */ 4603 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR); 4604 4605 if (tmp & (1 << p_hwfn->rel_pf_id)) { 4606 DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 4607 cdev->num_hwfns = 2; 4608 } else { 4609 cdev->num_hwfns = 1; 4610 } 4611 4612 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt, 4613 MISCS_REG_CHIP_TEST_REG) >> 4; 4614 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 4615 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL); 4616 MASK_FIELD(CHIP_METAL, cdev->chip_metal); 4617 4618 DP_INFO(cdev->hwfns, 4619 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 4620 QED_IS_BB(cdev) ? "BB" : "AH", 4621 'A' + cdev->chip_rev, 4622 (int)cdev->chip_metal, 4623 cdev->chip_num, cdev->chip_rev, 4624 cdev->chip_bond_id, cdev->chip_metal); 4625 4626 return 0; 4627 } 4628 4629 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 4630 void __iomem *p_regview, 4631 void __iomem *p_doorbells, 4632 u64 db_phys_addr, 4633 enum qed_pci_personality personality) 4634 { 4635 struct qed_dev *cdev = p_hwfn->cdev; 4636 int rc = 0; 4637 4638 /* Split PCI bars evenly between hwfns */ 4639 p_hwfn->regview = p_regview; 4640 p_hwfn->doorbells = p_doorbells; 4641 p_hwfn->db_phys_addr = db_phys_addr; 4642 4643 if (IS_VF(p_hwfn->cdev)) 4644 return qed_vf_hw_prepare(p_hwfn); 4645 4646 /* Validate that chip access is feasible */ 4647 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 4648 DP_ERR(p_hwfn, 4649 "Reading the ME register returns all Fs; Preventing further chip access\n"); 4650 return -EINVAL; 4651 } 4652 4653 get_function_id(p_hwfn); 4654 4655 /* Allocate PTT pool */ 4656 rc = qed_ptt_pool_alloc(p_hwfn); 4657 if (rc) 4658 goto err0; 4659 4660 /* Allocate the main PTT */ 4661 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 4662 4663 /* First hwfn learns basic information, e.g., number of hwfns */ 4664 if (!p_hwfn->my_id) { 4665 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt); 4666 if (rc) 4667 goto err1; 4668 } 4669 4670 qed_hw_hwfn_prepare(p_hwfn); 4671 4672 /* Initialize MCP structure */ 4673 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 4674 if (rc) { 4675 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 4676 goto err1; 4677 } 4678 4679 /* Read the device configuration information from the HW and SHMEM */ 4680 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 4681 if (rc) { 4682 DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 4683 goto err2; 4684 } 4685 4686 /* Sending a mailbox to the MFW should be done after qed_get_hw_info() 4687 * is called as it sets the ports number in an engine. 4688 */ 4689 if (IS_LEAD_HWFN(p_hwfn) && !cdev->recov_in_prog) { 4690 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt); 4691 if (rc) 4692 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n"); 4693 } 4694 4695 /* NVRAM info initialization and population */ 4696 if (IS_LEAD_HWFN(p_hwfn)) { 4697 rc = qed_mcp_nvm_info_populate(p_hwfn); 4698 if (rc) { 4699 DP_NOTICE(p_hwfn, 4700 "Failed to populate nvm info shadow\n"); 4701 goto err2; 4702 } 4703 } 4704 4705 /* Allocate the init RT array and initialize the init-ops engine */ 4706 rc = qed_init_alloc(p_hwfn); 4707 if (rc) 4708 goto err3; 4709 4710 return rc; 4711 err3: 4712 if (IS_LEAD_HWFN(p_hwfn)) 4713 qed_mcp_nvm_info_free(p_hwfn); 4714 err2: 4715 if (IS_LEAD_HWFN(p_hwfn)) 4716 qed_iov_free_hw_info(p_hwfn->cdev); 4717 qed_mcp_free(p_hwfn); 4718 err1: 4719 qed_hw_hwfn_free(p_hwfn); 4720 err0: 4721 return rc; 4722 } 4723 4724 int qed_hw_prepare(struct qed_dev *cdev, 4725 int personality) 4726 { 4727 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 4728 int rc; 4729 4730 /* Store the precompiled init data ptrs */ 4731 if (IS_PF(cdev)) 4732 qed_init_iro_array(cdev); 4733 4734 /* Initialize the first hwfn - will learn number of hwfns */ 4735 rc = qed_hw_prepare_single(p_hwfn, 4736 cdev->regview, 4737 cdev->doorbells, 4738 cdev->db_phys_addr, 4739 personality); 4740 if (rc) 4741 return rc; 4742 4743 personality = p_hwfn->hw_info.personality; 4744 4745 /* Initialize the rest of the hwfns */ 4746 if (cdev->num_hwfns > 1) { 4747 void __iomem *p_regview, *p_doorbell; 4748 u64 db_phys_addr; 4749 u32 offset; 4750 4751 /* adjust bar offset for second engine */ 4752 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 4753 BAR_ID_0) / 2; 4754 p_regview = cdev->regview + offset; 4755 4756 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 4757 BAR_ID_1) / 2; 4758 4759 p_doorbell = cdev->doorbells + offset; 4760 4761 db_phys_addr = cdev->db_phys_addr + offset; 4762 4763 /* prepare second hw function */ 4764 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 4765 p_doorbell, db_phys_addr, 4766 personality); 4767 4768 /* in case of error, need to free the previously 4769 * initiliazed hwfn 0. 4770 */ 4771 if (rc) { 4772 if (IS_PF(cdev)) { 4773 qed_init_free(p_hwfn); 4774 qed_mcp_nvm_info_free(p_hwfn); 4775 qed_mcp_free(p_hwfn); 4776 qed_hw_hwfn_free(p_hwfn); 4777 } 4778 } 4779 } 4780 4781 return rc; 4782 } 4783 4784 void qed_hw_remove(struct qed_dev *cdev) 4785 { 4786 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 4787 int i; 4788 4789 if (IS_PF(cdev)) 4790 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt, 4791 QED_OV_DRIVER_STATE_NOT_LOADED); 4792 4793 for_each_hwfn(cdev, i) { 4794 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4795 4796 if (IS_VF(cdev)) { 4797 qed_vf_pf_release(p_hwfn); 4798 continue; 4799 } 4800 4801 qed_init_free(p_hwfn); 4802 qed_hw_hwfn_free(p_hwfn); 4803 qed_mcp_free(p_hwfn); 4804 } 4805 4806 qed_iov_free_hw_info(cdev); 4807 4808 qed_mcp_nvm_info_free(p_hwfn); 4809 } 4810 4811 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 4812 { 4813 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 4814 u16 min, max; 4815 4816 min = (u16)RESC_START(p_hwfn, QED_L2_QUEUE); 4817 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 4818 DP_NOTICE(p_hwfn, 4819 "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 4820 src_id, min, max); 4821 4822 return -EINVAL; 4823 } 4824 4825 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 4826 4827 return 0; 4828 } 4829 4830 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 4831 { 4832 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 4833 u8 min, max; 4834 4835 min = (u8)RESC_START(p_hwfn, QED_VPORT); 4836 max = min + RESC_NUM(p_hwfn, QED_VPORT); 4837 DP_NOTICE(p_hwfn, 4838 "vport id [%d] is not valid, available indices [%d - %d]\n", 4839 src_id, min, max); 4840 4841 return -EINVAL; 4842 } 4843 4844 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 4845 4846 return 0; 4847 } 4848 4849 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 4850 { 4851 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 4852 u8 min, max; 4853 4854 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 4855 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 4856 DP_NOTICE(p_hwfn, 4857 "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 4858 src_id, min, max); 4859 4860 return -EINVAL; 4861 } 4862 4863 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 4864 4865 return 0; 4866 } 4867 4868 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 4869 u32 hw_addr, void *p_eth_qzone, 4870 size_t eth_qzone_size, u8 timeset) 4871 { 4872 struct coalescing_timeset *p_coal_timeset; 4873 4874 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 4875 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 4876 return -EINVAL; 4877 } 4878 4879 p_coal_timeset = p_eth_qzone; 4880 memset(p_eth_qzone, 0, eth_qzone_size); 4881 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 4882 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 4883 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 4884 4885 return 0; 4886 } 4887 4888 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle) 4889 { 4890 struct qed_queue_cid *p_cid = p_handle; 4891 struct qed_hwfn *p_hwfn; 4892 struct qed_ptt *p_ptt; 4893 int rc = 0; 4894 4895 p_hwfn = p_cid->p_owner; 4896 4897 if (IS_VF(p_hwfn->cdev)) 4898 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid); 4899 4900 p_ptt = qed_ptt_acquire(p_hwfn); 4901 if (!p_ptt) 4902 return -EAGAIN; 4903 4904 if (rx_coal) { 4905 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid); 4906 if (rc) 4907 goto out; 4908 p_hwfn->cdev->rx_coalesce_usecs = rx_coal; 4909 } 4910 4911 if (tx_coal) { 4912 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid); 4913 if (rc) 4914 goto out; 4915 p_hwfn->cdev->tx_coalesce_usecs = tx_coal; 4916 } 4917 out: 4918 qed_ptt_release(p_hwfn, p_ptt); 4919 return rc; 4920 } 4921 4922 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, 4923 struct qed_ptt *p_ptt, 4924 u16 coalesce, struct qed_queue_cid *p_cid) 4925 { 4926 struct ustorm_eth_queue_zone eth_qzone; 4927 u8 timeset, timer_res; 4928 u32 address; 4929 int rc; 4930 4931 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 4932 if (coalesce <= 0x7F) { 4933 timer_res = 0; 4934 } else if (coalesce <= 0xFF) { 4935 timer_res = 1; 4936 } else if (coalesce <= 0x1FF) { 4937 timer_res = 2; 4938 } else { 4939 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 4940 return -EINVAL; 4941 } 4942 timeset = (u8)(coalesce >> timer_res); 4943 4944 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 4945 p_cid->sb_igu_id, false); 4946 if (rc) 4947 goto out; 4948 4949 address = BAR0_MAP_REG_USDM_RAM + 4950 USTORM_ETH_QUEUE_ZONE_GTT_OFFSET(p_cid->abs.queue_id); 4951 4952 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 4953 sizeof(struct ustorm_eth_queue_zone), timeset); 4954 if (rc) 4955 goto out; 4956 4957 out: 4958 return rc; 4959 } 4960 4961 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, 4962 struct qed_ptt *p_ptt, 4963 u16 coalesce, struct qed_queue_cid *p_cid) 4964 { 4965 struct xstorm_eth_queue_zone eth_qzone; 4966 u8 timeset, timer_res; 4967 u32 address; 4968 int rc; 4969 4970 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 4971 if (coalesce <= 0x7F) { 4972 timer_res = 0; 4973 } else if (coalesce <= 0xFF) { 4974 timer_res = 1; 4975 } else if (coalesce <= 0x1FF) { 4976 timer_res = 2; 4977 } else { 4978 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 4979 return -EINVAL; 4980 } 4981 timeset = (u8)(coalesce >> timer_res); 4982 4983 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 4984 p_cid->sb_igu_id, true); 4985 if (rc) 4986 goto out; 4987 4988 address = BAR0_MAP_REG_XSDM_RAM + 4989 XSTORM_ETH_QUEUE_ZONE_GTT_OFFSET(p_cid->abs.queue_id); 4990 4991 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 4992 sizeof(struct xstorm_eth_queue_zone), timeset); 4993 out: 4994 return rc; 4995 } 4996 4997 /* Calculate final WFQ values for all vports and configure them. 4998 * After this configuration each vport will have 4999 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 5000 */ 5001 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 5002 struct qed_ptt *p_ptt, 5003 u32 min_pf_rate) 5004 { 5005 struct init_qm_vport_params *vport_params; 5006 int i; 5007 5008 vport_params = p_hwfn->qm_info.qm_vport_params; 5009 5010 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 5011 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 5012 5013 vport_params[i].wfq = (wfq_speed * QED_WFQ_UNIT) / 5014 min_pf_rate; 5015 qed_init_vport_wfq(p_hwfn, p_ptt, 5016 vport_params[i].first_tx_pq_id, 5017 vport_params[i].wfq); 5018 } 5019 } 5020 5021 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 5022 u32 min_pf_rate) 5023 5024 { 5025 int i; 5026 5027 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 5028 p_hwfn->qm_info.qm_vport_params[i].wfq = 1; 5029 } 5030 5031 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 5032 struct qed_ptt *p_ptt, 5033 u32 min_pf_rate) 5034 { 5035 struct init_qm_vport_params *vport_params; 5036 int i; 5037 5038 vport_params = p_hwfn->qm_info.qm_vport_params; 5039 5040 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 5041 qed_init_wfq_default_param(p_hwfn, min_pf_rate); 5042 qed_init_vport_wfq(p_hwfn, p_ptt, 5043 vport_params[i].first_tx_pq_id, 5044 vport_params[i].wfq); 5045 } 5046 } 5047 5048 /* This function performs several validations for WFQ 5049 * configuration and required min rate for a given vport 5050 * 1. req_rate must be greater than one percent of min_pf_rate. 5051 * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 5052 * rates to get less than one percent of min_pf_rate. 5053 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 5054 */ 5055 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 5056 u16 vport_id, u32 req_rate, u32 min_pf_rate) 5057 { 5058 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 5059 int non_requested_count = 0, req_count = 0, i, num_vports; 5060 5061 num_vports = p_hwfn->qm_info.num_vports; 5062 5063 if (num_vports < 2) { 5064 DP_NOTICE(p_hwfn, "Unexpected num_vports: %d\n", num_vports); 5065 return -EINVAL; 5066 } 5067 5068 /* Accounting for the vports which are configured for WFQ explicitly */ 5069 for (i = 0; i < num_vports; i++) { 5070 u32 tmp_speed; 5071 5072 if ((i != vport_id) && 5073 p_hwfn->qm_info.wfq_data[i].configured) { 5074 req_count++; 5075 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 5076 total_req_min_rate += tmp_speed; 5077 } 5078 } 5079 5080 /* Include current vport data as well */ 5081 req_count++; 5082 total_req_min_rate += req_rate; 5083 non_requested_count = num_vports - req_count; 5084 5085 if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 5086 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5087 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 5088 vport_id, req_rate, min_pf_rate); 5089 return -EINVAL; 5090 } 5091 5092 if (num_vports > QED_WFQ_UNIT) { 5093 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5094 "Number of vports is greater than %d\n", 5095 QED_WFQ_UNIT); 5096 return -EINVAL; 5097 } 5098 5099 if (total_req_min_rate > min_pf_rate) { 5100 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5101 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 5102 total_req_min_rate, min_pf_rate); 5103 return -EINVAL; 5104 } 5105 5106 total_left_rate = min_pf_rate - total_req_min_rate; 5107 5108 left_rate_per_vp = total_left_rate / non_requested_count; 5109 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 5110 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5111 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 5112 left_rate_per_vp, min_pf_rate); 5113 return -EINVAL; 5114 } 5115 5116 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 5117 p_hwfn->qm_info.wfq_data[vport_id].configured = true; 5118 5119 for (i = 0; i < num_vports; i++) { 5120 if (p_hwfn->qm_info.wfq_data[i].configured) 5121 continue; 5122 5123 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 5124 } 5125 5126 return 0; 5127 } 5128 5129 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 5130 struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 5131 { 5132 struct qed_mcp_link_state *p_link; 5133 int rc = 0; 5134 5135 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 5136 5137 if (!p_link->min_pf_rate) { 5138 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 5139 p_hwfn->qm_info.wfq_data[vp_id].configured = true; 5140 return rc; 5141 } 5142 5143 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 5144 5145 if (!rc) 5146 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 5147 p_link->min_pf_rate); 5148 else 5149 DP_NOTICE(p_hwfn, 5150 "Validation failed while configuring min rate\n"); 5151 5152 return rc; 5153 } 5154 5155 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 5156 struct qed_ptt *p_ptt, 5157 u32 min_pf_rate) 5158 { 5159 bool use_wfq = false; 5160 int rc = 0; 5161 u16 i; 5162 5163 /* Validate all pre configured vports for wfq */ 5164 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 5165 u32 rate; 5166 5167 if (!p_hwfn->qm_info.wfq_data[i].configured) 5168 continue; 5169 5170 rate = p_hwfn->qm_info.wfq_data[i].min_speed; 5171 use_wfq = true; 5172 5173 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 5174 if (rc) { 5175 DP_NOTICE(p_hwfn, 5176 "WFQ validation failed while configuring min rate\n"); 5177 break; 5178 } 5179 } 5180 5181 if (!rc && use_wfq) 5182 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 5183 else 5184 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 5185 5186 return rc; 5187 } 5188 5189 /* Main API for qed clients to configure vport min rate. 5190 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 5191 * rate - Speed in Mbps needs to be assigned to a given vport. 5192 */ 5193 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 5194 { 5195 int i, rc = -EINVAL; 5196 5197 /* Currently not supported; Might change in future */ 5198 if (cdev->num_hwfns > 1) { 5199 DP_NOTICE(cdev, 5200 "WFQ configuration is not supported for this device\n"); 5201 return rc; 5202 } 5203 5204 for_each_hwfn(cdev, i) { 5205 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 5206 struct qed_ptt *p_ptt; 5207 5208 p_ptt = qed_ptt_acquire(p_hwfn); 5209 if (!p_ptt) 5210 return -EBUSY; 5211 5212 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 5213 5214 if (rc) { 5215 qed_ptt_release(p_hwfn, p_ptt); 5216 return rc; 5217 } 5218 5219 qed_ptt_release(p_hwfn, p_ptt); 5220 } 5221 5222 return rc; 5223 } 5224 5225 /* API to configure WFQ from mcp link change */ 5226 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 5227 struct qed_ptt *p_ptt, u32 min_pf_rate) 5228 { 5229 int i; 5230 5231 if (cdev->num_hwfns > 1) { 5232 DP_VERBOSE(cdev, 5233 NETIF_MSG_LINK, 5234 "WFQ configuration is not supported for this device\n"); 5235 return; 5236 } 5237 5238 for_each_hwfn(cdev, i) { 5239 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 5240 5241 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt, 5242 min_pf_rate); 5243 } 5244 } 5245 5246 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 5247 struct qed_ptt *p_ptt, 5248 struct qed_mcp_link_state *p_link, 5249 u8 max_bw) 5250 { 5251 int rc = 0; 5252 5253 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 5254 5255 if (!p_link->line_speed && (max_bw != 100)) 5256 return rc; 5257 5258 p_link->speed = (p_link->line_speed * max_bw) / 100; 5259 p_hwfn->qm_info.pf_rl = p_link->speed; 5260 5261 /* Since the limiter also affects Tx-switched traffic, we don't want it 5262 * to limit such traffic in case there's no actual limit. 5263 * In that case, set limit to imaginary high boundary. 5264 */ 5265 if (max_bw == 100) 5266 p_hwfn->qm_info.pf_rl = 100000; 5267 5268 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 5269 p_hwfn->qm_info.pf_rl); 5270 5271 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5272 "Configured MAX bandwidth to be %08x Mb/sec\n", 5273 p_link->speed); 5274 5275 return rc; 5276 } 5277 5278 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 5279 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 5280 { 5281 int i, rc = -EINVAL; 5282 5283 if (max_bw < 1 || max_bw > 100) { 5284 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 5285 return rc; 5286 } 5287 5288 for_each_hwfn(cdev, i) { 5289 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 5290 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 5291 struct qed_mcp_link_state *p_link; 5292 struct qed_ptt *p_ptt; 5293 5294 p_link = &p_lead->mcp_info->link_output; 5295 5296 p_ptt = qed_ptt_acquire(p_hwfn); 5297 if (!p_ptt) 5298 return -EBUSY; 5299 5300 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 5301 p_link, max_bw); 5302 5303 qed_ptt_release(p_hwfn, p_ptt); 5304 5305 if (rc) 5306 break; 5307 } 5308 5309 return rc; 5310 } 5311 5312 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 5313 struct qed_ptt *p_ptt, 5314 struct qed_mcp_link_state *p_link, 5315 u8 min_bw) 5316 { 5317 int rc = 0; 5318 5319 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 5320 p_hwfn->qm_info.pf_wfq = min_bw; 5321 5322 if (!p_link->line_speed) 5323 return rc; 5324 5325 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 5326 5327 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 5328 5329 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5330 "Configured MIN bandwidth to be %d Mb/sec\n", 5331 p_link->min_pf_rate); 5332 5333 return rc; 5334 } 5335 5336 /* Main API to configure PF min bandwidth where bw range is [1-100] */ 5337 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 5338 { 5339 int i, rc = -EINVAL; 5340 5341 if (min_bw < 1 || min_bw > 100) { 5342 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 5343 return rc; 5344 } 5345 5346 for_each_hwfn(cdev, i) { 5347 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 5348 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 5349 struct qed_mcp_link_state *p_link; 5350 struct qed_ptt *p_ptt; 5351 5352 p_link = &p_lead->mcp_info->link_output; 5353 5354 p_ptt = qed_ptt_acquire(p_hwfn); 5355 if (!p_ptt) 5356 return -EBUSY; 5357 5358 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 5359 p_link, min_bw); 5360 if (rc) { 5361 qed_ptt_release(p_hwfn, p_ptt); 5362 return rc; 5363 } 5364 5365 if (p_link->min_pf_rate) { 5366 u32 min_rate = p_link->min_pf_rate; 5367 5368 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 5369 p_ptt, 5370 min_rate); 5371 } 5372 5373 qed_ptt_release(p_hwfn, p_ptt); 5374 } 5375 5376 return rc; 5377 } 5378 5379 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 5380 { 5381 struct qed_mcp_link_state *p_link; 5382 5383 p_link = &p_hwfn->mcp_info->link_output; 5384 5385 if (p_link->min_pf_rate) 5386 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 5387 p_link->min_pf_rate); 5388 5389 memset(p_hwfn->qm_info.wfq_data, 0, 5390 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 5391 } 5392 5393 int qed_device_num_ports(struct qed_dev *cdev) 5394 { 5395 return cdev->num_ports; 5396 } 5397 5398 void qed_set_fw_mac_addr(__le16 *fw_msb, 5399 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac) 5400 { 5401 ((u8 *)fw_msb)[0] = mac[1]; 5402 ((u8 *)fw_msb)[1] = mac[0]; 5403 ((u8 *)fw_mid)[0] = mac[3]; 5404 ((u8 *)fw_mid)[1] = mac[2]; 5405 ((u8 *)fw_lsb)[0] = mac[5]; 5406 ((u8 *)fw_lsb)[1] = mac[4]; 5407 } 5408 5409 static int qed_llh_shadow_remove_all_filters(struct qed_dev *cdev, u8 ppfid) 5410 { 5411 struct qed_llh_info *p_llh_info = cdev->p_llh_info; 5412 struct qed_llh_filter_info *p_filters; 5413 int rc; 5414 5415 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "remove_all"); 5416 if (rc) 5417 return rc; 5418 5419 p_filters = p_llh_info->pp_filters[ppfid]; 5420 memset(p_filters, 0, NIG_REG_LLH_FUNC_FILTER_EN_SIZE * 5421 sizeof(*p_filters)); 5422 5423 return 0; 5424 } 5425 5426 static void qed_llh_clear_ppfid_filters(struct qed_dev *cdev, u8 ppfid) 5427 { 5428 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 5429 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 5430 u8 filter_idx, abs_ppfid; 5431 int rc = 0; 5432 5433 if (!p_ptt) 5434 return; 5435 5436 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits) && 5437 !test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits)) 5438 goto out; 5439 5440 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 5441 if (rc) 5442 goto out; 5443 5444 rc = qed_llh_shadow_remove_all_filters(cdev, ppfid); 5445 if (rc) 5446 goto out; 5447 5448 for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; 5449 filter_idx++) { 5450 rc = qed_llh_remove_filter(p_hwfn, p_ptt, 5451 abs_ppfid, filter_idx); 5452 if (rc) 5453 goto out; 5454 } 5455 out: 5456 qed_ptt_release(p_hwfn, p_ptt); 5457 } 5458 5459 int qed_llh_add_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port) 5460 { 5461 return qed_llh_add_protocol_filter(cdev, 0, 5462 QED_LLH_FILTER_TCP_SRC_PORT, 5463 src_port, QED_LLH_DONT_CARE); 5464 } 5465 5466 void qed_llh_remove_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port) 5467 { 5468 qed_llh_remove_protocol_filter(cdev, 0, 5469 QED_LLH_FILTER_TCP_SRC_PORT, 5470 src_port, QED_LLH_DONT_CARE); 5471 } 5472 5473 int qed_llh_add_dst_tcp_port_filter(struct qed_dev *cdev, u16 dest_port) 5474 { 5475 return qed_llh_add_protocol_filter(cdev, 0, 5476 QED_LLH_FILTER_TCP_DEST_PORT, 5477 QED_LLH_DONT_CARE, dest_port); 5478 } 5479 5480 void qed_llh_remove_dst_tcp_port_filter(struct qed_dev *cdev, u16 dest_port) 5481 { 5482 qed_llh_remove_protocol_filter(cdev, 0, 5483 QED_LLH_FILTER_TCP_DEST_PORT, 5484 QED_LLH_DONT_CARE, dest_port); 5485 } 5486 5487 void qed_llh_clear_all_filters(struct qed_dev *cdev) 5488 { 5489 u8 ppfid; 5490 5491 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits) && 5492 !test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits)) 5493 return; 5494 5495 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) 5496 qed_llh_clear_ppfid_filters(cdev, ppfid); 5497 } 5498